JPH05343540A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the flatness of an interlayer insulating film and to prevent that the discontinuity and the like of a multilayer wiring is caused in a semiconductor device which is provided with the multilayer wiring. CONSTITUTION:In a region in which a signal wiring by means of a multilayer wiring does not exist, a first-layer dummy wiring 101 as an even-numbered lattice is arranged and a third-layer dummy wiring 102 as an odd-numbered lattice is arranged. Thereby, the flatness of interlayer insulating films 113, 114, 115 is improved. An increase in the parasitic capacitance due to the dummy wirings can be reduced more than a case where dummy wirings are arranged in all lattices, and the multilayer wiring can be made fine and promoted further.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having multi-layer wiring.

[0002]

2. Description of the Related Art A case of a four-layer aluminum wiring will be described as an example of a conventional semiconductor device having a multilayer wiring with reference to the drawings.

FIGS. 4A and 4B are a plan view and a sectional view taken along the line BB 'for explaining an example of a conventional semiconductor device.

As shown in FIGS. 4A and 4B, CAD
The first-layer signal lines 103 on the Y lattices 3 and 8 of the wirings connected by are respectively the second-layer signal lines 104 on the X lattices 2 and 4.
To the first through hole 105. X lattice 7
The upper second layer signal line 104 and the third layer signal line 1 on the Y grating 7
07 is connected to the second through hole 108, and the Y grid 9
The upper third-layer signal line 107 and the fourth-layer signal line 1 on the X lattice 5
The third through hole 109 and 10 are connected. X
The fourth layer signal line 110 on the gratings 6 and 9 is a passing signal line.

Here, the four-layer aluminum wiring is formed on the interlayer insulating film 112 on the P-type silicon substrate 111, and the interlayer insulating films 113, 114, 115 are provided between the signal lines 103, 107, 110 of the respective layers. Are formed. Then, the interlayer insulating film 113 uses a silicon oxide film and a coated glass (spin-on glass) film by a plasma CVD method to improve the step coverage of the signal line in the upper layer and to prevent step breakage, and a step portion generated by the signal line in the lower layer. Is smoothed and flattened.

[0006]

In this conventional multilayer wiring, since the interlayer insulating film 113 is not sufficiently flattened, a region where the lower wiring is dense, for example, as shown in FIG. , Y-lattices 7 to 9 have the interlayer insulating film 1
13 is flattened, the interlayer insulating film 113 is not sufficiently flattened in the region where the lower wiring is sparse, for example, the region from Y lattices 1 to 5 shown in FIG. There is a problem that the step coverage of the signal line 110 is deteriorated.

In addition, as shown in FIG. 4B, the upper layer wiring, for example, when processing the fourth layer signal line 110, the first layer signal line 103 and the third layer signal line 107 on the Y lattice 3 overlap each other. Since there is a step of 1.5 to 2.0 μm between the exposed portion and the portion below the Y gratings 5 and 6 where there is no signal line, the problem is that the photoresist film cannot be patterned due to the lack of focus during alignment and exposure. was there. Further, even if the photoresist film can be patterned, the photoresist film in the portion of the Y grating 3 is thinner than usual, so that the photoresist film disappears during dry etching and the fourth-layer signal line 110 is also etched. There was a problem of being disconnected.

As a means for solving this problem, there is a method of arranging dummy wirings in all areas where there is no wiring. In this method, wiring capacitance, that is, capacitance between adjacent wirings in the same layer and between wirings in the lower layer Also, there is a problem that the capacitance between the upper layer wirings increases and the circuit operation becomes slow.

[0009]

The semiconductor device of the present invention comprises:
In a semiconductor device having a multi-layered wiring in which wirings are arranged on a wiring grid set on a semiconductor substrate, on a even-numbered grid or an odd-numbered grid of at least one wiring layer other than the uppermost wiring layer of the multi-layered wiring. It has dummy wirings arranged and provided.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIGS. 1 and 2A and 2B are a plan view and a sectional view taken along the line AA 'shown in accordance with the design procedure for explaining the first embodiment of the present invention.

First, as shown in FIG. 1, the first layer dummy wirings 101 are arranged on the even lattice of the Y lattice and the third layer dummy wirings 102 are arranged on the odd lattice before the automatic wiring. ..

Next, as shown in FIGS. 2 (a) and 2 (b),
Wiring the signal lines necessary to form the integrated circuit. In other words, the first layer signal lines 103 and 106 of the Y gratings 3 and 8 and the second layer signal line 104 of the X gratings 2 and 4 are connected to the first through hole 1.
05, and the third layer signal lines 10 of the Y lattice 7 are connected.
7 and the second layer signal line 104 of the X lattice 7 are connected by the second through hole 108, and the third layer signal line 107 of the Y lattice 9 and the fourth layer signal line 110 of the X lattice 5 are connected to the third through hole 10.
Connected at 9. Then, the fourth-layer signal line 110 of the X-grating 9 is a signal line passing in this plane.

Although the first-layer dummy wiring 101 is arranged in front of the automatic wiring on the Y-lattice 8, the first-layer dummy wiring 101 is used because it is used as the first-layer signal line 106 by the automatic wiring. After being cut, one part becomes the first layer signal line 106, and the other part becomes the first layer dummy wiring 101 as it is. Similarly, a part of the third layer dummy wirings 102 of the Y lattices 7 and 9 is used as the third layer signal line 107, and the other portions are used as the dummy wirings 102.

Further, interlayer insulating films 113, 1 between the respective wiring layers
14 and 115 are flattened by a silicon oxide film and a coating glass (spin-on glass) film by a plasma CVD method.
03, there are first-layer dummy wirings 101, the interlayer insulating film 113 on the first wiring layer is completely flattened, and in the regions from the Y lattices 5 to 9, the first-layer dummy wirings 10 are formed.
The 1st and 1st layer signal lines 106 are arranged every other pitch and are not completely flattened, but become a fairly well flattened interlayer insulating film 113, and the third layer dummy wiring 10 is formed.
Since the second and third layer signal lines 107 are arranged in the concave portion of the interlayer insulating film 114, the step difference is alleviated and the interlayer insulating film 115 is almost completely flattened.

3 (a) and 3 (b) are plan views shown in accordance with the design procedure for explaining the second embodiment of the present invention.

First, as shown in FIG. 3A, the third-layer dummy wiring 102 is formed on the even lattice of the Y lattice before the automatic wiring.
The second-layer dummy wirings 301 are arranged on the odd lattice of the X lattice.

Next, as shown in FIG. 3B, signal lines are arranged by the same design procedure as in the first embodiment. In addition,
The connection state of the wiring is the same as that of the first embodiment and will not be described.

Also in this embodiment, dummy wirings are arranged in the second and third wiring layers, and the flatness of the interlayer insulating film can be greatly improved. In addition, although the present embodiment has no dummy wiring in the first wiring layer, when applied in the transistor cell, the first wiring layer is often used for the wiring in the transistor cell and is densely packed. The interlayer insulating film is flat even if it is not used, and the flattening is further improved.

[0020]

As described above, according to the present invention, the dummy wiring is formed on the even-numbered grid or the odd-numbered grid to improve the flatness of the interlayer insulating film and to disconnect the wiring due to the step of the upper wiring layer. This has the effect of preventing

For example, in the four-layer wiring structure, the level difference between the high portion and the low portion of the lower interlayer insulating film of the fourth layer aluminum wiring is conventionally 1.5 to 3.0 μm but is 0.5 μm or less. And the step coverage of the fourth layer wiring is almost 1
It will be 00%. Also, since this step difference is reduced, the thickness of the photoresist film in the through hole formation process and wiring formation process is almost uniform within the chip, and there is no problem that the focus is not partially adjusted during exposure, enabling fine patterning. Therefore, the number of wiring layers can be increased, that is, the wiring which has been conventionally four-layer wiring can be six- to eight-layer wiring.

Regarding the wiring capacity, the capacity of the adjacent wirings increases due to the addition of the dummy wirings. However, when the dummy wirings are in the entire lattice, the wiring capacity increase is about 20%. The increase in wiring capacitance is reduced to 5% or less.

Further, by changing the grid for arranging the dummy wirings between the wirings in the upper layer and the wirings in the lower layer, the unevenness of the interlayer insulating film can be alleviated and the flatness can be further improved.

As described above, according to the present invention, by flattening the interlayer insulating film, it is possible to further improve the miniaturization and multi-layering of the multi-layer wiring, and also to suppress the increase of the wiring capacitance to a low level, so that the semiconductor device can be highly integrated and have high performance. Can be promoted.

[Brief description of drawings]

FIG. 1 is a plan view shown according to a design procedure for explaining a first embodiment of the present invention.

2A and 2B are a plan view and a cross-sectional view taken along the line AA ′ shown in accordance with a design procedure for explaining the first embodiment of the present invention.

FIG. 3 is a plan view shown according to a design procedure for explaining a second embodiment of the present invention.

FIG. 4 is a plan view and a cross-sectional view taken along the line BB ′ for explaining an example of a conventional semiconductor device.

[Explanation of symbols]

 101 first layer dummy wiring 102 third layer dummy wiring 103 first layer signal line 104 second layer signal line 105 first through hole 106 first layer signal line 107 third layer signal line 108 second through hole 109 third through Hole 110 fourth layer signal line 111 P type silicon substrate 112, 113, 114, 115 interlayer insulating film 301 second layer dummy wiring

Claims (4)

[Claims] 1. A semiconductor device having a multilayer wiring in which wirings are arranged on a wiring grid set on a semiconductor substrate, wherein an even grid of at least one wiring layer other than the uppermost wiring layer of the multilayer wiring is provided. Alternatively, a semiconductor device having dummy wirings arranged on an odd lattice. 2. A dummy wiring arranged on an even grid of one wiring layer of a plurality of wiring layers and a dummy wiring arranged on an odd grid of another wiring layer different from the wiring layer. The semiconductor device according to claim 1, further comprising: 3. The wiring provided in the even-numbered wiring layer and the wiring provided in the odd-numbered wiring layer are arranged orthogonal to each other, and at least one wiring layer and the odd-numbered wiring layer of the even-numbered wiring layer. The semiconductor device according to claim 1, further comprising a dummy wiring provided in at least one wiring layer of the eye wiring layer. 4. The wiring provided in the even-numbered wiring layer and the wiring provided in the odd-numbered wiring layer are arranged orthogonal to each other, and the wirings of the even-numbered wiring layer and the odd-numbered wiring layer are arranged. The semiconductor device according to claim 1, further comprising a dummy wiring arranged only in one of the wiring layers.