JPH0680660B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD In the present invention, after the first and second wirings are formed, the third wiring metal is used to connect in a region surrounding a portion where the wirings overlap in two layers. The present invention relates to a method for manufacturing a semiconductor device.

(Prior Art) A conventional two-layer wiring structure is shown in FIG. In FIG. 1, reference numeral 1 is a substrate, 2 is an interlayer (first layer-second layer wiring) insulating film, 3
Is a first layer wiring, and 4 is a second layer wiring.

FIG. 2 is a diagram showing a manufacturing process of a semiconductor device having such a structure. First, FIG. 2A is a diagram in which the formation of the first layer wiring 3 is completed on the substrate 1. Next, as shown in FIG. 2 (b), an interlayer insulating film 2 is formed, and a 1st to 2nd layer wiring connection window (hereinafter referred to as a through hole) 3'is opened. Subsequently, as shown in FIG. 1C, the second layer wiring 4 is formed and the first layer wiring and the second layer wiring are connected.

The above is a conventional manufacturing process, and these manufacturing methods had the following defects. Through hole is the second layer wiring 4
In order to prevent disconnection at the step of the through hole, the wiring width is necessarily controlled by the diameter of the through hole, the through hole margin within the wiring width, the photo masking alignment margin, etc. . Therefore, the downsizing of devices such as logic circuits, which occupy the majority of the wiring area, has largely contributed to the reduction of the through hole diameter and the improvement of the alignment accuracy of the photomask.

(Object of the Invention) An object of the present invention is to connect the first and second wirings in a region surrounded by the wirings of two layers, that is, to set the first and second wiring widths in an opening portion wider than the wiring width. An object of the present invention is to obtain a method of manufacturing a semiconductor device in which the controlling factors can be reduced and the size can be reduced to the extent that it can be formed.

(Summary of the Invention) The main point of the present invention is to remove an interlayer insulating film in a region (through hole portion) in which the overlapping portions of the first and second layer wirings are sufficiently surrounded by the insulating film in the interlayer connection of the multilayer wiring. Then
It is to connect using the third wiring metal.

(Embodiment) An embodiment of a method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. FIG. 3 shows a sectional structure of a semiconductor device manufactured according to the embodiment.

In FIG. 3, 11 is a semiconductor substrate (hereinafter referred to as a substrate), 12 is an interlayer insulating film, 13 is a first wiring, 14 is a second wiring, and 15 is a third wiring metal.

Next, a method of manufacturing the semiconductor device having the structure of FIG.
This will be described with reference to FIGS. First, as shown in FIG. 4A, a first wiring 13 (aluminum is formed to a thickness of about 0.6 μ) is formed on a substrate 11.

Next, as shown in FIG. 4 (b), the interlayer insulating film 12 is formed on the entire surface.
As a result, PSG is generated to a thickness of about 0.6 μ. Then the second
The wiring 14 is formed with a thickness of about 1.2 μm of aluminum.

Continuing, as shown in FIG. 4 (d), the first and second wirings 13 and 14
Of the interlayer insulation film 12 (including the periphery of the overlapping portions of the first wiring 13 and the second wiring 14) with the photoresist 12 'as a mask, for example, a dry etching method (even if it is isotropic. Either direction is acceptable).

Next, as shown in FIG. 4 (e), the third wiring metal 15
(Aluminum is formed to a thickness of 1.2μ) and by RIE etching (reactive ion etching), the third wiring metal 15 on the entire surface is removed by etching by the film thickness, that is, 1.2μ of aluminum. The film of the third wiring metal 15 remains on the side wall of the portion where the first and second wirings 13 and 14 overlap and the removed portion of the interlayer insulating film 12, and as shown in FIG. The semiconductor device is completed.

5 (a) to 5 (e) show a second embodiment of the present invention for further enhancing the effect of the above embodiment.

Next, the second embodiment will be described. First, the fifth
FIG. 6A shows the first wiring on the substrate 11 as in the first embodiment.
After forming 13, the inter-layer insulating film 12 is produced.

Next, the second wiring 14 is formed as shown in FIG.
Further, the second interlayer insulating film 16 is formed on the entire surface.

Next, as shown in FIG. 5C, a region surrounded by the wiring connection portion is opened with a photoresist 17, and the second interlayer insulating film 16 is removed by, for example, dry etching.

Next, as shown in FIG. 5D, after the photoresist 17 is removed, a third wiring metal film 18 is deposited, and a third wiring region is formed in the photoresist 19 if necessary. Then, if the third wiring metal film 18 is removed by RIE etching for the film thickness,
As shown in FIG. 5 (e), the first and second inter-wiring connections 20, 1,
The second and third inter-wiring connections 21 and the second and third inter-wiring connections 22 are determined by the formation pattern of the third wiring.

Further, by depositing an insulating film, for example, a PSG film on the entire surface, a structure having a device function equivalent to that of a normal one is completed.

In the case of the second embodiment, after the formation of the second interlayer insulating film 16, the through holes are opened, the third wiring metal 18 is deposited, and then the third wiring is formed if necessary. Has the advantages listed below.

(1) Since the first to third wirings can be connected with one opening of the through hole, the through hole photolithography can be reduced by one time in the case of the three-layer wiring as compared with the conventional case.

(2) 1st and 2nd wiring 13,1 with one through hole
4. Since the second and third wirings 14 and 15 can be connected, the degree of freedom of wiring is increased.

(Effect of the Invention) As described above, according to the present invention, after the first and second wirings are formed, the third wiring metal is used so that the two layers are connected in the region surrounding the overlapping portion of the wirings. The wiring width is not affected by the diameter of the through hole or the margin between the through hole and the wiring, and the wiring width in the multilayer wiring can be reduced to the extent that it can be formed. According to the current design rules, the wiring pitch can be reduced from 7μ to 5μ, and the area ratio can be reduced to 1/2.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of a conventional semiconductor device, FIGS. 2 (a) to 2 (c) are process explanatory diagrams of a conventional semiconductor device manufacturing method, and FIG. 3 is a semiconductor device of the present invention. 4A to 4F are sectional views showing the structure of a semiconductor device manufactured by the manufacturing method of FIG. 5 (a) to 5 (e) are process explanatory views of another embodiment of the method for manufacturing a semiconductor device of the present invention. 11 ... Substrate, 12 ... Interlayer insulating film, 12 ', 17, 19 ... Photoresist, 13 ... First wiring, 14 ... Second wiring, 15 ...
… Third wiring metal, 16 …… Second interlayer insulating film, 18 …… Third wiring metal film.

Claims (1)

[Claims] 1. A step of forming a first wiring pattern on a semiconductor substrate, a step of forming an insulating film on the semiconductor substrate including the first wiring pattern, and a step of forming an insulating film on the first wiring pattern. , Second through the insulating film
Forming a wiring pattern, and removing the insulating film exposed in a predetermined region surrounding a region where the first and second wiring patterns are arranged above and below,
Exposing the side surfaces of the first and second wiring patterns, and thereafter depositing a wiring film on the semiconductor substrate including the second wiring pattern and the insulating film; and anisotropically forming the wiring film. Etching and leaving the third wiring pattern as a third wiring pattern so that at least the side surfaces of the first and second wiring patterns are in contact with each other.