JPH0778817A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To improve the reliability of a multilayered semiconductor by forming a contact hole above a conducting film pattern which hole penetrates a third insulating film and a first insulating film and in which the aperture edge of the third insulating film is retreated from the aperture edge of the first insulating film. CONSTITUTION:On a substrate 1 having conducting film patterns 2A, 2B, a first insulating film 3 which covers the surface of the substrate 1 and the surfaces of the patterns 2A, 2B along the surfaces is formed. A second insulating film 5 having quality different from the first insulating film 3 is formed which is flatly buried in a recessed part between the conducting film patterns 2A and 2B so as to expose the surface of the first insulating layer 3 on the conducting film patterns 2A, 2B. A third insulating film 6 having quality different from the first insulating film 3 which film 6 covers collectively the first insulating film 3 and the second insulating film 5 is formed. Contact holes 7A, 7B are formed above the conducting film patterns 2A, 2B which holes penetrate the third insulating film 6 and the first insulating film 3 and in which aperture 9 edges of the third insulating films are retreated from aperture 10 edges of the first insulating films.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a multilayer wiring structure for improving the coverage of thin film metal wiring and a method for forming the same.

In recent years, the miniaturization of metal wiring associated with higher integration in LSI has deteriorated the coverage at the step portion of the interlayer insulating film and the step portion of the contact hole, which causes disconnection of the metal wiring and resistance. L due to increase
There is a problem that the reliability of SI is significantly impaired, and improvement is desired.

[0003]

2. Description of the Related Art In a multilayer wiring structure used for an LSI or the like, in order to maintain wiring quality and ensure reliability of a semiconductor device, a step of flattening a surface of an interlayer insulating film which is a base of upper wiring is required. The included forming method is used.

At that time, conventionally, a method as described below with reference to the process sectional view of FIG. 5 has been mainly used. Refer to FIG. 5 (a). That is, first, a plurality of protruding lower layer metal wirings having various widths (thickness of about 7,000 Å to 1 μm) 52A, 52B, 52C,
52D, 52E, etc. are arranged at various intervals on a base body (the surface is made of an insulating film) 51, and this base body 51 is covered along the surface of the base body 51 and the surface of the lower layer metal wiring to a thickness of about 5000Å First insulating film made of, for example, phosphosilicate glass (PSG)
53 is formed by CVD means.

Next, referring to FIG. 5 (b), a spin-on-glass (SOG) film 55 having a thickness that sufficiently fills the recesses 54A, 54B, 54C, 54D and the like formed between the lower metal wirings is formed on the substrate. It is formed using a spin coating method.

Next, referring to FIG. 5 (c), all the lower layer metal wirings 52A, 52B, 52C and 52 are formed by anisotropic dry etching means using an etching gas (eg CF ₄ + CHF ₃ ) capable of etching SOG.
Etch back is performed until the SOG film 55 on D, 52E, etc. is completely removed, and the SOG film 55 is left buried in the recesses 54A, 54B, 54C, 54D, etc. to flatten the surface.

Then, referring to FIG. 5 (d), a thickness of, for example, PSG 50 is formed by the CVD method.
A third insulating film 56 of about 00Å is formed, and then the lower wiring 52
A, 52B, 52C, 52D, 52E, etc. interlayer insulating film, that is, the third
The contact holes 57A, 57B, 57C, 57D, 57E, etc. penetrating the insulating film 56 and the first insulating film 53 are formed by using ordinary photolithography means.

Next, referring to FIG. 5 (e), the thickness of 7000Å to 1 made of, for example, an aluminum (Al) alloy is formed on the above-mentioned substrate by using a sputtering method as usual.
A metal film for wiring having a thickness of about μm is formed, and then the metal film is patterned by using ordinary photolithography means,
On the third insulating film 56, for example, a contact hole 57
Lower metal wiring 52 through A, 57B, 57C, 57D, 57E, etc.
An upper metal wiring 58 for connecting A, 52B, 52C, 52D, 52E and the like in parallel is formed.

[0009]

However, in the conventional method as described above, as shown in FIG. 5 (b), the thickness of the spin-coated SOG film 55 is lower than that of the lower metal wiring 52A, 52B,
It is formed thicker in the upper area A ₁ that is densely arranged at a narrow interval such as 52C and in the upper area A ₃ of the wide wiring 52E, but is separated from other wiring such as the metal wiring 52D. The upper region A _{2 of the} lower layer wiring formed as a result tends to be thinly formed.

Further, since SOG is used for the insulating film for embedding in the above conventional method, the first insulating film (PSG) 53 under the SOG film 55 is etched with the same etchant as SOG.

Therefore, in the conventional method, the SOG film 55 is used.
In the area A ₂ where the SOG film 55 is thinly formed, the first insulating film (PSG film) 53 at the lower part is etched and the part thereof, for example, on the lower metal wiring 52D which is arranged apart from The film thickness of the first insulating film 53 is partially thin.

Therefore, in the above-mentioned conventional method, when it is always necessary to leave the first insulating film on the lower metal wiring in the etching back so as not to give etching damage to the lower metal wiring surface, as described above. The thickness of the first insulating film 53 must be formed as thick as about 5000 Å. Therefore, as shown in FIG. 5D, the first insulating film 53 remains at the thickness of the formed film, for example. Above the lower metal wirings 52A, 52B, 52C, 52E, etc., the first insulating film 53 and the third insulating film 53 formed thereon are provided.
The thickness of the interlayer insulating film composed of the insulating film 56 and the contact hole 52A formed in the insulating film 56 becomes larger than necessary.
The steps on the side walls of 52B, 52C, 52E, etc. become large. Therefore, the coverage of the upper-layer metal wiring 58 extending over these contact holes in these contact hole portions is as indicated by arrows C ₁ , C ₂ , C ₃ , C _4, etc. in FIG. 5 (e). There is a problem in that the reliability of the LSI is deteriorated due to an increase in wiring resistance or disconnection due to step breakage in the upper metal wiring 58, which is extremely bad. (Note that the coverage in the contact hole 57D on the lower-layer metal wiring 52D where the first insulating film 53 is thin becomes good as indicated by the arrow B.) Separately, although not shown, Silicon nitride (Si ₃
N ₄ ) film and polyimide for the second insulating film
Although a method without using the insulating film has been attempted, in this method, when the metal wiring of the upper layer is formed, the redeposition of the polyimide on the lower wiring surface exposed in the contact hole due to the degassing from the polyimide. However, there is a problem that contact failure occurs.

In view of the above, the present invention prevents variations in side wall step differences of contact holes and maintains an appropriate step difference to improve the coverage of wiring metal, thereby preventing an increase in resistance of the upper metal wiring and step breakage. An object of the present invention is to provide a semiconductor device having a multi-layered wiring structure and a method for manufacturing the same, which can prevent the occurrence of defective wiring contact due to the re-adhesion of foreign matter into the contact hole.

[0014]

To solve the above-mentioned problems, a first insulating layer is provided on a substrate having a plurality of projecting conductive film patterns, the first insulating film covering the surface of the substrate and the surface of the conductive film pattern along the surface. The film (preferably made of any one of a silicon oxide film, a silicon nitride film, and a phosphosilicate glass film) and a recess between the conductive film patterns exposes the surface of the first insulating film on the conductive film pattern. Such that the second insulating film (preferably made of polyimide) different from the first insulating film that is buried evenly and that the first insulating film and the second insulating film are collectively covered A third insulating film which is different from the first insulating film (preferably made of a silicon oxide film, a silicon nitride film, a phosphosilicate glass film which is different from the first insulating film, or a polyimide) And the third conductive film pattern on the conductive film pattern. A semiconductor device according to the present invention, wherein a contact hole is provided that penetrates the edge film and the first insulating film, and the opening edge of the third insulating film is set back from the opening edge of the first insulating film. Alternatively, a first insulating film (preferably a silicon oxide film or a silicon nitride film) is formed on a substrate having a plurality of projecting conductive film patterns, the first insulating film covering the substrate along the exposed surface of the substrate and the surface of the conductive film pattern. A step of forming a film or a phosphosilicate glass film), and a second insulating film (desirably an etching selectivity with respect to the first insulating film) on the substrate covered with the first insulating film. Is a non-silicon-containing polyimide film) having a thickness such that the surface is substantially flattened, and the second insulating film is formed with respect to the second insulating film rather than the first insulating film. Using the dominant etching means,
Etching back until the first insulating film on the conductive film pattern is exposed to flatten the recesses between the conductive film patterns with the second insulating film, and filling the recesses. A third insulating film (preferably a silicon oxide film, a silicon nitride film, a phosphosilicate glass) is formed so as to collectively cover the second insulating film and the exposed surface of the first insulating film on the conductive film pattern. A film or a polyimide film), and a contact hole that exposes the conductive film pattern through the third insulating film and the first insulating film on the conductive film pattern, Desirably, the first insulating film and the third insulating film having etching selectivity are used, and the opening end portion of the third insulating film in the contact hole is defined as the opening end portion of the first insulating film. Formed by including a selective etching process to make it more recessed Step, a method of manufacturing a semiconductor device according to the invention with a capital, or, in the above method, the second insulating film, a photosensitive polyimide film, the second
In the step of etching back the insulating film, the photosensitive polyimide film is exposed to reach the surface of the first insulating film on the conductive film pattern, and then the exposed region of the photosensitive polyimide film is removed by development. This is achieved by the method for manufacturing a semiconductor device according to the present invention, which comprises steps.

[0015]

FIG. 1 is a schematic sectional view for explaining the principle of the present invention. In the figure, 1 is a substrate, the surface of which is covered with an insulating film (not shown). 2A and 2B are conductive film patterns, which are made of aluminum alloy wiring or the like arranged so as to project on the substrate. A first insulating film 3 is made of, for example, silicon nitride (Si ₃ N ₄ ). Four
A, 4B, and 4C are recesses formed between the conductive patterns. 5
Is a second insulating film and is made of, for example, a non-silicon (Si) -containing polyimide having etching selectivity with respect to the first insulating film. A third insulating film 6 is made of, for example, the first insulating film and silicon oxide (SiO ₂ ) having etching selectivity. 7A and 7B are contact holes. Further, 8 is an upper layer metal wiring, which is made of an aluminum alloy or the like.

In the present invention, the conductive film patterns 2A, 2
Recess between the first insulating film 3 covering the surface of B, etc. along the surface and the conductive film patterns 2A, 2B, etc.
4A, 4B, 4C, etc. are provided with etching selectivity with respect to the second insulating film 5 which is buried by using an etch back means so that the conductive film patterns 2A, 2B and others are completely buried. The second insulating film 5 formed by coating on the first insulating film 3 on the conductive film patterns 2A, 2B, etc. is formed by using an etchant that preferentially etches the second insulating film 5. The second insulating film 5 is embedded in the recesses 4A, 4B, 4C, etc. by performing etch back until the exposed portions appear. As described above, the first insulating film 3 and the second insulating film 5
Even if the thickness of the second insulating film 5 formed by coating on the conductive film patterns 2A, 2B, etc. varies depending on the location, it is possible to obtain At the time of completion of the etch-back, the first insulating film 3 exposed on all the conductive film patterns 2A, 2B, etc.
Is hardly etched, and remains at a substantially uniform predetermined thickness during film formation.

Therefore, in the present invention, it is not necessary to form the first insulating film 3 particularly thick in order to prevent etching damage of the conductive film patterns 2A, 2B, etc.
The thickness may be about 1000 to 2000Å.

Further, in the present invention, the second insulating film 5
The etch back of all conductive film patterns is as described above.
The first insulating film 3 on 2A, 2B, etc. is exposed until the second insulating film 5 is formed on the first insulating film 3 in that portion.
In the absence of the above, a third insulating film 6 having a constant thickness, which is the remaining portion of the interlayer insulating film for ensuring the required insulating property, is directly laminated on the first insulating film 3.

Therefore, in the present invention, the thickness of the interlayer insulating film (first insulating film 3 + third insulating film 6) is reduced by the amount that the first insulating film 3 can be formed thin. , Contact holes 7A, 7 formed in this interlayer insulating film
Since the steps such as B are also reduced, the coverage of the upper metal wiring 8 in the step portions of these contact holes is improved, and obstacles such as step breaks are prevented.

Further, in the present invention, as described above,
Conductive film pattern for forming contact holes 7A, 7B, etc.
The interlayer insulating film on 2A, 2B, etc. is composed of only the first insulating film 3 and the third insulating film 6, and does not include the second insulating film 5 using an organic insulating film such as polyimide. Therefore, when forming the contact holes 7A, 7B and the like, organic contaminants do not redeposit on the conductive film patterns 2A, 2B and the like, and the occurrence of contact failure with the upper metal wiring 8 is prevented.

Further, in the present invention, preferably, a material having etching selectivity with respect to the first insulating film 3 is used for the third insulating film 6 (Si ₃ N ₄ film is used for the first insulating film 3). And a SiO ₂ film is used for the third insulating film). Then, a substantially vertical first opening 9 penetrating the third insulating film 6 and the first insulating film 3 is formed by anisotropic etching means through the window of the mask, and the third insulating film 6 is formed. By forming the tapered second opening 10 that extends in the lateral direction in the third insulating film 6 by the isotropic etching means that preferentially etches, the edge portion of the opening 10 of the third insulating film 6 is formed. Contact holes 7A, 7B, etc., which are recessed from the edge portion of the opening 9 of the first insulating film 3 are formed to further improve the coverage of the upper wiring 8 in the contact hole step portion.

As described above, the quality of the upper layer wiring is improved and L
The reliability of SI etc. can be improved.

[0023]

EXAMPLES The present invention will be described in detail below with reference to illustrated examples. 2 is a process sectional view (1) of an embodiment of the method of the present invention, FIG. 3 is a process sectional view (2) of an embodiment of the method of the present invention, and FIG. 4 is another of the method of the present invention. It is process sectional drawing of an Example. The same object is denoted by the same reference numeral throughout the drawings.

The semiconductor device according to the present invention is formed, for example, by the manufacturing method described below. See FIG. 2 (a). That is, the surface is covered with an insulating film (not shown), and a conductive film pattern, that is, a lower layer having a thickness of, for example, about 7,000 Å to 1 μm and having different arrangement intervals or width On the substrate 11 such as a semiconductor substrate on which aluminum (Al) wirings 12A, 12B, 12C, 12D, 12E, etc. are formed, an ordinary CVD method is used, and as the first insulating film, for example, Si ₃ N having a thickness of about 2000Å _Four
A film 3 is formed and then a second planarizing second layer is formed on the substrate.
As an insulating film of, for example, non-Si having a thickness of about 1 to 1.5 μm.
The containing polyimide film 15 is spin-coated. here,
The non-Si containing polyimide is used for the polyimide.
This is because in a subsequent step, the polyimide on the lower Si-based insulating film, for example, the Si ₃ N ₄ film can be completely removed by using oxygen plasma without damaging the lower layer.

[0025] refer to FIG. 2 (b) Then, a dry etching means using dominant for example, oxygen (O ₂₎ plasma to polyimide, the polyimide film 15, all of the lower Al wirings 12A, 12B, 12C, 12D
, 12E and the like, the Si ₃ N ₄ film 3 is exposed and etched back until the polyimide film 15 on the surface thereof is completely removed, and the recesses 14A, 14B, 14C, 14D, etc. between the wirings are The polyimide film 15 that flatly fills the recesses is left. In this etch back, the Si ₃ N ₄ film 3 has a high etching resistance and is hardly etched, so that the initial thickness thereof is maintained.

Next, referring to FIG. 2C, a third insulating film having a selectivity of etching with respect to the Si ₃ N ₄ film 13 of the first insulating film, for example, a thickness, is formed on the substrate by the CVD method. A PSG film 16 of about 5000Å is formed. Here, the lower Al wirings 12A, 12B, 12C, 12D
, 12E, etc. is the same as the first insulating film of Si ₃ N.
Since it is composed of only the _4th film 13 and the PSG film 16 of the third insulating film, the thickness of that portion is as thin as that of the first insulating film as compared with the conventional one, and the thickness of the lower Al wiring is reduced. A uniform thickness is formed on each lower layer Al wiring regardless of the width and the arrangement pitch.

Next, as shown in FIG. 2D, after forming a resist mask 22 having openings 21A, 21B, 21C, 21D, 21E for contact hole etching on the above substrate, first, for example, fluorine such as CF ₄ is used. The PSG film 16 is formed through the above-mentioned etching openings 21A, 21B, 21C, 21D, 21E by an isotropic dry etching means using a system gas as a main component and an etching gas which is dominant with respect to PSG. The PSG film 16 selectively etched
Through the PSG film 16 and the opening edge is a resist mask 22.
Of the etching openings 21A, 21B, 21C, 21D, 21E and the like, and the first opening 19 receding from the edge and having a tapered side wall 19
A, 19B, 19C, 19D, 19E, etc. are formed.

Then, referring to FIG. 2 (e), the resist mask 22 is used as it is.
_{By the} anisotropic dry etching method using ₄ gases (for example, by the reactive ion etching method), the first
Openings 19A, 19B, 19C, 19D, 19E, etc. of Si ₃ N ₄ film 13 exposed at the bottom of the resist mask etching openings 21
Form second openings 20A, 20B, 20C, 20D, 20E, etc. having substantially vertical sidewalls aligned with A, 21B, 21C, 21D, 21E, etc.

Next, referring to FIG. 2F, by removing the resist mask 22,
The first openings 19A, 19B, 19C, 19D, 19 are formed on the substrate having the lower-layer Al wirings 12A, 12B, 12C, 12D, 12E, etc.
The lower Al wiring 12A, 12B has a tapered side wall composed of E, etc. and the second openings 20A, 20B, 20C, 20D, 20E, etc.
, 12C, 12D, 12E, etc. are formed, and an interlayer insulating film having contact holes 17A, 17B, 17C, 17D, 17E, etc. is formed. The interlayer insulating film is composed of the first, second and third insulating films 13, 15 and 16, and the lower layer Al wiring 12A in which the contact holes 17A, 17B, 17C, 17D and 17E are formed. , 12B, 12C, 12D, 12E and the like, the second insulating film 15 using an organic material such as polyimide does not exist above the first insulating film using an inorganic material such as Si ₃ N ₄ or PSG. Since only 13 and the third insulating film 15 exist, the contact holes 17A, 17B, 17C, 17D,
The lower wiring surface exposed in 17E etc. is not contaminated by the adhesion of organic substances.

Next, as shown in FIG. 3, an Al film (including an Al alloy) having a thickness of about 1 μm is formed on the substrate by a sputtering method or the like as usual, and patterning is performed by using an ordinary photolithography means.
For example, the contact holes 17A, 17B, 17C, 17D
, 17E, etc., lower Al wiring 12A, 12B, 12C, 12D, 12E
The upper layer Al wiring 18 connected to the above is formed, and the multilayer Al wiring structure according to the present invention is completed.

According to the method of the present invention as shown in the above embodiment, the upper interlayer insulating films such as the lower Al wirings 12A, 12B, 12C, 12D and 12E are as thick as the first insulating film can be formed. Since the thickness of the contact hole can be made thinner than before, the step difference of the side wall of the contact hole is reduced, and according to a preferable method of the present invention, since the side wall of the contact hole is formed in a tapered shape, the contact holes 17A, 17B, 17C, 17D, The coverage of the upper-layer metal wiring formed on 17E or the like, for example, the upper-layer Al wiring 18 on these contact holes is improved, and step disconnection and increase in resistance at the contact hole portion of the upper-layer metal wiring are prevented.

In another method according to the present invention,
The photosensitive polyimide is used for the second insulating film, and the step of etching back the second insulating film can be replaced by the method described below with reference to FIG.

Referring to FIG. 4A, that is, for example, by a CVD method, on a substrate 11 on the surface of which a conductive film pattern similar to the above-mentioned embodiment, that is, lower layer Al wirings 12A, 12B, 12C, 12D, 12E and the like are formed. After the Si ₃ N ₄ film 3 having a thickness of about 2000 Å is formed as the first insulating film, a second insulating film for flattening is formed on the substrate, for example, with a thickness of 1 to 1.
A photosensitive polyimide film 23 having a thickness of about 5 μm is formed by spin coating, and then the Si ₃ N ₄ film 3 on the lower Al wirings 12A, 12B, 12C, 12D, 12E, etc. is formed on the entire surface of the photosensitive polyimide film 23. UV irradiation is performed with the irradiation energy reaching up to. Reference numeral 23 'indicates an exposure area. At this time, the wiring 12
Recesses 14A, 14B, 14 between A, 12B, 12C, 12D, 12E, etc.
The polyimide film 23 in C and 14D is not exposed.

Next, as shown in FIG. 4B, development is performed using a predetermined developing solution to dissolve and remove the photosensitive area 23 'of the polyimide film 23, and the wirings 12A, 12
Recesses 14A, 14B, 14C, 14 between B, 12C, 12D, 12E, etc.
A polyimide film 23 that fills these recesses flat is left in D. At this time, the wirings 12A, 12B, 12
A polyimide film 23 is formed on the Si ₃ N ₄ film 3 on C, 12D, 12E, etc.
Do not allow to remain. Then, the polyimide film 23 is solidified by a predetermined heat treatment. After that, through the steps described in FIGS. 2C to 2F in the above-described embodiment, a multilayer wiring structure similar to that shown in FIG. 3 is formed.

The multilayer wiring provided in the semiconductor device according to the present invention is formed by the manufacturing method according to the present invention as shown in the above two embodiments, and has a structure as shown in FIG. 3, for example. Then, as described above, the lower layer (Al) of the interlayer insulating film
The upper regions of the wirings 12A, 12B, 12C, 12D, 12E, etc. have a structure in which only the inorganic first insulating film 13 and the third insulating film 16 are laminated, and a polyimide film formed by coating for planarization.
The feature is that it does not include an organic insulating film such as 14. Therefore, the surface of the lower layer (Al) wiring 12A, 12B, 12C, 12D, 12E, etc. exposed in the contact holes 17A, 17B, 17C, 17D, 17E, etc. formed on the lower layer wiring is made of an organic substance. Without being contaminated, contact failure with the upper layer wiring 18 can be prevented.

Further, the lower layer wirings 12A, 12B, 12C, 12D,
The upper interlayer insulating film such as 12E is composed of only the first insulating film 13 and the third insulating film 16 as described above, and is etched between the first insulating film 13 and the second insulating film 15. Since the thickness of the first insulating film 13 itself can be significantly reduced and made uniform by providing the selectivity of, the contact holes 17A, 17B, 17C, 17D, 17E, etc. are shallower than before. And can be formed into a uniform shape, and further, the first insulating film
By selecting 13 and the third insulating film 16 as different ones having etching selectivity, the contact hole 17
A, 17B, 17C, 17D, 17E, etc. have tapered openings 19A, 19B, 19C, 19D, 19E, etc. on the upper part thereof, so that the step disconnection of the upper layer wiring 18 in the above contact hole part is caused. Also, the increase in resistance is greatly reduced compared to the conventional one.

[0037]

As described above, according to the present invention, in a multilayer wiring structure in which an interlayer insulating film can be flattened, contact failure between wiring layers, disconnection of upper layer wiring, increase in resistance, etc. are prevented. To be done. Therefore, the present invention largely contributes to the improvement of the reliability of a semiconductor device such as an LSI that is multi-layered.

[Brief description of drawings]

FIG. 1 is a schematic sectional view for explaining the principle of the present invention.

FIG. 2 is a process sectional view (1) of an embodiment of the method of the present invention.

FIG. 3 is a process sectional view of an embodiment of the method of the present invention (No. 2)

FIG. 4 is a process sectional view of another embodiment of the method of the present invention.

FIG. 5 is a process sectional view of a conventional method.

[Explanation of symbols]

 1 Base 2A, 2B Conductive Film Pattern 3 First Insulating Film 4A, 4B, 4C Recess 5 Second Insulating Film 6 Third Insulating Film 7A, 7B Contact Hole 8 Upper Layer Metal Wiring 9 First Insulating Film Opening 10 Opening of third insulating film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 21/90 A

Claims (7)

[Claims] 1. A plurality of protruding conductive film patterns (2A, 2)
A first insulating film (3) covering the surface of the substrate (1) and the surface of the conductive film pattern (2A, 2B) on the substrate (1) having B), and the conductive film. Pattern (2A, 2B)
The recesses between the first insulating film (3A) on the conductive film pattern (2A, 2B) are exposed so that the surface of the first insulating film (3) is exposed.
A second insulating film (5) different from the first insulating film (3),
The insulating film (3), the first insulating film (3) collectively covering the second insulating film (5), and the third insulating film (6) which is different from the first insulating film (3), and the conductive film On the upper part of the pattern (2A, 2B), the third
Of the first insulating film (3) and the opening (9) of the third insulating film (6) are penetrated through the insulating film (6) and the first insulating film (3). ) A semiconductor device having contact holes (7A, 7B) recessed from an edge portion. 2. A silicon oxide film, a silicon nitride film or a phosphosilicate glass film is used for the first insulating film (3), and a polyimide is used for the second insulating film (5). A silicon oxide film, a silicon nitride film, a phosphosilicate glass film which is different from the first insulating film, or a polyimide film is used for the third insulating film (6). Item 1. The semiconductor device according to item 1. 3. A step of forming a first insulating film on a substrate having a plurality of protruding conductive film patterns, the first insulating film covering the substrate along the exposed surface of the substrate and the surface of the conductive film pattern. Forming a second insulating film, which has etching selectivity with respect to the first insulating film, on the substrate covered with the first insulating film to a thickness such that the surface is substantially flattened; The second insulating film is etched back until the first insulating film on the conductive film pattern is exposed by using an etching means which is superior to the first insulating film with respect to the second insulating film. Accordingly, the step of flatly filling the recesses between the conductive film patterns with the second insulating film, the step of filling the recesses between the conductive film patterns with the second insulating film and the first insulating film on the conductive film patterns. Forming a third insulating film so as to collectively cover the exposed surface, and A method of manufacturing a semiconductor device, characterized in that it comprises a step of forming a contact hole to expose the conductive film pattern through the insulating film and the first insulating film of the third, the. 4. The silicon oxide film is formed on the first insulating film,
7. A silicon nitride film or a phosphosilicate glass film is used, and a silicon oxide film, a silicon nitride film, a phosphosilicate glass film, or a polyimide film is used as the third insulating film. 3. The method for manufacturing a semiconductor device according to 3. 5. The method for manufacturing a semiconductor device according to claim 3, wherein non-silicon-containing polyimide is used for the second insulating film. 6. A photosensitive polyimide film is used for the second insulating film, and the step of the etching back exposes the photosensitive polyimide film to the surface of the first insulating film on the conductive film pattern. 5. The method for manufacturing a semiconductor device according to claim 3, further comprising the step of selectively developing and removing the exposed region of the photosensitive polyimide film after performing the above step. 7. When forming the contact hole,
The first insulating film and the third insulating film having etching selectivity are used, and the opening edge portion of the third insulating film in the contact hole is set back from the opening edge portion of the first insulating film. 7. The method for manufacturing a semiconductor device according to claim 3, 4 or 5 or 6, further comprising a selective etching step.