JPH08316309A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: To provide a method for manufacturing a semiconductor device which forms a fine and reliable multilayer wiring structure. CONSTITUTION: After an interlayer insulation film 3 and the first resist pattern 4 having a hole 4a of specified width t are formed in this order on a conductor layer 2, etching is performed for forming a groove 5 for an upper wiring in the interlayer insulation film 3. Then, after the second resist pattern 7 provided with a through hole 7a having an opening whose inner dimension w is larger than the width t of the hole 4a is formed on the first resist pattern 4, etching is performed for forming a contact hole 8 in the interlayer insulation film 3 just under the groove 5, and further the first resist pattern 4 and the second resist pattern 7 are removed. Then, after a film consisting of a conductive material is so formed on the interlayer insulation film 3 as to fill up the groove 5 and the contact hole 8, the film consisting of the conductive material is removed up to where the top face of the interlayer insulation film 3 is exposed, for forming the upper wiring and the contact part, thus a multilayer wiring structure is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a multilayer wiring structure.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor device of this type, an upper layer wiring is formed above a conductor layer made of a silicon (Si) substrate or a lower layer wiring, and a conductive layer is formed between the conductor layer and the upper layer wiring. There is known a structure in which a columnar contact portion having properties is interposed.

In manufacturing such a semiconductor device, first, in order to form the above-mentioned multilayer wiring structure, first, referring to FIG.
As shown in (a), CVD (Chemical Vapor Deposit)
ion) to deposit silicon oxide (Si
An O ₂ ) -based interlayer insulating film 52 is deposited, and subsequently, a resist pattern 53 for forming a contact hole 54, which will be described later, is formed on this layer. Next, by using the resist pattern 53 as a mask, a contact hole 54 reaching the conductor layer 51 is formed in the interlayer insulating film 52 as shown in FIG. 4B, and then the resist pattern 53 is removed. As the etching for forming the contact hole 54, RIE (Reactive Ion Etcing), plasma etching, wet etching, or the like is used.

Next, the inside of the contact hole 54 is filled with aluminum (Al), tungsten (W), polysilicon (Poly).
By embedding with a conductive material such as —Si), a so-called plug portion is formed. For example, when a blanket-W plug forming method is used as a method for forming such a contact portion, first, as shown in FIG. Insulating film 52
A film 55 made of W is formed on top. A barrier metal layer may be formed on the interlayer insulating film 52 before forming the W film 55.

Then, the entire W film 55 is etched back by RIE to a position where the upper surface of the interlayer insulating film 52 is exposed, whereby W is buried in the contact hole 54 as shown in FIG. 4D. Conductor layer 51
In succession, a contact portion 56 made of a W-plug that is directly connected to this is formed. Next, as shown in FIG. 4E, the interlayer insulating film 5 is formed by sputtering or CVD.
A barrier metal layer 57 and a conductive material film 58 of Al or the like are sequentially formed on the upper surface of 2 so as to cover the upper surface of the contact portion 56, and then an upper layer wiring described later on the conductive material film 58 and so as to cover the contact portion 56. A resist pattern 59 for forming 60 is formed. Note that FIG. 4E shows a side cross section of the resist pattern 59 when the upper layer wiring 60 extending in a direction substantially perpendicular to the paper surface is formed.

Then, the conductive material film 58 and the barrier metal layer 5 are formed by RIE using the resist pattern 59 as a mask.
By patterning 7 and then removing the resist pattern 59, as shown in FIG. 4 (f), the contact portion 56 is continuously connected directly to it and extends in a direction substantially perpendicular to the paper surface. Then, the upper wiring 60 is formed to obtain a multilayer wiring structure. By the way, in the recent semiconductor device manufacturing field, in order to promote the miniaturization of the multilayer wiring structure, the width of the upper layer wiring 60 tends to be a layout substantially equal to the diameter of the contact portion 56, and this tendency will continue in the future. It is believed to progress.

[0007]

However, in the conventional method of manufacturing a semiconductor device, when the width of the upper layer wiring 60 is made to be substantially equal to the diameter of the contact portion 56 in the formation of the above-described multilayer wiring structure, the following will occur. Such problems arise.

As shown in FIG. 5A, the conductive material film 58 is formed.
When the resist pattern 59 for forming the upper layer wiring is formed on the upper surface, if the resist pattern 59 is aligned with the contact portion 56 in a shifted state, a portion of the contact portion 56 that is not covered with the resist pattern 59 will occur. Then, as shown in FIG. 5B, the interlayer insulating film 52 on the side surface side of the contact portion 56 not covered with the resist pattern 59.
However, the so-called slit 61 is generated in this portion because it is cut by RIE in the next step. Or Figure 5
As shown in (c), the contact portion 56 not covered with the resist pattern 59 is etched by the above-described RIE overetching, and a concave slit 62 is formed in the contact hole 54.

When the slits 61 and 62 are formed, the surface shape of the interlayer insulating film 52 is deteriorated. Therefore, when the interlayer insulating film is further formed on the upper wiring 60, the slit 6 is formed.
The insulating material is not completely embedded in the layers 1 and 62, and as a result, voids remain in the interlayer insulating film and the withstand voltage of that portion deteriorates. Further, when the upper wiring 60 is formed to be displaced from the contact portion 56 as described above,
Since the contact area between the contact portion 56 and the upper wiring 60 is reduced, the contact resistance is increased or the contact portion 5
The current concentrates on the connecting portion between the upper layer wiring 60 and the upper layer wiring 60, and the electrical reliability of the multilayer wiring structure deteriorates.

The present invention has been made to solve the above-mentioned problems, and the width of the upper layer wiring and the diameter of the contact portion can be formed to be substantially equal to each other without causing the occurrence of slits or the increase of contact resistance. Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming a fine multi-layer wiring structure having high electrical reliability.

[0011]

In the method of manufacturing a semiconductor device of the present invention, an interlayer insulating film is first formed on a conductor layer, and then a groove for an upper wiring is formed in the interlayer insulating film. Then, a contact hole reaching the conductor layer is formed in the interlayer insulating film immediately below the groove, and a film made of a conductive material is formed on the interlayer insulating film in a state of filling the groove and the contact hole. Subsequently, the film made of a conductive material is removed to a position where the upper surface of the interlayer insulating film is exposed, and the upper wiring formed by filling the conductive material in the groove and the conductive layer formed by filling the conductive material in the contact hole. And a contact portion continuous with the upper wiring, respectively, are formed to obtain a multilayer wiring structure.

In the step of forming the groove, a first resist pattern having a groove-shaped hole having a predetermined width is formed on the interlayer insulating film formed on the conductor layer, and then the first resist pattern is formed. The groove may be formed by etching using a mask, and in the step of forming the contact hole, a second resist pattern having a through hole having an inner size opening larger than the width of the hole is formed on the hole. Formed on the first resist pattern so that the through holes are located,
After that, the contact hole may be formed by etching using the first resist pattern and the second resist pattern as a mask, and then the first resist pattern and the second resist pattern may be removed.

[0013]

According to the method of manufacturing a semiconductor device of the present invention, since the contact hole is formed in the interlayer insulating film immediately below the groove,
A contact hole communicating with the groove is formed. Since the upper layer wiring and the contact portion are formed by embedding the same conductive material in the groove and the contact hole, the contact resistance at the connection portion between the upper layer wiring and the contact portion is improved. Further, since the upper layer wiring is formed by forming the conductive material in the groove of the interlayer insulating film on the interlayer insulating film and removing the conductive material film until the upper surface of the interlayer insulating film is exposed, the upper layer wiring is formed. The wiring is a groove-embedded wiring.

When a groove is formed using the first resist pattern having holes and a contact hole is formed using the second resist pattern having through holes,
Since the inner size of the opening of the through hole is larger than the width of the hole, the first resist pattern serves as a substantial mask during etching for forming the contact hole. Therefore, the contact hole is formed in an inner dimension substantially equal to the width of the hole, that is, the width of the groove, and is formed in a position directly below the upper layer wiring in a self-aligning manner. In addition, since the inner size of the opening of the through hole of the second resist pattern is larger than the width of the hole,
It becomes easy to secure an exposure margin such as DOF (depth of focus) in lithography for forming a resist pattern. Therefore, the margin for the misalignment between the first resist pattern and the second resist pattern is expanded, and the margin for the misalignment between the contact portion and the upper layer wiring is expanded, so that the misalignment between the contact portion and the upper layer wiring occurs. Is reduced.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings. FIG. 1 (a)-
(C), FIG. 2 (d) to (f), FIG. 3 (e), and (f) are diagrams for explaining one embodiment of the present invention in the order of steps, and in particular, the multilayer wiring which is a feature of the present invention. It is a figure which shows the formation process of a structure. Further, in FIGS. 1 to 3, (A) shows a portion where the upper layer wiring and the contact portion are formed, and (B) shows a portion where only the upper layer wiring is formed.

In this embodiment, in order to form the multilayer wiring structure 1, first, the steps shown in FIGS. 1A to 1C are performed in the same manner at the points (a) and (b). That is, as shown in FIG. 1A, a first interlayer insulating film 3a, a second interlayer insulating film 3b, and a third interlayer insulating film 3 are formed on a conductor layer 2 made of a Si substrate or a lower layer wiring by CVD.
c and are sequentially laminated to form the interlayer insulating film 3. At this time, in the anisotropic etching for forming the groove 5 later, the second interlayer insulating film 3b is made of an insulating material whose etching rate is smaller than that of the third interlayer insulating film 3c. The interlayer insulating film 3b is formed.

Here, the first interlayer insulating film 3a and the third interlayer insulating film 3a
The interlayer insulating film 3c is made of SiO ₂ and the second interlayer insulating film 3b is made of silicon nitride (SiN). Further, the first interlayer insulating film 3a is formed into a film having a thickness of about 0.05 μm to 1 μm.
The interlayer insulating film 3b is formed with a film thickness of about 0.01 μm to 0.5 μm, and the third interlayer insulating film 3c is formed with a film thickness of about 0.03 μm to 1 μm.

Next, a first resist film (not shown) is formed on the interlayer insulating film 3 by using a negative resist which is hardened when irradiated with light and becomes insoluble in a developing solution. After that, the first resist film is patterned by lithography into a shape in which the pattern of the upper layer wiring 10, which will be described later, is inverted, that is, the portion other than the pattern of the upper layer wiring 10 is insolubilized in the developing solution, and the width of the upper layer wiring 10 is approximately the same. Equal width t,
In this embodiment, the first resist pattern 4 having the groove-shaped hole 4a having a width t of about 0.1 μm to 5 μm is formed.

Next, as shown in FIG. 1B, a groove 5 for the upper wiring 10 is formed in the interlayer insulating film 3 by anisotropic etching such as RIE using the first resist pattern 4 as a mask. By the anisotropic etching, the width s of the groove 5 is formed to be about 0.1 μm to 5 μm, which is approximately equal to the width t of the hole 4a. Further, as described above, the second interlayer insulating film 3b is
Since the etching rate in this anisotropic etching is smaller than that of the third interlayer insulating film 3c, the second interlayer insulating film 3b becomes an etching stopper layer in this step. Therefore, most of the third interlayer insulating film 3c is used here.
Only this is etched to form a groove 5 having a depth from the upper surface of the third interlayer insulating film 3c to the upper surface of the second interlayer insulating film 3b.

Next, as shown in FIG. 1C, a second resist film 6 for forming a second resist pattern 7, which will be described later, is formed on the first resist pattern 4 by coating. At this time, the resist material forming the second resist film 6 is also embedded in the groove 5 and the hole 4a. The second resist film 6 formed here and the first resist pattern 4 maintain their shapes without being affected by the first resist pattern 4 when the second resist film 6 is patterned in the next step. It is necessary for the relationship to satisfy the condition. In this embodiment, the second resist film 6 is formed on the first resist pattern 4 made of a negative resist so as to satisfy the above conditions.
Is formed by using a positive resist whose solubility in a developing solution becomes high when irradiated with light.

Next, the second resist film 6 is patterned by lithography to form a second resist pattern 7 having a through hole 7a as shown in FIG. 2 (d). Here, the portion where the through hole 7a is formed is located on the hole 4a of the first resist pattern 4 at the position (a). The through hole 7a is formed to have an opening shape of, for example, a substantially circular shape or a quadrangular shape, and the inner dimension (inner diameter) w of the opening is set to be larger than the width t of the hole 4a. In this embodiment, the width t of the hole 4a is about 0.1 μm to 5 μm.
In contrast, the inner diameter w of the through hole 7a is 0.15 μm to 8 μm
It is formed within a certain range and larger than the width t of the hole 4a.

As described above, the second resist film 6 is made of a positive type resist, and in the lithography, only the portion where the through hole 7a is formed is exposed to increase the solubility in the developing solution. Therefore, in the development step in lithography, the second resist film 6 in the portion where the through hole 7a is formed and the resist material of the second resist film 6 embedded in the groove 5 and the hole 4a are dissolved in the developing solution. To be removed. Further, since the first resist pattern 4 is formed of a negative resist and is already hardened by the above-mentioned lithography, it is not affected by the above-mentioned lithography, and therefore, the shape of the first resist pattern 4 is passed through this step. Is maintained.

Then, as shown in FIG. 2E, anisotropic etching such as RIE is performed using the second resist pattern 7 and the first resist pattern 4 as a mask to form the groove 5 at the location (a). The groove 5 in the interlayer insulating film 3 immediately below the first interlayer insulating film 3a, that is, in the second interlayer insulating film 3b and the first interlayer insulating film 3a.
Contact hole 8 communicating with and reaching the conductor layer 2
To form. The anisotropic etching may be performed in two steps, such as etching the first interlayer insulating film 3a after etching the second interlayer insulating film 3b.

In this step, the hole 4a of the first resist pattern 4 is formed immediately below the through hole 7a of the second resist pattern 7.
Is located and the width t of the hole 4a is smaller than the inner dimension w of the through hole 7a, so that the first resist pattern 4 substantially serves as a mask in this step. Therefore, the inner dimension r of the formed contact hole 8 is approximately equal to the width t of the hole 4a, that is, approximately equal to the width s of the groove 5 of 0.1 μm to
It is formed to about 5 μm. Further, since the first resist pattern 4 which serves as a mask in this step is for forming the upper layer wiring 10 as described above, the contact hole 8
Will be formed in a position directly below the upper layer wiring 10 in a self-aligning manner.

Next, as shown in FIG. 2F, all the first resist pattern 4 and the second resist pattern 7 on the interlayer insulating film 3 are peeled off. Therefore, (a), (b)
The first resist pattern 4 and the second resist pattern 7 are removed at any of the positions.

Then, the steps shown in FIGS. 3 (g) and 3 (h) are carried out in the same manner for the portions (a) and (b). That is, by sputtering or CVD, a film (hereinafter referred to as a conductive material film) 9 made of a conductive material such as Al or W is formed on the upper surface of the interlayer insulating film 3 by 0.03 μm as shown in FIG.
It is formed to a thickness of m to 1 μm. At this time, in the portion (a), the inside of the groove 5 and the inside of the contact hole 8 communicating therewith are filled with the above conductive material, and in the portion (b), the inside of the groove 5 is filled with the above conductive material. .

Then, as shown in FIG. 3 (h), CMP
The conductive material film 9 is removed to a position where the interlayer insulating film 3 is exposed by (Chemical Mechanical Polishing) or anisotropic etching such as RIE. Because of this, (a)
At the location of, the upper layer wiring 10 in which the conductive material is embedded in the groove 5 is formed, and the contact hole 8 is formed.
Contact portions 11 each having a conductive material embedded therein and connected directly to the conductor layer 2 and the upper wiring 10 are formed. In addition, at the position of (b), the upper wiring 10 in which the conductive material is embedded in the groove 5 is formed. Through the above steps, the multilayer wiring structure 1 is obtained.

In the method of manufacturing a semiconductor device having the above-described multilayer wiring structure 1, the first resist pattern 4 serves as a substantial mask during anisotropic etching for forming the contact hole 8, so that the contact hole 8 is formed. Inner dimension r
Can be formed substantially equal to the width t of the hole 4a, that is, the width s of the groove 5. Therefore, the outer size (diameter) of the contact portion 11 in which the conductive material is embedded in the contact hole 8
Since it is possible to form the width of the upper layer wiring 10 in which the conductive material is buried in the groove 5 to be substantially equal to each other, the multilayer wiring structure 1
Can be promoted to be finer.

In the anisotropic etching for forming the contact hole 8, the first mask which substantially serves as a mask
Since the resist pattern 4 is for forming the upper layer wiring 10, the contact hole 8 can be formed in a position directly below the upper layer wiring 10 in a self-aligning manner, so that the first resist pattern 4 and the second resist pattern 7 are aligned with each other. The margin for misalignment can be expanded, and as a result, the margin for misalignment between the contact portion 11 and the upper layer wiring 10 can be expanded. Further, in order to make the inner dimension w of the opening of the through hole 7a of the second resist pattern 7 larger than the width t of the hole 4a, exposure such as DOF (depth of focus) in lithography for forming the second resist pattern 7 is performed. A margin can be easily secured.

Therefore, it is possible to prevent the occurrence of slits or the like due to the misalignment between the contact portion and the resist pattern for the upper layer wiring as in the conventional case. Further, since it is possible to prevent the contact area from decreasing due to the misalignment between the contact portion 11 and the upper wiring 10, it is possible to prevent the contact resistance from increasing and the current concentration at the connection portion between the contact portion 11 and the upper wiring 10 to be prevented. can do.
In addition, by filling the groove 5 and the contact hole 8 with the same conductive material, the upper wiring 10 and the contact portion 11 are formed.
And the contact resistance can be improved.

In the upper layer wiring 10 formed in the above embodiment, a conductive material is embedded in the groove 5 of the interlayer insulating film 3,
In addition, since it is a so-called trench-embedded wiring formed by removing the conductive material film 9 until the upper surface of the interlayer insulating film 3 is exposed, it is possible to obtain the multilayer wiring structure 1 having very good flatness.

In the above embodiment, the first interlayer insulating film 3a is used.
Since the second interlayer insulating film 3b, which serves as an etching stopper layer when the groove 5 is formed, is formed between the third interlayer insulating film 3c and the third interlayer insulating film 3c to form the interlayer insulating film in the present invention, any contact It is possible to easily form the groove 5 having a desired depth even at the portion forming portion. Therefore, according to the present embodiment, it is possible to obtain the multilayer wiring structure 1 which is fine and has high electrical reliability.

Although the first resist pattern 4 is formed of a negative resist and the second resist pattern 7 is formed of a positive resist in this embodiment,
The patterning of the second resist film 6 is not limited to the above combination as long as the condition that the first resist pattern 4 is not affected and the shape thereof is maintained is satisfied.

For example, in addition to the above combinations, the following combinations are possible. (1) As resist materials for forming a first resist film that is a precursor of the first resist pattern 4 and a second resist film 6 that is a precursor of the second resist pattern 7, those having different wavelengths of light to be exposed are used. To use. For example, the first resist film is formed of a resist material that is exposed to i-line, and the second resist film 6 is formed of a resist material that is exposed to an excimer laser. (2) The first resist film is formed of a resist material having a very low developing speed with respect to a certain developing solution, and the second resist film 6 is formed of a resist material having a high developing speed with respect to the same developing solution. (3) The first resist film and the second resist film 6 are formed of the same resist material, but only the first resist pattern 4 obtained by patterning the first resist film is further baked after the patterning, or Irradiate with UV light to cure.

In the case of (1), during lithography for forming the second resist pattern 7, even if exposure is performed using, for example, an excimer laser, the first resist pattern 4 is not exposed, so the first resist pattern 4 is not exposed. The second resist pattern 7 can be formed while maintaining the shape of the pattern 4. In the case of (2), during lithography for forming the second resist pattern 7, the second resist film 6 is rapidly developed until the first resist pattern 4 is dissolved in the developing solution and its shape is changed. Because it will be
It is possible to avoid the influence of the lithography on the first resist pattern 4. In the case of (3), since the first resist pattern 4 is further hardened, it is possible to prevent the first resist pattern 4 from being affected by the lithography for forming the second resist pattern 7. it can.

In this embodiment, the case where the conductive material film 9 is directly formed on the interlayer insulating film 3 has been described. However, before forming the conductive material film 9, titanium (T
i), a step of depositing a barrier metal layer such as titanium nitride (TiN) may be performed. Further, in this embodiment, the first
The second interlayer insulating film 3b is formed of an insulating material having a different etching rate in the anisotropic etching for forming the groove 5 from the interlayer insulating film 3a and the third interlayer insulating film 3c. Forming an interlayer insulating film in the present invention,
It is also possible to control the depth of the groove in the present invention by controlling the anisotropic etching time and the like.

[0037]

As described above, in the method of manufacturing a semiconductor device of the present invention, since the same conductive material is embedded in the groove and the contact hole communicating with the groove, the upper wiring and the contact portion are formed. The contact resistance between the upper layer wiring and the contact portion can be improved. Further, since the upper layer wiring is formed by removing the conductive material film formed so as to fill the groove with the conductive material until the upper surface of the interlayer insulating film is exposed, the upper layer wiring can be formed as the groove-embedded wiring. It is possible to obtain a multilayer wiring structure having good flatness.

Further, when the groove is formed using the first resist pattern having the groove-shaped hole and the contact hole is formed using the second resist pattern having the through hole, etching for forming the contact hole is performed. At the time of
Since the first resist pattern serves as a substantial mask, the contact hole can be formed to have an inner dimension that is substantially equal to the width of the hole, that is, the width of the groove, and the outer dimension (diameter) of the contact portion and the width of the upper layer wiring can be substantially equal. The contact holes can be formed equally, and the contact holes can be formed directly below the upper layer wiring in a self-aligned manner. Further, if the inner size of the opening of the through hole of the second resist pattern is larger than the width of the hole, the second
Since it is possible to easily secure an exposure margin when forming a resist pattern, it is possible to reduce the occurrence of misalignment between the contact portion and the upper layer wiring and prevent the reduction of the contact area between the contact portion and the upper layer wiring. it can. Therefore, according to the present invention, it is possible to prevent the occurrence of slits and the like due to the misalignment of the contact portion and the resist pattern for the upper layer wiring and the increase in the contact resistance due to the decrease in the contact area, etc. It is possible to manufacture a semiconductor device having a multilayer wiring structure with high reliability.

[Brief description of drawings]

1A to 1C are side cross-sectional views (No. 1) of a main part for explaining a first embodiment of a method for manufacturing a semiconductor device of the present invention in the order of steps, and (A) is an upper wiring. And a contact portion, and (B) shows a portion where only the upper layer wiring is formed.

2 (d) to 2 (f) are side cross-sectional views (No. 2) of the main part for explaining the first embodiment of the method for manufacturing a semiconductor device of the present invention in the order of steps, and FIG. And a contact portion, and (B) shows a portion where only the upper layer wiring is formed.

3 (g) and 3 (h) are side cross-sectional views (No. 3) of the main part for explaining the first embodiment of the method for manufacturing a semiconductor device of the present invention in the order of steps, and FIG. And a contact portion, and (B) shows a portion where only the upper layer wiring is formed.

4A to 4F are side cross-sectional views of a main part for explaining a conventional method of manufacturing a semiconductor device in the order of steps.

5 (a) to 5 (c) are side cross-sectional views of main parts for explaining the problem of the present invention.

[Explanation of symbols]

 1 Multilayer Wiring Structure 2 Conductor Layer 3 Interlayer Insulation Film 4 First Resist Pattern 4a Hole 5 Groove 7 Second Resist Pattern 7a Through Hole 8 Contact Hole 9 Conductive Material Film 10 Upper Layer Wiring 11 Contact Part

Claims (2)

[Claims] 1. An upper wiring is formed above a conductor layer,
A method of manufacturing a semiconductor device having a multi-layer wiring structure in which a conductive columnar contact portion is interposed between the upper layer wiring and the conductor layer, wherein an interlayer insulating film is formed on the conductor layer. And then forming a groove for the upper layer wiring in the interlayer insulating film, and a second step of forming a contact hole reaching the conductor layer in the interlayer insulating film immediately below the groove. Forming a film made of a conductive material on the interlayer insulating film in a state of filling the groove and the contact hole
And a step of removing the film made of the conductive material to a position where the upper surface of the interlayer insulating film is exposed, and filling the conductive film in the trench and the upper layer wiring formed by filling the conductive material in the trench. And a fourth step of forming the contact portion that is continuous with the conductor layer and the upper wiring, respectively, and obtains the multi-layer wiring structure. 2. The first step is a step of forming a first resist pattern having a groove-shaped hole having a predetermined width on an interlayer insulating film formed on the conductor layer, and then the first step. And a step of forming the groove by etching using a resist pattern as a mask, wherein the second step includes forming a second resist pattern having a through hole having an inner size opening larger than the width of the hole, A step of forming the contact hole on the first resist pattern so that the through hole is positioned above, and a step of forming the contact hole by etching using the first resist pattern and the second resist pattern as a mask after that; The manufacturing of a semiconductor device according to claim 1, comprising a step of removing the first resist pattern and the second resist pattern after the etching. Method.