KR20010003687A - Improved dual damascene process in semiconductor device - Google Patents

Abstract

PURPOSE: A method of improving a dual damascene process is to decrease the degree of difficulty for a lithography process and an etching process, thereby obtaining an increased yield rate in the process and stabilizing the characteristic of a semiconductor element. CONSTITUTION: A method of improving a dual damascene process comprises the steps of: forming the first conductive film(2), the first and the second interlayer insulation film(3,5), the first and the second anti-etching film on a substrate(1); forming the first mask pattern on the second anti-etching film; etching the second anti-etching film, and removing the first mask pattern; forming the second mask pattern on the resultant created by the etching and removing process; etching the second interlayer insulation film exposed by the process for forming the second mask pattern; etching an exposed anti-etching film; etching the interlayer insulation films which is exposed by etching the exposed anti-etching films; and embedding the second conductive film in a hole created by the etching the interlayer insulation films.

Description

Improved dual damascene process in semiconductor device

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an improved dual damascene process.

As is well known, memory devices have increased density four times every three years. In recent years, the period of increase in integration density has become shorter, and correspondingly, 1Gbit requiring a design rule of 0.2 µm or less is required. Lithographic techniques for DRAM (Dynamic Random Access Memory, or DRAM) have been introduced. However, lithography technology is fundamentally limited in resolution because resolution is limited by the light source wavelength and numerical aperture of the exposure equipment. Meanwhile, advances in planarization using Chemical Mechanical Polishing (CMP), and super-resolution techniques such as phase shift mask (PSM) and deformation lighting techniques have been introduced, which significantly reduces the limitations of lithography. . However, despite these achievements, contact patterns require smaller and deeper shapes as high integration increases, resulting in a significant increase in aspect ratio, that is, the ratio of contact depth to contact width. For example, in the case of 1Gbit DRAM, the aspect ratio required for the metal contact becomes 5 or more even if the three-layer wiring technology is applied. Therefore, in order to further reduce the aspect ratio, three or more wiring processes are required, which causes many problems due to the increase in the number of processes.

Dual damascene processes are emerging as a good technology to address these challenges. On the other hand, in the metal electrode formation process, there is a need for a copper (Cu) thin film having high conductivity for high speed operation. Due to problems such as an etching process and a reaction with an insulating film, a dual damascene process is necessary. It is becoming.

However, when using the dual damascene process, there is a difficulty in the process as the metal electrode portion and the metal contact portion are defined and the insulating film etching process is sequentially performed.

FIG. 1A is a layout showing a double metal wiring formed by a dual damascene process, FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. 1A, and FIG. 1 is a diagram illustrating a structure in which a predetermined process is completed. The substrate, 2 is a first metal layer, 3 is a first interlayer insulating film, 4 is an etch stopper film, 5 is a second interlayer insulating film, and 6 is a second metal layer, respectively.

2A-2F illustrate a dual damascene process according to the prior art.

First, referring to FIG. 2A, a first metal layer 2 is formed on a substrate 1 of a structure in which a predetermined process is completed, and the first interlayer insulating film 3, the etch stop film 4, and the second interlayer are formed on the entire surface of the resultant product. The insulating film 5 is sequentially formed, and the thickness of the second interlayer insulating film 5 is determined by the thickness of the upper metal electrode.

Subsequently, referring to FIG. 2B, a first mask pattern 7 (usually a photoresist pattern) defining a metal contact region is formed on the second interlayer insulating film 5 by a lithography process, and a second interlayer insulating film is formed. (5) and the etching prevention film 25 is etched.

Next, referring to FIG. 2C, the mask pattern 7 is removed and a mask pattern 8 defining a metal electrode region is formed again by a photolithography process. At this time, since the photoresist film is formed in the metal contact region existing in the portion where the metal electrode is to be formed, an exposure and development process capable of sufficiently developing a thick photoresist film in the metal contact region is required.

Next, referring to FIG. 2D, the second interlayer insulating film 5 of the metal electrode region and the first interlayer insulating film 3 of the metal contact region are etched. At this time, etching of the first interlayer insulating film 3 other than the metal contact region is prevented by the etching preventing film 4.

Subsequently, the mask pattern 8 is removed as shown in FIG. 2E, and the second metal layer 6 is formed on the entire surface of the resultant. Referring to FIG. 2F, the metal electrode region is formed by a CMP process or an etch-back process. By leaving the second metal layer 6 only, the dual damascene process is completed.

However, in the prior art, as the metal contact region is formed first, a lithography process capable of sufficiently developing a photoresist film formed on the metal contact region is required, which requires sufficient exposure and development processes. Since energy is influenced by variables other than controlling the size of the pattern, difficulty in forming a fine pattern occurs. Moreover, when the thickness of the photoresist is reduced to form the fine pattern, the difference in the photoresist thickness in the metal contact region and the relative thickness of the photoresist in other regions becomes larger so that the difficulty of the process is further increased.

3A-3F illustrate another prior art dual damascene process.

Referring to FIG. 3A, a first metal layer 2 is formed on a substrate 1 of a structure in which a predetermined process is completed, and a first interlayer insulating film 3, an etch stop film 4, and a second interlayer insulating film are formed on the entire surface of the resultant product. 5) are sequentially formed, and the thickness of the second interlayer insulating film 5 is determined by the thickness of the upper metal electrode.

Next, referring to FIG. 3B, a mask pattern 8 defining a region where a metal electrode is to be formed is formed by a photolithography process, and the second interlayer insulating film 5 is etched.

Subsequently, as shown in FIG. 3C, the mask pattern 8 is removed and a mask pattern 9 is formed which defines a region where a metal contact is to be formed by a lithography process. At this time, a portion of the portion where the metal electrode is to be formed must be masked to enable the etching process of the metal contact.

Subsequently, the etch stop layer 4 and the first interlayer insulating layer 3 of the metal contact region are etched as shown in FIG. 3D, the mask pattern 9 is removed as shown in FIG. 3E, and the second metal layer 6 is formed on the entire surface of the resultant. To form.

Subsequently, the dual damascene process is completed by leaving the second metal layer 6 only in the metal electrode region by the polishing process or the etch back process as shown in FIG. 3F.

However, in this other conventional technique, as the metal region is formed first, a lithography process is required in which a photoresist (ie, a mask pattern) must be formed inside the metal electrode region when defining the metal contact region. At this time, the thickness of the photoresist is increased by the thickness of the metal film, which increases the difficulty of the fine pattern forming process. In addition, when the overlap between the metal contact and the metal electrode is small, there is a difficulty in that the photoresist pattern should be thinly formed next to the second interlayer insulating film 5, and at the edge of the etched second interlayer insulating film 5. The pattern defect is caused by the reflection of light.

The present invention has been made to solve the problems of the prior art, the semiconductor device manufacturing method of the improved dual damachin process that can reduce the difficulty of the lithography process and etching process to stabilize the yield and device characteristics of the process The purpose is to provide.

1A and 1B show a layout and a cross-sectional view of a metal electrode formed by a dual damascene process;

2A to 2F are cross-sectional views showing a dual damascene process according to the prior art;

3a to 3f are cross-sectional views showing another dual damascene process according to the prior art;

4A-4H are cross-sectional views of a dual damascene process in accordance with one embodiment of the present invention.

* Names of symbols for main parts of the drawings

1: Board of the structure where the predetermined process is completed

2, 6: metal layer

3, 5: interlayer insulating film

4, 10: etching prevention film

7, 8, 9: mask pattern

In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising: a first step of sequentially stacking a first insulating film, a first etching prevention film, a second interlayer insulating film, and a second etching prevention film on a first conductive film; Forming a first mask pattern defining a contact region of a wiring on the second etch stop layer; Etching the second etch stop layer and removing the first mask pattern; A fourth step of forming a second mask pattern defining a region in which wirings are to be formed on the resultant of the third step; A fifth step of etching the second etch stop layer and the first etch stop layer exposed by performing the fourth step; A sixth step of etching the exposed second interlayer insulating film and the first interlayer insulating film formed by performing the fifth step; And a seventh step of embedding the second conductive film for wiring in the hole formed by performing the sixth step.

Preferably, the first and second etch stop layer is characterized in that the nitride film or the nitride oxide film.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

In the present embodiment, the double metal wiring is described as an example, but when the metal wiring is directly formed on the silicon substrate in the absence of the lower metal layer, the present invention can be applied to contact and wiring formation of a conductive film other than the metal wiring. will be.

4A to 4H are cross-sectional views illustrating a dual damascene process according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, a first metal layer 2 is formed on a substrate 1 of a structure in which a predetermined process is completed, and the first interlayer insulating film 3, the first etch stop film 4, and the second interlayer are formed on the entire surface of the resultant product. The insulating film 5 and the second etch stop film 10 are sequentially formed. The thickness of the second interlayer insulating film 5 is determined by the thickness of the upper metal electrode. Since the interlayer insulating layers are usually applied with an oxide layer, the first and second etch stop layers may be formed of a material having an etching selectivity with respect to the oxide layer.

4B, a photoresist pattern 7 is formed on the second etch stop layer 10 as a mask pattern defining a metal contact region by a lithography process, that is, the metal contact region is opened. 2 The etching prevention film 10 is etched.

Subsequently, as shown in FIG. 4C, the photosensitive film pattern 7 is removed, another photoresist film pattern 8 defining a region where the metal electrode is to be formed is formed, and the strong photoresist pattern and the second etch stop layer are used as an etching mask. The second interlayer insulating film 5 is etched.

Next, referring to FIG. 4D, the exposed second etch stop layer 10 and the first etch stop layer 4 are etched using the photoresist pattern 8 as an etch mask.

4E, the second interlayer insulating film 5 and the first interlayer insulating film 3 are etched using the photoresist pattern 8 and the first etch stop film 4 as etch masks.

Subsequently, as shown in FIG. 4F, the photoresist pattern 8 is removed, and a second metal layer 6 is formed on the entire surface of the resultant product. As shown in FIG. The dual damascene process is completed by leaving the first metal layer 6 only in the metal electrode region by the tooth back process.

FIG. 4H shows that the second etch stop film 10 is also removed when the second metal layer 6 is subjected to chemical mechanical polishing or etch back in the state of FIG. 4F, that is, the second interlayer insulating film 5 is Show polishing or etch back until revealed.

Comparing the prior art Figs. 2A to 2F and Figs. 3A to 3F and Figs. 4A to 4H, which is a method for forming a metal electrode according to the present invention,

In the prior art shown in Fig. 2C, there is a problem that the mask pattern (photosensitive film pattern) formed in the metal contact region where the second interlayer insulating film 5 is etched must be removed by a lithography process. This brings about a process difference because the thickness of the mask formed in the metal contact region becomes thick. On the other hand, there is a case where the thickness of the mask pattern becomes thin in a region adjacent to the metal contact region, which makes it difficult to adjust the size of the metal electrode region defined in the portion where the metal contact is formed.

In addition, in the prior art illustrated in FIG. 3C, a mask pattern defining a metal contact region is formed inside the metal electrode region, and there is a problem in that a thin layer is formed along the side surface of the second interlayer insulating film 5. As the size of the device becomes smaller, the process difficulty increases further when the size of the metal electrode and the metal contact overlap with each other. On the other hand, a pattern defect may occur at the time of defining a metal contact due to reflection of light at an edge of the second interlayer insulating film 5.

On the contrary, as shown in FIGS. 4B to 4C, since the second etch stop layer 10 may be thinly formed in one embodiment of the present invention, the difficulty of the process shown in FIG. 1C may be reduced. On the other hand, the second etch barrier 10 does not necessarily mean the introduction of a new etch barrier in the process. This is because an anti-reflective film (ARC: Anti-Reflection Coating, Anti-Reflection Layer) introduced to reduce the difficulty of the lithography process as the size of the device becomes smaller can be used as the second etch stop layer. In the case where the nitric oxide film is used as the antireflection film, the etching selectivity with the oxide film generally used as the interlayer insulating film may be adjusted to be used as the etch stop layer. A conductive film may be used as the second etch stop film. This is because, after using the metal film or the like, the metal film can be removed in the polishing step of the metal film.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention reduces the difficulty of the lithography process and the etching process occurring in the dual damascene process, thereby mitigating the obstacles of increasing the integration of the device, thereby facilitating the development of highly integrated and highly integrated devices. .

In addition, as it facilitates the adoption of a metal film with excellent conductivity, it can be used as a base technology for manufacturing low-cost, high value-added semiconductor device with excellent characteristics.

Claims (7)

A first step of sequentially stacking a first insulating layer, a first etch stop layer, a second interlayer insulating layer, and a second etch stop layer on the first conductive layer; Forming a first mask pattern defining a contact region of a wiring on the second etch stop layer; Etching the second etch stop layer and removing the first mask pattern; A fourth step of forming a second mask pattern defining a region in which wirings are to be formed on the resultant of the third step; A fifth step of etching the second interlayer insulating film exposed by performing the fourth step; A sixth step of etching the second etch stop layer and the first etch stop layer exposed by performing the fifth step; A seventh step of etching the second interlayer insulating film and the first interlayer insulating film exposed by performing the sixth step; And Eighth step of embedding the second conductive film for wiring in the hole formed by the seventh step Semiconductor device manufacturing method comprising a. The method of claim 1, The first and second etch stop layer is a semiconductor device manufacturing method, characterized in that the nitride film or oxynitride film. The method of claim 1, The second etching prevention film is a semiconductor device manufacturing method, characterized in that the conductive film. The method of claim 1, The eighth step, Depositing the second conductive film on the entire surface of the resultant product of which the seventh step is completed; And chemically polishing or etching back the second conductive layer to expose the second etch stop layer. The method of claim 3, The eighth step, Depositing the second conductive film on the entire surface of the resultant product of which the seventh step is completed; And chemically polishing or etching back the second conductive film so that the second interlayer insulating film is exposed. The method of claim 1, The first and second conductive film is a semiconductor device manufacturing method, characterized in that the metal film. The method of claim 1, The first and second mask patterns are first and second photoresist patterns, respectively. A method of manufacturing a semiconductor device, characterized in that the thickness of the second photoresist pattern is reduced so as to secure the lithography process margin or simplify the process so that the second photoresist pattern is removed during the sixth to seventh steps.