JPH1187276A - Plating to substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To selectively grow a plating from the bottoms of a groove and a hole to form the groove and the hole into a groove and a hole with large aspect ratios, and to block the hole and the groove to eliminate the formation of pores in the hole and the groove by a method, wherein the plating is applied to a substrate having the groove and the hole and when a metal layer fills the groove and the hole, the bottoms of the groove and the hole air irradiated with an energy beam. SOLUTION: A plug hole and a groove for wiring use are exposed and an energy beam B, such as an ion beam, which is emitted from an ion source and a high-speed atomic beam source and is accelerated at an appropriate acceleration energy, is irradiated on the surface of a substrate W in a state such that the surface of the substrate W other than the plug hole and the groove for wiring use is covered with an SiO2 layer and an SiN layer. The beam B is chiefly irradiated on the bottoms 26a and 28a of the plug hole and the groove for wiring use and modified layers 30a, which are improved in the plating adhesion, are formed on the parts of these bottoms 26a and 28a. Moreover, the substrate with the layers 30a is dipped into a plating solution containing a copper sulphate as its main component. When the substrate is treated on a prescribed condition, a plated metal layer is filled in the plug hole and the groove for wiring use, without forming pores in the interiors of the plug hole and the groove for wiring use to form a plug 40 and a wiring circuit 42.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for plating a substrate, and more particularly to a method and apparatus for filling a wiring groove or the like formed in a semiconductor substrate with a metal such as copper (Cu).

[0002]

2. Description of the Related Art Conventionally, in order to form a wiring circuit on a semiconductor substrate, Al has been formed on the substrate surface by sputtering or the like.
Alternatively, after forming an Al alloy, unnecessary portions of the film are removed by chemical dry etching using a pattern mask such as a resist. However, as the degree of integration increases, the wiring becomes thinner, the current density increases, and thermal stress or temperature rise occurs.
The alloy 1 is diluted, and eventually there is a risk of disconnection.

Therefore, copper having lower resistance and higher reliability has been attracting attention as a wiring material. However, it is difficult to form a wiring by forming a film and then patterning and etching like a conventional Al wiring. . Therefore, a groove for wiring is formed in advance, and the inside of the groove is buried by a method such as chemical vapor deposition (CVD), sputtering or plating, and then excess copper on the surface is removed by chemical mechanical polishing (CMP). Damascene wiring for forming wiring has been attempted.

[0004] Among these, plating has attracted attention because of its features such as lower process cost, higher purity copper material, and lower temperature process with less wafer damage than other processes.

[0005]

However, copper has a property of being easily oxidized or corroded and further easily diffused into SiO ₂ , and in order to prevent such a problem, the wiring portion of the base material is made of metal nitride or the like. It is necessary to form wiring after covering with a barrier layer. However, such materials are
In general, there has been a disadvantage that the adhesion of the plating is poor and that efficient plating is difficult.

Furthermore, in the case of a dual damascene in which a wiring groove for a semiconductor device having a design rule of <0.25 μm or a plug mainly made of tungsten at present is filled with the same material as the wiring material, the aspect ratio is at most 5 or more. Also. When such grooves and plugs are buried by plating, the growth occurs uniformly even in the vicinity of the opening edges of the grooves and plugs, so that the plating metal covers these lids, and it is easy for holes to be finally formed. There was a problem.

The present invention has been made in view of the above circumstances, and provides a method of plating a substrate capable of uniformly filling a material having a low electric resistivity such as copper or a copper alloy into a fine recess such as a fine wiring groove. The purpose is to do.

[0008]

According to a first aspect of the present invention, there is provided a method of plating a substrate having a groove or a hole and plating the substrate with the metal by filling the groove or the hole. A pretreatment step of irradiating an energy beam toward the substrate to improve plating adhesion on the bottom surface.

Thus, by selectively growing the plating from the bottom surface, it is possible to prevent a situation in which the groove or hole is closed and a hole is formed due to the plating grown at the entrance of the groove or hole having a large aspect ratio. You.

According to a second aspect of the present invention, there is provided the method of plating a substrate according to the first aspect, wherein the irradiation of the energy beam is performed through a mask that selectively exposes the groove or the hole. . As a result, the plating adhesion is selectively improved to reduce the plating adhesion to unnecessary portions, and therefore, the removal process is also facilitated.

The invention according to claim 3 is the method for plating a substrate according to claim 1, wherein a barrier layer is formed in the groove or the hole. The barrier layer is formed for the purpose of preventing the plating metal from diffusing into the base material layer. For example, a metal nitride is used, but usually the plating adhesion is poor.

According to a fourth aspect of the present invention, after performing the method of plating a substrate according to any one of the first to third aspects,
A method for processing a substrate, characterized in that unnecessary portions of metal adhering to the substrate are polished and removed by a chemical mechanical polishing apparatus.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3, shows a cross section of a semiconductor substrate W formed on the multilayer is formed, as shown in FIG. 1 (a), S on the lower the SiO ₂ layer 10
Cu conductive layer (wiring) 14 via insulating layer 12 such as iN
Is formed, and two layers of S are interposed via insulating layers 16 and 20.
iO ₂ layers 18 and 22 are sequentially deposited, and an uppermost insulating layer 24 is formed. Then, a plug hole 26 and a wiring groove 28 are formed in the uppermost layer and the second SiO ₂ layer by lithography / etching technology, and a barrier layer of about 50 nm made of metal nitride or the like is formed on the inner surface thereof. 30 are formed.

A process of filling the plug hole 26 and the wiring groove 28 with Cu or a Cu alloy to form a plug and a wiring will be described below. This includes a pre-treatment step of irradiating an energy beam toward the bottom of the groove or hole to improve the plating adhesion of the bottom, a plating step of filling metal, and a polishing step of removing excess plating. Become.

First, as shown in FIG. 1B, an SiO ₂ layer 32 is formed on the substrate W by a predetermined method (sputtering or the like), thereby forming the plug hole 26 and the wiring groove 2.
8 and cover other surfaces. And
Further forming a SiN film layer 34 on the surface of the SiO ₂ layer,
A protective film 36 having a two-layer structure of SiO ₂ and SiN is formed.
Next, a resist 38 is applied on the surface of the SiN layer, and the resist 38 is patterned and used as a mask to perform dry etching. Thereby, the SiO ₂ layer 32 and the SiN layer 34 covering the plug hole 26 and the wiring groove 28 are removed, and the plug hole 26 and the wiring groove 28 are exposed again as shown in FIG. .

Here, when the unnecessary resist is removed, the plug holes 26 and the wiring grooves 28 are exposed, and the other substrate surface is covered with the SiO ₂ and SiN layers. As shown in FIG. 2A, an ion beam or a fast atom emitted from an ion source or a fast atom beam source (not shown) and accelerated with an appropriate acceleration energy (for example, 30 KV for ions). An energy beam B such as a line is irradiated. As the ion species and atomic beam species, when plating copper in a later step, metals such as copper, gold, silver, platinum and palladium are optimal, but nucleus growth on the surface can be achieved even with a rare gas such as argon or oxygen. It has been confirmed that it has a promoting effect.

The ion beam or the high-speed atomic beam is mainly applied to the plug holes 26 and the bottom surfaces 26a and 28a of the wiring grooves 28, and as shown in FIG. The modified layer 30a thus formed is formed. Since these energy beams B, particularly high-speed atomic beams, have high rectilinearity, the plug holes 26 and the side walls 26b of the wiring grooves 28,
28b, so that the bottom surfaces 26a, 2
8a selectively enhances plating adhesion.

The mechanism for improving the adhesion of plating differs depending on the type of ion or atomic beam. When metals such as copper, gold, silver, platinum and palladium are used, these metal atoms are implanted on the surface of the barrier layer 30. This is considered to act as a nucleus when plating is applied, and when a rare gas such as argon or oxygen is used, microscopic irregularities are formed on the surface of the barrier layer 30 by the physical sputtering action, This is considered to act as a nucleus during plating adhesion.

As described above, the substrate having the modified layer 30a formed on the bottom surfaces 26a and 28b of the plug holes 26 and the wiring grooves 28 is immersed in a plating solution mainly composed of copper sulfate in a plating bath. Plating is performed under temperature and other conditions. In the plating process, the barrier layer 30 covering the plug hole 26 and the wiring groove 28 originally has poor adhesion of the plating, and therefore, the plating selectively adheres to the bottom surfaces 26a and 28a having the improved adhesion. And the bottom surface 26
a, and selectively grow from the plating metal attached to 28a.

As a result, as shown in FIG. 1C, the plating metal fills the plug holes 26 and the wiring grooves 28 without forming voids (voids) inside the plugs 40 and the plugs 40.
And a wiring circuit 42 are formed. In order to promote the inflow of the plating solution into the plug holes 26 and the wiring grooves 28,
Ultrasonic vibration or flow of a plating solution may be performed. As a plating method, either an electrolytic copper plating method or an electroless copper plating method can be adopted.

Next, the substrate W after the plating step is subjected to CMP.
(Chemical mechanical polishing) Polishing is performed by an apparatus to remove the extra plating metal layer 44 and the barrier layer 30 attached to the surface as shown in FIG. 3A, and to remove SiN or the like as shown in FIG. By forming the insulating layer 46, a semiconductor substrate on which a wiring of Cu or Cu alloy is formed is manufactured.

Note that the plug hole 2
6 and the wiring groove 28 overlap each other, the groove 28
When the modified layer 30 is formed on the bottom surface 28a, plating grows from this portion and closes the plug hole 26, which may cause a void. Therefore, when these overlap, as shown in FIG.
Is formed so as to cover the bottom surface 28a of the plug hole 26, and only the bottom surface 26a of the plug hole 26 is reformed to grow the plating.

Further, the resist mask may be formed such that a protective layer covering the side wall remains so as to prevent the energy beam from being irradiated on the side wall of the groove or hole. Further, as shown in FIG. 5, these side walls are tapered surfaces 26c, 28c
It may be.

[0024]

As described above, according to the present invention,
By selectively growing plating from the bottom surface, a material having a small electric resistivity such as copper or a copper alloy can be uniformly filled in a fine depression such as a fine wiring groove. Therefore, it is possible to provide a useful technique for promoting practical use of a semiconductor integrated circuit having a high density.

[Brief description of the drawings]

FIG. 1 is an explanatory view schematically showing steps of a plating method according to an embodiment of the present invention.

FIG. 2 is an explanatory view showing a step following FIG. 1 of the plating method according to the embodiment of the present invention.

FIG. 3 is an explanatory view showing a step following FIG. 2 of the plating method according to the embodiment of the present invention;

FIG. 4 is an explanatory view showing steps of a plating method according to another embodiment of the present invention.

FIG. 5 is an explanatory view showing steps of a plating method according to still another embodiment of the present invention.

[Explanation of symbols]

 26 hole 28 groove 26a bottom surface of hole 28a bottom surface of groove 30 barrier layer 36 mask B energy beam W substrate

Claims (4)

[Claims] 1. A method of plating a substrate having a groove or a hole and plating the substrate with a metal by filling the groove or the hole, the method comprising: irradiating an energy beam toward a bottom surface of the groove or the hole; A plating method for a substrate, comprising performing a pretreatment step for improving adhesion. 2. The method for plating a substrate according to claim 1, wherein the irradiation of the energy beam is performed via a mask that selectively exposes grooves or holes. 3. The method according to claim 1, wherein a barrier layer is formed in the groove or the hole. 4. The substrate according to claim 1, wherein unnecessary portions of the metal adhered to the substrate are polished and removed by a chemical mechanical polishing apparatus after performing the method of plating a substrate according to claim 1. Processing method.