JP2628339B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to a structure of a wiring connection hole in a multilayer wiring of an integrated circuit and a method of forming the same.

[Conventional technology]

FIGS. 7A and 7B show a conventional method for forming a wiring connection hole. The flattening of the surface 3 of the interlayer insulating film 2 improves the homogeneity of the transmission characteristics of the wiring and is effective in preventing the disconnection of the wiring and the leakage current between the wirings. In general, since the flattening of the multilayer wiring is performed on an uneven base, as the flatness of the surface 3 is improved, the depths of the wiring connection holes 4 and 5 formed by etching the openings of the photoresist 11 are increased. The difference in height approaches the height of the step of the unevenness of the base. For this reason, the time required for etching when forming the wiring connection holes 4 and 5 is different, and the exposed surface 8 of the base 6 of the shallower wiring connection hole 4 is deep even after the etching of the wiring connection hole 4 is completed. It is exposed to the etching atmosphere until the formation of the wiring connection hole 5 is completed. In this case, the etching rate of the interlayer insulating film 2 is a, the etching rate of the base 6 is b, and the depths of the wiring connection holes 4 and 5 are H4 and H5, respectively. When the etching is completed, the depth h6 (see FIG. 7B) at which the base 6 is etched is at least h6 = b (H5−H4) / a.

[Problems to be solved by the invention]

Etching of the base is not only unnecessary,
It may cause wiring failure. Further, since the pattern conversion difference due to the etching tends to increase due to exposure to the etching atmosphere when the etching is completed, it is necessary to make the etching time uniform from the viewpoint of making the pattern finer.

[Means for solving the problem]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a wiring connection hole in which the etching time of wiring connection holes having different depths is made uniform in the formation of the wiring connection hole, thereby improving the connection yield of the wiring connection hole and preventing the variation in pattern conversion difference. To provide.

In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device having conductive layers having different levels on one surface of a semiconductor substrate on which an electrode wiring is to be formed. The first insulating layer is different from the first insulating layer in that the etching rate of the second insulating layer can be higher than that of the first insulating layer.
A step of flattening the surface after forming in order of the second insulating film, a step of masking with a photoresist for forming a wiring connection hole, and a step of etching the second insulating layer with an etching rate of the first insulating layer. Forming a wiring connection hole having a different depth by using reactive ion etching that is higher than an etching rate.

6 (a) to 6 (f) are principle diagrams for explaining a structure of a semiconductor device according to the present invention and a method of forming the same in order of process. The main surface 10 of the substrate 1 has a step having a height H10 (a). The wiring 6 and the wiring 7 are formed on the main surface 10 (b). After that, an interlayer insulating material 2 is formed (c). Subsequently, an interlayer insulating film 20 having a different material from that of the interlayer insulating film 2 is formed. The surface of the interlayer insulating film 20 is flattened by, for example, an etching method to obtain a surface 3 (d). Holes 12 and 13 for forming wiring connection holes are formed by the photoresist 11 (e). next,
For example, the interlayer insulating film 20 is etched at an etching rate a20 by a reactive ion etching method (RIE) using the photoresist 11 as a mask. At this time, the etching rate of the interlayer insulating film 2 is set to a2. The time T6 during which the wiring 6 is exposed to the etching atmosphere until the etching of the connection hole 5 is completed is H10 / a20. For H10, see FIG. 6 (a). The larger the a20, the smaller the T6. Also, as a20 is larger than a2, the ratio of T6 to the etching completion time of the connection hole 5 is reduced, and the wiring connection hole formation time is made uniform (f). As described above, in the semiconductor device according to the present invention, the interlayer insulating film has a two-layer structure. As the depth of the wiring connection hole increases, the interlayer connection film 20 having a higher etching rate at the position of the wiring connection hole has a lower etching rate. It has a structural characteristic that the thickness ratio with respect to the insulating film 2 is increased.

〔Example〕

FIG. 1 is a sectional view showing a first embodiment of the method for forming a wiring connection hole according to the present invention. In the figure, 1 is a substrate on which semiconductor devices are integrated, 2 is an insulating film, 20 is an insulating film of a different material from 2, 3 is the surface of the uppermost insulating film, 4 and 5 are wiring connection holes, and 6 and 7 are wirings. , 8 and 9 are exposed portions of the wirings 6 and 7, respectively, 10 is the main surface of the substrate 1, and 11 is a photoresist.

Hereinafter, a method of manufacturing the wiring connection hole shown in FIG. 1 will be described with reference to FIG.

There is a step having a height H10 on a main surface 10 of a substrate 1 on which semiconductor device devices, for example, MOS field-effect transistors, bipolar transistors, element isolation regions, and the like are integrated. A wiring made of, for example, aluminum is formed on the main surface 10 by an aluminum deposition process, a photolithography process, and an etching process. The wiring 6 represents a wiring formed on the main surface 10 by a method with a high step, and the wiring 7 represents a wiring formed on the main surface 10 with a lower step. Next, an insulating film 2 made of, for example, SiO ₂ is deposited. The deposition of SiO ₂ is possible by a gas phase reaction or by sputtering. The thickness of SiO ₂ may be any thickness as long as the above-mentioned wiring can be deposited, and may be about 100 nm for a wiring height of 1 μm. The insulating film 2 may be Si ₃ N ₄ . Subsequently, an insulating film 20 made of PSG is deposited with a thickness of about 1 μm. Subsequently, the surface 3 of the insulating film 20 which is flattened by a surface flattening method such as an etching back method is obtained. For this purpose, for example, an organic polymer material layer 12 is applied thereon, and this is heat-treated to form a wiring structure having a flat surface. Next, the surface of the wiring structure thus configured is etched by RIE under the condition that the etching rates of the insulating film 20 and the organic polymer material layer 12 are the same, and the protrusions of the insulating film 20 are organically raised. The flat surface 3 is obtained by removing the molecular material layer 12 simultaneously with the etching.

Next, a photoresist 11 having a thickness of 1.6 μm is applied by a photolithography process, and then patterned to expose the opening positions 13 and 14 of the wiring connection holes, and the surface 3 is covered with the photoresist.

Etching of wiring connection holes uses a normal RIE device,
CHF ₃ / O ₂ mixed gas as the etching gas at a flow ratio of 9/50 SCCM,
When a pressure of 50 mTorr and an RF power of 1000 W are applied, the etching rate of PSG is 130 nm / min, and the etching rate of SiO ₂ is 36 nm.
/ Min. Now, as an example, the step H10 is 0.5 μm, the depth of the wiring connection hole 4 is 0.5 μm, and the depth of the wiring connection hole 5 is 1 μm.
The thickness of the insulating film 2 is set to 0.5 μm. In this case, the wiring connection hole 4 is about 3.
Receive 8 minute overetching. This is 22% of the total etching time. On the other hand, all of
In the case of O ₂ , the wiring connection hole 4 receives similar over-etching for about 13.9 minutes, which is 50% of the total etching time. When all the interlayer insulating films are made of PSG, the over-etching time of the wiring connection hole is the same as that of this embodiment, but this is 50% of the total etching time. As described above, the interlayer insulating film has a two-layer structure, and the etching rate of the upper layer is made larger than that of the lower layer, so that the wiring structure having a step on the base main surface 10 and a flat surface 3 has a different depth. The time required for completing the etching of the wiring connection hole can be reduced. As a result, unnecessary over-etching time can be shortened, so that it is possible to prevent a wiring connection failure and an increase in pattern conversion difference due to etching of the aluminum wiring due to the over-etching.

It goes without saying that the interlayer insulating film 20 may be left entirely on the surface after etching as shown in FIG.

FIG. 2 is a sectional view showing a second embodiment of the wiring connection hole forming method according to the present invention. Wiring connection hole is impurity diffusion layer
This is the case where the wiring connection holes 4 are formed on the wirings 16 and 17, and unnecessary over-etching time of the wiring connection holes 4 can be reduced as in the case of the first embodiment.

FIG. 3 is a sectional view showing a third embodiment of the wiring connection hole forming method according to the present invention.

Hereinafter, a method for manufacturing the wiring connection hole shown in FIG. 3 will be described with reference to FIG.

Etching of the wiring connection holes is performed as the first step using a mixed gas of CHF ₃ / O ₂ as the etching gas at a flow rate of 9/50 SCCM and a pressure of 50 mTo
rr, RF power 1000W applied, PSG etching rate 130n
m / min, the etching rate of SiO ₂ is 36 nm / min. First
In the stage, the time for etching the PSG is 0.5 μm and the time for etching the SiO ₂ is 0.14 μm. Subsequently, as a second stage, a CHF ₃ / O ₂ mixed gas was used as an etching gas at a flow ratio of 75/50 SCCM and a pressure of 75
An etching rate of PSG is 50 nm / min, an etching rate of SiO ₂ is 20 nm / min, and an etching rate of the photoresist 11 is 100 nm / min. As a second step, SiO ₂ was etched at 360 nm, and the photoresist was set at 0.9 nm.
Choose the time for μm etching. At this time, the photoresist undergoes side etching of about 50% of the above etching rate, and is enlarged by about 0.5 μm on one side from the start of the etching. At the end of the etching at the second stage, the wiring connection hole 4 completes the etching, and the exposed surface 8 of the underlying wiring 6 appears.
On the other hand, the wiring connection hole 5 has an etching portion of 0.14 μm in the interlayer insulating film 2. Subsequently, as the third step, the same etching conditions as those in the first step are selected, and SiO ₂ is etched by 0.14 μm to expose the exposed surface 9 of the underlying wiring 7, thereby completing the etching of the wiring connection hole 5. In the second stage, as the exposed portions 13 and 14 of the photoresist 11 are enlarged, the side walls of the wiring connection holes are inclined, and the hole diameter is larger toward the upper portion of the opening, and is larger in the exposed portions 8 and 9 of the underlying wiring. Is maintained.
As an effect, the wiring can easily enter the wiring connection hole and the turning of the wiring is improved, so that the connection yield in the wiring connection hole is improved. As another effect, since the exposed diameter of the underlying wiring does not increase, there is no need to increase the alignment margin between the wiring connection hole and the underlying wiring, which is advantageous for miniaturization of the wiring pitch.

When all the interlayer insulating films are made of SiO _{2 and} the tapered shape of the wiring connection hole is obtained by the same method as in the second stage of the third embodiment, the exposed portion 8 of the underlying wiring of the wiring connection hole 4 having a smaller depth is used. In order to keep the initial hole diameter, the timetable applicable to the second step in the wiring connection hole etching process is limited, so that the shape of the wiring connection hole is such that the inclination of the side wall is lower than 0.5 μm above the wiring connection hole 5. I can't. Therefore, the effect of the improvement of the wiring around becomes less effective as the hole diameter becomes finer and the step of the base becomes larger. It is also apparent that the over-etching time of the wiring connection hole is longer than that of the second embodiment.

When the tapered shape of the wiring connection hole is obtained by the same method as in the second stage of the third embodiment, all the PSGs are used as the interlayer insulating film, in order to prevent the hole diameter at the exposed portion 8 from being enlarged, As a shape, there is a practical problem that not only a taper cannot be formed in the lower portion 0.5 μm of the wiring connection hole 5 but also a stable etching condition for increasing the etching rate ratio between the photoresist and the PSG is difficult to find. In the case of the second stage of the third embodiment, since the enlargement of the photoresist becomes 0.2 μm on one side, it is hardly expected to improve the wiring layout.

As described above, according to the present invention, the etching times of the wiring connection holes having different depths can be made uniform. Further, the position of the taper of the side wall of the wiring connection hole can be set freely without changing the wiring pitch.

〔The invention's effect〕

As described above, in the present invention, the over-etching time of the wiring connection hole can be reduced. As an effect, the amount of etching of the wiring connection hole base due to over-etching is reduced, so that the wiring connection yield is improved. Further, as an effect, the enlargement of the wiring connection hole due to the side etching accompanying the over-etching is reduced, so that the controllability of the pattern conversion difference at the time of wiring connection hole etching is improved. This is advantageous for miniaturization of the wiring pitch. According to the present invention, the inclination of the side wall of the wiring connection hole can be controlled. Further, in the present invention, the position at which the wiring connection hole is enlarged can be set freely while maintaining the lowermost hole diameter of the wiring connection hole at the initial hole diameter. The effect is that the steepness of the step in the wiring connection hole is reduced without reducing the alignment margin of the wiring connection hole, and the result is that wiring coverage is improved up to the fine wiring connection hole. In addition, an improvement in the wiring connection yield can be realized.

[Brief description of the drawings]

FIGS. 1, 2, and 3 are cross-sectional views showing one embodiment of a semiconductor device according to the present invention, and FIGS. 4 (a) to 4 (h).
5A to 5D are cross-sectional views showing one embodiment of the method for manufacturing the semiconductor device shown in FIG. 1 in the order of steps, and FIGS. 5A to 5D are one embodiment of the method for manufacturing the semiconductor device shown in FIG. 6 (a) to 6 (f) are cross-sectional views showing the configuration principle of the semiconductor device according to the present invention in the order of steps, and FIGS. 7 (A) to 7 (f).
FIG. 2B is a cross-sectional view showing an example of a conventional method for manufacturing a semiconductor device in the order of steps. DESCRIPTION OF SYMBOLS 1 ... The board | substrate which integrates a semiconductor device 2 ... Insulating film 3 ... Surface of the uppermost insulating film 4,5 ... Wiring connection hole 6,7 ... Wiring 8,9 ... Exposure of wiring 6,7 Part 10: Main surface of substrate 1 11: Photoresist 12: Organic polymer material layer 13, 14: Openings of wiring connection holes 4, 5 of photoresist 11 16, 17: Impurity diffusion layer 20: Insulation Insulation film of a different material from film 2

Claims (1)

(57) [Claims] In a method of manufacturing a semiconductor device having conductive layers having different steps on one surface of a semiconductor substrate on which electrode wirings are to be formed, after the conductive layers are formed, etching rates in reactive ion etching are different from each other.
Forming an insulating layer capable of increasing the etching rate of the second insulating layer with respect to the first insulating layer in the order of the first and second insulating films, and thereafter planarizing the surface; Masking with a photoresist for
Forming a wiring connection hole having a different depth by using reactive ion etching in which the etching rate of the insulating layer is higher than that of the first insulating layer.