JPH01272121A - Through-hole structure and manufacture thereof - Google Patents

Abstract

PURPOSE:To shorten the overetching time of a through-hole by a method wherein a first insulating layer is laminated on the surface of a substrate, a second insulating layer composed of a material different from that of the first insulating Iayer is laminated on the first insulating layer, a third insulating layer composed of a material different from that of the second insulating layer is laminated on the second insulating layer and the through-hole is made in the insulating film layers. CONSTITUTION:An interlayer insulating film is constituted of three layers 20, 30, 40; when an etching rate of the intermediate layer 30 is made smaller than an etching rate of an uppermost layer, the etching completion time of through holes 4, 5, 6 with different depths can be made equal in a wiring structure where a stepped part is formed on a main face and whose surface is flat. As a result, since the overetching time can be shortened sharply, it is possible to prevent an increase in a defective connection of the etching holes due to overetching and an increase in a pattern conversion difference. In addition, an etching rate of a lowest layer may be made smaller than the etching rate of the intermediate layer and even in this case, an identical effect can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a through-hole structure in an integrated circuit and a method for manufacturing the same.

[Conventional technology]

FIGS. 3(a) and 3(b) show a conventional method for forming through holes. Figure 3 (al, (bJ
Inside, 1 is a substrate formed by integrating semiconductor devices, 2 is an interlayer insulating film, 3 is the surface of the insulating film, 4, 5.6 are through holes, 7, 8.9 are electrodes, 1θ, 11.12 are electrodes The exposed portion 13 is photoresist. Surface 3 of interlayer insulating film 2
Planarization improves the homogeneity of the transmission characteristics of the wiring, and is effective in preventing disconnection of the wiring and leakage current between the lines, so it has become essential as the wiring becomes finer. Generally, planarization in multilayer wiring is done on an uneven base, so the surface 3
As the flatness of the photoresist 13 improves, the difference in depth between the through holes 4.5 and 6 formed by etching in the opening of the photoresist 13 becomes closer to the height of the step of the underlying unevenness. . For this reason, the etching times required to form through holes 4.5 and 6 are different.
The exposed portion 12 of the electrode 9, which is the base of the shallower through hole 6, remains unchanged even after the etching of the through hole 6 is completed.
The through holes 4 and 5 are exposed to the etching atmosphere until the formation of the deeper through holes 4 and 5 is completed. In this case, the etching rate of the interlayer insulating film 2 is a, the etching rate of the underlying electrode 9 is b, and the depths of the through holes 4.5 and 6 are H4, H5, and H6, respectively. When etching is completed, the depth H9 to which the underlying electrode 9 is etched is at least h9=b(H4-H6)/a, assuming H4=H5. This underlying etching is not only unnecessary, but also causes wiring defects. Further, since the difference in batten conversion due to etching tends to increase by being placed in an etching atmosphere after etching is completed, it is necessary to make the etching time uniform from the viewpoint of finer etching.

Further, in order to allow variations in the etching rate a and H4 and H5, the etching time is longer than uH4/a.

At this time, in some cases, over-etching is performed even after the underlying surface has been exposed, so that under a certain variation value, the etching of the underlying surface is proportional to the thickness of the interlayer insulating film 2.

[Problem to be solved by the invention]

The present invention has been made in view of the above-mentioned circumstances.The present invention has been made in view of the above-mentioned circumstances.In forming through-holes, it is possible to equalize the etching time of through-holes of different depths, improve the connection yield of through-holes, and ・dispersion of mother tongue conversion difference. It is an object of the present invention to provide a fixed through-hole structure and a method for manufacturing the same.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a conductive layer or an impurity diffusion region formed on the surface of a substrate, a first insulating layer on the surface, and a first insulating layer on the first insulating layer. A second insulating layer made of a material different from that of the insulating layer and a third insulating layer made of a material different from the second insulating layer are laminated on the second insulating layer to form an insulating film layer. No, a through hole is formed in the insulating film layer! Particularly, in the above method for manufacturing a through hole, the first step of etching the third insulating layer using a photoresist as a mask, the second step of etching the second insulating layer, and the third step of etching the third insulating layer using a photoresist as a mask. 1
The third step of etching the insulating layer is characterized in that in at least one of the first step and the second step, the etching rate of the insulating layer is higher than the etching rate of the underlying insulating layer. It is something to do.

[Effect]

The present invention provides a film structure of an interlayer insulating film forming a through hole, including an uppermost insulating layer, an intermediate insulating layer having a composition different from the uppermost insulating layer, and a lowermost insulating layer having a composition different from the intermediate insulating layer. The etching time for through holes of different depths is divided into the etching time for the uppermost insulating layer, the etching time for the middle insulating layer, and the etching time for the lowermost insulating layer. By making the etching rate of the intermediate insulating film extremely small during etching, the amount of etching of the intermediate insulating layer can be reduced even when the thickness of the uppermost insulating film is different. After the etching of the uppermost 1-P3 edge column layer is completed, the remaining intermediate insulating layer and the lowermost insulating layer are etched to form through holes, but the intermediate insulating properties can be maintained even in through holes of different depths. By making the film thicknesses of the layer and the bottom I-insulating layer the same, the etching time for the through holes can be made the same.

At this time, the over-etching f of the through-hole base, which serves as a margin for variations in etching rate and film thickness, depends only on the bottom insulating layer. Since the etching time can be shortened and the over-etching time can be made equal, variations in characteristics due to the formation of through holes can be eliminated.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of a through-hole structure according to the present invention. In the figure, 1#'i is a substrate formed by integrating semiconductor devices with a conductive layer or an impurity diffusion region formed on its surface, 2011''! insulation film, 30 is a green insulation film made of a different material from 20, 40 is 30 is an insulating film made of a different material, 4, 5 and 6 are through holes, 7, 8 and 9 are electrodes, and 13 is a photoresist.

Hereinafter, a method for manufacturing the through hole shown in FIG. 1 will be explained using FIG. 2.

That is, as shown in FIG. 2 (sJ), a semiconductor device,
For example, a step formed by a dirt electrode 9 exists on the main surface of a substrate 1 on which MO8 field effect transistors are integrated. An insulating film 20 made of, for example, SlO□ is deposited on the main surface. Deposition of 5IO2 is also possible by vapor phase reaction, or by sino-motsutaring. The film thickness of 5102 may be as long as it can cover the above electrode.
If the height is 100 nm, then the height may be about 100 nm. Insulation 1! ! ! 20 may be 5t3N4. Subsequently, a vapor insulating film 30 made of non-dawg amorphous S1 is deposited to a thickness of about 100 nrn. The amorphous St may be deposited by a thermal decomposition reaction, a plasma reaction, or a sputtering method, and it does not matter whether the step portion is coated well or not. Then, S1 again
A surface m13 of the insulating film 40 is obtained by depositing 0□ to a thickness equal to or greater than the step difference of the dirt 11L pole 9 and flattening it by a surface flattening method such as an etch pack method. Therefore, for example, an organic polymer material layer is applied thereon and heat treated to form a wiring structure having a flat surface. Next, the surface of the wiring structure configured in this way is treated with reactive ions, for example.
Etching (RIE) is performed under conditions such that the etching rate of the insulating film 40 and the organic polymer material layer are the same, and the convex portion of the insulating film M40 is removed simultaneously with the etching of the organic polymer material layer to obtain a flat surface 3.

Next, the photoresist 13 is patterned by a photolithography process to expose the opening positions of the through holes, and the surface 3 is covered with the photoresist.

Next, as shown in FIG. 2(b), the through-holes were etched using an ordinary RIE device, and the etching ys-K CHF3102 mixture was heated at a flow rate ratio of 9/75S.
C.C.M.

When a pressure of 50 mTorr and an RF force of 1000 W are applied, the etch rate for an S amount of 0□ is 36 nm/min.
The etching rate of amorphous S1 is 4 layers m/min.

Now, as an example, the depth of through hole 4.5 is 11000.
n, and the depth of the through hole 6 is 500 nm. In this case, the thickness of the top layer 5102 of the through hole 4.5 is 8.
00 nm, and the thickness of the top layer SlO□ of through hole 6 is 3
00 nm. Assuming over-etching of 2096 nm as a margin for variations in etch rate and film thickness, the amorphous S1 layer of through hole 6 will be over-etched by approximately 74 nm by the time the top layer S10□ is etched. This means that 74% of the thickness was etched. Next, the second
As shown in Figure (e), the amorphous S1 that is the intermediate layer is etched using a cylindrical or parallel plate type plasma etching device, using a CF4102 mixed gas as the etching gas at a flow rate of 9515 SCCM and a pressure of 500 mTgr.
When an RF tc force of 150 W is applied, the etch rate for Si is 150 nm for 7 minutes, and the etch rate for SiO□ is 10 nm for 7 minutes, so that only amorphous Si is isotropically etched.

Also, in a normal RIE device, the etch rate ratio of Sl and 5IO2 can be set to about 5:1 using the same etching gas. Etching of 20 nm occurs, but this is rarely a problem.Next, as shown in FIG. 2(d), the bottom layer 5IO2 is etched under the same etching conditions as the top layer.
Assuming zero factor overetching, the overetching time for the underlying IIf electrode is equal to <0.6 minutes for all through holes, which poses no practical problem at all.

In this way, by forming the interlayer insulating film into a three-layer structure and making the etching rate of the middle layer smaller than the etching rate of the top layer, a wiring structure with a step on the main surface and a flat surface 3 can be etched deep. The etching completion time for through holes of different sizes can be made equal. As a result, the over-etching time can be significantly shortened, thereby preventing through-hole connection failures and increases in nonatane conversion differences due to over-etching. Note that the etching rate of the bottom layer may be lower than the etching rate of the middle layer.
In this case as well, effects similar to those described above can be obtained.

〔Effect of the invention〕

As explained above, the present invention can reduce the auto-quenching time of through-holes. The effect is that the amount of etching on the base of the five through holes is reduced due to over-etching, so that the wiring connection yield is improved. Further, as an effect, the enlargement of the through hole due to over-etching and side etching is reduced, so that the controllability of the 2-tanf conversion difference during through-hole etching is improved.

This is advantageous for miniaturizing the wiring pitch.

[Brief explanation of the drawing]

Figure M1 is a cross-sectional view showing an embodiment of the through-hole structure of the present invention, and Figures 2 (-) to (d) show an example of the method for manufacturing the through-hole shown in Figure 1 in order of steps. cross section,
FIGS. 3(a) and 3(b) are cross-sectional views showing an example of a conventional through-hole manufacturing method in the order of steps. 1...Substrate formed by integrating semiconductor devices, 2...
Insulation k, 3...Surface of top insulating film, 4,5.6...
・Through hole, 7, 8.9... Electrode, 10, 11° 12... Exposed part of electrode, 13... Photoresist,
20... Insulating film, 3θ... Insulating film having a different composition from the insulating film 20, 40... Insulating film having a different composition from the insulating film 30. Applicant's agent Patent attorney Takehiko Suzue Figure 2

Claims (2)

[Claims] (1) A conductive layer or an impurity diffusion region is formed on the surface of the substrate, and a first insulating layer is formed on the surface and a material different from the first insulating layer is formed on the first insulating layer. A third insulating layer made of a material different from that of the second insulating layer is laminated on the second insulating layer to form an insulating film layer, and a through-hole is formed in the insulating film layer. A through-hole structure characterized by holes. (2) A conductive layer or an impurity diffusion region is formed on the surface of the substrate, and a first insulating layer is formed on the surface and a material different from the first insulating layer is formed on the first insulating layer. A third insulating layer made of a material different from that of the second insulating layer is laminated on the second insulating layer to form an insulating film layer, and a through-hole is formed in the insulating film layer. In the method for manufacturing a through hole in which a hole is formed, the first step of etching the third insulating layer using a photoresist as a mask, the second step of etching the second insulating layer, and the first insulating layer are etched. a third step of etching the insulating layer, and the etching rate of the insulating layer is higher than the etching rate of the base insulating layer in at least one of the first step and the second step. manufacturing method.