JPH10321623A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a thickness of a via hole on a wiring of the same layer uniform by restraining tendency to depending or a wiring stability to the width of a layer insulating film, and preventing the layer insulation film on a wiring pad from thickening. SOLUTION: In the semiconductor device with a multilayered wiring structure of n (n is an integer more than 3) layers whose flatness of layer insulation films 3, 5 on each wiring layer is not more than 0.3 μm, wiring pads 6a, 6b of a bonding pad not exceeding (n-1) layers are subjected to patterning spaces 8a, 8b so as not to form an isolated wiring part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring structure, and more particularly, to a semiconductor device having an interlayer insulating film subjected to a planarization process and a method of manufacturing the same.

[0002]

2. Description of the Related Art High performance of a semiconductor integrated circuit (LSI),
As the integration density increases, the wiring pitch is reduced, and at the same time, the number of wiring layers is increasing. Due to the increase in the number of wiring layers, unevenness occurs in the interlayer insulating film.

On the other hand, a high NA stepper is adopted to cope with a fine wiring pitch. Since this high NA stepper has a shallow depth of focus, a high flatness is required for the substrate when forming a pattern. As described above, unevenness occurs in the interlayer insulating film due to the increase in the number of wiring layers, so that planarization is performed by various methods. recent years,
CMP (Chemical Mechanical P
In many cases, the surface is planarized by using a polishing (chemical mechanical polishing) technique.

However, in the case of etching a connection hole (hereinafter, referred to as a via hole) on a substrate planarized by CMP, particularly in the case of a multilayer wiring structure of three or more layers, a bonding pad portion and the like are not provided. It has been found that the following problems occur when such a portion that opens a wide space is mixed.

FIGS. 12 and 13 show a conventional wiring structure. FIG. 12 is a plan view, and FIG. 13 is a sectional view taken along line AA ′ of FIG. As shown in FIG. 1, a first wiring pattern layer 2 is formed on a silicon substrate 1 on which transistors and the like are formed.
Is formed, and an interlayer insulating film 3 such as PETEOS is formed so as to cover the first wiring pattern layer 2.
After the surface is planarized by the method described above, a via hole 7a is formed by via hole etching. This via hole 7
Reference numeral a denotes a connection hole of a minimum size, which is used in a wiring portion for electrical connection in a circuit block in an LSI chip or between circuit blocks. Then, a second layer is formed on the interlayer insulating film 3.
A second-layer wiring pattern layer 4 is formed, a second interlayer insulating film 5 is formed so as to cover the second-layer wiring pattern layer 4, and is planarized by CMP or the like.

A via hole 7b is formed in this interlayer insulating film 5 by via hole etching. In the wiring portion of the semiconductor device, a wide wiring pad portion 11 (11a, 11a) for a bonding pad is usually provided for each wiring layer.
b) is provided, and a large opening is formed in the insulating films 3 and 5 thereon.

That is, when forming the above-described via hole 7a, the wiring pad portion 11a for the bonding pad is different from other via holes as shown in FIG.
A large area is opened, and an upper wiring pad portion 11b is formed in the same manner. In the case where multi-layer wiring is performed without flattening the interlayer insulating films, this basically does not cause any particular problem. However, when each interlayer insulating film is flattened, no particular problem occurs when the first via hole 7a is etched, but a problem occurs when the second via hole 7b is formed.

This is because the first via hole is not completely filled only in the wiring pad portion 11 for the bonding pad, so that the thickness of the interlayer insulating film 5 above the wide opening becomes thick. As shown in FIG. 13, an interlayer insulating film 5 covering the second wiring layer 4 on a normal via hole size.
Is smaller than the thickness b of the interlayer insulating film 5 on the wiring pad portion 11a. Therefore, when the second via hole 7b is formed, a portion having a different etching depth occurs. In such a case, the normal size via hole 7b
Has a shallower hole depth than the wiring pad portion 11b,
As described above, the portion having the film thickness a is considerably over-etched until the etching of the deep portion is completed. If the amount of over-etching is large, the holes are widened, so that the wiring design rules are squeezed, and problems such as generation of foreign matter occur.

The present applicant has already proposed a semiconductor device and a method of manufacturing the same in which the problem of the wiring pad portion for via hole etching and bonding which occurs when forming such a multi-layered wiring portion of a flattened semiconductor device has been solved. (See Japanese Patent Application No. 8-106560).

One of the above proposed methods will be described with reference to FIGS. FIG. 6 is a plan view, and FIG.
FIG. 3 is a sectional view taken along line A ′.

First, a silicon substrate 1 covered with an insulating film
A first-layer metal wiring pattern layer 2 is formed, and the first-layer metal wiring pattern layer 2 is provided with a wiring pad portion 12a for a bonding pad. An interlayer insulating film 3 is deposited on the first metal wiring pattern layer 2 so as to cover the metal wiring pattern layer 2, and the insulating film 3 is planarized by CMP.

Via holes 7a are formed in interlayer insulating film 3, and a plurality of via holes 7a are arranged in an array on wiring pad portion 12a for a bonding pad, as shown in FIGS. It is formed as follows.
The via hole 7a is filled with metal (tungsten) 9 by a buried metal process such as a blanket tungsten method, and a second-layer metal wiring pattern layer 4 is formed on the interlayer insulating film 3.

The first-layer wiring pad portion 12a and the second-layer wiring pad portion 12b are connected by a metal 9 embedded in a via hole 7a.

An interlayer insulating film 5 is provided so as to cover the second metal wiring pattern layer 4, and a via hole 7b is formed in the interlayer insulating film 5. Via holes 7b are filled with metal 9 by a buried metal process, and a third metal wiring pattern layer 13 is provided thereon.

When using the above-mentioned buried metal 9,
It is best that the size of the via holes 7a (7b) is the same everywhere. However, the minimum via hole size used for the wiring portion for connection in the circuit blocks between the wiring layers or between the circuit blocks over the entire chip. If the opening is formed in a rectangular shape having a short side of a size of twice or less or a size of twice or less the minimum size, the via hole 7a (7
The filling of the embedded metal 9 into b) can be performed.

As described above, in the first method, the bonding pad portions as shown in FIG. 7 are connected by the via holes 7a (7b).

However, in this method, for example, 100
The interlayer insulating films 3 and 5 on the μm-square wiring pad portions 12a (12b) are formed to be at least 100 nm thicker than the metal wiring finely processed to 0.4 to 0.5 μm. For this reason, depending on how to set the etching conditions for the via hole 7b, the dimensions of the via hole 7b,
There is a fear that resistance variation and conduction failure may occur.

The reason why the thickness of the interlayer insulating films 3 and 5 on the wiring pad portions 12a (12b) becomes thicker depends on the wiring width of the metal depending on the method of forming the interlayer insulating film and the method of flattening the interlayer insulating film. It is mentioned.

As an example, PETEO by a plasma CVD method conventionally used for forming an interlayer insulating film is used.
High-density plasma C that forms a film while performing deposition and sputter etching at the same time, when S is used, and in recent years, has been introduced in the generations after the sub-half micron.
In the case where the VD method (hereinafter abbreviated as HDP-CVD) is used, the results of examining the dependence of the interlayer insulating film thickness on the metal wiring width when the planarization is performed by the CMP method are shown in FIGS. Shown in FIG. 4 is a characteristic diagram showing a change in film thickness before and after CMP when an interlayer insulating film is formed by HDP-CVD, and FIG. 5 is a characteristic diagram showing a change in film thickness before and after CMP when an interlayer insulating film is formed by PETOS. is there. As the metal shape, ten lines were formed in a line (L) / space (S) shape in which the one formed entirely as a single part and the one having the same line width and space width were alternately arranged. Things.

It can be seen that in any of the film forming methods, the interlayer insulating film having a metal width of 100 μm is 100 nm or more thicker than the minimum metal width. Furthermore, when the CMP method is used as a method of planarizing the interlayer insulating film, it is difficult to planarize the pattern in which a plurality of 100 μm square pads are arranged in an array, and the interlayer insulating film on the pad becomes thicker. Would. Further, as shown in FIG. 7, the difference between the thickness (b) of the interlayer insulating film on the pad portion 12b and the thickness (a) of the interlayer insulating film on the minimum metal is 100 nm or more. Then, as the wiring pad portions are stacked, the step of the interlayer insulating film increases (d>
c).

The other method will be described with reference to FIGS. FIG. 8 is a plan view, and FIG. 9 is a sectional view taken along line AA ′ of FIG. In this method, a wiring pad portion 14 for a bonding pad which a semiconductor chip has for input / output is provided.
Is formed only on the uppermost part of the multilayer metal wiring layer.

This method will be described with an example of a three-layer wiring. As described above, the first substrate is placed on the silicon substrate 1 covered with the insulating film.
A first-layer metal wiring pattern layer 2 is formed by depositing and patterning a first-layer wiring metal. The insulating film here may or may not be planarized. The first metal wiring pattern layer 2 does not have a wiring pad portion for a bonding pad. An interlayer insulating film 3 is deposited thereon, and the interlayer insulating film 3 is planarized by CMP.

Thereafter, via holes 7a are formed in interlayer insulating film 3.
Is formed, and the second metal wiring pattern layer 4 is deposited and patterned. The second metal wiring pattern layer 4 also has no wiring pad portion for a bonding pad. Thereafter, a second interlayer insulating film 5 is deposited and planarized, and a second via hole 7b is opened. Third on this
A metal wiring pattern layer 13 as a layer is deposited and patterned. A wiring pad portion 14 for a bonding pad is formed only on the third metal wiring pattern layer 13.

In the case of the above-mentioned method, the lower metal wiring layer is connected to the third wiring by the via hole 7a (7b), and the wiring pad portion 1 for the bonding pad is formed in the third layer.
4.

However, in this case, connecting to the third-layer wiring by the via holes 7a (7b) at any place in the chip makes the third-layer wiring denser, so that bonding pads are not used. It is necessary to connect to an upper layer using a via hole near the wiring pad portion 14. Therefore, there is a disadvantage that the wiring cannot be arranged in the vicinity of the wiring pad portion 6 for the bonding pad, and the chip size is slightly increased.

By the way, on n layers (n is an integer of 3 or more),
That is, the opening of the wiring pad portion for the uppermost bonding pad is only above the wiring pad portion for the bonding pad. Therefore, even though the thickness of this portion is somewhat thicker, there is no via hole in this insulating film, so that the above-described problem relating to hole etching does not need to be considered.

Therefore, in the method shown in FIGS. 10 and 11, the structure of the above-described semiconductor device in which the wiring pad portion 14 for the bonding pad is formed only on the uppermost portion of the multilayer metal wiring layer is improved, and the n-th metal wiring Layer and (n-1) th
Wiring pad portions 15b, 15 for bonding pads
c is arranged. With this configuration, the above-mentioned disadvantages that slightly increase the chip size are improved, and the degree of freedom in design is increased by increasing the number of metal wiring layers that can be connected to the wiring pad section 15 for bonding pads. Is what you do.

Then, a passivation film 16 is formed thereon.
Is deposited, and only the wiring pad portion for the bonding pad is etched to form an opening 17. Here, since the planarization is not performed, the passivation film 16 is formed conformally, and the wiring pad portion 15 for the bonding pad can be etched without any problem.

[0029]

8 and 9 described above.
In the configuration of the semiconductor device in which the pad portion is formed only on the uppermost portion of the multilayer wiring as shown in (1), the wiring which needs to be connected to the pad portion in the lower wiring layer is connected to the pad of the wiring layer via the via hole Therefore, it is necessary to route the wiring for opening the via hole, and there is a disadvantage that the chip size is slightly increased. If a sufficient via hole is not secured, the yield may be reduced due to poor conduction.

As a method for solving this problem, in the configuration in which the pad portion is arranged in the uppermost n-th wiring layer and the (n-1) th layer below it as shown in FIGS. However, with respect to the current and future trends in which the number of layers is increased to three or more, it is still impossible to eliminate the disadvantage that the chip size is slightly increased. Also,
If a sufficient via hole is not secured, there is a fear that the yield may decrease due to poor conduction.

The present invention suppresses the occurrence of the dependence of the interlayer insulating film on the metal wiring on the metal wiring width, prevents the interlayer insulating film on the wiring pad from becoming thick, and reduces the via hole thickness on the wiring of the same layer. The purpose is to make the uniformity.

Further, by connecting a plurality of via holes in the pad portion between the wiring layers, a sufficient number of via holes can be secured in the pad without increasing the chip size, and poor conduction and yield can be prevented. It is also intended to eliminate the fear of a drop or the like.

[0033]

The semiconductor device of the present invention has an n-layer (n is an integer of 3 or more) multilayer wiring structure in which the flatness of an interlayer insulating film on each wiring layer is 0.3 μm or less. The semiconductor device is characterized in that the wiring pad portion for the bonding pad of the (n-1) th layer or less is patterned with a predetermined space so as not to generate an isolated wiring portion.

According to the above structure, the dependency of the interlayer insulating film thickness after the formation and planarization of the interlayer insulating film on the metal width can be suppressed.
Flatness can be improved.

Further, in the semiconductor device of the present invention, the n (n) where the flatness of the interlayer insulating film on each wiring layer is 0.3 μm or less.
(N is an integer of 3 or more) in a semiconductor device having a multilayer wiring structure having a predetermined space so that a wiring portion having a width of 10 μm or more is not isolated in (n-1) or less layers. It is characterized by being patterned.

According to the above structure, the dependency of the thickness of the interlayer insulating film after the formation and planarization of the interlayer insulating film on the metal width can be suppressed.
Flatness can be improved.

In each of the above structures, the width of the wiring portion remaining after patterning is preferably set to 10 μm or less.

According to the above-described structure, the effect of suppressing the dependence of the thickness of the interlayer insulating film on the metal width after the formation and planarization of the interlayer insulating film is great. Is improved.

Further, in each of the above structures, it is preferable that the space between the wirings remaining after patterning is set to the minimum design rule.

According to the above structure, the metal area is increased while suppressing the metal width dependence of the interlayer insulating film after the interlayer insulating film is formed and planarized, so that the number of via holes for conduction is reduced. More can be obtained and its arrangement becomes easier. Further, the bonding strength is improved.

The connection hole between the wiring layers is formed in a rectangular shape having a short side having a size not more than twice the minimum connection hole size between the wiring layers or a size not more than twice the minimum connection hole size. It is good to consist only of.

When the n-th (n> 1) -th via hole is configured as described above, the (n + 1) -th wiring layer can be formed flat, so that the (n + 1) -th via-hole variation And flatness can be improved.

Further, the connection between the wiring layers is preferably made by a plurality of connection holes of the above-mentioned size.

According to the above configuration, the connection between the wirings can be reliably established, and the reliability is improved.

According to the method of manufacturing a semiconductor device of the present invention, the interlayer insulating film on each wiring layer has a flatness of 0.3 μm or less.
In a method for manufacturing a semiconductor device having a multilayer wiring structure of (n is an integer of 3 or more) layers, a pattern is formed having a predetermined space so that a wiring portion in which a wiring pad portion of a bonding pad portion is not formed on a substrate. Forming a wiring layer, and depositing an interlayer insulating film covering the wiring layer, planarizing the interlayer insulating film, and forming a plurality of connection holes in the interlayer insulating film on the wiring pad portion for the bonding pad. And forming a wiring layer by patterning with a predetermined space so that a wiring portion where a wiring pad portion of a bonding pad portion is not isolated is formed on the interlayer insulating film. Connecting a wiring pad portion for a lower bonding pad through the intermediary of the bonding pad.

According to the above method, the dependency of the interlayer insulating film thickness after the formation and planarization of the interlayer insulating film on the metal width can be suppressed.
Flatness can be improved, and variations in via hole dimensions, resistance, and poor conduction can be prevented.

Further, an interlayer insulating film from the first layer to the (n-1) th layer may be formed by high-density plasma CVD.

According to the above configuration, the effect of suppressing the metal width dependence of the interlayer insulating film thickness after the formation and planarization of the interlayer insulating film is greater than that achieved by the conventional film forming method.
Further, the variation in the depth of the via hole can be suppressed, and the flatness can be improved.

Further, it is preferable that the interlayer insulating film is planarized from the first layer to the (n-1) th layer by a chemical mechanical polishing method.

Further, since this method has a self-flattening ability, when the above-described CMP is used as the flattening method, the polishing time is short and the throughput can be realized.

[0051]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. The same parts as those of the conventional example are denoted by the same reference numerals.

FIG. 1 is a plan view showing an embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA 'of FIG. FIG. 3 is a plan view showing another embodiment of a wiring pad portion for a bonding pad according to the present invention. In this embodiment, an example of a three-layer wiring will be described.

First, a transistor is formed, a first-layer wiring metal is deposited on a silicon semiconductor substrate 1 covered with an insulating film, and is patterned to form a first metal wiring pattern layer 2. . The insulating film on the silicon semiconductor substrate 1 may not be planarized. The first metal wiring pattern layer 2 has a wiring pad portion 6a for a bonding pad. At this time, the wiring pad portion 6a is patterned in a lattice shape or a stripe shape as shown in FIG. 1 or FIG. That is, a predetermined space 8a is provided in the pattern portion 6a so that the wiring pad portion 6a is not isolated. All wiring widths in the wiring pads 6a remaining after patterning are set to 10 μm or less, and the space between the wirings is set to a minimum design rule. The shape of the wiring pad portion 6a is not limited to a lattice shape or a stripe shape and may be any shape as long as it is patterned so as not to generate an isolated metal. Here, for example, metal width 5
A slit-shaped wiring pad portion 6a shown in FIG. 3 having an area corresponding to a pad of 100 μm square was formed by 10 sets of μm and space width of 5 μm.

Next, a first interlayer insulating film 3 is deposited on the first metal wiring pattern layer 2,
Is flattened by CMP.

The planarization of the interlayer insulating film 3 is performed by CMP or the like until the step in the chip becomes 0.3 μm or less according to a request from lithography. This flatness requirement is that, for example, when patterning a fine wiring such as a 0.5 μm line & space, the depth of focus of lithography is about 1.5 μm, and furthermore, the positional accuracy on the apparatus is not sufficient at present. Since the stepper requires about 0.75 μm, it is premised that the step of the wiring portion must be reduced to about 0.75 μm or less in total.

In the case of three-layer wiring, when the flattening is performed twice, the maximum step height is acceptable, but the flatness of each layer is at least 0.325 μm or less, preferably 0.3 mm or less.
It needs to be 30 μm or less.

Next, the interlayer insulating film 3 is formed by lithography.
Then, the resist of the via hole 7a is patterned.
At this time, as shown in FIGS. 1 to 3, via holes 7a are formed in the wiring pad portions 6a for the bonding pads.
The resist is patterned so that a plurality of holes are arranged in an array, and then the interlayer insulating film 3 is etched by dry etching to form a via hole 7a. The formation of the first via hole 7a is designed so that a plurality of the via holes 7a are arranged on the metal so as to ensure conduction to the wiring pad portion 6a.

The depth of the first via hole 7a is
As shown in FIG. 4 and FIG. 5, the depth of the first via hole 7a on the wiring pad portion is larger when the slit-shaped wiring pad portion 6a of 5 μm line and space is used than when the wiring pad portion of 100 μm square is used. And the variation can be kept small.

At this time, the depth of the first via hole 7 a corresponds to the depth of the first via hole 7 a on an isolated 5 μm metal, and does not depend on the method of forming the first interlayer insulating film 3. The effect of suppressing the variation is that PETEOS
The effect is greater when HDP-CVD is used than when. Further, since the depth of the first via hole 7a on the wiring pad 6a is reduced, the wiring pad 6
The effect is greater as the flatness in the vicinity of “a” is improved and the number of wiring layers is increased.

Then, after tungsten (W) is deposited by CVD or the like, the via hole 7a is filled with metal (tungsten) 9 by a buried metal process such as a blanket tungsten method that leaves tungsten only in the hole by etch back.

In the case of using a buried metal, it is best that the size of the via hole is the same everywhere. However, the via hole is used in a circuit block between wiring layers or in a wiring portion for connection between circuit blocks over the entire chip. Experiments have shown that filling a via hole with a buried metal is possible even if it is opened with a rectangular shape with a short side that is less than twice the minimum via hole size or less than twice the minimum size. ing.

The etch back in the buried metal process gives good results even when dry etching is used.
The flatness at the time of depositing the wiring metal of the layer is improved.

Subsequently, a second-layer metal wiring pattern layer 4 is formed on the interlayer insulating film 3. Also in the metal wiring pattern layer 4, the wiring pad portion 6b is formed in a slit shape as in the case of the metal wiring pattern 2 of the first layer.

Next, a second interlayer insulating film 5 is deposited on the second-layer metal wiring pattern layer 4,
Is flattened by CMP, and the second via hole 7b is opened. Regarding the wiring pad portion 6b, the formation of the second via hole 7b is performed in the same manner as the formation of the first via hole 7a. Thereafter, similarly, after tungsten (W) is deposited by CVD or the like, the via hole 7b is filled with metal (tungsten) 9 by a buried metal process such as a blanket tungsten method that leaves tungsten only in the hole by etch back. A third layer of metal is deposited thereon and patterned to form a third layer of metal.
A metal wiring pattern layer 10 was formed. At this time, the wiring pad portion 6c does not need to be formed in a slit shape, and may be a normal non-patterned sheet shape.

By using the above method, it is possible to reduce the depth of the via hole on a portion having a large metal width such as the pad portion of the wiring layer, thereby suppressing the variation in the entirety and improving the flatness. Can be.

In the above-described embodiment, the wiring pad portion 6a (6b) has been described. However, in the case where the wiring width is 10 μm or more, a predetermined space is similarly provided so as not to generate an isolated metal. To pattern the wiring.

[0067]

As described above, according to the present invention, it is possible to suppress the metal width dependency of the interlayer insulating film thickness after the interlayer insulating film is formed and planarized, so that the variation in the depth of the via hole can be reduced. Pressing and flatness can be improved, and variations in via hole dimensions, resistance variations and poor conduction can be eliminated.

[Brief description of the drawings]

FIG. 1 is a plan view showing an embodiment of the present invention.

FIG. 2 is a sectional view taken along line A-A 'of FIG.

FIG. 3 is a plan view showing another embodiment of a wiring pad portion for a bonding pad according to the present invention.

FIG. 4 shows an interlayer insulating film formed by HDP-CVD.
FIG. 4 is a characteristic diagram showing a change in film thickness before and after MP.

FIG. 5 shows an interlayer insulating film formed by PETOS and CMP
It is a characteristic view which shows the change of the film thickness before and behind.

FIG. 6 is a plan view showing a conventional semiconductor device which solves a problem of a semiconductor device having a multilayer wiring structure in which an interlayer insulating film is planarized.

FIG. 7 is a sectional view taken along line A-A ′ of FIG. 6;

FIG. 8 is a plan view showing a semiconductor device which solves the problem of a conventional semiconductor device having a multilayer wiring structure in which an interlayer insulating film is planarized.

9 is a sectional view taken along line A-A 'of FIG.

FIG. 10 is a plan view showing a semiconductor device which solves a problem of a conventional semiconductor device having a multilayer wiring structure in which an interlayer insulating film is planarized.

11 is a sectional view taken along line B-B 'of FIG.

FIG. 12 is a plan view showing a conventional semiconductor device having a multilayer wiring structure in which an interlayer insulating film is planarized.

13 is a sectional view taken along line A-A 'of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2, 4, 10 Metal wiring pattern layer 3, 5 Interlayer insulating film 6 Wiring pad part 6a, 6b, 6c Wiring pad part 7a, 7b Via hole 8a, 8b Space 9 Metal

Claims (11)

[Claims] 1. An interlayer insulating film on each wiring layer has a flatness of 0.1.
In a semiconductor device having a multilayer wiring structure of n (n is an integer of 3 or more) layers of 3 μm or less, a predetermined wiring pad portion for bonding pads of (n−1) layers or less is formed so that an isolated wiring portion does not occur. A semiconductor device characterized by being patterned with a space. 2. The semiconductor device according to claim 1, wherein the width of the wiring portion remaining after patterning is 10 μm or less. 3. The semiconductor device according to claim 1, wherein a space between the wirings remaining after being patterned is a minimum design rule. 4. The flatness of an interlayer insulating film on each of the wiring layers is not more than 0.
In a semiconductor device having a multilayer wiring structure of n (n is an integer of 3 or more) layers of 3 μm or less, a wiring portion having a width of 10 μm or more in a layer of (n−1) layers or less is not formed. A semiconductor device characterized by being patterned with a predetermined space. 5. The semiconductor device according to claim 4, wherein the width of the wiring portion remaining after patterning is 10 μm or less. 6. The semiconductor device according to claim 4, wherein a space between the wirings remaining after being patterned is a minimum design rule. 7. The connection hole between each wiring layer is opened in a rectangular shape having a short side having a size not more than twice the minimum connection hole size between each wiring layer or a size not more than twice the minimum connection hole size. 7. The semiconductor device according to claim 1, wherein said semiconductor device is only one. 8. The semiconductor device according to claim 1, wherein the connection between the respective wiring layers is made by a plurality of connection holes of the size shown in claim 7. 9. The interlayer insulating film on each wiring layer has a flatness of 0.1.
In a method for manufacturing a semiconductor device having a multi-layer wiring structure of n (n is an integer of 3 or more) layers of 3 μm or less, a predetermined space is provided so that a wiring portion for a bonding pad is not formed on a substrate. Forming a wiring layer by patterning, depositing an interlayer insulating film covering the wiring layer, and planarizing the interlayer insulating film; and an interlayer insulating film on the wiring pad portion for the bonding pad. Forming a plurality of connection holes in a row, and forming a wiring layer by patterning with a predetermined space on the interlayer insulating film so as not to form a wiring portion in which a wiring pad portion of a bonding pad portion is isolated. Connecting a wiring pad portion for a lower bonding pad through a connection hole;
A method for manufacturing a semiconductor device, comprising: 10. The method according to claim 9, wherein an interlayer insulating film is formed from the first layer to the (n-1) th layer by a high-density plasma CVD method. 11. The semiconductor device according to claim 9, wherein the planarization of the interlayer insulating film from the first layer to the (n-1) th layer is performed by a scientific mechanical polishing method. Manufacturing method.