JP2001156071A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reliable semiconductor device which can suppress dishing in a pad region through a CMP step to realize suitable photolithography and etching step, and also to provide a method for manufacturing the semiconductor device. SOLUTION: A pad region 1 is a wiring end formed simultaneously with a wiring structure flattened by chemical mechanical polishing(CMP) in the semiconductor device. A conductive layer 3 made of mainly a Cu-plated film is formed and flattened in a stepped recess of an interlayer insulating film 2. A plurality of projections 4 (made of the same SiO2 film as the interlayer insulating film 2) are formed in the interior of the stepped recess in the film 2 to the halfway of the step difference. The pad region 1 is flattened by covering all the projections 4 with the conductive layer 3 (barrier metal and Cu-plated film) and burying the recess with the conductive layer to eliminate the step difference with the insulating film 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to a pad for external connection formed at a lead-out end of an IC,
In particular, the present invention relates to a semiconductor device accompanied by a CMP (Chemical Mechanical Polishing) process and a method of manufacturing the same.

[0002]

2. Description of the Related Art As semiconductor integrated circuits become more highly integrated and semiconductor chips become smaller, the size of pads having an area for electrical connection with the outside of the chip is not so small. This is because it is necessary to secure a certain size in order to obtain stability of electrical connection such as bonding wires and bumps connected to the pads and to avoid high resistance.

By the way, chemical mechanical polishing, that is, C
In the manufacture of a semiconductor device having an MP process, a conductive layer and an insulating layer (interlayer insulating film) between conductive layers each undergo a necessary planarization step. Thereby, the layers are stacked while being planarized. Therefore, the pad region is also formed by stacking the conductive members for forming the conductive layer while being planarized by CMP.

FIG. 4 is a sectional view showing a pad portion of a conventional semiconductor device. Although not shown, the pad region 401 is a terminal portion which is connected to the wiring structure of the semiconductor integrated circuit and is electrically connected to the outside by a bonding wire or the like. The pad region 401 has a form in which the conductive layer 403 is stacked from the stepped bottom of the interlayer insulating film 402.

[0005]

For the pad region 401 shown in FIG. 4, for example, a copper plating film containing Cu as a main component is applied as the conductive layer 403. In this case, the conductive layer 403 is usually formed through a plurality of CMP steps constituting each conductive layer by copper plating similarly to the wiring structure (not shown). Here, two CMP steps have been performed, and the broken line indicates the stage at the end of the first CMP step.

As described above, the pad region 401 is deposited on the copper plating film (403) in a large region at the bottom through the step of the interlayer insulating film 402, so that the amount of the copper plating film near the center of the pad is smaller than that in the periphery. Less. Since the flattening is performed by the CMP process in this state, the dishing phenomenon is remarkable. That is, the copper plating film (403) near the center of the pad decreases. Moreover, multiple times of CMP
Due to the process, the degree of dishing increases.

By the above dishing, the pad area 4
No. 01 is in a situation where the resist loses its shape or undergoes over-etching in the photolithography and etching steps after the interlayer insulating film is deposited every time after the CMP step. Therefore, the other wiring regions are adapted to the conditions for forming the pad region 401, although the appropriate photolithography and etching processes can be performed. For this reason, in the wiring region of the same step (not shown), problems such as deformation of the bottom of the contact plug due to the over-etching and deterioration of the deposition of the barrier metal occur.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to suppress dishing in a pad region through a CMP process, and to provide a highly reliable semiconductor device capable of performing an appropriate photolithography and etching process, and a semiconductor device thereof. It is to provide a manufacturing method.

[0009]

SUMMARY OF THE INVENTION The present invention relates to a semiconductor device having a wiring structure which is planarized by chemical mechanical polishing. And a pad region having a conductive member included in the wiring structure that covers the protrusion and fills the depression to eliminate a step with the interlayer insulating film.

Further, the method of manufacturing a semiconductor device according to the present invention comprises:
A method for manufacturing a semiconductor device having a wiring structure that is planarized by chemical mechanical polishing, wherein a step of forming a depression due to a step with an interlayer insulating film and a plurality of protrusions provided in the middle of the step, and A plating step of a conductive member that covers all the portions and fills the depressions; and a chemical mechanical polishing step of flattening the conductive member so as to eliminate a step with the interlayer insulating film.

According to the semiconductor device and the method of manufacturing the same of the present invention, the presence of the plurality of protrusions acts so that the plating amount of the conductive member near the center of the pad region does not decrease. That is, the unevenness of the bottom formed by the plurality of protrusions in the pad region contributes to the bottom-up fill phenomenon in the plating process of the conductive member.

[0012]

1A and 1B are main parts of a pad portion of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view, and FIG. 1B is a plan view. It is sectional drawing which follows the 1B-1B line of (a). The pad region 1 is a wiring end formed at the same time as a wiring structure planarized by chemical mechanical polishing (CMP) in the semiconductor device, and is a region electrically connected to the outside by a bonding wire or the like (not shown). It is. The pad region 1 has a form in which the conductive layer 3 is stacked in a recess having a step of the interlayer insulating film 2 on the semiconductor substrate and flattened. Here, the interlayer insulating film 2 is made of, for example, a SiO2 film, and the conductive layer 3 is mainly made of C2.
It is made of a u-plated film (a Cu-plated film is not shown, but includes a barrier metal as a lowermost layer).

In FIG. 1, a plurality of projections 4 are provided in a recess formed by a step between the interlayer insulating film 2 and the middle of the step. The projection 4 is made of, for example, the same insulating member (SiO 2 film) as the interlayer insulating film 2. That is, the pad region 1 is formed of the conductive layer 3 (barrier metal and Cu plating film).
Thereby, the protrusions 4 are entirely covered to fill the depressions, and are planarized so as to eliminate a step with the interlayer insulating film 2.

According to the above configuration, the plurality of protrusions 4 act so as not to reduce the amount of the plating film as the conductive layer 3 laminated near the center of the pad region 1. With this, CM
Even after the P step, dishing is always suppressed in the pad region 1 and flatness is maintained. This will be described in detail below based on the manufacturing method.

FIGS. 2A to 2F respectively show FIGS.
FIG. 14 is a cross-sectional view showing a substantial part of a method of manufacturing a pad portion of the semiconductor device in the order of steps. The same parts as those in FIG. 1 are described with the same reference numerals.

First, as shown in FIG. 2A, a resist layer 5 is patterned on an interlayer insulating film (SiO 2 film) 2 by using a photolithography technique. As a result, the pad region 1 at the wiring end of the semiconductor integrated circuit is formed. At this time, the resist layer 5 also includes a resist pattern serving as a plurality of protrusions in the pad region 1. The resist layer 5 also forms a resist pattern for forming a part of the wiring structure of the semiconductor integrated circuit in another region (not shown).

Next, as shown in FIG. 2B, a predetermined amount of the interlayer insulating film 2 is etched using the resist layer 5 as a mask.
For the etching, an anisotropic etching technique using RIE (Reactive Ion Etching) is used. As a result, the depression 11 due to a step with the interlayer insulating film 2 as the pad region 1 and a plurality of projections 41 in the depression are formed. After that, the resist layer 5 is peeled off.

Next, as shown in FIG. 2C, a resist layer 6 exposing a predetermined portion near the upper portion of the projection 41 is formed by using a photolithography technique. Thereafter, a plurality of protrusions 4 provided from the bottom of the depression 11 to the middle of the step of the interlayer insulating film 2 are formed by anisotropic etching (FIG. 2D). 2B to 2D, a part of a desired wiring structure pattern (a groove for forming a wiring or a plug opening) in a semiconductor integrated circuit is formed in another region (not shown). I have.

Next, as shown in FIG. 2E, a barrier metal 31 for forming a wiring structure and a Cu seed film 32 are deposited in a groove pattern on the interlayer insulating film 2. Thereafter, a plating process is performed, and the Cu plating film 33 covers all the protrusions 4 and fills the depressions 11. At this time, the coating amount of the Cu plating film 33 near the center of the pad region is not reduced by the plurality of protrusions 4. That is, the unevenness of the bottom formed by the plurality of protrusions 4 causes a bottom-up fill phenomenon of Cu plating. As a result, the Cu plating film 33 has rather raised portions in the entire pad region.

Next, as shown in FIG. 2F, the pad region 1 is also flattened at the same time when the wiring structure to be flattened by the CMP process is formed. By utilizing the bottom-up fill phenomenon, Cu near the center of the pad region
The coating amount of the plating film 33 is large. This allows
The dishing of the pad region 1 is largely suppressed, and the planarized conductive layer 3 can be formed.

The pad region 1 includes a plurality of CMs constituting each conductive layer in a wiring structure of a semiconductor integrated circuit (not shown).
It is often formed through a P process. Although not shown, at the time of forming another upper layer wiring structure, FIG.
If the steps (1) to (f) are performed again in the same pad region 1, the configuration as shown in FIG. 1 is obtained.

That is, according to the method of the above embodiment,
The pad region 1 can always achieve the coating state of the Cu plating film 33 that can suppress dishing in the CMP process. Thus, the pad region 1 has a structure that can maintain flatness even in a configuration in which Cu plating films are stacked over a plurality of wiring forming steps.

FIGS. 3A and 3B are main parts of a pad portion of a semiconductor device according to a second embodiment of the present invention, wherein FIG. 3A is a plan view and FIG. 3B is a plan view of FIG. 3B-3
It is sectional drawing which follows the B line. The same parts as those in the first embodiment are denoted by the same reference numerals.

In this embodiment, the conductive layer constituting the pad region 1 is different from that of the first embodiment, and the conductive layers 301 and 302 are formed in a recess having a step of the interlayer insulating film (SiO 2 film) 2. It has a stacked and flattened configuration. That is, the conductive layer 301 is made of lower aluminum and the conductive layer 302 is made of an upper Cu plating film (the Cu plating film is not shown but includes a barrier metal as the lowermost layer).

Referring to FIG. 3, a plurality of protrusions 4 are provided in a recess formed on the conductive layer 301 with the interlayer insulating film 2 up to the middle of the step. The protrusion 4 is formed of the same insulating member (SiO2 film) as the interlayer insulating film 2. That is, the pad region 1 is formed in the conductive layer 302 (barrier metal and C
The protrusion 4 is entirely covered with a u-plated film to fill the depression, and is flattened so as to eliminate a step with the interlayer insulating film 2.

The manufacturing method according to the second embodiment will be described.
As shown in FIG. 3B, the protrusion 4 is formed on the upper conductive layer 3.
02 (Cu plating film). The aluminum layer serving as the lower conductive layer 301 may be formed in a process that does not go through the CMP step, and maintains good flatness by heat treatment. After that, the same steps as those in FIGS. 2A to 2E are performed on the conductive layer 301. Thus, a Cu plating film, that is, an upper conductive layer 302 is formed.

According to the second embodiment and the manufacturing method thereof, similarly to the first embodiment, the unevenness of the bottom formed by the plurality of projections 4 causes a bottom-up fill phenomenon of Cu plating, and the flattening by the CMP process is excellent. To As a result, dishing of the pad region 1 is greatly suppressed, and the planarized conductive layer 3 can be formed.

According to each of the above embodiments, in the pad region 1, a plurality of protrusions 4 are always provided at the bottom before one Cu plating step. Then, in the Cu plating process, the plating film is raised over the entire depression in the pad region by utilizing the bottom-up fill phenomenon of plating.
As a result, a phenomenon in which dishing increases each time the CMP process is performed does not occur. As a result, a highly accurate resist can be always formed in the photolithography and etching steps after the interlayer insulating film 2 is deposited through the CMP step. In addition, the structure can reduce over-etching that adversely affects other wiring regions. As a result, appropriate photolithography and etching steps can be performed in the wiring region, which contributes to achieving a good state of the bottom of the contact plug and a good coverage of the barrier metal.

In each of the above embodiments, the projections are provided in the pad areas and the bottom-up fill phenomenon of Cu plating is used. However, the present invention is not limited to this. Providing a projection as in the present invention has the effects of promoting the swelling during Al deposition and suppressing dishing in the pad region even in the subsequent CMP process.

[0030]

As described above, according to the present invention, the presence of the projections in the pad region acts so that the plating amount of the conductive member near the center of the pad region does not decrease.
In other words, the unevenness of the bottom formed by the plurality of protrusions in the pad area contributes to the bottom-up fill phenomenon in the plating process of the conductive member, and the unevenness of the bottom promotes the swelling during the lamination of the conductive member in addition to the plating process. I do. As a result, it is possible to provide a highly reliable semiconductor device capable of performing dishing in a pad region through a CMP process and performing an appropriate photolithography and etching process, and a method of manufacturing the same.

[Brief description of the drawings]

FIGS. 1A and 1B are each a main portion of a pad portion of a semiconductor device according to a first embodiment of the present invention, FIG. 1A is a plan view, and FIG. It is sectional drawing which follows the -1B line.

2 (a) to 2 (f) are cross-sectional views showing a main part of a method of manufacturing a pad portion relating to the semiconductor device of FIG. 1 in the order of steps.

FIGS. 3A and 3B are main parts of a pad portion of a semiconductor device according to a second embodiment of the present invention. FIG. 3A is a plan view, and FIG. 3B is 3B of FIG. It is sectional drawing which follows the -3B line.

FIG. 4 is a cross-sectional view showing a pad portion of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Pad area 2 ... Interlayer insulating film (SiO2 film) 3 ... Conductive layer 31 ... Barrier metal 32 ... Cu seed film 33,302 ... Cu plating film 301 ... Aluminum layer 4,41 ... Protrusion 5,6 ... Resist layer

Claims (7)

[Claims] 1. A semiconductor device having a wiring structure that is planarized by chemical mechanical polishing, comprising: a plurality of protrusions provided halfway in a recess formed by a step with an interlayer insulating film; A semiconductor device comprising: a pad region having a conductive member included in the wiring structure, wherein the pad region entirely covers the depression and eliminates a step with the interlayer insulating film. 2. The semiconductor device according to claim 1, wherein said protrusion is made of the same insulating member as said interlayer insulating film. 3. The semiconductor device according to claim 1, wherein said conductive member includes at least a plating film. 4. The semiconductor device according to claim 2, wherein one of the pad regions is formed by laminating the wiring structure in multiple layers. 5. A method of manufacturing a semiconductor device having a wiring structure which is planarized by chemical mechanical polishing, wherein a plurality of protrusions are provided as a pad region due to a step with an interlayer insulating film, and a part of the depression is provided in the middle of the step. A step of forming a conductive member that covers all the protrusions and fills the depressions; and a chemical mechanical polishing step of flattening the conductive member so as to eliminate a step with the interlayer insulating film. A method for manufacturing a semiconductor device, comprising: 6. The method according to claim 6, wherein the step of forming the protrusion is achieved by forming the original shape at the time of forming a depression due to a step with the interlayer insulating film, and then selectively etching the intermediate shape to a length in the middle of the step. The method of manufacturing a semiconductor device according to claim 4. 7. The method of manufacturing a semiconductor device according to claim 5, wherein one of the pad regions is formed together with the formation of the wiring structure in multiple layers.