KR100273114B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100273114B1 KR100273114B1 KR1019980009723A KR19980009723A KR100273114B1 KR 100273114 B1 KR100273114 B1 KR 100273114B1 KR 1019980009723 A KR1019980009723 A KR 1019980009723A KR 19980009723 A KR19980009723 A KR 19980009723A KR 100273114 B1 KR100273114 B1 KR 100273114B1
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- interlayer insulating
- insulating film
- forming
- interlayer dielectric
- predetermined portion
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- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title abstract description 14
- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 239000011229 interlayer Substances 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims description 6
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 239000011521 glass Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000005498 polishing Methods 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자 제조방법에 관한 것으로, 보다 상세하게는 다층 배선 형성시 층간 절연막의 단차를 줄일 수 있도록 공정을 변경해 주므로써, SOG 에치백 공정이나 CMP 공정의 적용없이도 층간 절연막의 평탄화 특성을 향상시킬 수 있도록 한 반도체 소자 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, by changing the process to reduce the step difference of the interlayer insulating film when forming the multilayer wiring, thereby improving the planarization characteristics of the interlayer insulating film without applying the SOG etch back process or the CMP process. The present invention relates to a method for manufacturing a semiconductor device.
반도체 집적회로의 미세화가 진행됨에 따라 소자의 집적도를 높여 칩 사이즈를 최소화함과 동시에 소자의 성능(performance)을 최대로 높이는 방향으로 기술 개발이 이루어지고 있어, 소자 제조시 미세 패턴 가공과 다층 배선 공정의 필요성이 커지고 있다.As the miniaturization of semiconductor integrated circuits progresses, technology development is being conducted in the direction of minimizing chip size by increasing device integration and maximizing device performance. The need is growing.
도 1a 내지 도 1c에는 이와 관련된 종래 반도체 소자의 다층 배선 형성방법을 도시한 공정수순도가 제시되어 있다. 이를 참조하여 그 제조방법을 크게 제 3 단계로 구분하여 살펴보면 다음과 같다.1A to 1C show a process flowchart showing a method of forming a multilayer wiring of a related-art semiconductor device. Referring to this, the manufacturing method is divided into three stages.
제 1 단계로서, 도 1a에 도시된 바와 같이 절연기판(예컨대, 절연막이 형성되어 있는 반도체 기판)(10) 상의 소정 부분에 도전성막(예컨대, Al 합금이나 Cu 합금 등) 재질의 금속 배선(12)을 형성하고, 이를 포함한 기판(10) 전면에 UDO(undoped oxide) 재질의 제 1 층간 절연막(14)을 형성한 다음, 그 위에 소정 두께의 SOG(16)를 형성하고 열처리를 실시하여 이를 경화시켜 준다. 이어, 금속 배선(12) 상부의 제 1 층간 절연막(14) 표면이 노출되도록 SOG를 에치백한다. 이와 같이 SOG 에치백 공정을 적용하여 제 1 층간 절연막(14)의 공극을 메꾸어 준 것은 층간 절연막의 평탄도를 향상시켜 주어, 후속 공정 진행 과정에서 층간 절연막의 단차 문제로 인해 야기될 수 있는 공정 불량을 방지하기 위함이다.As a first step, as shown in FIG. 1A, a metal wiring 12 made of a conductive film (eg, an Al alloy or a Cu alloy) is formed on a predetermined portion on an insulating substrate (eg, a semiconductor substrate on which an insulating film is formed) 10. ), A first interlayer insulating film 14 of UDO (undoped oxide) material is formed on the entire surface of the substrate 10 including the same, and then a SOG 16 having a predetermined thickness is formed thereon and heat treated to harden it. Let it be. Next, the SOG is etched back to expose the surface of the first interlayer insulating film 14 on the metal wiring 12. The filling of the voids of the first interlayer insulating film 14 by applying the SOG etchback process improves the flatness of the interlayer insulating film, and thus, the process defect that may be caused by the step difference problem of the interlayer insulating film in the subsequent process. This is to prevent.
제 2 단계로서, 에치백 공정에 의해 평탄화된 제 1 층간 절연막(14)과 SOG(16) 상에 UDO 재질의 제 2 층간 절연막(18)을 형성하고, 그 위에 콘택 홀 형성부를 한정하는 감광막 패턴(미 도시)을 형성한 다음, 이를 마스크로 이용하여 제 1 및 제 2 층간 절연막(14),(18)을 선택식각한다. 그 결과, 금속 배선(12)의 표면이 소정 부분 노출되는 구조의 비어 홀(h)이 형성된다.As a second step, a second interlayer insulating film 18 of UDO material is formed on the first interlayer insulating film 14 and SOG 16 planarized by an etch back process, and a photoresist pattern defining a contact hole forming portion thereon. After forming (not shown), the first and second interlayer insulating films 14 and 18 are selectively etched using this as a mask. As a result, a via hole h having a structure in which the surface of the metal wiring 12 is partially exposed is formed.
제 3 단계로서, 상기 비어 홀(h)을 포함한 제 2 층간 절연막(18) 상의 소정 부분에 도전성 플러그(20)를 형성해 주므로써, 본 공정 진행을 완료한다.As a third step, the conductive plug 20 is formed in a predetermined portion on the second interlayer insulating film 18 including the via hole h, thereby completing the process.
이때, 상기 제 1 및 제 2 층간 절연막(14),(18)의 평탄화 공정은 SOG 에치백 공정이 아닌 CMP 공정을 적용하여 층간 절연막을 평탄화해 주는 방식으로 실시해 줄 수도 있는데, 이 경우에는 다음의 공정수순에 의거하여 막질 평탄화 공정이 진행된다. 여기서는 기 언급된 공정과 차별화되는 부분을 중심으로 살펴본다.In this case, the first and second interlayer insulating films 14 and 18 may be planarized by applying a CMP process instead of an SOG etch back process to planarize the interlayer insulating film. The film quality planarization process proceeds based on the process procedure. This section focuses on what differentiates it from the aforementioned processes.
제 1 단계로서, 금속 배선이 형성된 절연기판 전면에 제 1 및 제 2 층간 절연막을 형성한 다음, 막질 평탄화 특성을 향상시키기 위하여 700 ~ 900℃의 온도에서 열처리를 실시하고 CMP 공정으로 이를 평탄화한다. 이때, 상기 열처리 공정은 생략해도 무방하다.As a first step, first and second interlayer insulating films are formed on the entire surface of the insulating substrate on which the metal wiring is formed, and then heat treatment is performed at a temperature of 700 to 900 ° C. in order to improve film quality planarization characteristics, and planarization thereof is performed by a CMP process. In this case, the heat treatment step may be omitted.
제 2 단계로서, 사진식각공정을 이용하여 제 2 층간 절연막 상에 콘택 홀 형성부를 한정하는 감광막 패턴을 형성하고, 이를 마스크로 이용하여 금속 배선(12)의 표면이 소정 부분 노출되도록 제 1 및 제 2 층간 절연막을 식각하여 비어 홀을 형성한다.As a second step, a photoresist pattern defining a contact hole forming portion is formed on the second interlayer insulating layer by using a photolithography process, and the first and the first layers are formed so that the surface of the metal wiring 12 is partially exposed using the mask. The interlayer insulating film is etched to form via holes.
제 3 단계로서, 상기 비어 홀을 포함한 상기 제 2 층간 절연막 상에 도전성 플러그를 형성하므로써, 본 공정 진행을 완료한다.As a third step, the process progress is completed by forming a conductive plug on the second interlayer insulating film including the via hole.
그러나, 상기에 언급된 공정을 이용하여 반도체 소자의 다층 배선을 형성할 경우에는 다음과 같은 문제가 발생하게 된다. 다층 배선 형성시, 층간 절연막의 평탄화 특성을 향상시키기 위하여 SOG 에치백 공정을 적용하여 층간 절연막의 공극을 메꾸어 주거나 혹은 열처리 공정과 CMP 공정을 적용하여 층간 절연막을 평탄화해 주는 등의 부수적인 공정이 추가되므로, 이로 인해 공정 복잡화와 비용 상승이 초래되어져 생산성이 저하되는 현상이 발생하게 된다.However, when the multilayer wiring of the semiconductor device is formed using the above-mentioned process, the following problem occurs. When forming the multi-layered wiring, additional processes such as filling the voids of the interlayer insulating film by applying the SOG etch back process or flattening the interlayer insulating film by applying the heat treatment process and the CMP process to improve the planarization characteristics of the interlayer insulating film Therefore, this leads to process complexity and cost increase, resulting in a decrease in productivity.
이에 본 발명의 목적은, 반도체 소자의 다층 배선 형성시 SOG 에치백 공정이나 CMP 공정의 적용없이도 층간 절연막의 평탄화 특성을 향상시킬 수 있도록 공정을 변경해 주므로써, 공정 단순화에 기인한 비용 절감 효과와 생산성 향상 효과를 동시에 얻을 수 있도록 한 반도체 소자 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to change the process to improve the planarization characteristics of the interlayer insulating film without applying the SOG etch back process or CMP process when forming the multilayer wiring of the semiconductor device, thereby reducing the cost and productivity due to the process simplification The present invention provides a method for manufacturing a semiconductor device that can simultaneously obtain an improvement effect.
도 1a 내지 도 1c는 종래 반도체 소자의 다층 배선 형성방법을 도시한 공정수순도,1A to 1C are process flowcharts showing a method for forming a multilayer wiring of a conventional semiconductor device;
도 2a 내지 도 2d는 본 발명에 의한 반도체 소자의 다층 배선 형성방법을 도시한 공정수순도이다.2A to 2D are process flowcharts showing a method for forming a multilayer wiring of a semiconductor device according to the present invention.
상기 목적을 달성하기 위하여 본 발명에서는, 절연기판 상에, 상기 기판의 표면이 소정 부분 노출되도록 요홈부가 구비된 제 1 층간 절연막을 형성하는 공정과; 상기 요홈부를 포함한 상기 제 1 층간 절연막 상에 도전성막을 형성하는 공정과; 상기 요홈부 상측의 상기 도전성막 상에 감광막 패턴을 형성하는 공정과; 상기 감광막 패턴을 마스크로 이용하여 상기 도전성막을 식각하여 금속 배선을 형성하고, 상기 감광막 패턴을 제거하는 공정과; 상기 금속 배선을 포함한 상기 제 1 층간 절연막 상에, 상기 금속 배선의 표면이 소정 부분 노출되도록 비어 홀이 구비된 제 2 층간 절연막을 형성하는 공정; 및 상기 비어 홀을 포함한 상기 제 2 층간 절연막 상의 소정 부분에 도전성 플러그를 형성하는 공정으로 이루어진 반도체 소자 제조방법이 제공된다.In order to achieve the above object, in the present invention, a step of forming a first interlayer insulating film having a groove portion on the insulating substrate to expose a predetermined portion of the surface of the substrate; Forming a conductive film on the first interlayer insulating film including the recess; Forming a photosensitive film pattern on the conductive film above the recess; Etching the conductive film to form a metal wiring by using the photosensitive film pattern as a mask, and removing the photosensitive film pattern; Forming a second interlayer insulating film having a via hole on the first interlayer insulating film including the metal wiring so that a surface of the metal wiring is partially exposed; And a step of forming a conductive plug in a predetermined portion on the second interlayer insulating film including the via hole.
상기와 같이 공정을 진행할 경우, SOG 에치백 공정이나 CMP 공정의 추가없이도 층간 절연막의 평탄화 특성을 향상시킬 수 있게 되므로, 다층 배선 형성시 이들 공정을 적용할 필요가 없게 되어 공정 단순화를 기할 수 있게 된다.When the process proceeds as described above, the planarization characteristics of the interlayer insulating film can be improved without the addition of an SOG etch back process or a CMP process, so that these processes need not be applied when forming a multi-layer wiring, thereby simplifying the process. .
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 2a 내지 도 2d는 본 발명에 의한 반도체 소자의 다층 배선 형성방법을 도시한 공정수순도를 나타낸 것으로, 이를 참조하여 그 제조방법을 크게 제 4 단계로 구분하여 살펴보면 다음과 같다.2A to 2D show a process flow diagram illustrating a method for forming a multilayer wiring of a semiconductor device according to the present invention. Referring to this, the manufacturing method is divided into four steps.
제 1 단계로서, 도 2a에 도시된 바와 같이 절연기판(예컨대, 절연막이 형성되어 있는 반도체 기판)(100) 상에 UDO 재질의 제 1 층간 절연막(102)을 형성한 다음, 사진식각공정을 이용하여 제 1 층간 절연막(102)의 표면이 소정 부분 노출되도록 그 위에 감광막 패턴(104)을 형성한다. 이어, 감광막 패턴(104)을 마스크로 이용하여 제 1 층간 절연막(102)을 등방성 식각하여 기판(100) 상의 제 1 층간 절연막(102) 내에 요홈부를 형성한다.As a first step, as shown in FIG. 2A, a first interlayer insulating film 102 made of UDO material is formed on an insulating substrate (eg, a semiconductor substrate on which an insulating film is formed), and then a photolithography process is used. Thus, the photosensitive film pattern 104 is formed thereon such that the surface of the first interlayer insulating film 102 is partially exposed. Subsequently, the first interlayer insulating layer 102 isotropically etched using the photoresist pattern 104 as a mask to form recesses in the first interlayer insulating layer 102 on the substrate 100.
이와 같이 제 1 층간 절연막(102) 내에 요홈부를 형성해 준 것은, 이후 금속 배선 형성시 금속 배선을 이루는 도전성막의 일부가 요홈부 내에 충진되도록 하여 최종적으로 만들어지는 금속 배선의 높이가 제 1 층간 절연막(102)의 표면을 기준으로할 때 기존의 경우보다 1/2 이상 줄어든 효과를 얻기 위함이다.As such, the grooves are formed in the first interlayer insulating film 102. Then, when the metal wires are formed, a portion of the conductive film forming the metal wires is filled in the grooves so that the height of the metal wires finally formed is increased by the first interlayer insulating film ( Based on the surface of 102), this is to obtain an effect that is reduced by 1/2 or more than the existing case.
제 2 단계로서, 도 2b에 도시된 바와 같이 감광막 패턴(104)을 제거하고, 요홈부를 포함한 제 1 층간 절연막(102) 상에 소정 두께의 도전성막(예컨대, Al 합금이나 Cu 합금 등)(106)을 형성한 다음, 사진식각공정을 이용하여 그 위에 금속 배선 형성부를 한정하는 감광막 패턴(104)을 형성한다.As a second step, as shown in FIG. 2B, the photosensitive film pattern 104 is removed, and a conductive film (eg, an Al alloy or a Cu alloy, etc.) having a predetermined thickness is disposed on the first interlayer insulating film 102 including the recesses. ), And then using the photolithography process, a photosensitive film pattern 104 defining a metal wiring forming portion is formed thereon.
제 3 단계로서, 도 2c에 도시된 바와 같이 감광막 패턴(104)을 마스크로 이용하여 도전성막(106)을 등방성 식각하여 도전성막 재질의 금속 배선(106a)을 형성하고, 감광막 패턴(104)을 제거한다. 이때, 상기 도전성막(106)은 건식식각법이나 습식식각법을 이용하여 등방성 식각되는데, 이러한 공정은 형성하고자 하는 금속 배선의 선폭이 6 ~ 7㎛ 정도를 가질 경우에도 동일하게 적용된다.As a third step, as shown in FIG. 2C, the conductive film 106 is isotropically etched using the photosensitive film pattern 104 as a mask to form the metal wiring 106a of the conductive film material, and the photosensitive film pattern 104 is formed. Remove In this case, the conductive film 106 is isotropically etched by using a dry etching method or a wet etching method. The process is similarly applied to the case where the line width of the metal wire to be formed has a thickness of about 6 to 7 μm.
이어, 금속 배선(106a)을 포함한 제 1 층간 절연막(108) 상에 UDO 재질의 제 2 층간 절연막(108)을 형성하고, 상기 금속 배선(106a)의 표면이 소정 부분 노출되도록 이를 선택 식각하여 비어 홀(h)을 형성한다.Subsequently, a second interlayer insulating film 108 made of UDO material is formed on the first interlayer insulating film 108 including the metal wiring 106a, and selectively etched so that the surface of the metal wiring 106a is partially exposed. The hole h is formed.
이와 같이 공정을 진행할 경우, 제 1 층간 절연막(102)의 표면을 기준으로 했을 때 금속 배선(106a)의 두께가 기존의 경우보다 1/2 이상 줄어든 상태에서 제 2 층간 절연막(108)의 증착 공정이 이루어진 효과를 얻을 수 있게 되므로, SOG 에치백 공정이나 혹은 열처리와 CMP가 조합된 공정의 적용없이도 제 2 층간 절연막(108)의 평탄화 특성을 기존과 동일한 수준까지 향상시킬 수 있게 된다. 이로 인해, 다층 배선 형성시 이들 공정을 스킵(skip)할 수 있게 되는 것이다.When the process is performed in this way, the deposition process of the second interlayer insulating film 108 in a state in which the thickness of the metal wiring 106a is reduced by 1/2 or more compared with the conventional case based on the surface of the first interlayer insulating film 102. Since this effect can be obtained, the planarization characteristics of the second interlayer insulating film 108 can be improved to the same level as before without the application of the SOG etch back process or the combination of heat treatment and CMP. For this reason, these processes can be skipped at the time of forming a multilayer wiring.
제 4 단계로서, 도 2d에 도시된 바와 같이 비어 홀(h)을 포함한 제 2 층간 절연막(108) 상의 소정 부분에 도전성 플러그(110)를 형성하여, 금속 배선(106a)과 도전성 플러그(110)가 서로 전기적으로 접속되도록 하므로써 본 공정 진행을 완료한다.As a fourth step, as shown in FIG. 2D, the conductive plug 110 is formed in a predetermined portion on the second interlayer insulating film 108 including the via hole h, thereby forming the metal wire 106a and the conductive plug 110. This process is completed by allowing the to be electrically connected to each other.
이상에서 살펴본 바와 같이 본 발명에 의하면, 단순 공정 변경을 통하여 SOG 에치백 공정이나 CMP 공정의 추가없이도 층간 절연막의 평탄화 특성을 현격하게 향상시킬 수 있게 되므로, 다층 배선 형성시 이들 공정의 적용이 필요없게 되어 공정 단순화와 비용 절감 및 생산성 향상 효과를 동시에 얻을 수 있게 된다.As described above, according to the present invention, the planarization characteristics of the interlayer insulating film can be improved remarkably without the addition of the SOG etch back process or the CMP process through a simple process change, so that the application of these processes is unnecessary when forming the multilayer wiring. This simplifies the process, reduces costs and increases productivity.
Claims (4)
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| KR1019980009723A KR100273114B1 (en) | 1998-03-20 | 1998-03-20 | Method for manufacturing semiconductor device |
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