KR20010010171A - Method for forming electrical interconnection using dual damascene process - Google Patents

Abstract

PURPOSE: A method for forming a dual damascene wiring is provided to make a dual damascene wiring having a fine line width, by forming a topology having a small step difference on a semiconductor substrate after filling inorganic SOG layer in a via contact hole. CONSTITUTION: A first insulation layer pattern for defining a via contact hole is formed on a semiconductor substrate. Inorganic SOG layer fills the via contact hole so as to expose an upper surface of the first insulation layer pattern. A second insulation layer pattern for defining a wiring area(42) is formed on the first insulation layer pattern. The inorganic SOG layer for filling the via contact hole is etched and removed. A conductive material fills the exposed via contact hole and the exposed wiring area, thereby making a dual damascene wiring.

Description

Method for forming electrical interconnection using dual damascene process

The present invention relates to a method for forming dual damascene wiring in the manufacture of semiconductor integrated circuit devices.

Recently, the dual damascene process has been widely used in forming metal interconnections of semiconductor integrated circuit devices. In the dual damascene process, a dual damascene wiring pattern defining a via contact hole and a wiring region is generally formed and a physical deposition process is performed to fill the dual damascene wiring pattern with a conductive material to complete the dual damascene wiring. It includes a step.

However, when forming a pattern defining the dual damascene wiring according to the prior art, various problems may occur. Hereinafter, the problems of the prior art will be described in detail with reference to the accompanying drawings.

1 and 2, in order to form a dual damascene wire as shown in FIG. 1, first, an interlayer insulating film pattern 14 defining a via contact hole 12 is formed on an upper portion of a semiconductor substrate 10. Form. Next, a photosensitive film pattern 16 defining a metal wiring region 18 (see FIG. 3) is formed on the interlayer insulating film pattern 14.

3 is a cross-sectional view illustrating an etching profile after performing an etching process to form the metal wiring region 18.

Referring to FIG. 3, an etching process is performed using the photoresist pattern 16 as an etching mask to form the metal wiring region 18. However, during the etching process, the bottom and sidewalls of the via contact hole 12 are also etched to damage the via contact hole profile shown by the dotted line. Although the metallization region 18 is formed using a dry etching method having excellent anisotropic etching characteristics to form the via contact hole 12 having a right angle profile as shown by the dotted line, the via contact hole 12 is formed. It is also difficult to keep the sidewall profile completely vertical, as well as the surface (eg source or drain) on the semiconductor substrate exposed by the via contact hole 12 during the process of forming the metallization region 18. In the case of a semiconductor device having a multi-layer wiring structure or the like, an upper portion of the exposed lower wiring layer is etched to a predetermined depth d1. Therefore, when the via contact hole 12 is first patterned in one interlayer insulating film 14 and then the metal wiring region 18 is formed as described with reference to FIGS. 2 and 3, the via contact hole 12 is formed. It can be seen that the profile of the sidewalls does not remain in the desired shape (dotted line).

1 and 4, in order to form a dual damascene wiring as shown in FIG. 1, first, an interlayer insulating film 14 for forming a metal wiring region 18 is formed and an upper portion of the interlayer insulating film 14 is formed. The photosensitive film pattern 16 which defines the metal wiring area | region 18 is formed in this. Next, the interlayer insulating film 14 is etched using the photoresist pattern 16 as an etch mask to form the metal wiring region 18.

Referring to FIG. 5, after the photoresist pattern 16 (see FIG. 3) is removed, the photoresist 20 may be formed to form a photoresist pattern defining a via contact hole on the interlayer insulating layer 14 on which the metal wiring region 18 is formed. ) Is applied. Next, a photolithography process should be performed to form a photoresist pattern (dotted line) to define the via contact hole. By the way, in order to form the photosensitive film pattern (dotted line) of a preferable form, the upper surface of the applied photosensitive film 20 should be flat. However, as can be seen from FIG. 5, when the metal wiring region 18 is formed before the via contact hole in one interlayer insulating film 14, the flatness of the photosensitive film 20 coated to form the photosensitive film pattern is formed. The degree falls, and thus there is a problem in that it is difficult to form a preferred photoresist pattern such as a dotted line.

Therefore, the technical problem to be achieved by the present invention is to provide a dual damascene wiring forming method that can solve the problems of the conventional dual damascene wiring forming method.

1 is a layout for a dual damascene wiring completed by the prior art.

2 and 3 are cross-sectional views of an exemplary embodiment of a pattern forming method for defining a dual damascene wiring according to the related art, but according to line AA ′ of FIG. 1.

4 and 5 are cross-sectional views illustrating another exemplary embodiment of a pattern forming method for defining a dual damascene wiring according to the related art, in accordance with line AA ′ of FIG. 1.

6 to 13 are process cross-sectional views showing an embodiment of a dual damascene wire forming method according to the present invention.

14 to 16 are cross-sectional views illustrating another embodiment of the method for forming a dual damascene wire according to the present invention.

In the dual damascene wiring forming method of the present invention, the first insulating film pattern defining the via contact hole is formed on the semiconductor substrate, and then the upper surface of the first insulating film pattern is exposed. A spin on glass (SOG) film is filled in the via contact hole. Next, after forming a second insulating film pattern defining a wiring region on the first insulating film pattern, the inorganic SOG film is removed. Finally, the inorganic SOG film is removed to fill the exposed via contact hole and wiring region with a conductive material to complete the dual damascene wiring.

In addition, the dual damascene wiring forming method according to the present invention may proceed as follows. First, a first insulating layer pattern defining a via contact hole is formed on the semiconductor substrate, and then an inorganic SOG film is filled in the via contact hole so that the upper surface of the first insulating layer pattern is exposed. Subsequently, a second insulating film is formed on the first insulating film pattern and the inorganic SOG film, and the second insulating film is etched so that the lower portion of the second insulating film remains to a predetermined thickness and the inorganic SOG film is removed. Finally, the second insulating layer existing on the via contact hole is removed while forming a third insulating layer pattern defining a wiring region on the remaining first insulating layer. Finally, the conductive material is filled in the via contact hole and the wiring region to complete the dual damascene wiring.

The inorganic SOG film filling the via contact hole has a chemical formula of Si _x O _y H _z , and it is more preferable to fill the via contact hole by selecting HSQ (Hydrogen Silsesquioxna) as the inorganic SOG.

The process of removing the inorganic SOG film may be performed using a wet etching method, but the wet etching process may be performed using a buffered oxide etchant (BOE) or diluted hydrofluoric acid (HF) solution as an etchant.

Hereinafter, a method of forming dual damascene wiring according to the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings, the thicknesses of layers or regions are exaggerated for clarity. In the drawings like reference numerals refer to like elements. In addition, if a layer is described as being on top of another layer or substrate, the layer may be present directly on top of the other layer or substrate and a third layer may be interposed therebetween.

6 to 13 are cross-sectional views illustrating a preferred embodiment of the method for forming a dual damascene wire according to the present invention.

Referring to FIG. 6, first, an interlayer insulating film is formed on the semiconductor substrate 30. Next, the interlayer insulating layer is patterned using a photolithography technique to form the first insulating layer pattern 34 defining the via contact hole 32. The interlayer insulating film is preferably formed of silicon oxide, silicon nitride or silicon oxynitride. The forming of the via contact hole 32 is preferably performed by a dry etching method so that the sidewall has a vertical profile. In addition, a bottom portion of the via contact hole 32 exposes an upper surface of the semiconductor substrate 30, and the semiconductor substrate 30 includes a source / drain region, a gate electrode, or a multilayer wiring structure of a transistor formed on the semiconductor substrate 30. In the case of the semiconductor device having a may be a lower wiring layer.

Referring to FIG. 7, the inside of the via contact hole 32 defined by the first insulating layer pattern 34 is filled with the inorganic SOG film 35. In some cases, the via contact hole 32 may be filled with BoroPhosphoSilicate Glass (BPSG), BoroSilicate Glass (BBG), UndoppedSilicate Glass (USG), PhosphoSilicate Glass (PSG), or TetraEthoxylosilane (TEOS) -oxide having good step coverage. Although it is possible to fill the inside of the via contact hole 32 with the inorganic SOG film 35, the reason why the inorganic SOG film 35 is more preferable than BPSG, PSG, BSG, USG, and TEOS-oxide is as follows. .

In order to complete the dual damascene wiring according to the present invention, a process of removing an insulating material (eg, an inorganic SOG film) filled in the via contact hole 32 must be performed, for example, an etching process. However, in recent years, as the degree of integration of semiconductor devices increases, the design rule of the dual damascene wiring pattern is also decreasing. Therefore, the insulating film pattern profile defining the dual damascene wiring pattern is extremely fine, so as not to damage the insulating film pattern defining the dual damascene wiring pattern in a process that is performed before the step of filling the conductive material in the dual damascene wiring pattern. This is a very important task. In order to effectively remove the insulating material (eg, inorganic SOG film) while maintaining the dual damascene wiring pattern in a desirable profile, the etching rate of the insulating material must be much larger than the insulating film pattern defining the dual damascene wiring pattern (ie, etching selection). The rain should be big). Therefore, it is preferable to proceed with the step of removing the insulating material using a wet etching method of the dry or wet etching method. In the wet etching process, for example, the wet etching process using BOE or diluted hydrofluoric acid solution as an etchant, the inorganic SOG film 35 has a wet etching rate 10 times higher than that of the BPSG, BSG, PSG, USG, and TEOS-oxide films. As described above, filling the via contact hole 32 with the inorganic SOG film 35 rather than filling the via contact hole 32 with BPSG, PSG, BSG, USG, or TEOS-oxide is used to define the profile of the insulating film pattern defining the dual damascene wiring pattern. It is easier to remove the inorganic SOG film 35 without damaging it. In addition, the inorganic SOG film 35 not only has a high etching selectivity with respect to the first insulating film pattern 34 (for example, silicon oxide) defining the via contact hole 32, but also has excellent step coverage characteristics and film quality. It has several advantages, including less defects.

The inorganic SOG film 35 has a chemical formula of Si _x O _y H _z , and the inorganic SOG film 35 is preferably filled with the via contact hole 32 by selecting HSQ.

Referring to FIG. 8, the entire surface of the semiconductor substrate 30 on which the inorganic SOG film 35 (see FIG. 7) is formed is planarized. The planarization is performed until the upper surface of the first insulating film pattern 34 is exposed, and is preferably performed by chemical mechanical polishing (CMP) or etch back. As shown in FIG. 8, after the planarization process is finished, an upper surface of the first insulating layer pattern 34 is exposed. In order to ensure that the upper surface of the first insulating film pattern 34 is exposed in the planarization process, the upper surface of the inorganic SOG film 35 is slightly recessed than the upper portion of the first insulating film pattern 34. The planarization process may be performed as much as possible, but the first insulating film pattern (see FIG. 9) may be used to improve the global flatness of the insulating film 38 (see FIG. 9) formed on the inorganic SOG film 35 and the first insulating film pattern 34. More preferably, the planarization process is performed such that the upper surface of 34) and the upper surface of the inorganic SOG film 35 coincide with each other.

Referring to FIG. 9, a planarization process is performed to form a second insulating film 38 for forming wiring regions on the entire surface of the planarized semiconductor substrate 30. Next, a photoresist film is coated on the second insulating film 38 and a photographic process is performed to form the photoresist pattern 40 for forming the wiring area. Since the second insulating film 38 is formed on the first insulating film pattern 34 and the inorganic SOG film 35 which are globally planarized through the planarization process, the upper surface thereof has a uniform flatness and is formed on the second insulating film 38. Since the formed photoresist film also has a good flatness of the upper surface of the second insulating film 38, which is a lower film thereof, the upper surface has a uniform flatness. The second insulating film 38 is formed by selecting an insulating material having an appropriate dielectric constant in consideration of the parasitic capacitance occurring in the multi-layered wiring structure, but preferably, silicon oxide, silicon nitride, or silicon oxynitride. In the case of a semiconductor integrated circuit device having a multilayer wiring structure, the thickness of the second insulating film 38 should be determined in consideration of the parasitic capacitance between wiring layers caused in the multilayer wiring structure and the three-dimensional topology of the semiconductor integrated circuit device. Preferably it is between 500 kV and 3000 kV.

Referring to FIG. 10, the second insulating film 38 is etched using the photoresist pattern 40 (see FIG. 9) as an etching mask, but the second insulating film 38 is etched until the upper surface of the inorganic SOG film 35 is exposed. A second insulating film pattern 38 ′ defining s is formed. After forming the second insulating film pattern 38 ′, the photosensitive film pattern 40 (see FIG. 9) is removed. The etching process is preferably carried out by a dry etching method to form a wiring region 42 having a vertical profile of the sidewalls.

Referring to FIG. 11, the via contact hole 32 and the wiring area 42 are formed by completely removing the inorganic SOG film 35 (see FIG. 10) exposed by the forming of the second insulating film pattern 38 ′. A dual damascene wiring pattern is formed. The removal of the inorganic SOG film 35 is preferably performed by a wet etching method, and the etching end point is preferably an upper surface of the semiconductor substrate 30 exposed by the via contact hole 32. As an etchant for performing the wet etching process on the inorganic SOG film 35, it is preferable to select and use a high etching selectivity for the first insulating film pattern 34 and the second insulating film pattern 38 '. Or it is preferable to use diluted hydrofluoric acid solution.

Referring to FIG. 12, a conductive material is filled in a dual damascene wiring pattern including the via contact hole 32 and the wiring region 42. Next, the entire surface of the semiconductor substrate 30 filled with the conductive material is planarized to expose the upper portion of the second insulating layer pattern 38 ′, thereby completing the dual damascene wiring 44. The conductive material may be aluminum, gold, silver, tungsten, polysilicon doped with impurities, or an alloy thereof. However, since the conductive material to be filled in the dual damascene wiring pattern is preferably the smaller the specific resistance, it is more preferable to fill copper in the dual damascene wiring pattern. In addition, instead of filling one type of conductive material in the dual damascene wiring pattern, it is also possible to fill and fill various types of conductive materials in the dual damascene wiring pattern in a layered structure. For example, the via contact hole 32 may be filled with aluminum, and the wiring area 42 may be filled with copper to complete the dual damascene wiring 44.

Referring to FIG. 13, in some cases, another conductive material layer 46 may be formed before the conductive material is filled in the dual damascene wiring pattern. Another conductive material layer 46 is preferably formed of a double film of Ti / TiN. The another conductive material layer 46 is not limited to a double film of Ti / TiN, but is not limited to titanium (Ti), zirconium (Zr), half ni 윰 (Hf), vanadium (V), molybdenum (Mo), and titanium. It may be a single layer of (Ta) or chromium (Cr) or a layered structure of two or more bilayers therebetween. In some cases, the another conductive material layer 46 may include titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), molybdenum (Mo), titanium (Ta), or chromium (Cr). It may be a nitride (Nitride), carbide (Carbide) or silicide (Silicide).

A preferred embodiment of the method for forming a dual damascene wire according to the present invention described with reference to FIGS. 6 to 13 has been performed to remove the inorganic SOG film after completing the insulating film pattern defining the wiring area. Another preferred embodiment of the dual damascene wiring forming method of the present invention in which the inorganic SOG film is removed before forming the insulating film pattern 50 (see FIG. 16) defining the wiring area is described with reference to FIGS. 14 to 16. Explain.

Forming a first insulating film pattern defining a via contact hole on the semiconductor substrate and filling the via contact hole with an inorganic SOG film to expose an upper surface of the first insulating film pattern with reference to FIGS. 6 to 8. Since the same process as in the preferred embodiment of the present invention described above, detailed description of the two steps will be omitted.

Referring to FIG. 14, a second insulating film 48 is formed on the first insulating film pattern 34 and the inorganic SOG film 35. The second insulating film 48 is preferably formed of silicon oxide, silicon nitride or silicon oxynitride.

Referring to FIG. 15, a portion of the lower portion of the second insulating film 48 remains, and the inorganic SOG film 35 is etched to remove it. Since the second insulating layer 48 has a pinhole (not shown) which is generally a kind of defect, an etchant penetrates into the via contact hole 32 through the pinhole to remove the inorganic SOG film 35. Since the etching process must remove the inorganic SOG film 35 while remaining under the second insulating film 48 and must not damage the sidewall profile of the via contact hole 32, An etching process with an etching selectivity must be selected. Therefore, the wet etching process may be performed to remove the inorganic SOG film 35 existing under the second insulating film 48. In selecting the etchant of the wet etching process, it should be selected that the inorganic SOG film 35 can be etched and removed faster than the first insulating film pattern 34 or the second insulating film 48. It is preferable to proceed with the wet etching process by selecting a hydrofluoric acid solution as an etchant. When the wet etching process is performed using the etchant under appropriate etching process conditions, a portion of the lower portion of the second insulating film 48 remains as shown in FIG. 15, and the inorganic SOG film 35 is removed.

Referring to FIG. 16, a third interlayer insulating film is formed on the remaining second insulating film 48 to have a predetermined thickness. Next, a photolithography process is performed on the third interlayer insulating film to form a third insulating film pattern 50 defining the wiring area 42, thereby forming dual damascene comprising the via contact hole 32 and the wiring area 42. A wiring pattern is formed. The third interlayer insulating film is preferably formed of silicon oxide, silicon nitride or silicon oxynitride.

After the dual damascene wiring pattern is formed, a dual damascene wiring is completed by filling a conductive material in the dual damascene wiring pattern as described with reference to FIGS. 12 and 13, and in some cases, the conductive material. Another conductive material layer may be filled before this is filled. Since the conductive material and another conductive material layer are the same as the conductive material and another conductive material layer described with reference to FIGS. 12 and 13, a detailed description thereof will be omitted.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical idea of the present invention.

By filling the inorganic SOG film in the via contact hole to form a topology with a small step height on the upper surface of the semiconductor substrate, an insulating film pattern for the wiring area is stably formed. In addition, by filling the via contact hole with an inorganic SOG film having a very high etch selectivity for the insulating film pattern defining the via contact hole and the insulating film pattern defining the wiring area, the profile of the dual damascene wiring pattern is maintained even if the inorganic SOG film is removed in a subsequent process. It is not damaged very much.

Claims (6)

(a) forming a first insulating film pattern defining a via contact hole on the semiconductor substrate; (b) filling an inorganic SOG film into the via contact hole so that an upper surface of the first insulating film pattern is exposed; (c) forming a second insulating film pattern defining a wiring region on the first insulating film pattern; (d) etching away the inorganic SOG film filled in the via contact hole; (e) filling the conductive material in the via contact hole and the wiring region exposed by removing the inorganic SOG film to complete the dual damascene wiring. The method of claim 1, wherein the inorganic SOG film is HSQ. The method of claim 1, wherein the step (d) is a wet etching process using BOE or diluted hydrofluoric acid solution as an etchant. (a) forming a first insulating film pattern defining a via contact hole on the semiconductor substrate; (b) filling an inorganic SOG film into the via contact hole so that an upper surface of the first insulating film pattern is exposed; And (c) forming a second insulating film on the first insulating film pattern and the inorganic SOG film; (d) performing an etching process on the second insulating film so that the lower portion of the second insulating film remains at a predetermined thickness and the inorganic SOG film is removed; (e) removing the second insulating film on the top of the via contact hole while forming a third insulating film pattern defining a wiring region on the remaining second insulating film; And (f) filling the conductive region in the wiring region and the via contact hole to complete the dual damascene wiring. 5. The method of claim 4, wherein the inorganic SOG film is HSQ. 5. The method of claim 4, wherein step (d) is a wet etching process using BOE or diluted hydrofluoric acid solution as an etchant.