JPH11150114A - Semiconductor device and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of dishing phenomenon of thinning phenomenon. SOLUTION: Via holes 35a and 35b are respectively formed on an interlayer insulating film 33 on wiring patterns 31a and 31b. An insulating member 37 constitute of the interlayer insulating film is formed vertically to a semiconductor substrate in the via hole 35a. An interlayer insulating film 39 is formed on the interlayer insulating film 33. Pads 41a and 41b are respectively formed on the interlayer insulating film 39 on the via holes 35a and 35b. An insulating member 43 constituted of the interlayer insulating film is formed in a direction vertical to the semiconductor substrate in the pad 41a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device in which a wiring or the like is embedded in a groove and a method for manufacturing the same.

[0002]

2. Description of the Related Art At present, various problems have become remarkable with respect to VLSI multilayer wiring technology. Above all, when the wiring is multi-layered for the purpose of higher integration of the wiring density, the absolute step becomes larger as the wiring becomes higher, so that the margin of the depth of focus in the lithography process of forming the wiring becomes narrower, and the formation of fine wiring becomes difficult. It becomes difficult. So 3
For a multi-layer wiring of more than one layer, complete complete planarization is indispensable. As a solution, a CMP (Chemical Mechanical Polishing) method for polishing an insulating film or a metal film has been spotlighted. In the CMP method, a wafer is pressed against a polishing pad attached to a surface plate while flowing a polishing liquid (hereinafter referred to as slurry) containing silica particles and the like, and the surface plate is rotated while applying a weight to the wafer to select only convex portions. This is a method of polishing.

[0003] A process of forming trench wiring using this technique has been proposed by, for example, CWKaanta et al. (VMIC Conference 1991, p. 144). Groove wiring, especially dual damascene (dual) that simultaneously forms wiring and via holes
The process of the damascene method will be described with reference to FIGS.

(A) First, on a lower metal wiring 1 made of aluminum or the like formed on a semiconductor substrate via an insulating film,
A silicon oxide film 3 is formed on the entire surface as an interlayer insulating film.
Thereafter, a photoresist 5 is formed on the silicon oxide film 3, and an opening 7 for an upper wiring is formed in the silicon oxide film 3 by a lithography process and an oxide film etching process. (B) Next, after removing the photoresist 5, a photoresist 9 is newly formed, and an opening 11 for a via hole connecting the lower wiring and the upper wiring is formed by a lithography process and an oxide film etching process. (C) After removing the photoresist 9, a wiring film 13 of aluminum or the like is formed on the entire surface of the substrate by sputtering or CVD. (D) Thereafter, the wiring 15 and the via hole 17 can be formed by polishing the wiring film 13 to the silicon oxide film 3 by using the CMP method.

However, when two or more types of films having the same height from the semiconductor substrate are actually polished at the same time, the difference in the polishing rate causes the film thickness at the center of the pattern formed of the film having a high polishing rate. And a dishing phenomenon, that is, a depression occurs. FIG. 2A is a schematic diagram illustrating the dishing phenomenon. An opening 21 is formed in the silicon oxide film 19, and a metal 23 such as aluminum formed by a CMP method is formed in the opening 21. A depression is formed in the metal 23. Since the difference between the polishing rates of the insulating film and the metal film is remarkable, a dishing phenomenon is likely to appear, particularly in a large area such as a bonding pad. As a result, in the worst case, the metal in the bonding pad area may be lost.

Further, the insulating film and the metal film in the wiring portion are polished at the same time, and a thinning phenomenon that the entire wiring becomes thin may occur. FIG. 2 (B)
FIG. 3 is a schematic diagram illustrating a thinning phenomenon. A plurality of openings 27 for wiring patterns are formed in the silicon oxide film 25, and a metal 29 such as aluminum formed by a CMP method is formed in the openings 27. At the center of the region where a plurality of wiring patterns are formed, a depression is formed due to a thinning phenomenon. In a region where the wiring pattern is formed in close proximity, the insulating film forming the pattern may be excessively polished, and in the worst case, the pattern may be lost.

To prevent the occurrence of such wiring defects,
For example, even if dishing occurs, a groove in the bonding pad area is formed in advance deeper than other metal wiring so that the metal in the bonding pad area is not lost.
A method has been proposed in which metal in the pad region is left (see Japanese Patent Application Laid-Open No. 7-130737 (conventional example)).

[0008]

However, the above-mentioned prior art is not a fundamental solution for preventing dishing. For example, when a depression of 1 μm is formed in a pad region, a similar trench wiring is formed in an upper layer. When an insulating film is formed to cover the pad region, the insulating film near the upper portion of the pad region has a thickness of about 1 μm.
Will occur. This step has an adverse effect on the subsequent lithography step and oxide film etching step, and may cause abnormalities in dimensions and resistance value.

Accordingly, the present invention prevents the occurrence of dishing and thinning phenomena when forming a wide wiring portion such as a bonding pad region with a groove wiring, thereby improving the wiring reliability and yield of a semiconductor device. It is intended for.

[0010]

According to the present invention, there is provided a semiconductor device in which two or more layers of multilayer wiring are used, and the wiring of each layer is insulated by an interlayer insulating film.
In the metal pattern formed in the pad region and the wiring region in the semiconductor substrate and the multilayer wiring, there is provided an insulating member continuous from the top surface to the bottom surface of the metal pattern. For example, in a pad region or a wiring region having a maximum width of 10 μm or more,
Since the insulating member is provided continuously from the top surface to the bottom surface of the metal pattern forming the pad region or the wiring region, dishing that occurs when the pad region and the wiring region are formed is not formed.

The method of manufacturing a semiconductor device according to the present invention is characterized in that, when an interlayer insulating film on a pad region is etched in order to form a pad region and a wiring region in a semiconductor substrate and a multilayer wiring, the pad region, the wiring region or the same is etched. An insulating member pattern composed of an interlayer insulating film continuous from the top surface to the bottom surface of the pad region or the wiring region is left in both regions.
In a pad region or a wiring region having a maximum width of, for example, 10 μm or more, a continuous insulating member pattern is left from the top surface to the bottom surface of the pad region or the wiring region. When the region and the wiring region are formed, the occurrence of the dishing phenomenon can be suppressed.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device has a plurality of insulating members in one pad area or one wiring area;
It is preferable that these insulating members are not in contact with other insulating members or interlayer insulating films. As a result, a pad area or a wiring area having a large area can be formed without any electrically isolated metal pattern in the pad area or the wiring area. The minimum size of the insulating member is preferably 1 μm or more. As a result, the thinning phenomenon can be suppressed. One insulating member and another insulating member adjacent thereto,
Alternatively, the distance between the insulating member adjacent to the interlayer insulating film and the interlayer insulating film is preferably 10 μm or less. As a result, the dishing phenomenon can be effectively suppressed.

In the method of manufacturing a semiconductor device, a plurality of insulating member patterns made of an interlayer insulating film are provided in one pad region, and each of the insulating member patterns is used for both another insulating member pattern and an interlayer insulating film. Preferably not in contact. As a result, an electrically isolated metal pattern is eliminated in the pad region or the wiring region, and a pad region or a wiring region having a large area can be formed. The minimum size of the insulating film member pattern is preferably 1 μm or more. As a result, the thinning phenomenon can be suppressed. It is preferable that the distance between another insulating member pattern adjacent to one insulating member pattern or the insulating member pattern adjacent to the interlayer insulating film and the interlayer insulating film is 10 μm or less. As a result, the dishing phenomenon can be effectively suppressed.

A dual hole in which a connection hole for electrically connecting between a pad region formed in an upper wiring and a pad region formed in a lower wiring is formed simultaneously with a pad region formed on the connection hole. In the case of using the damascene method, it is preferable that the connection hole is formed in the same pattern as the pattern of the pad region. As a result, the connection area between the upper pad region and the lower pad region increases, and electrical conduction between the wirings can be reliably obtained. Further, the layout design of the pad region can be easily performed.

[0015]

3A and 3B are views showing an embodiment of a semiconductor device according to the present invention, wherein FIG. 3A is a sectional view of a wiring portion, and FIG. 3B is a top view of a pad region in FIG. (C) is a top view of a pad region of another embodiment, and a cross-sectional view is the same as (A). On a semiconductor substrate (not shown) covered with an insulating film (not shown), wiring patterns 31a and 31b made of a metal such as Al-Si-Cu are formed. An interlayer insulating film 33 made of, for example, a silicon oxide film is formed so as to cover the wiring patterns 31a and 31b. Via holes 35a and 35b are formed in the interlayer insulating film 33 on the wiring patterns 31a and 31b, respectively, and a metal such as Al-Si-Cu is buried in the via holes 35a and 35b. An insulating member 3 made of an interlayer insulating film is provided in the via hole 35a in a direction perpendicular to the semiconductor substrate.
7 are formed. On the interlayer insulating film 33, an interlayer insulating film 39 is formed. Pads 41a and 41b are provided in the interlayer insulating film 39 on the via holes 35a and 35b, respectively.
Is formed of a metal such as Al-Si-Cu, for example. In the pad 41a, in a direction perpendicular to the semiconductor substrate,
An insulating member 43 made of an interlayer insulating film is formed.

The shape of the insulating member 43 is not limited to the shape shown in, for example, (B) or (C), but the insulating member 43 and the insulating member 43 adjacent thereto, or the interlayer insulating film 39 and the adjacent insulating film 39 adjacent thereto. The distance between the insulating members 43 is 10 μm.
m or less. Further, it is preferable that the dimension of the minimum portion viewed from the upper surface of the insulating member 43 is 1 μm or more. Further, it is preferable to form the insulating member 43 as shown in (B) or (C) so that all the metal formed on the pad 41a is electrically connected.

The size of the via hole is preferably smaller than the width of the wiring having the minimum width among the wirings formed on the substrate and the multilayer wiring. As a result, an increase in the groove width of the metal wiring portion can be suppressed, and dishing can be suppressed. In this case, when the number of via holes is increased and the upper and lower wirings are electrically connected at a plurality of locations, electrical conduction between the upper and lower wirings can be reliably obtained.

FIGS. 4 and 5 are process diagrams showing one embodiment of a method of manufacturing a semiconductor device according to the present invention. In this embodiment, an example in which the present invention is applied to a second layer in a semiconductor device having three wiring layers will be described. Here, it is simply applied to only two layers, but there is no problem when applying from the first layer.

(A) An insulating film (not shown) is formed on a silicon substrate (not shown) on which a transistor portion is formed.
The insulating film is planarized by using a CMP method. Next, for example, after forming Al-Si-Cu by, for example, a sputtering method,
First wiring patterns 31a and 31b are formed. The metal used for the wiring patterns 31a and 31b is Al-Cu, C
u, W or the like may be used without particular limitation, and it goes without saying that a film forming method may be a sputtering method or a CVD method. For example, PETEOS (Plasma Enhansment-Tetra Eth
yl Ortho Silicate: Plasma CVD using TEOS as raw material
A first interlayer insulating film 45 such as an oxide film formed by a method is deposited, and the interlayer insulating film 45 is planarized by a CMP method using a silica-based slurry. If the thickness of the interlayer insulating film 45 becomes smaller than the sum of the design value of the depth of the first via hole and the thickness of the second wiring pattern formed in a later step, the thickness becomes the design value. The interlayer insulating film 45 is redeposited so as to be equal to.

Next, after forming a photoresist pattern 47 for trench wiring, the interlayer insulating film 45 is etched so that a part of the interlayer insulating film 45 on the wiring pattern 31a remains as an insulating member 45a. The openings 49a and 49b for the wiring pattern are formed. At this time, the opening 49
The pattern 45a of the interlayer insulating film 45 left in FIG.
It is patterned into a rectangular shape or a square shape as shown in FIG. In this shape, it is preferable that the metal to be buried in the opening 49a is patterned so that isolated metal does not occur in the opening 49a. That is, the insulating members 45a of the interlayer insulating film 45 remaining after being patterned in the openings 49a may be isolated, and may be patterned so as not to be in contact with the other insulating members 45a and the interlayer insulating film 45. The distance between the insulating member 45a and another adjacent insulating member 45a and the distance between the interlayer insulating film 45 and the nearest insulating member 45a (width of the groove) are as follows:
When the thickness is 10 μm or less, it is effective for preventing dishing. Wirings and pads formed by the openings 49a are 10
This is particularly effective in the case of a wide wiring or pad having a width of μm or more.

(B) Next, the photoresist pattern 47
Is removed, a photoresist pattern 51 is formed,
The interlayer insulating film 45 is etched to form openings 53a,
53b is formed. In the case where the opening 49a is a wide wiring or pad having a width of 10 μm or more, it is preferable to arrange a plurality of via holes under the opening 49a in such a number that conduction can be ensured. Further, the via hole under the pad region may be formed in the same pattern as the opening 49a.

(C) After removing the photoresist pattern 51, a metal film such as Al-Si-Cu is deposited on the substrate by, for example, a sputtering method, and the metal films are buried in the openings 49 and 53. Next, CMP of the metal film is performed with a slurry using, for example, alumina as an abrasive, and a portion where the interlayer insulating film 45 is exposed is defined as an end point of the CMP. Thereafter, after cleaning with a chemical such as HF, the via holes 55a,
Simultaneous formation of 55b and second wiring patterns 57a and 57b is completed. At this time, the wiring pattern 57a is
The structure is as shown in (B) and (C). As a result, even if the wiring pattern 57a is a wide wiring or pad region having a width of 10 μm or more, the dishing phenomenon and the thinning phenomenon occur because the insulating member 45a including the interlayer insulating film 45 is formed in a slit shape or a lattice shape. Can be suppressed. In the case where the wiring is multilayered, the above steps are repeated.

Subsequently, a via hole and a metal wiring in the uppermost layer are formed. However, the uppermost layer of the metal wiring does not require much flatness, and is manufactured here by a conventional method. (D) First, after depositing a second interlayer insulating film 59 made of, for example, a PETEOS film, openings 61a and 61b for second via holes are formed on the wiring patterns 57a and 57b by lithography and etching. .

(E) After that, a metal such as Al-Si-Cu which is to be the uppermost wiring pattern is deposited by, for example, a sputtering method, and then a high pressure of, for example, 700 kg / cm ² is applied to open the openings 61a, 61b. Is filled with metal to form via holes 65a and 65b. Next, the wiring patterns 63a, 63a are formed by lithography and etching.
3b is formed. At this time, the wiring pattern 63a is
Even in the case of a wide wiring or a pad region having a width of m or more, a sheet shape is sufficient since flatness is not so required. (F) Finally, after depositing the passivation film 65,
The process is completed by opening the wiring pattern 63a.

By using the above manufacturing method, it is possible to prevent dishing or thinning occurring in a wide metal portion such as a pad region of a wiring layer at the time of metal CMP, and to suppress poor wiring continuity. Wiring reliability and yield can be improved.

FIG. 6 is a diagram showing the relationship between the metal line width and the wiring depth when metal CMP is performed while changing the polishing time. The metal wirings are isolated or arranged at equal intervals. The horizontal axis represents the width of the metal wiring, the vertical axis represents the depth of the metal wiring after CMP, and the symbols in the graph each represent the polishing time (see legend). From this figure, the metal width (groove width)
Of 10 μm or less is effective for preventing dishing.

Further, it is effective to prevent thinning that the short side of the interlayer insulating film left in the opening for pad or wiring by patterning is 1 μm or more. FIG. 7 shows the relationship between the metal line width and the wiring depth when the metal of the trench wiring is buried with high-pressure aluminum and then subjected to CMP of the metal. The metal wiring has two types of film thickness (700 μm, 800
μm) and are isolated or arranged at equal intervals. Compared to Fig. 6, the one embedded with high-pressure aluminum
It can be seen that thinning occurs in the lines arranged at equal intervals with a line width of 1 μm or less. From this figure, it can be seen that setting the metal width (groove width) to 1 μm or more is effective in preventing thinning.

[0028]

As described above, the semiconductor device according to the present invention is provided with an insulating member that is continuous from the top surface to the bottom surface of the metal pattern in the metal pattern formed in the pad region and the wiring region in the semiconductor substrate and the multilayer wiring. In addition, dishing that occurs when the pad region and the wiring region are formed is not formed, and highly reliable electrical conduction between the upper and lower layers can be obtained. The semiconductor device includes a plurality of insulating members in one pad region or a wiring region, and the insulating members do not come into contact with other insulating members or the interlayer insulating film. Thus, a pad region or a wiring region having a large area without an electrically isolated metal pattern can be formed. When the minimum dimension of the insulating member is 1 μm or more, the thinning phenomenon can be suppressed. If the distance between one insulating member and another insulating member adjacent thereto or between the insulating member adjacent to the interlayer insulating film and the interlayer insulating film is 10 μm or less, the dishing phenomenon can be effectively suppressed.

The method of manufacturing a semiconductor device according to the present invention is characterized in that, when an interlayer insulating film on a pad region is etched in order to form a pad region and a wiring region in a semiconductor substrate and a multilayer wiring, the pad region, the wiring region or the same is etched. Since an insulating member pattern composed of an interlayer insulating film continuous from the top surface to the bottom surface of the pad region or the wiring region is left in both regions, the pad region and the wiring region are formed by CMP after the metal is buried in the pad region and the wiring region. In this case, the occurrence of the dishing phenomenon can be suppressed. In the method of manufacturing a semiconductor device, a pattern of a plurality of interlayer insulating films is provided in one pad region, and the insulating member patterns are made not to be in contact with the patterns of the other insulating members and the interlayer insulating film. In the pad region or the wiring region, a metal pattern that is electrically isolated can be eliminated, and a pad region or a wiring region having a large area can be formed. The minimum dimension of the insulating member pattern is preferably 1 μm or more. As a result, the thinning phenomenon can be suppressed.
It is preferable that a distance between one insulating member pattern and another insulating member pattern adjacent thereto or an insulating member pattern adjacent to the interlayer insulating film and the interlayer insulating film is 10 μm or less. As a result, the dishing phenomenon can be effectively suppressed.

In the case where the connection hole is formed using the dual damascene method, if the connection hole is formed in the same pattern as the pad region, the connection area between the upper pad region and the lower pad region is increased, and the connection between the wirings is surely reduced. Can be obtained. Further, the layout design of the pad region can be easily performed.

[Brief description of the drawings]

FIG. 1 is a process diagram showing a conventional example.

FIG. 2 is a cross-sectional view illustrating a dishing phenomenon and a thinning phenomenon in a pad region.

3A and 3B are diagrams illustrating an example, in which FIG. 3A is a cross-sectional view of a wiring portion, and FIG. 3B is a top view of a pad region in FIG.
(C) is a top view of a pad region of another embodiment, and a cross-sectional view is the same as (A).

FIG. 4 is a process chart showing one embodiment of a manufacturing method.

FIG. 5 is a process diagram showing a continuation of the embodiment.

FIG. 6 is a diagram illustrating a relationship between a metal line width and a wiring depth when metal CMP is performed while changing a polishing time.

FIG. 7: After embedding the metal of the trench wiring with high-pressure aluminum, C
FIG. 4 is a diagram illustrating a relationship between a metal line width and a wiring depth when MP is performed.

[Explanation of symbols]

 31a, 31b Wiring pattern 33, 37, 39, 43 Interlayer insulating film 35a, 35b Via hole 41a, 41b Pad

Claims (9)

[Claims] 1. A semiconductor device in which two or more layers of multilayer wiring are used and the wiring of each layer is insulated by an interlayer insulating film, wherein a metal pattern formed in a pad region and a wiring region in the semiconductor substrate and the multilayer wiring. A semiconductor device provided therein with an insulating member continuous from the top surface to the bottom surface of the metal pattern. 2. The semiconductor device according to claim 1, wherein a plurality of said insulating members are provided in one of said pad regions or said wiring regions, and said insulating members are not in contact with other insulating members nor with said interlayer insulating film. 13. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein a minimum dimension of the insulating member is 1 μm or more. 4. A distance between the insulating member adjacent to one insulating member or the insulating member adjacent to the interlayer insulating film and the interlayer insulating film is 10 μm or less. 3. The semiconductor device according to claim 1. 5. A method for manufacturing a semiconductor device in which two or more layers of multilayer wiring are used and the wiring of each layer is insulated by an interlayer insulating film. When etching the interlayer insulating film on the pad region and the wiring region, the insulating member made of the interlayer insulating film continuous from the top surface to the bottom surface of the pad region or the wiring region in the pad region, the wiring region, or both regions. A method for manufacturing a semiconductor device, wherein a pattern is left. 6. A method according to claim 1, wherein a plurality of said insulating member patterns are provided in one of said pad regions or said wiring regions, and said insulating member patterns are not in contact with other insulating member patterns nor with said interlayer insulating film. Item 6. The method for manufacturing a semiconductor device according to Item 5. 7. The minimum size of the insulating member pattern is 1 μm.
The method for manufacturing a semiconductor device according to claim 5, wherein m is not less than m. 8. The distance between another insulating member pattern adjacent to one insulating member pattern or an insulating member pattern adjacent to the interlayer insulating film and the interlayer insulating film is 10.
The method for manufacturing a semiconductor device according to claim 5, 6 or 7, wherein the thickness is not more than μm. 9. A connection hole for electrically connecting between a pad region formed in an upper wiring and a pad region formed in a lower wiring is formed simultaneously with a pad region formed on the connection hole. 9. The method of manufacturing a semiconductor device according to claim 5, wherein when the contact hole is formed using a dual damascene method, the connection hole is formed in the same pattern as a pad region.