JP3299486B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using chemical mechanical polishing for planarizing a multilayer wiring, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor device having a multi-layer wiring, planarization of an interlayer film for alleviating unevenness caused by an underlying wiring is one of important technologies. In recent years, chemical mechanical polishing (hereinafter, referred to as CMP) has become widespread as one of the planarization techniques. In this CMP method, a wafer is pressed against a polishing pad attached to a surface plate while pouring a polishing liquid containing silica particles, and the surface plate is rotated while applying a load to the wafer, so that only protrusions on the wafer surface are selectively formed. By polishing,
This is a method of flattening. Regarding CMP, see, for example, JP-A-4-155927 and JP-A-6-27561.
No. 6 discloses this method. Japanese Patent Application Laid-Open No. 7-74175 discloses a method of using a wiring dummy pattern in order to suppress a difference in flatness due to density of underlying wiring when performing CMP. Further, in Japanese Patent Application Laid-Open No. 7-74175, CM is used as an interlayer insulating film.
The use of two types of films, a plasma nitride film with a low polishing rate of P and a silicon oxide film with a high polishing rate, enhances the polishing stop function, prevents excessive polishing of the interlayer insulating film, and achieves planarization. It also shows that it is realized.

The technique relating to the wiring dummy pattern has been known for a flattening method other than chemical mechanical polishing for a long time, and is disclosed in, for example, JP-A-61-276345. Also, a technique for generating a dummy pattern by an automatic placement and routing system is disclosed in Japanese Patent Laid-Open No. 2-2409.
No. 46 discloses this. Further, Japanese Patent Application Laid-Open No. 6-69201 discloses a method in which parasitic capacitance is not increased by using an insulating film without using a metal wiring for a dummy pattern.

[0004]

However, the above-mentioned prior art has the following problems. JP 7
As disclosed in JP-A-74175, when a wiring layer is used as a dummy pattern, there is a problem that if the space between the wirings is small, the parasitic capacitance increases and the operation speed is reduced.

Further, when dummy patterns are arranged so as to fill up the wiring space, when layout correction during development frequently occurs, when a pattern of another layer is corrected, if there is no dummy pattern, Even if there is no need for correction, correction may be necessary because of the presence of the dummy pattern. In this case, there arises a problem that the time and cost required for the correction increase.

Further, when two types of films, a plasma nitride film having a low polishing rate in CMP and a silicon oxide film having a high polishing rate, are employed, the plasma nitride film has a large stress and deteriorates the reliability of wiring. There is. That is, the coefficient of expansion differs between the nitride film and the silicon substrate, which causes stress. If this stress is applied to the aluminum wiring for a long period of time, stress migration occurs, and the aluminum wiring breaks. In addition, since the wet etching rate is extremely different between the plasma nitride film and the silicon oxide film, if a contact hole is formed in a later step, a step is formed in the contact hole, which causes a problem that the contact yield is reduced.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device and a semiconductor device which do not increase the parasitic capacitance even when a dummy pattern is used and do not increase the frequency of pattern correction due to the presence of the dummy pattern. It is an object of the present invention to provide a manufacturing method thereof.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor device, comprising: a wiring on a semiconductor substrate; and an interlayer formed on the entire surface of the semiconductor substrate on which the wiring exists and having a flattened upper surface. a semiconductor device comprising an insulating film, before
When the interlayer insulating film has a low polishing rate due to chemical mechanical polishing,
High inter-layer insulating film and high polishing rate by chemical mechanical polishing
The wiring has a dummy pattern, and a distance between the dummy pattern and a wiring used as a signal line is set to be 3 μm or more and 200 μm or less.

According to the above configuration, when the distance between the dummy pattern of the wiring on the semiconductor substrate and the wiring used as the signal line is about 3 μm, the parasitic capacitance between the wirings is sufficiently reduced. Since the capacitance does not decrease, the parasitic capacitance can be ignored by setting the wiring interval to 3 μm or more, and the operation speed does not decrease. In addition, when planarization is performed by using CMP, a dent that occurs in a central portion of the interlayer insulating film where there is no wiring is reduced by setting the wiring interval to 200 μm or less. That is, even if the dummy pattern is located at a distance of about 200 μm from the wiring pattern, the effect of flattening as the dummy pattern can be sufficiently exhibited. Along with this, since the dummy pattern is not arranged near the wiring, even when correcting the pattern of another layer,
There is no need to correct the dummy pattern, and the layout can be easily corrected. In addition, line parasitic capacitance increases as described above.
This prevents delays in operating speed and prevents the interlayer insulating film from flattening.
And the interlayer insulating film is made by chemical mechanical polishing.
Lower interlayer insulating film with low polishing rate and chemical mechanical polishing
Since it is composed of an upper interlayer insulating film with a high polishing rate,
Some overetching of upper interlayer insulating film during manufacturing
The lower interlayer insulating film is almost completely etched
Not done. By adopting these two types of membranes,
The polishing stop function has been enhanced, and the
To prevent excessive polishing and deterioration of wiring reliability.
Can be.

According to a second aspect of the present invention, there is provided a semiconductor device comprising: a wiring on a semiconductor substrate; and an interlayer insulating film formed on the entire surface of the semiconductor substrate on which the wiring is present and having a flattened upper surface. And the interlayer insulating film is
Lower interlayer insulating film with low polishing rate
It consists of an upper interlayer insulating film with a high polishing rate by polishing,
The wiring has a dummy pattern, and the dummy pattern exists in a scribe lane portion around the semiconductor chip. The scribe lane usually has a width of about 50 to 100 μm, and a wiring layout exists at about 50 μm from the periphery of the chip. As described in claim 1, even if the distance of the wiring dummy pattern is about 200 μm, Therefore, even if the dummy pattern exists in the scribe lane around the semiconductor chip as described above, sufficient flattening can be obtained. In addition, since there is sufficient space between the dummy pattern and the wiring, there is no problem that the parasitic capacitance between the wirings increases, and the layout can be easily corrected. Also, since the parasitic capacitance between lines does not increase, the operating speed is reduced.
In addition to preventing delay and flattening the interlayer insulating film,
In addition, when the interlayer insulating film is
High inter-layer insulating film and high polishing rate by chemical mechanical polishing
Since it is composed of an interlayer insulating film, the upper interlayer
Even if the insulating film is over-etched to some extent,
The lower interlayer insulating film is hardly etched. This
Polishing stop function by using two types of films
To prevent excessive polishing of the interlayer insulating film during planarization.
In addition, it is possible to prevent the reliability of the wiring from deteriorating.

According to a third aspect of the present invention, there is provided a semiconductor device comprising a wiring on a semiconductor substrate, and an interlayer insulating film formed on the entire surface of the semiconductor substrate on which the wiring is present and having a flattened upper surface. And the interlayer insulating film is
Lower interlayer insulating film with low polishing rate
It consists of an upper interlayer insulating film with a high polishing rate by polishing,
The wiring has a dummy pattern, and the dummy pattern exists in a portion of the bonding pad. A wiring layout exists at 50 μm from the periphery of the bonding pad. However, as described in claim 1, even if the distance of the wiring dummy pattern is as large as about 200 μm, the wiring pattern has the effect as a dummy pattern. Sufficient planarization can be obtained even if a dummy pattern exists in the portion. In addition, since there is sufficient space between the dummy pattern and the wiring, there is no problem that the parasitic capacitance between the wirings increases, and the layout can be easily corrected. Furthermore, as described above
Prevents delay in operation speed because line-to-line parasitic capacitance does not increase
In addition to achieving flattening of the interlayer insulating film,
Lower interlayer insulating film with low polishing rate by chemical mechanical polishing
And an upper interlayer insulating film with a high polishing rate by chemical mechanical polishing
Since it is composed of
Even if over-etching is performed to some extent, lower layer interlayer insulation
The film is hardly etched. These two types
By adopting a film, the polishing stop function is enhanced and flattened
Over-polishing of the interlayer insulating film during
Deterioration of reliability can be prevented.

According to a fourth aspect of the present invention, there is provided a semiconductor device comprising: a wiring on a semiconductor substrate; and an interlayer insulating film formed on the entire surface of the semiconductor substrate on which the wiring is present and having a flattened upper surface. And the wiring has a dummy pattern.
Between the dummy pattern and the wiring used as a signal line.
Set the distance to be 3μm or more and 200μm or less
And the dummy patterns are arranged in a block shape.
The space of the dummy pattern block is 1 μm or more 5
μm or less, and the line is 1 μm or more and 5 μm or less. This
Dummy patterns are arranged in blocks as shown in
Mee pattern block space is 1μm or more and 5μm
In the following, by setting the line to 1 μm or more and 5 μm or less,
By inserting a space in the dummy pattern,
-The thickness of the interlayer insulating film on the pattern is used as the signal line.
Thickness can be almost the same as the interlayer insulating film on the wiring
You. Further, the parasitic capacitance between wirings is sufficiently low as in the first aspect.
Thus, the interlayer insulating film can be planarized.

According to a fifth aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate;
Wiring on the semiconductor substrate where the wiring exists
And an interlayer insulating film formed on the surface and having a flattened upper surface.
Semiconductor device, wherein the wiring has a dummy pattern.
This dummy pattern is
The dummy pattern exists in the part of the
The dummy patterns are arranged in a
Source is 1 μm or more and 5 μm or less and line is 1 μm or more and 5 μm or less.
μm or less. In this way, the dummy pattern is
Are arranged in a matrix pattern and the space of the block of the dummy pattern
Is 1 μm or more and 5 μm or less, and the line is 1 μm or more and 5 μm
By setting the following, the space in the dummy pattern
The thickness of the interlayer insulating film on the dummy pattern
Is almost the same as the interlayer insulating film on the wiring used as a signal line
It can be a film thickness. In addition, wiring is performed in the same manner as in claim 2.
The parasitic capacitance between the electrodes is sufficiently reduced, and the interlayer insulating film is flattened.
be able to.

According to a sixth aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate;
Wiring on the semiconductor substrate where the wiring exists
And an interlayer insulating film formed on the surface and having a flattened upper surface.
Semiconductor device, wherein the wiring has a dummy pattern.
Then, this dummy pattern is
Exist, the dummy pattern is arranged in a block shape,
The space of the block of the dummy pattern is 1 μm or more.
5 μm or less, and the line is 1 μm or more and 5 μm or less.
Thus, the dummy patterns are arranged in blocks,
Space of block of dummy pattern is 1μm or more and 5μ
m and the line must be 1 μm or more and 5 μm or less.
By inserting a space in the dummy pattern,
The thickness of the interlayer insulating film on the me pattern is used for signal lines.
The thickness can be almost the same as the interlayer insulating film on the wiring
Wear. In addition, the parasitic capacitance between the wirings is sufficient as in the third aspect.
Thus, the interlayer insulating film can be planarized.

According to a seventh aspect of the present invention, there is provided a semiconductor device according to the fourth aspect.
In 5 or 6, the interlayer insulating film is chemically mechanically polished.
Lower interlayer insulating film with low polishing rate by chemical mechanical polishing
And an upper interlayer insulating film with a high polishing rate.
You. As described above, the interlayer insulating film is polished by chemical mechanical polishing.
Polishing by chemical mechanical polishing
Since it is composed of an upper interlayer insulating film with a high polishing rate,
By adopting two types of films such as
Prevents excessive polishing of inter-insulation film and reduces wiring reliability.
Can be prevented.

The semiconductor device according to the eighth aspect is the first aspect.
In 2, 3, or 7, the lower interlayer insulating film is made of CVD acid.
The oxide film and the upper interlayer insulating film are BPSG films. Chemical Mechanical Laboratory
The etching rate when polishing is performed with respect to the CVD oxide film.
Because the BPSG film is about 5 times faster, the lower interlayer insulating film is C
VD oxide film and BPSG film for upper interlayer insulating film
More over-etching for BPSG film
Is performed, the CVD oxide film is almost completely etched.
Therefore, a wide etching margin can be obtained. This
Therefore, while securing the margin of over-etching,
The reliability of wiring that occurs when using a plasma nitride film
No degradation occurs. That is, the conventional plasma nitride film is
When using aluminum wiring with high stress,
Aluminum wiring breaks due to less migration
Of the BPSG film.
Stress migration
It does not happen and reliability is secured.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
Forming a first wiring on a semiconductor substrate, the entire surface of the semiconductor substrate formed with the first wiring, a chemical mechanical
Lower interlayer insulating film with low polishing rate by polishing and Chemical Mechanical Engineering
Forming an interlayer insulating film consisting of an upper interlayer insulating film having a high polishing rate by polishing , flattening the interlayer insulating film by chemical mechanical polishing, and forming a second wiring on the flattened interlayer insulating film. Forming a first wiring having a dummy pattern, and a distance between the dummy pattern and a wiring used as a signal line is 3 μm or more and 200 μm or less. Set to.

As described above, in the step of forming the first wiring on the semiconductor substrate, the first wiring has a dummy pattern, and the distance between the dummy pattern and the wiring used as the signal line is 3 μm or more and 200 μm or more. Since the setting is made as follows, the operation speed is not reduced, and the layout of the interlayer insulating film is facilitated and the layout is easily corrected. That is, when the distance between the dummy pattern and the wiring used as the signal line is about 3 μm, the parasitic capacitance between the wirings is sufficiently reduced. Therefore, the operation speed does not decrease by setting the wiring interval to 3 μm or more. In addition, when planarization is performed by using CMP, a dent that occurs in a central portion of the interlayer insulating film where there is no wiring is reduced by setting the wiring interval to 200 μm or less. For this reason, even if the dummy pattern exists at a position separated from the wiring pattern by about 200 μm, the effect of flattening can be sufficiently exhibited as the dummy pattern. Further, since the interlayer insulating film is planarized in this manner, even if the second wiring is formed on the interlayer insulating film, disconnection or short circuit of the second wiring due to a focus shift does not occur. Also, since the dummy pattern is not arranged near the wiring, even when correcting the pattern of another layer,
There is no need to correct the dummy pattern, and the layout can be easily corrected. In addition, line parasitic capacitance increases as described above.
This prevents delays in operating speed and prevents the interlayer insulating film from flattening.
And the interlayer insulating film is made by chemical mechanical polishing.
Lower interlayer insulating film with low polishing rate and chemical mechanical polishing
Since it is composed of an upper interlayer insulating film with a high polishing rate,
Some overetching of upper interlayer insulating film during manufacturing
The lower interlayer insulating film is almost completely etched
Not done. By adopting these two types of membranes,
The polishing stop function has been enhanced, and the
To prevent excessive polishing and deterioration of wiring reliability.
Can be.

A method of manufacturing a semiconductor device according to claim 10 includes the steps of forming a first wiring on a semiconductor substrate, the entire surface of the semiconductor substrate formed with the first wiring, chemical
Lower interlayer insulating film with low polishing rate by mechanical polishing and chemical machine
Forming an interlayer insulating film comprising an upper interlayer insulating film having a high polishing rate by mechanical polishing; a step of flattening the interlayer insulating film by chemical mechanical polishing; Forming a second wiring in the semiconductor device, wherein the first wiring has a dummy pattern, and the dummy pattern is arranged in a scribe lane around the semiconductor chip.

As described above, in the step of forming the first wiring on the semiconductor substrate, the first wiring has a dummy pattern, and the dummy pattern is arranged in the scribe lane around the semiconductor chip. Sufficient planarization of the insulating film can be obtained. That is, the scribe lane usually has a width of about 50 to 100 μm, and is about 5 μm from the chip periphery.
Although a wiring layout exists at 0 μm, even if the distance of the wiring dummy pattern is as large as about 200 μm, the dummy pattern has an effect as a dummy pattern. Therefore, as described above, the dummy pattern is arranged in the scribe lane surrounding the semiconductor chip. However, sufficient planarization can be obtained. Further, since the interlayer insulating film is planarized in this manner, even if the second wiring is formed on the interlayer insulating film, disconnection or short circuit of the second wiring due to a focus shift does not occur. Also,
Since there is sufficient space between the dummy pattern and the wiring, there is no problem that the parasitic capacitance between the wirings increases, and the layout can be easily modified. Furthermore, the parasitic capacitance between lines increases as described above.
This prevents delays in operating speed and prevents interlayer insulation
And the interlayer insulating film is used for chemical mechanical polishing.
Lower interlayer insulating film with low polishing rate and chemical mechanical polishing
It is composed of an upper interlayer insulating film with a high polishing rate.
In the manufacturing process, the upper interlayer insulating film
Even if etching is performed, the lower interlayer insulating film is almost completely etched.
Is not performed. Use of these two types of membranes
Enhances the polishing stop function, and provides interlayer insulation during planarization.
Prevents excessive polishing of film and deterioration of wiring reliability
Can be

A semiconductor device manufacturing method according to claim 11, wherein a step of forming a first wiring on a semiconductor substrate and a step of forming a first wiring on the entire surface of the semiconductor substrate on which the first wiring is formed are performed .
Lower interlayer insulating film with low polishing rate by mechanical polishing and chemical machine
Forming an interlayer insulating film comprising an upper interlayer insulating film having a high polishing rate by mechanical polishing; a step of flattening the interlayer insulating film by chemical mechanical polishing; Forming a second wiring in the semiconductor device, wherein the first wiring has a dummy pattern, and the dummy pattern is arranged at a bonding pad portion.

As described above, in the step of forming the first wiring on the semiconductor substrate, the first wiring has a dummy pattern and this dummy pattern is arranged at the bonding pad portion. The flattening is obtained. That is, although the wiring layout exists at 50 μm from the periphery of the bonding pad, even if the distance of the wiring dummy pattern is about 200 μm, the wiring pattern has an effect as a dummy pattern. Even if present, sufficient planarization can be obtained. Further, since the interlayer insulating film is planarized in this manner, even if the second wiring is formed on the interlayer insulating film, disconnection or short circuit of the second wiring due to a focus shift does not occur. In addition, since there is sufficient space between the dummy pattern and the wiring, there is no problem that the parasitic capacitance between the wirings increases, and the layout can be easily corrected. Furthermore, on
As described above, the operating speed is slow because the parasitic capacitance between lines does not increase.
To prevent spreading and to planarize the interlayer insulating film,
The lower layer whose interlayer insulating film has a low polishing rate by chemical mechanical polishing
Interlayer insulating film and upper layer with high polishing rate by chemical mechanical polishing
Since it is composed of an interlayer insulation film, the upper interlayer insulation
Even if the film is over-etched to some extent, the lower layer
The interlayer insulating film is hardly etched. like this
The use of two types of films enhances the polishing stop function.
To prevent excessive polishing of the interlayer insulating film during planarization and
Deterioration of wiring reliability can be prevented.

According to a twelfth aspect of the invention, there is provided a method of manufacturing a semiconductor device , comprising the steps of: forming a first wiring on a semiconductor substrate;
An interlayer insulation is provided on the entire surface of the semiconductor substrate on which the first wiring is formed.
Forming an edge film, and chemically and mechanically polishing the interlayer insulating film.
And a step of flattening on the flattened interlayer insulating film.
Manufacturing a semiconductor device including a step of forming a second wiring
Wherein the first wiring has a dummy pattern,
Distance between this dummy pattern and wiring used as signal lines
Is set to be not less than 3 μm and not more than 200 μm.
The dummy pattern is arranged in a block shape,
Space of block of dummy pattern is 1μm or more and 5μ
m and the line is 1 μm or more and 5 μm or less. this
The dummy patterns are arranged in a block
-Space of pattern block is 1μm or more and 5μm or less
Below, by setting the line to 1 μm or more and 5 μm or less
By inserting a space in the dummy pattern,
-The thickness of the interlayer insulating film on the pattern is used as the signal line.
Thickness can be almost the same as the interlayer insulating film on the wiring
You. Further, the parasitic capacitance between wirings is sufficiently low as in the ninth aspect.
Thus, the interlayer insulating film can be planarized.

According to a thirteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device , comprising: forming a first wiring on a semiconductor substrate;
An interlayer insulation is provided on the entire surface of the semiconductor substrate on which the first wiring is formed.
Forming an edge film, and chemically and mechanically polishing the interlayer insulating film.
And a step of flattening on the flattened interlayer insulating film.
Manufacturing a semiconductor device including a step of forming a second wiring
Wherein the first wiring has a dummy pattern,
This dummy pattern is scribed around the semiconductor chip.
And the dummy pattern is in a block shape.
And the space of the block of the dummy pattern
Is 1 μm or more and 5 μm or less, and the line is 1 μm or more and 5 μm
It is as follows. Thus, the dummy pattern is block-shaped
And the space of the block of the dummy pattern is 1
The line is 1 μm or more and 5 μm or less, with μm or more and 5 μm or less
By inserting a space in the dummy pattern
The thickness of the interlayer insulating film on the dummy pattern is
With the same thickness as the interlayer insulating film on the wiring used as the signal line
can do. In addition, similar to the tenth aspect, the wiring gap
Raw capacity is sufficiently reduced, and the interlayer insulating film must be flattened
Can be.

According to a fourteenth aspect of the present invention, in the method of manufacturing a semiconductor device, a step of forming a first wiring on a semiconductor substrate;
An interlayer insulation is provided on the entire surface of the semiconductor substrate on which the first wiring is formed.
Forming an edge film, and chemically and mechanically polishing the interlayer insulating film.
And a step of flattening on the flattened interlayer insulating film.
Manufacturing a semiconductor device including a step of forming a second wiring
Wherein the first wiring has a dummy pattern,
Place this dummy pattern on the bonding pad
The dummy pattern is arranged in a block shape,
Space of block of dummy pattern is 1μm or more and 5μ
m and the line is 1 μm or more and 5 μm or less.

As described above, the dummy pattern has a block shape.
And the space of the block of the dummy pattern is 1
The line is 1 μm or more and 5 μm or less, with μm or more and 5 μm or less.
By inserting a space in the dummy pattern
The thickness of the interlayer insulating film on the dummy pattern is
With the same thickness as the interlayer insulating film on the wiring used as the signal line
can do. In addition, similar to the eleventh aspect, the spacing between the wirings
Raw capacity is sufficiently reduced, and the interlayer insulating film must be flattened
Can be.

According to a fifteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the twelfth, thirteenth or fourteenth aspect, the interlayer insulation is provided.
The edge film has a lower interlayer insulation with a low polishing rate by chemical mechanical polishing.
Edge film and upper interlayer insulation with high polishing rate by chemical mechanical polishing
It is composed of a rim and a rim. Thus, the interlayer insulating film is
A lower interlayer insulating film having a low polishing rate by chemical mechanical polishing,
It consists of an upper interlayer insulating film with a high polishing rate by chemical mechanical polishing.
The use of these two types of membranes
Only prevents excessive polishing of the interlayer insulating film during planarization.
Thus, it is possible to prevent the reliability of the wiring from deteriorating. Claim 1
6. The method of manufacturing a semiconductor device according to claim 6, wherein
In 1 or 15, the lower interlayer insulating film is formed by CVD oxidation.
The film and the upper interlayer insulating film are BPSG films. The etching rate, which is the polishing rate when performing chemical mechanical polishing, is CVD.
Since the BPSG film is about five times faster than the oxide film, the lower interlayer insulating film is a CVD oxide film and the upper interlayer insulating film is a BPSG film.
By using the G film, even if the BPSG film is over-etched to some extent, the CVD oxide film is hardly etched, and a wide etching margin can be obtained. For this reason, while the margin of the over-etching is secured, the deterioration of the reliability of the wiring which occurs when the plasma nitride film is used does not occur. That is, the conventional plasma nitride film has a lot of stress, and when an aluminum wiring is used, the aluminum wiring is disconnected due to stress migration.
Since the G film has almost no stress, stress migration does not occur and reliability is ensured.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to a first embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS .
It will be described based on. FIG. 1 is a layout diagram of a semiconductor device according to a first embodiment of the present invention, and FIG. 2A is a cross-sectional view of the semiconductor device before CMP according to the first embodiment of the present invention. FIG. 2B is a cross-sectional view of the semiconductor device after the CMP. In FIG. 2A, a first wiring 2 exists on a semiconductor substrate 1, and an interlayer insulating film 3
Exists. The interlayer insulating film 3 is planarized by CMP (chemical mechanical polishing) as shown in FIG. The first wiring 2 has a dummy pattern 5 as shown in FIG. 1, and the distance c between the dummy pattern 5 and the wiring 4 used as a signal line is set to be 3 μm or more and 200 μm or less. Have been. The planarized interlayer insulating film 3
The second wiring 6 is formed thereon (FIG. 6C). Figure
11 (a) is a CM of the semiconductor device according to the embodiment of the present invention.
FIG. 11B is a cross-sectional view of the semiconductor device before P. FIG.
It is sectional drawing of the semiconductor device after the CMP. FIG.
1A, a wiring 2 exists on a semiconductor substrate 1, and the wiring 2
Has an interlayer insulating film on the entire surface. This interlayer insulating film is made of C
Lower interlayer insulating film 12 and C having a low polishing rate by MP
The upper interlayer insulating film 13 having a high polishing rate by MP
The lower interlayer insulating film 12 is formed as a CVD oxide film,
0.1 μm, and the upper interlayer insulating film 13 is used as a BPSG film.
Then, the film thickness is set to 1.4 μm.

Next, a method of manufacturing the semiconductor device will be described. As shown in FIG. 6A, a first wiring 2 is formed on a semiconductor substrate 1, and an interlayer insulating film 3 is formed thereon. Next, as shown in FIG. 6B, the interlayer insulating film 3 is
Flatten by MP. Here, for example, when the thickness of the wiring 2 is 0.5 μm and the thickness of the interlayer insulating film 3 is 1.5 μm, the interlayer insulating film 3 is flattened by CMP as shown in FIG. However, a dent b occurs in the central part where there is no wiring. FIG. 3 shows the relationship between the dent b and the wiring interval a. In FIG. 3, when the wiring interval a is 100 μm, the dent b is as small as 0.05 μm. When etch back or SOG, which is a conventional planarization technique, is used, the wiring interval a is about 5 μm, and the recess b is 0.5 μm, which is the film thickness of the wiring 2. Even when CMP is used, when the wiring interval is infinite, the dent b is 0.5 μm, which is the film thickness of the wiring 2.

As described above, when the CMP is used, even when the wiring interval a is about 100 μm, the dent b is very small, 0.05 μm. That is, in the planarization using the CMP, even if the dummy pattern is present at a position separated from the wiring pattern by about 100 μm, the effect on the planarization is sufficiently exhibited as the dummy pattern. In this embodiment, the distance c between the dummy pattern 5 and the wiring 2 is set to be 200 μm or less.

FIG. 5 is a graph showing a simulation result of the dependency of the parasitic capacitance on the distance between wirings. condition is,
As shown in FIG. 4, the upper wiring 6 is on the entire surface, the thickness of the interlayer insulating film 3 on the wiring 2 is 0.5 μm, and the thickness of the wiring 2 is also 0.5 μm. FIG. 5 shows the line capacitance when the wiring interval a is infinite, that is, when only the wiring capacitance with the upper layer wiring 6 is set to 1. As is evident in FIG.
It can be said that the capacitance is sufficiently reduced when the wiring interval a is about 3 μm, and hardly decreases when the wiring interval a is larger than 3 μm. That is, if the wiring interval a is about 3 μm, the parasitic capacitance can be ignored. Therefore, in this embodiment, the dummy pattern 5
Is set so that the distance c between the wiring 2 and the wiring 2 is 3 μm or more and 200 μm or less. Also, when forming the interlayer insulating film 3, the semiconductor
A wiring 2 is formed on a substrate 1 and a CMP is performed thereon.
Polishing speed by lower interlayer insulating film 12 with low polishing speed and CMP
An upper interlayer insulating film 13 having a high degree of speed is formed. Next, the whole surface
The interlayer insulating film is planarized by CMP. Where C
The etching rate at the time of performing MP is different from that of the CVD oxide film.
Thus, the BPSG film is about five times faster. Therefore, FIG.
As shown in (b), the upper interlayer insulating film 13 of the BPSG film is formed.
CV
The lower interlayer insulating film 12 of the D oxide film is almost etched.
Not. For this reason, widen the etching margin
Can be.

Thereafter, as shown in FIG. 6C, a desired second wiring 6 is formed on the flattened interlayer insulating film 3. At this time, since the underlying interlayer insulating film 3 is flattened, the disconnection or short circuit of the wiring 6 due to the focus shift does not occur. As described above, according to this embodiment, the dummy pattern 5 is 3 μm from the wiring 4 as a signal line.
m or more, the wiring capacitance does not increase, and since the number of dummy patterns 5 is small near the wirings 4, there is no need to correct the dummy patterns 5 due to the layout change of the wirings 4, and the time required for the correction is reduced. And costs do not increase. Further, the dummy pattern 5 is set within 200 μm from the wiring 4.
Is present, and no dent b is generated when planarization is performed using CMP, or is extremely small.

In this embodiment, the distance c between the dummy pattern 5 and the wiring 4 is not less than 3 μm and not more than 200 μm. However, when the conditions of CMP and the thickness of the underlying wiring are different, the same applies outside this range. May be obtained. Further, as shown in FIG.
May be arrayed with a space S of 2 μm in 2 μm blocks, for example. Thus, the dummy pattern 5
By providing a space S therein, the thickness of the interlayer insulating film 3 on the dummy pattern 5 can be made substantially the same as the thickness of the interlayer insulating film 3 on the wiring 4. The space S of the block is 1 μm or more and 5 μm or less, and the line L is 1 μm.
m and 5 μm or less. Also, dummy pattern
When the blocks 5 are arranged in a block shape as described above,
The edge film 3 includes a lower interlayer insulating film 12 and an upper interlayer insulating film 13.
It is not necessary to configure.

FIGS. 8 to 1 show a second embodiment of the present invention.
Description will be made based on 0. 8 and 9 are layout diagrams of the semiconductor device according to the embodiment of the present invention. FIG. 8 shows an example of a semiconductor memory, and FIG. 9 shows an example of a semiconductor logic.
Each of the semiconductor chips has a scribe lane 7 and a bonding pad 8. Since the actual wiring layout is very fine compared to the chip size, FIG.
Also, in FIG. 9, the circuit section 9 is collectively displayed.

Next, FIG. 10 shows a semiconductor wafer. Semiconductor chip 11 formed on circular semiconductor wafer 10
Is cut into individual semiconductor chips by scribing the boundary of each semiconductor chip, and then assembled into a package to become a final product. Here, the semiconductor wafer 1
The area required to scribe 0 is a scribe lane 7, which usually has a width of about 50 to 100 μm.
The scribe lane 7 exists on the lattice on the semiconductor wafer 10 as shown in FIGS. And
In this semiconductor device, the wiring has a dummy pattern, and the dummy pattern exists in a portion of the scribe lane 7 around the semiconductor chip.

Normally, when wiring is laid out, up to 50 μm around the chip is used, so there is a wiring layout at 50 μm around the chip. As described in the first embodiment, the distance between the wiring and the dummy pattern is 2
There is an effect as a dummy pattern even at a distance of about 00 μm. Therefore, by providing the dummy pattern in the scribe lane 7, a sufficient flattening can be obtained.

In this method of manufacturing a semiconductor device, a dummy pattern is arranged in the scribe lane 7 as described above when forming wiring on a semiconductor substrate. Then, as in the first embodiment, the lower layer having a low polishing rate by CMP is used.
Interlayer insulation film and upper interlayer insulation with high polishing rate by CMP
An interlayer insulating film made of a film is formed, the interlayer insulating film is planarized by performing CMP on the entire surface, and a desired wiring is formed thereon. This method facilitates the layout of the dummy pattern as compared with the first embodiment, but requires that the wiring layout be performed up to the vicinity of the scribe lane 7. In addition,
Block the dummy pattern as in the first embodiment.
And the space S of the block is 1 μm or more and 5 μm
In the following, the line L may be 1 μm or more and 5 μm or less.
No. In this case, the interlayer insulating film is a lower interlayer insulating film and an upper interlayer insulating film.
It does not have to be composed of an insulating film.

It is needless to say that the dummy pattern arranged in the scribe lane 7 may be used for other purposes, for example, as wiring for fixing the substrate potential to the chip. A third embodiment of the present invention will be described. 8 and 9 used in the description of the second embodiment, in this semiconductor device, the wiring has a dummy pattern, and the dummy pattern exists in the bonding pad 8 portion.

Normally, when wiring is laid out, it is used up to 50 μm around the bonding pad.
A wiring layout exists at 50 μm around the bonding pad. As described in the first embodiment, even if the distance between the wiring and the dummy pattern is about 200 μm, the effect as the dummy pattern can be obtained. For this reason, by providing a dummy pattern in the portion of the bonding pad 8, sufficient planarization can be obtained.

In the method of manufacturing a semiconductor device, a dummy pattern is arranged on the bonding pad 8 as described above when forming a wiring on a semiconductor substrate. Then the first
Similar to the embodiment, the lower slow polishing rate by CMP
Interlayer insulation film and upper interlayer insulation with high polishing rate by CMP
An interlayer insulating film including an edge film is formed, and the entire surface is subjected to CMP to flatten the interlayer insulating film, and a desired wiring is formed thereon. This method facilitates the layout of the dummy pattern as compared with the first embodiment, but requires that the wiring layout be performed up to the vicinity of the bonding pad. What
In addition, similar to the first embodiment, the dummy pattern is
The block space S is 1 μm or more 5
μm or less, and the line L is 1 μm or more and 5 μm or less,
Is also good. In this case, the interlayer insulating film is
It does not have to be composed of an interlayer insulating film.

It goes without saying that the dummy pattern arranged on the bonding pad 8 may be used for another purpose, such as arranging a length measurement pattern.

[0042]

[0043]

[0044]

According to the semiconductor device of the first aspect of the present invention, when the distance between the wiring dummy pattern on the semiconductor substrate and the wiring used as the signal line is about 3 μm, the parasitic capacitance between the wirings is sufficiently reduced. However, since the parasitic capacitance does not decrease with a longer wiring interval, the parasitic capacitance can be ignored by setting the wiring interval to 3 μm or more, and the operation speed does not decrease. In addition, when planarization is performed by using CMP, a dent that occurs in a central portion of the interlayer insulating film where there is no wiring is caused by a wiring interval of 2.
The thickness is reduced by setting the thickness to 00 μm or less. That is,
Even if the dummy pattern exists at a position separated from the wiring pattern by about 200 μm, the effect of flattening can be sufficiently exhibited as the dummy pattern. Along with this, since the dummy pattern is not arranged near the wiring, it is not necessary to correct the dummy pattern even when correcting the pattern of another layer, and the layout can be easily corrected. In addition,
As the line-to-line parasitic capacitance does not increase,
Prevention and planarization of the interlayer insulating film.
Insulation film lower interlayer insulation with low polishing rate by chemical mechanical polishing
Edge film and upper interlayer insulation with high polishing rate by chemical mechanical polishing
Since it is composed of an edge film, it can be used as an upper interlayer insulating film during manufacturing.
On the other hand, even if some over-etching is performed,
The insulating film is hardly etched. Two kinds like this
By adopting a kind of film, the polishing stop function is enhanced,
Prevents excessive polishing of interlayer insulating film during planarization and wiring
Can be prevented from deteriorating.

According to the semiconductor device of the second aspect of the present invention, the scribe lane usually has a width of about 50 to 100 μm, and a wiring layout exists at about 50 μm from the periphery of the chip. As described above, even if the distance of the wiring dummy pattern is about 200 μm, the effect as a dummy pattern can be obtained, so that sufficient flattening can be obtained even if the dummy pattern exists in the scribe lane surrounding the semiconductor chip as described above. Can be In addition, since there is sufficient space between the dummy pattern and the wiring, there is no problem that the parasitic capacitance between the wirings increases, and the layout can be easily corrected. Furthermore, the line-to-line parasitic capacitance does not increase as described above.
This prevents delays in operating speed and ensures that the interlayer insulating film is flat.
And the interlayer insulating film is polished by chemical mechanical polishing.
Polishing by chemical mechanical polishing
Since it is composed of an upper interlayer insulating film with a high polishing rate,
Some overetching of upper interlayer insulating film during fabrication
The lower interlayer insulating film is almost completely etched.
Not. Polishing by adopting these two types of films
Of the interlayer insulation film during planarization
To prevent polishing and to prevent deterioration of wiring reliability.
it can.

According to the semiconductor device of the third aspect of the present invention, the wiring layout exists at 50 μm from the periphery of the bonding pad, but the distance of the wiring dummy pattern is as large as about 200 μm as described in the first aspect. However, since it has an effect as a dummy pattern, sufficient flattening can be obtained even if the dummy pattern exists in the bonding pad portion as described above. In addition, since there is sufficient space between the dummy pattern and the wiring, there is no problem that the parasitic capacitance between the wirings increases, and the layout can be easily corrected. Sa
In addition, since the line-to-line parasitic capacitance does not increase as described above,
Preventing speed delay and flattening the interlayer insulating film
In both cases, the interlayer insulating film has a low polishing rate due to chemical mechanical polishing.
Low interlayer insulating film and high polishing rate by chemical mechanical polishing.
It is composed of an upper interlayer insulating film,
Perform some over-etching on the interlayer insulating film
However, the lower interlayer insulating film is hardly etched. This
Stop polishing by adopting two kinds of films such as
Function to prevent excessive polishing of the interlayer insulating film during planarization.
It is possible to prevent the deterioration of the reliability of the wiring.

According to the semiconductor device of the fourth aspect of the present invention, the dummy patterns are arranged in a block shape,
Space of pattern block is 1μm or more and 5μm or less
By making the line 1 μm or more and 5 μm or less,
By inserting a space in the dummy pattern, the dummy pattern
The thickness of the interlayer insulating film on the turn is
The thickness can be substantially the same as the interlayer insulating film on the line.
In addition, the parasitic capacitance between wirings is sufficiently reduced as in the first embodiment.
Thus, the interlayer insulating film can be planarized.

According to the semiconductor device of the present invention, the dummy patterns are arranged in a block shape,
Space of pattern block is 1μm or more and 5μm or less
By making the line 1 μm or more and 5 μm or less,
By inserting a space in the dummy pattern, the dummy pattern
The thickness of the interlayer insulating film on the turn is
The thickness can be substantially the same as the interlayer insulating film on the line.
In addition, the parasitic capacitance between wirings is sufficiently reduced as in the second aspect.
Thus, the interlayer insulating film can be planarized.

According to the semiconductor device of the present invention, the dummy patterns are arranged in a block shape,
Space of pattern block is 1μm or more and 5μm or less
By making the line 1 μm or more and 5 μm or less,
By inserting a space in the dummy pattern, the dummy pattern
The thickness of the interlayer insulating film on the turn is
The thickness can be substantially the same as the interlayer insulating film on the line.
Further, the parasitic capacitance between the wirings is sufficiently reduced as in the third aspect.
Thus, the interlayer insulating film can be planarized.

According to claim 7, the interlayer insulating film is formed by a chemical mechanical
Lower interlayer insulating film with low polishing rate
It consists of an upper interlayer insulating film with a high polishing rate.
Therefore, by adopting such two kinds of films, flatness can be obtained.
Over-polishing of the interlayer insulating film during
Deterioration of reliability can be prevented. In claim 8, the chemical
The etching rate when mechanical polishing is performed is as follows: CVD oxide film
Because the BPSG film is about 5 times faster, the lower interlayer insulation
The film is a CVD oxide film and the upper interlayer insulating film is a BPSG film
As a result, the BPSG film is over-etched to some extent.
Almost all CVD oxide film is etched
Not allow for a wide etching margin
You. Therefore, a margin for over-etching is secured.
However, the wiring signal that occurs when a plasma nitride film is used
No reliability deterioration occurs. That is, conventional plasma nitriding
The film has a lot of stress, and when using aluminum wiring,
Aluminum wiring breaks due to stress migration
However, the BPSG film has poor reliability.
Because there is almost no stress, stress migration
And reliability is ensured.

According to the method of manufacturing a semiconductor device according to the ninth aspect of the present invention, in the step of forming the first wiring on the semiconductor substrate, the first wiring has a dummy pattern, and the dummy pattern and the signal Since the distance from the wiring used as the line is set to be not less than 3 μm and not more than 200 μm, the operation speed is not reduced, and the layout of the interlayer insulating film is facilitated and the layout can be easily corrected. That is, when the distance between the dummy pattern and the wiring used as the signal line is about 3 μm, the parasitic capacitance between the wirings is sufficiently reduced,
With a larger wiring interval, the parasitic capacitance does not decrease and can be ignored. Therefore, the operation speed does not decrease by setting the wiring interval to 3 μm or more. In addition, when planarization is performed by using CMP, a dent that occurs in a central portion of the interlayer insulating film where there is no wiring is reduced by setting the wiring interval to 200 μm or less. For this reason, even if the dummy pattern exists at a position separated from the wiring pattern by about 200 μm, the effect of flattening can be sufficiently exhibited as the dummy pattern. Further, since the interlayer insulating film is planarized in this manner, even if the second wiring is formed on the interlayer insulating film, disconnection or short circuit of the second wiring due to a focus shift does not occur. For this reason, the upper-layer wiring focus margin is widened, and the wiring can be miniaturized. Further, since the dummy pattern is not arranged near the wiring, even when the pattern of another layer is corrected, the layout of the layout can be easily corrected without having to correct the dummy pattern. Furthermore, on
As described above, the operating speed is slow because the parasitic capacitance between lines does not increase.
To prevent spreading and to planarize the interlayer insulating film,
The lower layer whose interlayer insulating film has a low polishing rate by chemical mechanical polishing
Interlayer insulating film and upper layer with high polishing rate by chemical mechanical polishing
Since it is composed of an interlayer insulation film, the upper interlayer insulation
Even if the film is over-etched to some extent, the lower layer
The interlayer insulating film is hardly etched. like this
The use of two types of films enhances the polishing stop function.
To prevent excessive polishing of the interlayer insulating film during planarization and
Deterioration of wiring reliability can be prevented.

According to the semiconductor device manufacturing method of the present invention, in the step of forming the first wiring on the semiconductor substrate, the first wiring has a dummy pattern,
Since the dummy pattern is arranged in the scribe lane around the semiconductor chip, sufficient planarization of the interlayer insulating film can be obtained. That is, the scribe lane is usually 50 to
There is a width of about 100 μm, and about 50 μm from the chip periphery
Has a wiring layout. However, even if the distance of the wiring dummy pattern is about 200 μm, the wiring pattern has an effect as a dummy pattern. Therefore, as described above, the dummy pattern is arranged in the scribe lane around the semiconductor chip. However, sufficient planarization can be obtained. Further, since the interlayer insulating film is planarized in this manner, even if the second wiring is formed on the interlayer insulating film, disconnection or short circuit of the second wiring due to a focus shift does not occur. For this reason, the focus margin of the upper layer wiring is widened, and the wiring can be miniaturized. In addition, since there is sufficient space between the dummy pattern and the wiring, there is no problem that the parasitic capacitance between the wirings increases, and the layout can be easily corrected. Furthermore, on
As described above, the operating speed is slow because the parasitic capacitance between lines does not increase.
To prevent spreading and to planarize the interlayer insulating film,
The lower layer whose interlayer insulating film has a low polishing rate by chemical mechanical polishing
Interlayer insulating film and upper layer with high polishing rate by chemical mechanical polishing
Since it is composed of an interlayer insulation film, the upper interlayer insulation
Even if the film is over-etched to some extent, the lower layer
The interlayer insulating film is hardly etched. like this
The use of two types of films enhances the polishing stop function.
To prevent excessive polishing of the interlayer insulating film during planarization and
Deterioration of wiring reliability can be prevented.

According to the method of manufacturing a semiconductor device of the present invention, in the step of forming the first wiring on the semiconductor substrate, the first wiring has a dummy pattern,
Since this dummy pattern is arranged at the bonding pad portion, sufficient planarization of the interlayer insulating film can be obtained. That is, although the wiring layout exists at 50 μm from the periphery of the bonding pad, even if the distance of the wiring dummy pattern is about 200 μm, the wiring pattern has an effect as a dummy pattern. Even if present, sufficient planarization can be obtained. Further, since the interlayer insulating film is planarized in this manner, even if the second wiring is formed on the interlayer insulating film, disconnection or short circuit of the second wiring due to a focus shift does not occur. For this reason, the focus margin of the upper layer wiring is widened, and the wiring can be miniaturized. Also,
Since there is sufficient space between the dummy pattern and the wiring, there is no problem that the parasitic capacitance between the wirings increases, and the layout can be easily modified. Furthermore, the parasitic capacitance between lines increases as described above.
This prevents delays in operating speed and prevents interlayer insulation
And the interlayer insulating film is used for chemical mechanical polishing.
Lower interlayer insulating film with low polishing rate and chemical mechanical polishing
It is composed of an upper interlayer insulating film with a high polishing rate.
In the manufacturing process, the upper interlayer insulating film
Even if etching is performed, the lower interlayer insulating film is almost completely etched.
Is not performed. Use of these two types of membranes
Enhances the polishing stop function, and provides interlayer insulation during planarization.
Prevents excessive polishing of film and deterioration of wiring reliability
Can be A semiconductor device according to claim 12 of the present invention.
According to the method of manufacturing the device, the dummy pattern is
Arranged, the space of the dummy pattern block is 1μ
m or more and 5 μm or less, and the line is 1 μm or more and 5 μm or less.
Space in the dummy pattern
The thickness of the interlayer insulating film on the dummy pattern is
The thickness should be almost the same as the interlayer insulating film on the wiring used as the wire.
Can be Further, as in the ninth aspect, a parasitic capacitance between wirings may be provided.
The amount decreases sufficiently, and the interlayer insulating film can be planarized.
Wear.

The semiconductor device according to claim 13 of the present invention
According to the manufacturing method, the dummy patterns are arranged in a block shape.
The space of the dummy pattern block is 1 μm or less.
Upper 5μm or less, line should be 1μm or more and 5μm or less
Space in the dummy pattern
The thickness of the interlayer insulating film on the dummy pattern is
The thickness of the interlayer insulating film on the wiring used
Can be. Further, the parasitic capacitance between the wirings is the same as in the tenth aspect.
Is sufficiently reduced and the interlayer insulating film can be planarized.
You. According to the semiconductor device manufacturing method of the present invention, the dummy patterns are arranged in a block shape, and
Mee pattern block space is 1μm or more and 5μm
In the following, by setting the line to 1 μm or more and 5 μm or less,
By inserting a space in the dummy pattern,
-The thickness of the interlayer insulating film on the pattern is used as the signal line.
Thickness can be almost the same as the interlayer insulating film on the wiring
You. In addition, the parasitic capacitance between the wirings is sufficient as in the eleventh aspect.
Thus, the interlayer insulating film can be planarized.

According to a fifteenth aspect, the interlayer insulating film is made of a chemical mechanical device.
Lower interlayer insulating film with low polishing rate by polishing and chemical machinery
Composed of upper interlayer insulating film with high polishing rate
Therefore, by adopting these two types of membranes,
Prevents excessive polishing of the interlayer insulating film during
Deterioration of reliability can be prevented. In claim 16,
Since the etching rate, which is the polishing rate when chemical mechanical polishing is performed, is about 5 times faster than the CVD oxide film for the BPSG film, the lower interlayer insulating film is a CVD oxide film and the upper interlayer insulating film is a BPSG film. Thus, even if the BPSG film is over-etched to some extent, the CVD oxide film is hardly etched, and a wide etching margin can be obtained. For this reason, while the margin of the over-etching is secured, the deterioration of the reliability of the wiring which occurs when the plasma nitride film is used does not occur. That is, the conventional plasma nitride film has a lot of stress, and when an aluminum wiring is used, a reliability failure occurs such that the aluminum wiring is disconnected due to stress migration. However, the BPSG film has almost no stress.
Stress migration does not occur and reliability is ensured.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing a layout of a semiconductor device according to a first embodiment of the present invention.

FIG. 2A is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention before the CMP, and FIG. 2B is a cross-sectional view after the CMP.

FIG. 3 is a graph showing a relationship between a wiring interval and a recess in the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor device used for a simulation explaining the first embodiment;

FIG. 5 is a graph showing a relationship between a wiring interval and a line capacitance in a simulation result for explaining the first embodiment;

FIGS. 6A to 6C are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 7 is a conceptual diagram showing another layout in a modification of the semiconductor device according to the first embodiment of the present invention;

FIG. 8 is a conceptual diagram showing a chip layout of the semiconductor device according to the second and third embodiments of the present invention.

FIG. 9 is a conceptual diagram showing another chip layout of the semiconductor device according to the second and third embodiments of the present invention.

FIG. 10 is a plan view of a semiconductor wafer for describing second and third embodiments of the present invention.

11 (a) and (b) are sectional views of a semiconductor device in the form of implementation of the present invention.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 first wiring 3 interlayer insulating film 4 wiring used as signal line 5 dummy pattern 6 second wiring 7 scribe lane 8 bonding pad 9 circuit section 10 semiconductor wafer 11 semiconductor chip 12 lower interlayer insulating film 13 upper interlayer insulating film

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-10-125681 (JP, A) JP-A-10-335333 (JP, A) JP-A-8-139088 (JP, A) JP-A-7-107 74175 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/3205

Claims (16)

(57) [Claims] And 1. A on the semiconductor substrate wiring, a semiconductor device provided with said formed over the entire surface of the semiconductor substrate upper surface planarized interlayer dielectric film wiring is present, the
The interlayer insulating film is a lower layer with a low polishing rate by chemical mechanical polishing.
Interlayer insulating film and upper layer with high polishing rate by chemical mechanical polishing
A semiconductor device comprising an interlayer insulating film, wherein the wiring has a dummy pattern, and a distance between the dummy pattern and a wiring used as a signal line is set to be 3 μm or more and 200 μm or less. 2. A on the semiconductor substrate wiring, a semiconductor device provided with said formed over the entire surface of the semiconductor substrate upper surface planarized interlayer dielectric film wiring is present, the
The interlayer insulating film is a lower layer with a low polishing rate by chemical mechanical polishing.
Interlayer insulating film and upper layer with high polishing rate by chemical mechanical polishing
A semiconductor device comprising an interlayer insulating film, wherein the wiring has a dummy pattern, and the dummy pattern exists in a scribe lane portion around a semiconductor chip. 3. A on the semiconductor substrate wiring, a semiconductor device provided with said formed over the entire surface of the semiconductor substrate upper surface planarized interlayer dielectric film wiring is present, the
The interlayer insulating film is a lower layer with a low polishing rate by chemical mechanical polishing.
Interlayer insulating film and upper layer with high polishing rate by chemical mechanical polishing
A semiconductor device comprising an interlayer insulating film, wherein the wiring has a dummy pattern, and the dummy pattern exists in a portion of a bonding pad. 4. A on the semiconductor substrate wiring, a semiconductor device provided with said formed over the entire surface of the semiconductor substrate upper surface planarized interlayer dielectric film wiring is present, the
The wiring has a dummy pattern, and this dummy pattern
If the distance from the wiring used as the signal line is 3 μm or more, 200
μm or less, and the dummy pattern is
The blocks of the dummy pattern are arranged in a block shape.
Is 1 μm or more and 5 μm or less, and the line is 1 μm
A semiconductor device having a thickness of at least 5 μm or less . 5. A wiring on a semiconductor substrate and the wiring is present.
Formed on the entire surface of the semiconductor substrate to be flattened.
What semiconductor device der having a by an interlayer insulating film, wherein
The wiring has a dummy pattern, and this dummy pattern is
In the scribe lane area around the conductor chip,
The dummy pattern is arranged in a block shape, and
Space of pattern block is 1μm or more and 5μm or less
Wherein the line is not less than 1 μm and not more than 5 μm.
Semiconductor device. 6. A wiring on a semiconductor substrate and the wiring is present.
Formed on the entire surface of the semiconductor substrate to be flattened.
A semiconductor device, comprising:
The wiring has a dummy pattern, and this dummy pattern
In the area of the padding pad, and the dummy pattern
Are arranged in a block shape, and the dummy pattern
The space of the mark is 1 μm or more and 5 μm or less, and the line is 1 μm.
a semiconductor device having a diameter of not less than m and not more than 5 μm . 7. The method according to claim 1, wherein the interlayer insulating film is formed by chemical mechanical polishing.
Lower interlayer insulating film with low polishing rate and chemical mechanical polishing
Claim: Consists of an upper interlayer insulating film with a high polishing rate
Item 7. The semiconductor device according to item 4, 5 or 6 . 8. The method according to claim 8, wherein the lower interlayer insulating film is a CVD oxide film,
4. The method according to claim 1, wherein the interlayer insulating film is a BPSG film.
8. The semiconductor device according to 7 . 9. A step of forming a first wiring on a semiconductor substrate, and forming a lower interlayer insulating film having a low polishing rate by chemical mechanical polishing on an entire surface of the semiconductor substrate on which the first wiring is formed.
Film and upper interlayer insulating film with high polishing rate by chemical mechanical polishing
A step of forming an interlayer insulating film consisting of: a step of flattening the interlayer insulating film by chemical mechanical polishing; and a step of forming a second wiring on the flattened interlayer insulating film. A method of manufacturing, wherein the first wiring has a dummy pattern, and a distance between the dummy pattern and a wiring used as a signal line is set to be 3 μm or more and 200 μm or less. Manufacturing method. 10. A step of forming a first wiring on a semiconductor substrate, and lower interlayer insulation having a low polishing rate by chemical mechanical polishing over the entire surface of the semiconductor substrate on which the first wiring is formed.
Upper interlayer insulation with high polishing rate by edge film and chemical mechanical polishing
Semiconductor device including a step of forming an interlayer insulating film composed of the film, and the step of flattening by chemical mechanical polishing the interlayer insulating film, and forming a second wiring planarized interlayer insulating film The method of manufacturing a semiconductor device according to claim 1, wherein the first wiring has a dummy pattern, and the dummy pattern is arranged in a scribe lane around a semiconductor chip. 11. A step of forming a first wiring on a semiconductor substrate, and forming a lower interlayer insulating layer having a low polishing rate by chemical mechanical polishing on an entire surface of the semiconductor substrate on which the first wiring is formed.
Upper interlayer insulation with high polishing rate by edge film and chemical mechanical polishing
Semiconductor device including a step of forming an interlayer insulating film composed of the film, and the step of flattening by chemical mechanical polishing the interlayer insulating film, and forming a second wiring planarized interlayer insulating film The method of manufacturing a semiconductor device according to claim 1, wherein the first wiring has a dummy pattern, and the dummy pattern is arranged at a bonding pad portion. 12. A first wiring is formed on a semiconductor substrate.
Process, on the semiconductor substrate on which the first wiring is formed
Forming an interlayer insulating film on the entire surface;
Step of planarizing by chemical mechanical polishing and planarized layer
Forming a second wiring on the inter-insulation film
A method of manufacturing a device, wherein the first wiring is a dummy pattern.
And use it as a signal line with this dummy pattern.
The distance from the wiring will be 200 μm or less if it is 3 μm or more.
And the dummy patterns are arranged in a block.
And the space of the block of the dummy pattern is 1 μm.
m to 5 μm, line is 1 μm to 5 μm
A method for manufacturing a semiconductor device, comprising: 13. A first wiring is formed on a semiconductor substrate.
Process, on the semiconductor substrate on which the first wiring is formed
Forming an interlayer insulating film on the entire surface;
Step of planarizing by chemical mechanical polishing and planarized layer
Forming a second wiring on the inter-insulation film
A method of manufacturing a device, wherein the first wiring is a dummy pattern.
And the dummy pattern around the semiconductor chip.
The dummy pattern is placed in the scribe lane
Are arranged in a block shape, and the dummy pattern
The space of the mark is 1 μm or more and 5 μm or less, and the line is 1 μm.
A method for manufacturing a semiconductor device, wherein the thickness is not less than m and not more than 5 μm . 14. A first wiring is formed on a semiconductor substrate.
Process, on the semiconductor substrate on which the first wiring is formed
Forming an interlayer insulating film on the entire surface, the layer insulating film
Step of planarizing by chemical mechanical polishing and planarized layer
Forming a second wiring on the inter-insulation film
A method of manufacturing a device, wherein the first wiring is a dummy pattern.
The dummy pattern is
And the dummy pattern is arranged in a block shape.
And the space of the block of the dummy pattern is 1
The line is 1 μm or more and 5 μm or less, with μm or more and 5 μm or less.
A method for manufacturing a semiconductor device. 15. The method according to claim 15, wherein the interlayer insulating film is formed by chemical mechanical polishing.
The lower interlayer insulating film with low polishing rate
And an upper interlayer insulating film with a high polishing rate.
15. The method for manufacturing a semiconductor device according to claim 12, 13, or 14 . 16. The method according to claim 16, wherein the lower interlayer insulating film is a CVD oxide film,
12. The interlayer insulating film is a BPSG film.
16. A method for manufacturing a semiconductor device according to item 15.