JP2002083792A - Manufacturing method for semiconductor device, and the semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method for a semiconductor device and the semiconductor device, with which polishing film thickness can be controlled highly accurately. SOLUTION: In the manufacturing method for semiconductor device, with which a monitor pattern 9 is formed on a scribe line 3 on the surface of a wafer in the same process as formation of wiring (function pattern), a layer insulating film is formed on the wafer in the state of covering wiring and the monitor pattern 9, and the layer insulating film is polished to be flattened, while managing the polishing film thickness by measuring the film thickness of the layer insulating film on the monitor pattern 9; plural monitor patterns 9 are formed on the scribe line 3 and on the basis of the film thickness of the layer insulating film measured on these monitor patterns 9; and the polishing film thickness is controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, and more particularly to a method of manufacturing a semiconductor device for performing planarization polishing while controlling the film thickness and a semiconductor device to which the method is applied.

[0002]

2. Description of the Related Art In recent years, as a feature of a semiconductor integrated circuit, miniaturization of an element in an area direction is progressing, but miniaturization in a height direction is not so advanced. For this reason, recently, semiconductor elements have become three-dimensional, and the absolute step in chip size or wafer size has increased.

In particular, in a semiconductor memory, in order to increase the capacitance of a capacitor while miniaturizing the memory cell, a memory cell portion is three-dimensional, and a large step is generated between the memory cell portion and a peripheral circuit. In a logic IC, wiring is multi-layered for high performance and high speed, and a large step occurs in a sparse part and a dense part of the wiring. This step becomes a major problem during exposure in lithography.

[0004] Along with the increase in resolution of lithography, a problem has been the shallow depth of focus in exposure. The depth of focus has rapidly become shallow due to the increase in the lens diameter and the decrease in the wavelength, and this is an obstacle to miniaturization as the semiconductor element becomes three-dimensional. For further miniaturization, a flattening technique for reducing the absolute step so that exposure can be performed even if the depth of focus is shallow must be incorporated into the process.

Conventionally used SOG and BPSG
The planarization technique of the interlayer insulating film such as reflow is a local (in the range of several μm) planarization technique, and cannot reduce an absolute step in a chip size or a wafer size. At present, chemical mechanical polishing (CMP) can reduce the absolute step.
(Referred to as “polishing”) (see Japanese Patent Publication No. 5-30052, Japanese Patent Application Laid-Open No. 7-285050, etc.).

As an apparatus for performing CMP polishing, there is an apparatus as shown in FIG. This CMP apparatus has a rotating disk 11
And a polishing head 115 disposed opposite to the rotating disk
And A polishing cloth 112 is attached to the rotating disk 111 with an adhesive, and a packing material 114 is attached to the polishing head 115 with an adhesive. Then, the semiconductor wafer 113 having the surface to be polished provided on the packing material 114 is held by a vacuum suction force or a surface tension of water. When CMP polishing is performed using such an apparatus, the layer to be polished is
The semiconductor wafer 113 is held by the polishing head 115 via the packing material 114 in a state facing the one side. Next, the rotating disk 111 and the polishing head 115 are rotated around their respective rotation axes. And the rotating disk 111
The polishing head 115 is pressed against the rotating disk 111 at a predetermined pressure while supplying the polishing agent 116 thereon. As a result, the layer to be polished on the surface of the semiconductor
Polished.

FIG. 8 is a view showing an example of a manufacturing process of a semiconductor device for performing such CMP polishing.
As shown in FIG. 1A, an oxide film 22 is formed on a surface layer of a silicon substrate 21 using a nitride film 24 as a mask, and a first diffusion layer 23 is formed below the oxide film 22. Next, FIG.
As shown in (b), an electrode 25 is formed on the oxide film 22 and a second surface is formed on the exposed surface from which the silicon nitride film (24) has been removed.
Is formed. Thereafter, as shown in FIG. 8C, an interlayer insulating film 27 is formed, and a first wiring 28 is formed thereon. Next, as shown in FIG. 8D, an interlayer insulating film 29 is formed so as to cover the first wiring.
Thereafter, as shown in FIG. 8E, the above-mentioned CMP polishing is performed to flatten the surface of the interlayer insulating film 29. After the above, as shown in FIG.
Is formed.

Here, before forming the second wiring 30, a step of forming a contact hole for connecting the wirings in the vertical direction by etching in the interlayer insulating film 29 is performed. In this case, if the thickness of the interlayer insulating film 29 is large, the contact hole does not reach the first wiring 28, resulting in poor connection. Conversely, if the thickness of the interlayer insulating film 29 is small, the contact hole penetrates through the first wiring 28, which causes a problem such as an increase in the resistance value. Therefore, in the step of flattening the interlayer insulating film 29 described with reference to FIG. 8E, the thickness of the interlayer insulating film 29 on the first wiring 28 is reduced when performing CMP polishing for product management. It is necessary to measure and detect the film thickness (formed film thickness) at the time of forming the interlayer insulating film 29, the amount of polishing, and the film thickness after polishing.

Therefore, usually, a monitor pattern for film thickness measurement is provided on the same layer as the first wiring 28,
The film thickness of the interlayer insulating film 29 is measured on this monitor pattern, and thereby the film thickness before and after polishing is controlled (see JP-A-11-219922).

FIG. 9 is a diagram showing an example of the arrangement of monitor patterns on a wafer (ie, on a semiconductor substrate).
As shown in this figure, the front side of the wafer 1 is divided into a plurality of chip areas 5 by scribe lines 3.
Then, monitor patterns 8 and 9 having a quadrangular planar shape as viewed from above are provided in the center of the scribe line 3 or in the chip region 5. Further, for example, the monitor pattern 8 in the chip region 5 is provided inside or at the periphery of each functional region 5a, and further, adjacent to the functional region 5a.

The process from the formation of the monitor patterns 8 and 9 to the flattening process will be described with reference to the cross-sectional process drawing of the main part of FIG. First, as shown in FIG. 10A, a base insulating film 2 made of silicon oxide is formed on the surface of a wafer 1 made of silicon, and a surface layer of the base insulating film 2 is etched to form scribe lines 3. . At this time, the island pattern 4 is left near the center of the scribe line 3. This also divides the front side of the wafer 1 into chip regions 5. In the drawing, one scribe line 3
And two chip areas 5 arranged on both sides thereof. Next, as shown in FIG. 10B, a wiring layer 6 made of aluminum or polysilicon is formed on the base insulating film 2. Thereafter, as shown in FIG. 10C, the wiring layer 6 is patterned to form a linear wiring 7 and quadrangular monitor patterns 8, 9. Here, wiring 7
Are formed in the chip area 5 and the monitor patterns 8 and 9
Are formed above the island pattern 4 in the scribe line 3 or in the chip region 5.

When an insulating film having a flat surface is formed on the wafer 1 so as to cover the wiring 7, first, FIG.
As shown in (d), the wiring 7 and the monitor patterns 8, 9
Is formed on the base insulating film 2 so as to cover the base insulating film 2. Next, while measuring the film thickness of the interlayer insulating film 10 on the monitor patterns 8 and 9,
The interlayer insulating film 10 is polished by CMP.

At this time, as one of management methods for keeping the variation in the film thickness of the interlayer insulating film 10 within a certain standard range, the film thickness at a certain location is measured and the film thickness is adjusted to the center value of the standard range. Therefore, there is a means for making the variation in the film thickness within the standard range even if there is variation in the process.

[0014]

However, the above-described manufacturing method has the following problems. FIG. 11 shows FIG.
FIG. 12 is an enlarged cross-sectional view of the process from (d) to FIG. 10 (e), and FIG. 12 is a plan view of FIG. Note that FIG.
Corresponds to the II-II section in FIG. 12, and the illustration of the interlayer insulating film is omitted in FIG. As shown in these figures, it is generally known that CMP polishing has an underlying pattern dependency in flatness. In other words, the polishing rate is higher in a portion having a lower pattern density (here, on the monitor pattern 9 in the scribe line 3) than in a surrounding portion having a higher pattern density (here, the chip region 5).

Therefore, the interlayer insulating film 10 after polishing is
Has a large depression on the scribe line 3 and becomes like a wavy line h2 in FIG. Where CMP
Assuming that a completely planarized surface has been formed by the polishing, the surface looks like a wavy line h1 in FIG. 11, and the difference is indicated by d2 in the figure.

Further, as shown in FIG.
(E) A wiring 7 'and a monitor pattern 8', 9 'are further formed on the upper layer, and as shown in FIG. 3B, an interlayer is formed so as to cover the wiring 7' and the monitor pattern 8 ', 9'. Even when the insulating film 10 'is formed and polished by CMP, the surface of the interlayer insulating film 10' does not become a completely flat surface as described above. This is the same regardless of the number of the upper layer.

As described above, after CMP polishing,
The thickness of the interlayer insulating film 10 on the monitor pattern 9 arranged on the scribe line 3 has a different value depending on the density of the wiring 7 arranged in the chip region 5 around the monitor pattern 9. Only by measuring the thickness of the interlayer insulating film 10 on the arranged monitor pattern 9, the interlayer insulating film 1 over the entire wafer or chip region is measured.
It is impossible to grasp the film thickness of 0, and it is not possible to grasp where the measured value is in the film thickness distribution of the interlayer insulating film 10. For this reason, when the polished film thickness of the interlayer insulating film 10 is controlled based on this measurement value, the film thickness in the vicinity of the measurement point falls within the management specification range, but the thickness of the other portions exceeds the specification range. There is.

On the other hand, when a plurality of monitor patterns 8 are arranged in the chip area 5,
Since the wiring formation area inside the semiconductor device is reduced, restrictions are imposed on the circuit design of the semiconductor device, which causes a reduction in the degree of freedom in circuit design.

In addition, wiring 7 as thin as a memory cell region
Cannot be arranged in an area in which (continuously) must be densely arranged. Further, on such a thin wiring 7, since the spot diameter of the film thickness measuring device is larger than the wiring width, the film thickness cannot be measured directly on the thin wiring 7. That is, it is impossible to directly measure the thickness of the interlayer insulating film 10 in such a dense region of the thin wiring 7. For this reason, it is not possible to accurately detect variations in the thickness of the interlayer insulating film 10 in the plane of the chip region due to polishing, and the thickness of the interlayer insulating film 10 in each part on the chip region is within the standard range. It is not possible to judge exactly whether or not.

Accordingly, the present invention provides a method of manufacturing a semiconductor device capable of improving the accuracy of measuring the thickness of a layer to be polished and performing flattening polishing while accurately controlling the thickness of the polished film over the entire chip region on the wafer surface. It is an object to provide a method and a semiconductor device.

[0021]

According to the present invention, there is provided a semiconductor device for flattening and polishing a layer to be polished formed on a wafer while covering a functional pattern on the surface of the wafer. The present invention relates to a method and a semiconductor device to which the method is applied.

In the first manufacturing method, a plurality of monitor patterns are formed on a scribe line on the wafer surface side in the same step as the step of forming a functional pattern on the wafer. Then, when flattening and polishing the polished layer covering the functional pattern and the monitor pattern, the polished film thickness is managed based on the film thickness of the polished layer measured on the plurality of monitor patterns.

The first semiconductor device is a semiconductor device to which the above-described first manufacturing method is applied. The first semiconductor device is provided on a scribe line on the wafer surface side when measuring the thickness of the upper layer to be polished. A plurality of monitor patterns are provided.

In the first manufacturing method and the first semiconductor device, a plurality of monitor patterns are arranged on the scribe line, so that the monitor patterns are not arranged in the chip region, and the plurality of monitor patterns are arranged on the wafer. The thickness of the polished layer can be measured. Therefore, it is possible to accurately predict the variation in the thickness of the layer to be polished in the chip region surrounded by the scribe line from a plurality of thickness measurement values, while securing the design freedom of the functional pattern in the chip region. Become.

In the second manufacturing method, three steps from the end of the dense area of the functional pattern are performed in the same step as the formation of the functional pattern.
When a monitor pattern is formed in a region closer than 00 μm, and the functional layer and the polished layer covering the monitor pattern are planarized and polished, the monitor pattern is formed based on the thickness of the polished layer measured on the monitor pattern. It is characterized in that the thickness of the polished film is controlled.

The second semiconductor device is a semiconductor device to which the above-described second manufacturing method is applied. The second semiconductor device has an upper layer covering a region closer than 300 μm from the end of the dense region of the functional pattern provided on the wafer. A feature is that a monitor pattern serving as a base is provided when measuring the thickness of the polishing layer.

According to the second manufacturing method and the second semiconductor device, 300 μm from the end of the dense area of the functional pattern.
The monitor pattern is arranged in a closer area. here,
In a region closer than 300 μm from the end of the dense region, the change in the thickness of the polished layer covering the functional pattern shows almost constant behavior according to the distance from the dense region. For this reason, it is possible to accurately predict the thickness of the layer to be polished on the dense area where the monitor pattern cannot be arranged, based on the distance from the dense area of the monitor pattern and the thickness of the layer to be polished on the monitor pattern. Will be possible.

According to the third manufacturing method of the present invention, a monitor pattern is previously incorporated in a design area in which the arrangement of the functional pattern is standardized, and the same step as the formation of the functional pattern is performed. A monitor pattern is formed within the standard design area. Then, when performing the flattening polishing, the polishing film thickness is controlled based on the film thickness of the layer to be polished measured on the monitor pattern.

The third semiconductor device is a semiconductor device to which the above-mentioned third manufacturing method is applied, and measures the thickness of an upper layer to be polished in a standard design region of a standardized functional pattern. It is characterized in that a monitor pattern serving as a base when performing the operation is incorporated.

In the third manufacturing method and the third semiconductor device, since the monitor pattern is incorporated in the standard design region in advance, in the semiconductor device having the standard design region, the monitor pattern around the monitor pattern is not provided. The arrangement state of the functional patterns is always kept constant. Therefore, by measuring the thickness of the layer to be polished on the monitor pattern, the thickness of the layer to be polished in the standard design region can be predicted without being interfered by the arrangement state of the functional patterns around the monitor pattern. .

[0031]

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the same components as those described in the related art are denoted by the same reference numerals and will be described, and redundant description will be omitted.

(First Embodiment) FIG. 1 is a plan view of a main portion of a wafer surface for explaining a first embodiment, and FIG.
FIGS. 2A and 2B are main-portion cross-sectional views for describing the first embodiment. Some components are shown only in FIG.

The semiconductor device according to the first embodiment will be described in the order of manufacturing steps with reference to these drawings. First, a base insulating film 2 is formed on the surface of the wafer 1, and the surface layer of the base insulating film 2 is etched to form scribe lines 3, whereby the front side of the wafer 1 is divided into chip regions 5. . At this time, a plurality of island-shaped patterns 4 are left near the center of the scribe line 3 in a state surrounding the chip region 5.

Next, a wiring forming layer is formed on the base insulating film 2 and is patterned to form a wiring 7 as a functional pattern in the chip region 5. These wirings 7
Is a thick wiring 7a having a line width of several μm or a thin wiring 7b having a line width of 1 μm or less. At the same time as the formation of these wirings 7 (7a, 7b), a monitor pattern 9 is formed on the island pattern 4 in the scribe line 3. That is, a plurality of monitor patterns 9 having the same material and structure as the wiring 7 (7a, 7b) are formed in the scribe line 3 so as to surround the chip region 5.

The monitor pattern 9 has a diameter of a measuring beam (for example, 4 to 5 μm) in the film thickness measurement to be performed later.
It is preferably a quadrilateral having a width similar to that of m) and a length greater than this width. Here, as for the monitor patterns 9 around the chip region 5, the greater the number, the more accurate the measurement of the film thickness can be obtained.
Around the small chip area 5 of 10 mm × 10 mm or less, 3 to 4 monitor patterns 9 are arranged on one side,
Around a large chip area 5 of not less than 20 mm × 20 mm,
The monitor pattern 9 is arranged every 3 to 5 mm. However,
When the same wiring layout is repeatedly arranged in the chip region 5, it is not necessary to arrange the monitor patterns 9 on the four sides of the chip region 5 where measurement is desired. What is necessary is just to arrange the monitor pattern 9.

FIG. 2A shows the scribe line 3
The cross section of a portion where the thick wiring 7a is densely arranged in the chip region 5 on one side and the thin wiring 7b is densely arranged in the chip region 5 on the other side is illustrated. Also,
FIG. 2B shows a cross section of a portion in which thin wires 7b are arranged at a low density in the chip region 5 on one side of the scribe line 3 and no wires are arranged in the chip region 5 on the other side. .

As described above, the wiring 7 (7a, 7b)
After the formation of the monitor pattern 9 and the monitor pattern 9, an interlayer insulating film 10 serving as a layer to be polished (shown only in FIG.
To form Here, in the cross-sectional view of FIG. 2, the surface on which the interlayer insulating film 10 is formed is indicated by a broken line.

Next, the interlayer insulating film 10 having such a film forming surface is polished by CMP to thereby form the interlayer insulating film 1.
0 is flattened. The surface of the interlayer insulating film 10 after the CMP polishing is shown by a solid line.

As shown in these figures, the thickness of the interlayer insulating film 10 after the CMP is affected by the arrangement of the underlying patterns (ie, the wiring and the monitor pattern), and the thick wirings 7a are densely arranged. Thicker on the area where
Similarly, the thickness also increases on the monitor pattern 9a adjacent to this area. On the other hand, the film thickness of the interlayer insulating film 10 is thin on a region where the thin wires 7b are arranged at a low density, on a region where the wires are not arranged, and on the monitor pattern 9b adjacent thereto. Become. this is,
This is because the polishing rate at each part on the surface of the interlayer insulating film 10 differs depending on the density of the polished surface.

Therefore, in this CMP polishing step, the interlayer insulating film 1 on the monitor pattern 9 (9a, 9b) is formed.
By measuring the film thickness of 0, the CMP polishing is performed while controlling the polishing amount (that is, the polishing film thickness).

At this time, the film thickness of the interlayer insulating film 10 on each of the plurality of monitor patterns 9 (9a, 9b) arranged at each part in the scribe line 3 is measured. Then, while controlling the polishing amount based on the measured value, the CMP polishing is completed without excess or deficiency.

Here, in order to control the polishing amount, it is necessary to know the maximum value and the minimum value of the interlayer insulating film 10 in the chip region 5. However, it is actually difficult to find such a place, and it is required to obtain a value as close as possible. Further, such a value can be obtained by arranging a large number of monitor patterns 8 in the chip area 5, but in such a case, the effective area (that is, the wiring area) in the chip area 5 is reduced. Let
This imposes restrictions on the wiring design. When a monitor pattern is arranged in a gap between wirings in the chip region 5 so as not to restrict wiring design,
When registering the position of the monitor pattern in the film thickness measuring device, it becomes difficult to find the monitor pattern.

Then, the maximum value and the minimum value of the thickness of the interlayer insulating film 10 measured on all the monitor patterns 9 (9a, 9b) arranged on the scribe line 3 are used to determine the interlayer thickness in the chip region 5. The minimum value and the maximum value of the thickness of the insulating film 10 are predicted.

That is, the point 12c where the thickness of the interlayer insulating film 10 becomes the maximum value in the chip region 5 is a portion where the thick wiring 7a is arranged most densely. And
Since each monitor pattern 9 is narrower than the thick wiring 7a and has a sparse arrangement, the maximum value of the film thickness on the monitor pattern 9 is smaller than the maximum value of the film thickness in the chip region 5. Become. For example, in FIG. 1, the polished interlayer insulating film has the largest thickness on the monitor pattern 9a arranged between the regions 5a where the wirings having a large line width are densely arranged. Is smaller than the maximum value of the film thickness in the chip region 5.

On the other hand, a point 12d where the film thickness of the interlayer insulating film 10 is minimum in the chip region 5 is a portion where the thin wiring 7b is arranged most sparsely. Since each monitor pattern 9 is wider than the thin wiring 7b, the minimum value of the film thickness on the monitor pattern 9 is larger than the minimum value of the film thickness in the chip region 5. For example, in FIG. 1, the thickness of the polished interlayer insulating film is the smallest on the monitor pattern 9b between the regions 5b where the thin lines 7b are sparsely arranged. 5 is larger than the minimum value of the film thickness.

From the above, all monitor patterns 9
From the maximum value and the minimum value of the film thickness of the interlayer insulating film 10 measured on (9a, 9b), the minimum value and the maximum value of the film thickness of the interlayer insulating film 10 in the chip region 5, that is, the variation of the polishing amount. Can be expected. Then, based on these measured values, the CMP polishing is terminated without excess or deficiency while controlling the polishing amount.

For example, an intermediate value between the maximum value and the minimum value of the film thickness of the interlayer insulating film 10 in the chip region 5 is the maximum value and the minimum value of the film thickness of the interlayer insulating film 10 on the monitor pattern 9. Is almost equal to the intermediate value of.

Therefore, in order to suppress the variation of the film thickness of the interlayer insulating film 10 within a certain standard range and finish the CMP polishing, an intermediate value of the measured film thickness of the interlayer insulating film 10 (that is, approximately the chip region 5) is used. CMP polishing is performed so that the intermediate value of the film thickness within the range is the center value of the standard range. Thereby, even if there is a variation in the process, the variation in the film thickness of the interlayer insulating film 10 in the chip region 5 falls within the standard range.

In the manufacturing method described in the first embodiment and the semiconductor device of the first embodiment in which the plurality of monitor patterns 9 are arranged on the scribe line 3, the interlayer insulation is provided at a plurality of locations around the chip region 5. The thickness of the film 10 can be measured. Therefore, the interlayer insulating film 10 in the chip area 5 plane is obtained from a plurality of thickness measurement values.
Can be accurately predicted. Therefore, it is possible to perform the CMP polishing without arranging a plurality of monitor patterns in the chip region 5, that is, while controlling the polishing amount with high accuracy while securing the freedom of the wiring design in the chip region 5. become.

In the above-described first embodiment, a monitor pattern from which the average value of the film thickness of the interlayer insulating film 10 is obtained is selected in advance from among the monitor patterns 9 and C
At the time of MP polishing, the film thickness of the interlayer insulating film 10 may be measured only on the selected monitor pattern. Here, the average value is a statistical value such as an average value or an intermediate value of the thicknesses of the interlayer insulating films 10 on all the monitor patterns 9.

For example, as described above, the intermediate value between the maximum value and the minimum value of the film thickness of the interlayer insulating film 10 in the chip region 5 is the maximum value of the film thickness of the interlayer insulating film 10 on the monitor pattern 9. It is almost equal to the intermediate value between the value and the minimum value.

Therefore, prior to the CMP polishing during the manufacturing process, a test CMP polishing is performed in advance, and the thickness of the interlayer insulating film 10 on all the monitor patterns 9 is measured. Then, for example, monitor patterns indicating the above-described maximum value and minimum value are selected from the obtained measured values, and the monitor patterns 9a and 9b from which the measured values are obtained are used as monitor patterns for measurement during the manufacturing process. Select it. The monitor patterns 9a and 9b selected here are:
From the viewpoint of reducing the time required for the measurement, it is desirable that the number is small as long as the accuracy of the prediction of the variation of the interlayer insulating film 10 on the chip region 5 is maintained.

In the CMP polishing in the manufacturing process, an intermediate value obtained from the film thickness of the interlayer insulating film 10 measured on the selected monitor patterns 9a and 9b is used to calculate the thickness of the interlayer insulating film 10 on the chip region 5. The intermediate value is predicted, and the CMP polishing is completed without excess or deficiency as described above.

As described above, by selecting a monitor pattern showing an average value from all the monitor patterns 9 and measuring the film thickness of the interlayer insulating film 10 only on the selected monitor pattern, In addition to the effect of the first embodiment, an effect that the time required for measurement can be reduced can be obtained. Note that the monitor pattern selected by the experimental CMP polishing is not limited to the one showing the maximum value and the minimum value described above, and the average of the film thickness of the interlayer insulating film 10 on all the monitor patterns 9 is not limited. What is necessary is just to show a suitable value.

(Second Embodiment) FIG. 3 is a cross-sectional view of a principal part for describing a second embodiment. The semiconductor device of the second embodiment and a method of manufacturing the same will be described below with reference to FIG. .

First, the wiring 7 is formed on the chip region on the front surface side of the wafer 1. At this time, in a part of the chip area, for example, a dense area 5c in which thin wires 7b are continuously generated in a dense state like a memory area is arranged. Then, at the same time as the formation of the wiring 7b, the monitor pattern 8 is formed at a position closer than 300 μm from the end A of the dense area 5c (end of the dense area).

Here, it is assumed that the monitor pattern 8 has the same planar shape as that described in the first embodiment. Then, at a position closer than 300 μm from the dense area end A,
For example, the center position O of the monitor pattern 8 is arranged. That is, the distance t between the dense area end A and the center position O of the monitor pattern 8 is a value smaller than 300 μm.

After the above, an interlayer insulating film 10 is formed so as to cover the wiring 7 and the monitor pattern 8. Next, the surface of the interlayer insulating film 10 is planarized by subjecting the interlayer insulating film 10 to CMP polishing. At this time, by measuring the film thickness of the interlayer insulating film 10 on the monitor pattern 8, the film thickness of the interlayer insulating film 10 on the dense area 5c is predicted, and the CMP polishing is performed while controlling the polishing amount. The amount of polishing on the dense area 5c is determined from the relationship between the distance t between the end A of the dense area and the monitor pattern 8 and the thickness of the interlayer insulating film 10 on the monitor pattern 8.

FIG. 4A is a graph showing the relationship between the distance t between the dense area end A and the monitor pattern 8 and the thickness of the interlayer insulating film 10 on the monitor pattern 8. FIG. 4B shows the thickness of the interlayer insulating film at the dense region end A in FIG. 4A (that is, at the distance t = 0).
It is a graph according to the same value. From these graphs,
It can be seen that within a range of 300 μm from the end A of the dense region, the change in the thickness of the interlayer insulating film 10 shows the same behavior corresponding to the distance from the end A of the dense region irrespective of the overall thickness. .

Here, FIGS. 5A and 5B are cross-sectional views of portions around the dense area 5c where the arrangement state of the wiring 7 is different after CMP polishing. FIG. 5 (a)
FIG. 5 (b) shows a portion where the thick line 7a is densely arranged around the dense region 5c where the thin line 7b is densely arranged. FIG. 5 (b) shows the thin line around the dense region 5c. 7b
Indicates a portion arranged in a sparse state.

As shown in these figures, the interlayer insulating film 10 on the region 5a where the thick wiring 7a is densely arranged is provided.
Is thicker than the film thickness 13b of the interlayer insulating film 10 on the region 5b where the thin wires 7b are sparsely arranged. Along with this, the film thickness 13ea of the interlayer insulating film 10 on the dense area 5c located near the area 5a where the thick wiring 7a is densely arranged is reduced to the area 5b where the thin wiring 7b is arranged in a sparse state. Is thicker than the film thickness 13eb of the interlayer insulating film 10 on the dense region 5c located near the center.

However, with reference to the end of the dense region 5c (ie, the end of the dense region A), when the distance from the end A of the dense region is small, the change in the thickness of the interlayer insulating film 10 with respect to the distance from the end A of the dense region The quantities 14a and 14b have substantially the same value, and the closer to the dense area end A, the smaller the variation. Conversely, the further away from the dense area end A, the more the change in film thickness 1
The difference between 4c and 14d increases.

From the above, the position close to the dense region end A to the extent that the amount of change in the thickness of the interlayer insulating film 10 is maintained at substantially the same value, that is, as shown in the graph of FIG. By measuring the film thickness of the interlayer insulating film 10 on the monitor pattern at a position closer than 300 μm from the distance, the film thickness of the interlayer insulating film 10 in the dense region 5c is predicted.

In other words, when controlling the thickness of the polished film during CMP polishing, if it is desired to detect the film thickness of the interlayer insulating film 10 in the dense region 5c, it is necessary to preliminarily measure 3 to 3
A relationship between the distance t between the dense area end A and the monitor pattern 8 in the range of 00 μm and the thickness of the interlayer insulating film 10 on the monitor pattern 8 (that is, FIG. 4) is obtained. In the CMP process in the manufacturing process, the distance t between the dense area end A and the monitor pattern 8 and the thickness of the interlayer insulating film 10 measured on the monitor pattern 8 arranged near the dense area 5c The thickness of the interlayer insulating film 10 in the dense region 5c is determined in light of the above relationship,
The polishing film thickness is controlled based on the film thickness.

For example, the distance t between the dense area end A and the monitor pattern 8 in the range of 300 μm from the dense area end A
And the film thickness of the interlayer insulating film 10 on the monitor pattern 8 is such that the film thickness of the interlayer insulating film 10 is reduced by 10 nm every 100 μm from the dense area end A.
In the case of a quadratic relationship, the thickness (nm) of the interlayer insulating film in the dense region 5c = the thickness (n) of the monitor pattern
m) + distance t (μm) × 10 (nm) / 100 (μm)
Required by

According to the method of the second embodiment described above, the interlayer insulation in the dense region 5c in which the wiring 7b having a small line width such that the thickness of the interlayer insulation film 10 cannot be measured is densely arranged at the upper portion. The thickness of the interlayer insulating film 10 on the monitor pattern 8 disposed around the film 10
Can be accurately predicted from the thickness of the film. Therefore, as data for managing the polishing film thickness in the CMP polishing, the interlayer insulating film 10 on the dense region 5c is used as data.
It is possible to use the film thickness of, and it is possible to improve the accuracy of controlling the polishing film thickness.

(Third Embodiment) FIG. 6 is a plan view for explaining a third embodiment. Hereinafter, a semiconductor device of the third embodiment and a method for manufacturing the same will be described with reference to FIG.

The semiconductor device shown in this figure has a configuration in which a plurality of macros 15 and other areas 16 are arranged in a chip area 5. Each macro 15 is a functional area in which the wiring layout is standardized (that is, a standard design area). For example, a memory 15a in which thin wirings (not shown) are continuously generated in a dense state, and a peripheral circuit area 15b And the same layout.

Here, in particular, a plurality of monitor patterns 8 are incorporated as patterns constituting these macros 15 in the design stage of the semiconductor device. That is, in the semiconductor device provided with the macro 15, the monitor pattern 8 is arranged at the same position in each macro 15 even for different products.
In this case, the memory area 15a is a dense area in which thin wirings are densely arranged, and inside this area, the monitor pattern 8
There is no gap to place. For this reason, the monitor pattern 8 is arranged in an empty area outside the dense area 5c, in the peripheral circuit area 15b or in the vicinity thereof.

When the interlayer insulating film (not shown) covering these regions is polished by CMP, the thickness of the interlayer insulating film on each monitor pattern 8 is measured, and the thickness of the polished film is determined based on the measured value. Manage.

At this time, from among the plurality of monitor patterns 8 arranged in advance in one macro 15, the thickness of the interlayer insulating film is set to the average value or the intermediate value of the thickness of the interlayer insulating film in the macro 15. May be selected, and the thickness of the interlayer insulating film on the selected monitor pattern may be measured. Also, if the thickness of the interlayer insulating film is macro 1
5, a monitor pattern having a value showing a certain difference with respect to the average value or the intermediate value of the film thickness of the interlayer insulating film is selected, and the film thickness of the interlayer insulating film on the selected monitor pattern is measured. May be. In this case, an average value or an intermediate value is calculated from the measured film thickness to control the thickness of the polished film.

According to such a method, by incorporating the monitor pattern 8 in the standardized macro 15 in advance, the wiring layout around the monitor pattern 8 can always be kept constant. Therefore, even if the products are different, the thickness distribution of the polished layer in the macro 15 can be measured by measuring the thickness of the interlayer insulating film on these monitor patterns 8 without being interfered by the peripheral wiring layout. (Or average value of film thickness),
It is possible to improve the control accuracy of the polishing film thickness.

In the third embodiment, as described in the second embodiment, some of the plurality of monitor patterns 8 are set to 300 μm from the end of the dense wiring area such as the memory area 15a. By arranging the interlayer insulating film 10 in a closer area, the thickness of the interlayer insulating film 10 in the memory area 15a can be accurately predicted. Therefore, CMP
As data for controlling the thickness of the polished film in polishing, the thickness of the memory region 15a can be used, and the accuracy of controlling the polished film thickness can be further improved.

[0074]

As described above, according to the method of manufacturing a semiconductor device and the semiconductor device of the present invention, it is possible to more accurately grasp the thickness of the layer to be polished in the entire chip region, and In the flattening polishing of the layer, it is possible to improve the control accuracy of the polishing film thickness. As a result, it is possible to obtain a semiconductor device in which the thickness accuracy of the layer to be polished is well controlled.

[Brief description of the drawings]

FIG. 1 is a plan view for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining the first embodiment of the present invention.

FIG. 3 is a sectional view for explaining a second embodiment of the present invention.

FIG. 4 is a graph for explaining a second embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining the dependence of the film thickness after polishing on the underlying pattern.

FIG. 6 is a plan view for explaining a third embodiment of the present invention.

FIG. 7 is a diagram for explaining CMP polishing.

FIG. 8 is a cross-sectional process diagram for explaining CMP polishing in the manufacturing process of the semiconductor device.

FIG. 9 is a plan view showing an arrangement of monitor patterns for explaining a conventional semiconductor device and a method of manufacturing the same.

FIG. 10 is a sectional process view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 11 is a cross-sectional view (part 1) for describing a problem of the conventional technique.

FIG. 12 is a plan view for explaining a problem of a conventional technique.

FIG. 13 is a sectional view (part 2) for describing a problem of the conventional technique.

[Explanation of symbols]

1 ... wafer, 3 ... scribe line, 5 ... chip area,
7, 7a, 7b ... wiring (functional pattern), 8, 9, 9
a, 9b: monitor pattern, 10: interlayer insulation film (layer to be polished), 15: macro (standard design area), A: edge of dense area, t: distance

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/88 S (72) Inventor Tetsuya Shiratsuka 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Within Fujitsu Limited (72) Inventor Naoki Iya 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture F-term within Fujitsu Limited (reference) 4M106 AA01 AA07 AA12 CA24 CA48 DH03 DH57 DJ32 5F033 HH00 QQ48 RR00 UU03 VV12 WW01 XX01 5F043 AA29 DD16 DD25 FF07 GG03

Claims (11)

[Claims] 1. A monitor pattern is formed on a scribe line on a wafer surface side in the same step as the formation of a functional pattern, and a layer to be polished is formed on the wafer so as to cover the functional pattern and the monitor pattern. In a method of manufacturing a semiconductor device for performing flattening and polishing of a polished layer while controlling a polished film thickness based on a film thickness of the polished layer measured on a pattern, the step of forming the monitor pattern includes: Forming a plurality of monitor patterns on a scribe line, in the step of flattening and polishing the layer to be polished, the polishing of the layer to be polished based on the film thickness of the layer to be polished measured on the plurality of monitor patterns. A method for manufacturing a semiconductor device, comprising controlling a polished film thickness. 2. The method for manufacturing a semiconductor device according to claim 1, wherein prior to the step of flattening and polishing the layer to be polished, trial flattening and polishing are performed on the plurality of monitor patterns. Measuring the film thickness of the polishing layer, selecting a monitor pattern from which an average value can be obtained from the measured film thickness, and performing the flattening polishing of the polished layer, Controlling the polished film thickness of the polished layer based on the film thickness of the polished layer measured by the method. 3. A method of manufacturing a semiconductor device in which a layer to be polished formed on a wafer is planarized and polished so as to cover a functional pattern on a wafer surface side, wherein the functional pattern is formed in the same step as the formation of the functional pattern. Forming a monitor pattern in an area closer than 300 μm from the end of the dense area, forming a layer to be polished on the wafer so as to cover the functional pattern and the monitor pattern, and measuring the polished layer measured on the monitor pattern. A method for manufacturing a semiconductor device, comprising: flattening and polishing a layer to be polished while controlling a polishing film thickness based on a film thickness of the layer. 4. The method of manufacturing a semiconductor device according to claim 3, wherein prior to the step of flattening and polishing the layer to be polished, trial flattening and polishing are performed to form an edge of the dense region of the functional pattern and In the step of obtaining the relationship between the distance to a monitor pattern and the thickness of the layer to be polished on the monitor pattern, and performing the flattening polishing, the thickness of the layer to be polished measured on the monitor pattern And determining the thickness of the layer to be polished on the dense area of the functional pattern by associating the distance between the monitor pattern and the edge of the dense area with the relationship, and managing the polished film thickness based on this value. A method for manufacturing a semiconductor device, comprising: 5. A method for manufacturing a semiconductor device for planarizing and polishing a layer to be polished formed on a wafer in a state of covering a functional pattern on a front surface side of the wafer, wherein a standard design area in which arrangement of the functional patterns is standardized. In the same step as the formation of the functional pattern, the monitor pattern is formed in a standard design region on the front surface side of the wafer, and the monitor pattern is formed in a state of covering the functional pattern and the monitor pattern. Forming a layer to be polished on a wafer, and performing flattening polishing of the layer to be polished while controlling a polishing film thickness based on the film thickness of the layer to be polished measured on the monitor pattern. A method for manufacturing a semiconductor device. 6. The semiconductor device manufacturing method according to claim 5, wherein the monitor pattern is arranged in an area closer than 300 μm from an end of a dense area of the functional patterns in the standard design area. Device manufacturing method. 7. The method of manufacturing a semiconductor device according to claim 6, wherein before the step of flattening and polishing the layer to be polished, trial flattening and polishing is performed so that the edge of the dense region of the functional pattern is The relationship between the distance to a monitor pattern and the thickness of the polished layer is obtained, and in the step of performing the planarization polishing, the thickness of the polished layer measured on the monitor pattern and the monitor pattern are determined. A semiconductor wherein the thickness of the polished layer on the dense area of the functional pattern is determined by associating the distance with the edge of the dense area with the relationship, and the polished film thickness is controlled based on this value. Device manufacturing method. 8. A scribe line on a wafer surface side,
A semiconductor device comprising a plurality of monitor patterns serving as bases when measuring the thickness of an upper layer to be polished. 9. A monitor pattern serving as a base when measuring a film thickness of an upper layer to be polished is provided in an area closer than 300 μm from an end of a dense area of a functional pattern provided on a wafer. Characteristic semiconductor device. 10. A monitor pattern serving as a base when measuring the film thickness of an upper layer to be polished is incorporated in the standard design region of the standardized function pattern together with the function pattern. Semiconductor device. 11. The semiconductor device according to claim 10, wherein the monitor pattern is arranged in an area closer than 300 μm from an end of a dense area of the functional patterns in the standard design area.