KR100518244B1 - Method of manufacturing alignment keys - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an alignment key. In particular, an opening is formed by removing a predetermined portion of an etched layer to be etched in advance, and then the alignment key is formed on an exposed wafer surface or an underlying layer of the etched layer. Therefore, the present invention relates to an alignment key manufacturing method used in a semiconductor exposure apparatus which prevents degradation of the alignment key caused by CMP. The method of manufacturing an alignment key according to the present invention comprises the steps of forming a first layer on a substrate, removing a predetermined portion of the first layer to form an opening exposing a predetermined portion of the substrate, and a first including an opening. Forming a second layer on the layer, and forming a first pattern of the second layer remaining by patterning the second layer on the first layer, and simultaneously opening a second pattern of the remaining second layer. It is formed to include.

Description

Method of manufacturing alignment keys

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an alignment key. In particular, an opening is formed by removing a predetermined portion of an etched layer to be etched in advance, and then the alignment key is formed on an exposed wafer surface or an underlying layer of the etched layer. Therefore, the present invention relates to an alignment key manufacturing method used in a semiconductor exposure apparatus which prevents degradation of the alignment key caused by CMP.

With the high integration of semiconductor devices, it is important to secure accurate wafer alignment as well as critical dimensions such as line widths of devices for manufacturing ultra-high density semiconductor devices of 256M or more.

In general, in the manufacture of semiconductor devices, securing the correct alignment is controlled in a photo process of transferring a desired pattern onto a wafer.

Measurement and correction of alignment is performed before the actual light source is irradiated to the etched layer formed on the wafer.In the first case, the automatic measurement and correction is performed by the exposure apparatus, and additional external input is provided only when the primary automatic correction is insufficient. Secondary correction is done to finally correct the degree of alignment. At this time, since the measurement of the alignment key is made by automatic measurement by the exposure apparatus, the accuracy of the alignment is guaranteed according to the accuracy of the measurement in this process.

As semiconductor devices are highly integrated, the height of the memory cell region is further increased to ensure satisfactory capacitance in a limited narrow area. Therefore, the step between the memory cell filtration and the peripheral area becomes larger, which makes it difficult to process the photo process for narrow space patterning. In order to solve this problem, a capacitor having sufficient steps is patterned, and then CMP is used as a planarization process for the entire wafer to eliminate accumulated steps.

CMP has a high polishing rate due to the higher pressure at the relatively high pressure due to the different pressure of the contact area due to the topography when each part in the chip having different heights is in contact with the polishing pad. In order to make up for the weak points such as mechanical elements and scratches on the surface during polishing and process control uncertainty, the slurry is distributed in the polishing site to increase the ductility of the contact area, thereby reducing the scratch and polishing between the thin films. It is a global planarization process that combines chemical elements to achieve polishing rate selectivity, reducing the step by different heights on one chip.

1 is a schematic cross-sectional view of a general chemical mechanical polishing (hereinafter referred to as CMP) process.

Referring to FIG. 1, patterns 11, such as elements, are formed on one surface of the wafer 10, and the patterns 11 are covered with a predetermined layer 12, such as an insulating layer.

In order to planarize the topography of the chip or wafer 10 due to the patterns 11, the polishing cloth 13 is polished with the abrasive 110 interposed on the predetermined layer 12.

As a result of the polishing, the surface of the predetermined layer 12 of the dead part of the wafer 10 is planarized by the combination of the mechanical element caused by the above-described topography difference and the chemical element by the abrasive.

2 is a cross-sectional view illustrating a thinning problem of the CMP process, and FIG. 3 is a cross-sectional view illustrating a dishing problem of the CMP process.

Referring to FIG. 2, as a result of performing the CMP on the predetermined pattern 21 formed on the substrate 20 and the predetermined layer 22 covering the predetermined pattern 21, the upper portion of the area where the patterns 21 are densified is polished more than the surroundings. It is further eroded by the thickness d so that the thickness of the predetermined layer 22 is thinned. Thus, the overall planarization is not satisfactory.

Referring to FIG. 3, as a result of performing the CMP on the predetermined patterns 31 formed on the substrate 30 and the predetermined layer 32 covering the predetermined patterns, the predetermined layer 32 of the portion where the patterns 31 are not dense is formed. More polished than the surrounding area. At this time, since the removed part is similar to the dish shape (D), this is called a dishing effect. Similarly, the CMP results are not satisfactory.

4A to 4E are cross-sectional views illustrating a method for manufacturing an alignment key according to the prior art, and FIG. 5 is a layout of an exposure mask for patterning a memory cell array on an alignment key and an etched layer according to the prior art.

Referring to FIG. 4A, an underlayer 41 of an etched layer to be patterned on the wafer 40 is formed by a deposition method or the like.

Referring to FIG. 4B, the etched layer 41 is formed on the base layer 41 by a deposition method or the like.

4C and 5, patterning the etched layer by photolithography using an exposure mask 50 in which patterns 542 for patterning the etched layer and patterns 543 for forming the alignment key are defined. The alignment key 43 is formed together with the patterns 42 of the main chip region.

Referring to FIG. 4D, the planarization layer 44 is formed on the base layer 41 including the patterns 42 of the main chip region and the alignment key 43 by an interlayer insulating layer such as ILD. do.

Referring to FIG. 4E, in order to planarize the overall topography of the wafer, CMP using the surface of the patterns 42 and 43 as the stop layer is applied to the planarization layer to secure the planarization of the wafer. At this time, due to the above-described thinning or dishing effect, the portion AK1 on which the alignment key 430 is formed is eroded more than the surroundings, so that a part of the alignment key 430 is removed.

Therefore, detection of alignment keys becomes difficult in subsequent photo processes.

As a result, the alignment key manufacturing method according to the prior art described above, first, due to the dishing effect according to the density or density of the pattern during CMP, and the contact area with the pad is larger, resulting in a dishing effect that is proportional to the feature size. In the photo process, the density of patterns on the periphery of the chip on which the alignment key is located to ensure the alignment between layers is largely different from that of the memory cell area. There is a problem in that the reliability of the alignment key is degraded by overpolishing.

Accordingly, an object of the present invention is to remove the predetermined portion of the etched layer to be etched in advance to form an opening, and then form an alignment key in the form of embedded alignment keys on the exposed wafer surface or the underlying layer of the etched layer. It is to provide an alignment key manufacturing method used in a semiconductor exposure apparatus to prevent deterioration.

An alignment key manufacturing method according to the present invention for achieving the above object comprises the steps of forming a first layer on the substrate, forming a opening to expose a predetermined portion of the substrate by removing a predetermined portion of the first layer; Forming a second layer on the first layer including openings, and patterning the second layer to form a first pattern of the remaining second layer on the first layer, and simultaneously to the remaining second layer And forming a second pattern formed in the opening.

The CMP process is a planarization process mainly used for isolation layers, interlayer dielectric layers and intermetal dielectrics. If such CMP is not stably controlled, that is, over-polishing occurs in a predetermined portion, deterioration of the alignment key used for interlayer alignment in a subsequent exposure process occurs.

In the present invention, in order to solve such a problem, an overpolishing problem is solved by forming an area where an alignment key is to be formed in a form buried on the underlayer of the layer to be formed.

In general, the thinning effect is a phenomenon in which the polishing rate varies depending on the density of the pattern. Since the pattern density of the alignment key is formed on the wafer is higher than the periphery, the polishing rate of the high density region is increased according to the polishing selectivity of the increased thin film, and the dishing effect is the feature size. As a result, the wider the area, the larger the contact area with the pad, which is the polishing cloth, and the polishing of this area occurs easily.

Therefore, in order to prevent deterioration due to polishing of the alignment key, the alignment key manufacturing method is improved to avoid the aforementioned two effects.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 6 is a layout of an exposure mask for forming an opening for forming an embedded alignment key according to the present invention, and FIGS. 7A to 7E are cross-sectional views illustrating a method for manufacturing an alignment key according to the present invention.

6 and 7A, an underlayer 71 of an etched layer to be patterned to form memory elements in a memory cell region on a wafer 70 is formed by an deposition method using an insulating layer such as an oxide film. do.

In addition, the underlying layer 71 is formed by photolithography using a mask 60 in which an alignment key formation region W defined to be located at a periphery of the plurality of memory cell array regions MC is defined. A predetermined portion of) is removed to expose the surface of the wafer 70.

Referring to FIG. 7B, various elements of the memory cell may form the etching target layer 71 on the underlying layer 71 including the exposed wafer 70 surface by deposition or the like.

Referring to FIG. 7C, a pattern 720 of the main chip region is patterned by photolithography using an exposure mask (not shown) in which patterns for patterning an etched layer and patterns for forming an alignment key are defined. ) Together to form an alignment key 721. At this time, a portion of the etched layer 722 may remain on the side of the underlying layer 71 that partially exposes the wafer surface, but does not affect the degradation of the alignment key 721.

In addition, since the alignment key 721 has a design rule, there is no difficulty in patterning even if there is a step with a peripheral portion as shown.

Accordingly, while the patterns 720 of the main chip region are formed on the underlayer 71, the alignment key 721 is manufactured to be positioned on the wafer 70 positioned lower than the underlayer 71. Surrounded by topography is lower than the surrounding area, preventing overpolishing during CMP.

Referring to FIG. 7D, the planarization layer 73 is deposited on the base layer 71 including the patterns 720 and the alignment key 721 of the main chip region, and an interlayer insulating layer such as an ILD on the wafer 70. It is formed by such a method.

Referring to FIG. 7E, in order to planarize the overall topography of the wafer, CMP using the surface of the patterns 720 of the main chip region as the stop layer is applied to the planarization layer to secure the planarization of the wafer. At this time, the portion AK2 on which the alignment key 721 is formed is formed lower than the periphery to be free from the above-described thinning or dishing effect.

Therefore, detection of alignment keys becomes difficult in subsequent photo processes.

Accordingly, the present invention has the advantage that the alignment key is prevented from being deteriorated by the CMP to facilitate detection of the alignment key in a subsequent photo process.

1 is a schematic cross-sectional view of a general chemical mechanical polishing (hereinafter referred to as CMP) process

Figure 2 is a cross-sectional view showing a thinning problem of the CMP process

3 is a cross-sectional view showing a dishing problem of the CMP process;

4A to 4E are cross-sectional views illustrating a method for manufacturing an alignment key according to the prior art.

5 is a layout of an exposure mask for patterning a memory cell array on an alignment key and an etched layer according to the related art.

6 is a layout of an exposure mask for forming an opening for forming an embedded alignment key according to the present invention.

7A to 7E are cross-sectional views illustrating a method for manufacturing an alignment key according to the present invention.

Claims (5)

Forming a first layer on the substrate, Removing a predetermined portion of the first layer to form an opening exposing the predetermined portion of the substrate; Forming a second layer on the first layer including the opening; An alignment comprising forming the first pattern of the second layer remaining by patterning the second layer on the first layer, and simultaneously forming a second pattern of the remaining second layer in the openings Key manufacturing method. The method of claim 1, wherein the first pattern is formed for a pattern constituting a memory cell array of a semiconductor memory device, and the second pattern is formed for a photo key for confirming an alignment degree for exposure. . The method of claim 1, wherein after forming the first pattern and the second pattern, Forming a third layer on the first layer and the substrate including the first pattern and the second pattern; And chemically polishing the third layer to planarize the surface of the upper portion of the substrate. The method of claim 1, wherein a plurality of the second patterns are formed at a peripheral portion of the first pattern. The method of claim 1, wherein the third layer is formed for planarization in a device isolation layer, an interlayer insulating layer, or an interwire insulating layer forming process.