JP4258158B2 - Planarization processing method and semiconductor device manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor device manufacturing, and in particular, a planarization processing method and a semiconductor device manufacturing method for planarizing a planarization processing layer on a semiconductor wafer having a large-area element formation region by chemical mechanical polishing. About.
[0002]
[Prior art]
As semiconductor devices are miniaturized and highly integrated, gate electrodes and wirings are becoming thinner and pitches are being reduced. Therefore, it is important to evaluate the lithography technique necessary for forming the gate electrode and the wiring and the conditions such as the film quality related to the manufacture as the element, and are evaluated in advance with the evaluation wafer. That is, in the evaluation wafer, patterns of various elements including conditions such as dimensions and pitches according to the actual design are formed, and the manufacturing process is evaluated. Such an evaluation wafer may be called a TEG (Test Element Group) wafer.
[0003]
With the recent miniaturization and higher integration, the number of wiring layers has increased, and chemical mechanical polishing, so-called CMP (Chemical Mechanical Polishing) technology is indispensable for planarization treatment between formation layers. That is, the selectivity of the polishing rate is generated by the pressure difference of the polishing pad applied to the uneven portion of the planarized layer and the selection ratio depending on the slurry, and the uneven portion is made smooth after a predetermined time.
[0004]
The evaluation wafer is also planarized between the formation layers using the CMP technique. For example, a case where a trench element isolation insulating film is formed as the element isolation region will be described below.
[0005]
9 (a) and 9 (b) are cross-sectional views showing intermediate processes when forming a trench element isolation region in the prior art. As shown in FIG. 9A, a mask pattern of a nitride film (silicon nitride film or the like) 92 is formed on a Si semiconductor substrate 91, and an element isolation trench 93 is formed by etching. After the trench 93 is oxidized (not shown), an oxide film 94 is formed by a CVD (Chemical Vapor Deposition) method. The deposition level of the oxide film 94 varies according to the unevenness of the trench 93.
[0006]
The evaluation wafer (91) is provided with a large element region 95 in which gate wirings are spread at a predetermined pitch. As a result, the oxide film 94 on the element region 95 having a large area is deposited higher than the other regions, and a large area of the trapezoidal (convex portion) region 941 is formed.
[0007]
In the polishing pad in CMP, a larger pressure is applied to the convex portion than the concave portion with respect to the planarized layer (oxide film 94), and the polishing rate is increased. However, the present situation is that the pressure of the polishing pad is dispersed in the convex portion having a large area, and the polishing rate is reduced. That is, the trapezoidal region 941 on the element region 95 cannot be flattened in the same manner as other fine uneven regions of low deposition level, and there is a concern that the flattening error may increase.
[0008]
Therefore, as shown in FIG. 9B, the photolithography technique is used for the trapezoidal region 941 of the oxide film 94 on the element region 95 having a larger area than other regions so as to be close to other deposition levels. The whole is etched to a certain depth. The convex portion 942 is formed by a formation margin of a resist mask pattern. If CMP is performed after such a configuration, a flattening level with less error can be realized. Although not shown, the nitride film 92 is detected as a CMP stopper film, and then the nitride film is removed. Thereby, a trench element isolation insulating film in which the oxide film 94 is embedded in the trench 93 is formed.
[0009]
[Problems to be solved by the invention]
However, as shown in FIG. 9B, the countermeasure for the trapezoidal region 941 of the large-area oxide film 94 inevitably has a problem of dicing unique to CMP. Since the large element region 95 naturally cannot have a trench, there is almost no unevenness, and therefore there is a risk of dishing.
[0010]
FIG. 10 is a cross-sectional view when FIG. 9B is planarized using CMP and the nitride film 92 is detected as a CMP stopper film. Dicing occurs on the large element region 95, and the nitride film 92 is exposed earlier than the other regions, and the CMP process is completed. Even if the nitride film 92 is removed in this state, the nitride film 92 is not completely removed because the oxide film 94 remains on the nitride film 92.
[0011]
Conventionally, in order to avoid such a situation, the CMP process has been excessively performed for a period of time assuming that the oxide film 94 remaining on the nitride film 92 is further removed after the nitride film 92 is detected. As a result, there is a problem that the CMP efficiency is lowered, the deterioration of the polishing pad is progressed, and the film thickness variation of the oxide film (94) as the trench element isolation film is affected.
[0012]
The present invention has been made in consideration of the above-described circumstances, and can reduce dishing and the like even when including a large-area region with little unevenness, and a flat surface with little film thickness variation with a small amount of polishing. It is an object of the present invention to provide a pre-planarization processing method that realizes a smoothing level.
[0013]
[Means for Solving the Problems]
The planarization method and the semiconductor device manufacturing method according to the present invention include a first region and a first region out of a substrate having a first region and a second region having a larger area than the first region. Forming a trench between the second region to separate the first region and the second region;
Forming an insulating film on the substrate and in the trench;
Forming a dummy pattern having a plurality of irregularities on the insulating film on the second region;
Flattening the insulating film by chemical mechanical polishing.
[0014]
According to the planarization processing method and the semiconductor device manufacturing method according to the present invention, a dummy pattern having a plurality of irregularities and having a predetermined depth is formed over the entire trapezoidal region. As a result, the selectivity of the polishing rate in the polishing pad is utilized, and the slurry is spread over the entire recess, thereby realizing uniform CMP.
[0015]
The dummy pattern is preferably formed by a photolithography technique in order to realize uniform CMP. Alternatively, a plurality of opening patterns are formed by a photolithography technique. Further, in this method of manufacturing a semiconductor device, after the step of planarizing the insulating film, the first element is further formed in the first region, and the first element is formed in the second region. A larger second element may be formed.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
FIGS. 1A and 1B are cross-sectional views illustrating a planarization method included in a method for manufacturing a semiconductor device according to an embodiment of the present invention in order of steps. As shown in FIG. 1 (a), in the semiconductor wafer 10, the layer 11 to be flattened with unevenness due to the unevenness (not shown) of the lower layer forming portion has a large area with a partial height. The trapezoidal region 12 is provided. Regarding the process of flattening by CMP, that is, chemical mechanical polishing, to the flattening end level indicated by the dotted line L, the insulating film 11 remains unpolished in the trapezoidal region 12, and dishing may occur in the peripheral region of the trapezoidal region 12.
[0017]
Therefore, as shown in FIG. 1B, as a pre-process of CMP, a dummy pattern 13 having a predetermined depth is formed on the platform region 12 of the planarized layer 11 so as to have a plurality of irregularities. . The dummy pattern 13 is patterned deeply to the vicinity of the level of another low region around the trapezoidal region 12 by using, for example, a photolithography technique.
[0018]
When the CMP is performed after the pretreatment as shown in FIG. 1B, the polishing rate of the polishing pad (not shown) is reduced by the dummy pattern 13 having a predetermined depth formed on the entire plate-like region 12 and having a plurality of irregularities. Selectivity is utilized, and the slurry spreads throughout the recess. Therefore, uniform CMP can be achieved up to the planarization end level L, and planarization with reduced film thickness error with reduced dishing can be realized.
[0019]
2 and 3 are plan views showing specific examples of the dummy pattern 13 formed on the large area of the trapezoidal region 12 as the CMP pretreatment as shown in FIG.
[0020]
In FIG. 2, the lattice groove pattern 131 is formed by photolithography. In FIG. 3, a plurality of opening patterns 132 are formed by a photolithography technique. That is, the hatched patterns 131 and 132 are both concave portions, and the slurry spreads over the entire concave portion, while suppressing the dispersion of the pressure of the polishing pad at the convex portions, thereby realizing uniform CMP.
[0021]
4 to 8 are cross-sectional views showing, in the order of steps, the formation of the trench element isolation region to which the semiconductor device manufacturing method according to the present invention is applied. As shown in FIG. 4, a nitride film (silicon nitride film) 42 serving as a mask pattern is formed on a Si semiconductor substrate 41, and a trench 43 for element isolation is formed by etching. The mask pattern is not limited to that made of a silicon nitride film, and it is sufficient if the etching rate ratio (selection ratio) between the substrate 41 and the nitride film 42 is high under the etching conditions of the substrate 41. Further, under the etching conditions of the insulating film 45, it is more preferable that the mask pattern has a high etching rate ratio (selection ratio) between the insulating film 45 and the mask pattern. Here, it includes a portion where an element region A2 having a larger area than the surrounding element region A1 is provided.
[0022]
Next, as shown in FIG. 5, after the trench 43 is oxidized to form an oxide film 44, an insulating film 45 is formed by a CVD (Chemical Vapor Deposition) method. For example, the insulating film 45 is a silicon oxide film. The insulating film 45 has different deposition levels according to the unevenness of the trench 43. The insulating film 45 on the large-area element region A <b> 2 is deposited higher than the other regions, and becomes a large-area trapezoidal (convex) region 451.
[0023]
Next, as shown in FIG. 6, a dummy pattern 46 having a predetermined depth is formed so as to have a plurality of irregularities in the large area of the trapezoidal region 451. The dummy pattern 46 is patterned deeply to a level near a low region around the trapezoidal region 451 using, for example, a photolithography technique. Thus, a plurality of openings or lattice groove patterns may be formed in at least a part of the trapezoidal region 451. The dummy pattern 46 takes the form shown in the examples of FIGS.
[0024]
Next, CMP is performed as shown in FIG. The dummy pattern 46 of a predetermined depth having a plurality of irregularities formed over the entire trapezoidal region 451 makes use of the selectivity of the polishing rate in a polishing pad (not shown), and the slurry spreads over the entire recess. Thus, uniform CMP can be achieved up to detection of exposure of the nitride film 42 serving as a CMP stopper film, and flattening with reduced film thickness error with reduced dishing can be realized. The stopper film 42 is not limited to a nitride film, and it is sufficient that the etching rate ratio (selection ratio) between the insulating film 45 and the stopper film 42 is high under the etching conditions of the insulating film 45. Thereafter, as shown in FIG. 8, a trench element isolation insulating film in which the oxide film 45 is buried in the trench 43 is formed through a process of removing the silicon nitride film 42.
Next, an element is formed in each of the peripheral element region A1 and the large-area element region A2. The width of the element provided in the large-area element region A2 may be larger than the width of the element provided in the peripheral element region A1. Each element may be a MIS transistor having a gate electrode. In this case, the width of the gate electrode in the element region A2 may be larger than the width of the gate electrode in the element region A1.
[0025]
According to the above configuration, at the end of the CMP process by detecting the exposure of the stopper film, the insulating film 45 is hardly left on the stopper film, and the removal of the remaining insulating film 45 is very easy to control compared to the conventional case. Therefore, it is possible to shift to the stopper film removal process in a more appropriate state while minimizing the decrease in CMP efficiency and the deterioration of the polishing pad. Therefore, the influence of the film thickness variation of the insulating film 45 as the trench element isolation film is very small, and high reliability can be maintained in the subsequent element manufacturing process.
[0026]
Note that the pre-planarization processing method of the present invention is not limited to the above-described embodiment, and is effective for a trapezoidal region that is uniformly higher than the planarization end level of the planarization processing layer in which the problem of dishing is a concern. is there. That is, by forming a dummy pattern having a predetermined depth so as to have a plurality of projections and depressions at the stage before CMP in the above problem area, polishing residue and dishing can be reduced in CMP, and more accurate. A high level of planarization can be achieved.
[0027]
【The invention's effect】
As described above, according to the present invention, a dummy pattern having a predetermined depth and having a plurality of projections and depressions is formed on a large area of a trapezoidal area having a dishing concern. Thereby, the selectivity of the polishing rate is utilized in the polishing pad, and the slurry is spread over the entire recess. Therefore, uniform CMP is achieved up to the flattening end level L, and the slurry spreads over the entire recess. As a result, there is provided a pre-planarization pretreatment method that can reduce polishing residue and dishing even when including a large-area region with little unevenness, and realizes a flattening level with little film thickness variation with a small amount of polishing. Can do.
[Brief description of the drawings]
FIGS. 1A and 1B are cross-sectional views showing a planarization pretreatment method according to an embodiment of the present invention in the order of steps.
FIG. 2 is a plan view showing a first specific example of a dummy pattern formed for a large area of a trapezoidal region as a CMP pretreatment as shown in FIG.
FIG. 3 is a plan view showing a second specific example of a dummy pattern formed for a large area of a trapezoidal region as a CMP pretreatment as shown in FIG.
FIG. 4 is a first cross-sectional view showing the formation of a trench element isolation region to which the planarization pretreatment method according to the present invention is applied in the order of steps.
FIG. 5 is a second cross-sectional view subsequent to FIG. 4 showing the formation of the trench isolation region to which the planarization pretreatment method according to the present invention is applied in the order of steps;
6 is a third cross-sectional view subsequent to FIG. 5 showing the formation of the trench isolation region to which the pre-planarization processing method according to the present invention is applied in the order of steps;
7 is a fourth cross-sectional view subsequent to FIG. 6 illustrating the formation of the trench isolation region to which the planarization pretreatment method according to the present invention is applied in the order of steps;
FIG. 8 is a fifth cross-sectional view subsequent to FIG. 7 showing the formation of the trench isolation region to which the planarization pretreatment method according to the present invention is applied in the order of steps;
FIGS. 9A and 9B are cross-sectional views showing intermediate processes when forming a trench isolation region in the prior art. FIGS.
FIG. 10B is a cross-sectional view when FIG. 9B is planarized using CMP and a nitride film is detected as a stopper film for CMP.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Semiconductor wafer 11 ... Planarization process layer 12,451,941 ... Platform region 942 ... Convex part 13,46 ... Dummy pattern 131 ... Lattice groove pattern 132 ... Opening pattern 41 ... Si semiconductor substrate 42 ... Nitride film (silicon Nitride film etc.)
43 ... Trench 44, 45 ... Oxide films A1, A2 ... Element region L ... Planarization end level

Claims (8)

A semiconductor substrate comprising a first element region having a width W1 on the surface and a second element region having a width W2 larger than the width W1 , and the first element region and the second element region forming a preparative wrench located between,
Before Symbol trench, by forming an insulating film on said first element region and said second element region, forming the base-like region in the second element region,
Forming a plurality of dummy patterns having a predetermined depth in the trapezoidal region ;
Wherein the insulating film, flattening processing method which comprises a step of performing chemical mechanical polishing, a.   The planarization method according to claim 1, wherein the dummy pattern is a lattice groove pattern formed by a photolithography technique.   The planarization method according to claim 1, wherein the dummy pattern is formed with a plurality of opening patterns by a photolithography technique. A semiconductor substrate comprising a first element region having a width W1 on the surface and a second element region having a width W2 larger than the width W1 , and the first element region and the second element region forming a preparative wrench located between,
Before Symbol trench, by forming an insulating film on said first element region and said second element region, forming the base-like region in the second element region,
Forming a plurality of dummy patterns having a predetermined depth in the trapezoidal region ;
Wherein the insulating film, a method of manufacturing a semiconductor device which comprises a step of performing chemical mechanical polishing, a. Before SL first device region, the first element having a first gate width formed in said second element region, the having a greater than the first gate width second gate width 2 5. The method of manufacturing a semiconductor device according to claim 4 , further comprising a step of forming the element. 6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of forming a transistor in the first element region and the second element region.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the dummy pattern is formed by forming a lattice groove pattern by a photolithography technique.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the dummy pattern includes a plurality of opening patterns formed by a photolithography technique.

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