JP6127500B2 - Electro-optical device manufacturing method, electro-optical device, and electronic apparatus - Google Patents

Description

  The present invention relates to a method for manufacturing a substrate for an electro-optical device, an electro-optical device, and an electronic apparatus.

  There is known an electro-optical device including an electro-optical material (for example, liquid crystal) between an element substrate in which a plurality of pixels and switching elements are provided in a display area, and a counter substrate disposed to face the element substrate. Yes. Examples of the electro-optical device include a liquid crystal device used as a liquid crystal light valve of a projector. Such a liquid crystal device is required to realize high light utilization efficiency.

  In view of this, a prism (reflecting portion) is provided in the display region of one of the element substrate and the counter substrate, and the light incident on the liquid crystal device is efficiently guided to the pixel region, thereby improving the substantial aperture ratio of the liquid crystal device. A configuration has been proposed (see, for example, Patent Document 1). Such a prism is formed as a groove having a V-shaped cross section in a non-opening region between pixels on a substrate, and the side surface of the groove that has become hollow by closing the opening of the groove is used as a reflecting surface. The reflected light is reflected toward the pixel region.

JP 2011-128292 A

  By the way, as in the technique described in Patent Document 1, in the method of depositing a metal material on the substrate surface and closing the opening of the groove, the metal material enters the inside of the groove from the opening side, and the side surface of the groove Of these, the portion that functions as the reflecting surface of the prism may be extremely narrow. On the other hand, for example, a sacrificial layer is deposited on the substrate surface to fill the groove with the sacrificial layer, and a sealing layer that covers the sacrificial layer after polishing and removing a portion of the sacrificial layer located outside the groove is provided. A method is conceivable in which after forming and removing the sacrificial layer through the through-hole provided in the sealing layer, the sealing layer is further covered with another sealing layer to close the through-hole. In such a method, when the portion of the sacrificial layer located outside the groove is removed, the sacrificial layer is polished when the substrate surface is polished so that the unevenness of the substrate surface is relaxed and the sacrificial layer does not remain outside the groove. At the same time, the substrate surface is also polished.

  However, in the display area where the groove is formed on the substrate surface, the ratio of the substrate material to the unit area is smaller than the non-display area where the groove is not formed (outside of the display area). Polishing deeply causes a step between the display area and the non-display area. If the level difference between the display area and the non-display area is large, the level difference cannot be sufficiently relaxed even if the leveling layer is provided on the sealing layer and the surface of the leveling layer is polished. There is a problem that it may be difficult. In this case, if a part of the non-display area is removed to reduce the level difference, a step of removing a part of the non-display area is required separately, which causes a problem that productivity is lowered.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 A method for manufacturing a substrate for an electro-optical device according to this application example includes a first region in which a reflecting portion including a groove is disposed, and a second region that surrounds the outside of the first region. A method of manufacturing the substrate for an electro-optical device, comprising: forming the groove in the first region of the light-transmitting substrate; depositing a sacrificial layer on the main surface side; Filling the interior with the sacrificial layer; polishing the main surface side of the substrate to remove a portion of the sacrificial layer located outside the groove; the main surface and the main surface; Forming a first sealing layer that covers the sacrificial layer inside the groove, and forming a through hole at a position overlapping the sacrificial layer inside the groove of the first sealing layer; Removing the sacrificial layer inside the groove through the through hole, covering the first sealing layer, and A second sealing layer forming step for forming a second sealing layer that closes the through-hole, and a second polishing step for polishing the main surface side of the substrate, before the second polishing step. A concave portion is formed in the second region on the main surface side.

  According to the method of this application example, since the concave portion is formed in the second region of the substrate, when the main surface side of the substrate is polished in the first polishing step, the polishing amount of the first region is the polishing amount of the second region. The step difference between the first region and the second region caused by the increase can be reduced. Then, since the second polishing step is performed after the step between the first region and the second region is relaxed, the main surface side of the substrate can be easily flattened and the flatness can be improved in the second polishing step. be able to.

  Application Example 2 In the method for manufacturing an electro-optical device substrate according to the application example, it is preferable that the concave portion is formed before the second sealing layer forming step.

  According to the method of this application example, the second sealing layer is formed so as to cover the first region and the second region after the step between the first region and the second region on the main surface of the substrate is relaxed. The surface of the second sealing layer can be a surface with few steps. Thereby, the flatness of the main surface side of the substrate can be further improved in the second polishing step.

  Application Example 3 In the method for manufacturing the electro-optical device substrate according to the application example, it is preferable that the concave portion is formed in the through hole forming step.

  According to the method of this application example, not only the through hole but also the concave portion is formed in the step of forming the through hole in the first sealing layer, so that a step of forming the concave portion is not required separately. As a result, the productivity of the electro-optical device substrate can be improved as compared with a case where a step of forming the recess is separately required.

  Application Example 4 In the method for manufacturing the electro-optical device substrate according to the application example, it is preferable that the concave portion is formed so as to surround an outer side of the first region.

  According to the method of this application example, since the concave portion is formed so as to surround the outside of the first region, the step difference from the second region can be reduced around the first region. Thereby, the flatness of the main surface side of the substrate can be further improved.

  Application Example 5 In the method for manufacturing the substrate for an electro-optical device according to the application example, it is preferable that a plurality of the recesses are formed with a predetermined interval.

  According to the method of this application example, a plurality of recesses are formed with a predetermined interval between adjacent recesses. If the pressure which pressurizes a board | substrate is constant, the grinding | polishing load in a grinding | polishing process will become so large that the contact area of a board | substrate and a polishing pad is small. Therefore, the contact area between the substrate and the polishing pad in the second polishing step is adjusted by appropriately setting the interval between the adjacent recesses, and the difference between the polishing rate of the first region and the polishing rate of the second region is controlled. can do. Thereby, the flatness of the main surface side of the substrate can be further improved.

  Application Example 6 A method for manufacturing a substrate for an electro-optical device according to the application example, in which a mark is formed in a region overlapping with the concave portion between the through hole forming step and the second polishing step. And a step of forming a planarization layer covering the mark and the second sealing layer.

  According to the method of this application example, since the concave portion is formed in the second region and the mark is formed in the region overlapping with the concave portion, the mark on the main surface side of the substrate is compared with the case where the concave portion is not formed. A step with the first region can be reduced. Therefore, when polishing the surface of the flattening layer in the second polishing step, the remaining thickness of the flattening layer on the mark can be easily ensured compared to the case where no recess is formed, and the mark disappears. Or part of the mark can be prevented from being removed.

  Application Example 7 In an electro-optical device according to this application example, a first substrate provided with a plurality of pixel electrodes and switching elements corresponding to each of the plurality of pixel electrodes, and opposed to the first substrate. A second substrate disposed; and an electro-optic material layer provided between the first substrate and the second substrate, wherein one of the first substrate and the second substrate is applied as described above. The electro-optical device substrate manufactured by the manufacturing method of the example electro-optical device substrate is provided.

  According to the configuration of this application example, either the first substrate or the second substrate included in the electro-optical device is manufactured on the electro-optical material layer side manufactured by the method for manufacturing the electro-optical device substrate of the application example. An electro-optical device substrate having good surface flatness and high productivity is provided. Therefore, it is possible to provide an electro-optical device having excellent display quality and cost competitiveness.

  Application Example 8 An electronic apparatus according to this application example includes the electro-optical device according to the application example.

  According to the configuration of this application example, it is possible to provide an electronic apparatus including an electro-optical device that is excellent in display quality and cost competitiveness.

It is the schematic which shows the structure of the liquid crystal device which concerns on 1st Embodiment. 2 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device according to the first embodiment. FIG. It is a schematic plan view which shows arrangement | positioning of a pixel. It is a schematic sectional drawing which shows the structure of a pixel and a prism (reflection part). FIG. 3 is a schematic cross-sectional view showing the method for manufacturing the electro-optical device substrate according to the first embodiment. FIG. 3 is a schematic cross-sectional view showing the method for manufacturing the electro-optical device substrate according to the first embodiment. FIG. 3 is a schematic cross-sectional view showing the method for manufacturing the electro-optical device substrate according to the first embodiment. FIG. 3 is a schematic cross-sectional view showing the method for manufacturing the electro-optical device substrate according to the first embodiment. FIG. 3 is a schematic cross-sectional view showing the method for manufacturing the electro-optical device substrate according to the first embodiment. FIG. 3 is a schematic cross-sectional view showing the method for manufacturing the electro-optical device substrate according to the first embodiment. FIG. 10 is a schematic diagram illustrating a method for manufacturing a substrate for an electro-optical device according to a second embodiment. It is the schematic which shows the structure of the projector as an electronic device which concerns on 3rd Embodiment.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. The drawings to be used are appropriately enlarged, reduced or exaggerated so that the part to be described can be recognized. In addition, illustrations of components other than those necessary for the description may be omitted.

  In the following embodiments, for example, when “on the substrate” is described, the substrate is disposed so as to be in contact with the substrate, or is disposed on the substrate via another component, or the substrate. It is assumed that a part is arranged so as to be in contact with each other and a part is arranged via another component.

(First embodiment)
<Electro-optical device>
Here, an active matrix liquid crystal device including a thin film transistor (TFT) as a pixel switching element will be described as an example of the electro-optical device. This liquid crystal device can be suitably used, for example, as a light modulation element (liquid crystal light valve) of a projection display device (projector) described later.

  First, a liquid crystal device as an electro-optical device according to the first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a schematic diagram illustrating the configuration of the liquid crystal device according to the first embodiment. Specifically, FIG. 1A is a schematic plan view showing the configuration of the liquid crystal device, and FIG. 1B is a schematic cross-sectional view taken along the line H-H ′ of FIG. FIG. 2 is an equivalent circuit diagram showing an electrical configuration of the liquid crystal device according to the first embodiment.

  As shown in FIGS. 1A and 1B, the liquid crystal device 1 according to the first embodiment includes an element substrate 20 as a first substrate and a counter as a second substrate disposed opposite to the element substrate 20. A substrate 30 and a liquid crystal layer 40 as an electro-optical material layer disposed between the element substrate 20 and the counter substrate 30 are provided. In the present embodiment, the counter substrate 30 includes the prism substrate 10 as the electro-optical device substrate of the present invention.

  The liquid crystal device 1 operates in, for example, a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode. The liquid crystal device 1 is a transmissive liquid crystal device that modulates light incident from the counter substrate 30 side and emits the light to the element substrate 20 side.

  As shown in FIGS. 1A and 1B, the element substrate 20 is slightly larger than the counter substrate 30, and both substrates are bonded via a sealing material 42 arranged in a frame shape. The liquid crystal layer 40 is composed of a liquid crystal having positive or negative dielectric anisotropy as an electro-optical material enclosed in a space surrounded by the element substrate 20, the counter substrate 30, and the sealing material 42.

  The sealing material 42 is made of an adhesive such as a thermosetting or ultraviolet curable epoxy resin. Spacers (not shown) are mixed in the sealing material 42 to keep the distance between the element substrate 20 and the counter substrate 30 constant. A frame-shaped light shielding layer 32 provided on the counter substrate 30 is disposed inside the sealing material 42 disposed in a frame shape. The light shielding layer 32 is made of, for example, a light shielding metal or metal oxide.

  Inside the light shielding layer 32 is a display area E as a first area in which a plurality of pixels P are arranged. The display area E is an area that substantially contributes to display in the liquid crystal device 1. A region surrounding the display region E including the region where the light shielding layer 32 is formed is referred to as a non-display region F as a second region. The non-display area F is an area that does not contribute to display. Although not shown in FIGS. 1A and 1B, in the display area E, the light-shielding portion (the non-opening area D2 shown in FIG. It is provided in the shape.

  A data line driving circuit 51 and a plurality of external connection terminals 54 are provided outside the sealing material 42 on one side of the element substrate 20 along the one side. Further, an inspection circuit 53 is provided inside the sealing material 42 along the other one side facing the one side. Further, a scanning line driving circuit 52 is provided inside the sealing material 42 along the other two sides that are orthogonal to these two sides and face each other.

  A plurality of wirings 55 that connect the two scanning line driving circuits 52 are provided inside the sealing material 42 on one side where the inspection circuit 53 is provided. Wirings connected to the data line driving circuit 51 and the scanning line driving circuit 52 are connected to a plurality of external connection terminals 54. In addition, a vertical conduction portion 56 is provided at a corner portion of the counter substrate 30 to establish electrical continuity between the element substrate 20 and the counter substrate 30. The arrangement of the inspection circuit 53 is not limited to this, and the inspection circuit 53 may be provided at a position along the inner side of the seal material 42 between the data line driving circuit 51 and the display area E.

  In the following description, the direction along one side where the data line driving circuit 51 is provided is defined as the X direction, and the direction along the other two sides orthogonal to the one side and facing each other is defined as the Y direction. . The direction of the H-H ′ line in FIG. 1A is a direction along the Y direction. Further, a direction orthogonal to the X direction and the Y direction and going upward in FIG. In the present specification, viewing from the normal direction (Z direction) of the surface of the counter substrate 30 of the liquid crystal device 1 is referred to as “plan view”.

  As shown in FIG. 1B, on the liquid crystal layer 40 side of the element substrate 20, a TFT 24 (see FIG. 4) as a switching element provided for each pixel P, a light-transmissive pixel electrode 28, A signal wiring (not shown) and an alignment film 29 covering the pixel electrode 28 are provided. The pixel electrode 28 is made of a light-transmitting conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

  The counter substrate 30 includes a prism substrate 10 as a substrate for an electro-optical device provided with a prism 15 (see FIG. 4) as a reflecting portion described later. A light shielding layer 32, a planarization layer 33, a common electrode 34, and an alignment film 35 that covers the common electrode 34 are provided on the counter substrate 30 on the liquid crystal layer 40 side.

  As shown in FIGS. 1A and 1B, the light shielding layer 32 is provided in a frame shape at a position overlapping the scanning line driving circuit 52, the plurality of wirings 55, and the inspection circuit 53 in a plan view. The light shielding layer 32 serves to shield light incident from the counter substrate 30 side and prevent malfunctions due to light in peripheral circuits including these drive circuits. Further, unnecessary stray light is shielded from entering the display area E, and high contrast in the display of the display area E is ensured.

The planarization layer 33 shown in FIG. 1B is formed so as to cover the light shielding layer 32. The planarization layer 33 is formed of an insulating film such as a silicon oxide film (SiO ₂ ), and has light transmittance. The flattening layer 33 is provided so that the unevenness caused by the light shielding layer 32 and the like is alleviated and the surface on the liquid crystal layer 40 side on which the common electrode 34 is formed becomes flat. Examples of the method for forming the planarizing layer 33 include a method of forming a film using a plasma CVD (Chemical Vapor Deposition) method or the like.

  The common electrode 34 is made of a light-transmitting conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), for example, and covers the planarization layer 33 and, as shown in FIG. The upper and lower conductive portions 56 provided at the four corners 30 are electrically connected to the wiring on the element substrate 20 side.

  The alignment film 29 and the alignment film 35 are selected based on the optical design of the liquid crystal device 1. For example, the alignment film 29 and the alignment film 35 are formed by depositing an organic material such as polyimide and rubbing the surface thereof, so that liquid crystal molecules are subjected to a substantially horizontal alignment process, or SiOx (silicon oxide). ) And the like formed by using a vapor phase growth method and aligned substantially perpendicularly to the liquid crystal molecules.

  The liquid crystal constituting the liquid crystal layer 40 modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. For example, in the normally white mode, the transmittance for incident light decreases according to the voltage applied in units of each pixel P. In the normally black mode, the transmittance for incident light increases in accordance with the voltage applied in units of each pixel P, and light having a contrast corresponding to an image signal is emitted from the liquid crystal device 1 as a whole.

  As shown in FIG. 2, in the display area E, the scanning lines 2 and the data lines 3 are formed so as to be insulated from each other. The direction in which the scanning line 2 extends is the X direction, and the direction in which the data line 3 extends is the Y direction. The pixel P is provided corresponding to the intersection of the scanning line 2 and the data line 3. Each pixel P is provided with a pixel electrode 28 and a TFT 24 (Thin Film Transistor) as a switching element.

  A source electrode (not shown) of the TFT 24 is electrically connected to the data line 3 extending from the data line driving circuit 51. Image signals (data signals) S1, S2,..., Sn are supplied to the data line 3 from the data line driving circuit 51 (see FIG. 1) in a line sequential manner. A gate electrode (not shown) of the TFT 24 is a part of the scanning line 2 extending from the scanning line driving circuit 52. The scanning signals G1, G2,..., Gm are supplied to the scanning line 2 from the scanning line driving circuit 52 in a line sequential manner. A drain electrode (not shown) of the TFT 24 is electrically connected to the pixel electrode 28.

  The image signals S1, S2,..., Sn are written to the pixel electrode 28 via the data line 3 at a predetermined timing by turning on the TFT 24 for a certain period. The image signal of a predetermined level written in the liquid crystal layer 40 through the pixel electrode 28 in this manner is constant by the liquid crystal capacitance formed between the common electrode 34 (see FIG. 3) provided on the counter substrate 30. Hold for a period.

  In order to prevent leakage of the held image signals S 1, S 2,..., Sn, the storage capacitor 5 is formed between the capacitor line 4 formed in parallel along the data line 3 and the pixel electrode 28. Is formed and arranged in parallel with the liquid crystal capacitor. Thus, when a voltage signal is applied to the liquid crystal of each pixel P, the alignment state of the liquid crystal changes depending on the applied voltage level. As a result, the light incident on the liquid crystal layer 40 (see FIG. 4) is modulated to enable gradation display.

  Next, the planar arrangement of the pixels P and the structure of the prism substrate 10 will be described with reference to FIGS. FIG. 3 is a schematic plan view showing the arrangement of pixels. FIG. 4 is a schematic cross-sectional view showing the structure of the pixel and the prism (reflecting portion). Specifically, FIG. 4 is a schematic cross-sectional view taken along the line A-A ′ of FIG. 3.

  As shown in FIG. 3, the pixels P are arranged in a matrix in the display area E in the X direction and the Y direction. In the display area E, an area where light is shielded by the light shielding portion is referred to as a non-opening area D2. The non-opening region D2 is provided in a lattice shape extending in the X direction and the Y direction. In addition, a region that transmits light surrounded by the non-opening region D2 is referred to as an opening region D1. An opening area D1 divided into a quadrangle (substantially square) in plan view by the non-opening area D2 is an area (pixel area) of the pixel P.

  A scanning line 2 (see FIG. 2) is provided in the non-opening region D2 extending in the X direction. A data line 3 (see FIG. 2) is provided in the non-opening region D2 extending in the Y direction. The scanning lines 2 and the data lines 3 are made of a light-shielding conductive material, and these constitute a light-shielding portion of the liquid crystal device 1. The light shielding layer 32 of the counter substrate 30 may be provided in a lattice shape so as to overlap the non-opening region D2, and may be a part of the light shielding portion.

  The pixel electrode 28 provided on the element substrate 20 is quadrangular (substantially square) in plan view, and is arranged so that the outer edge portion overlaps the non-opening region D2 in a plane. In the present embodiment, the width of the non-opening region D2 is set to the same width in the X direction and the Y direction. In addition, the groove 12 (prism 15) provided in the counter substrate 30 is disposed in the non-opening region D2.

  Although not shown in FIG. 3, a TFT 24 is disposed for each pixel P in the vicinity of the intersection of the non-opening region D2. By disposing the TFT 24 in the non-opening region D2, the incidence of light on the TFT 24 is suppressed.

  As shown in FIG. 4, the element substrate 20 includes a substrate 21, a scanning line 2, an insulating layer 23, a TFT 24, an insulating layer 25, a data line 3, an insulating layer 27, a pixel electrode 28, and an orientation. And a film 29. The substrate 21 is made of a light transmissive material such as glass or quartz.

  The scanning line 2 is, for example, a simple metal or alloy containing at least one of metal materials such as Al (aluminum), Mo (molybdenum), W (tungsten), Ti (titanium), Ta (tantalum), and Cr (chromium). , Metal silicide, polysilicide, nitride, or a laminate of these, and has light shielding properties.

The insulating layer 23 is provided so as to cover the substrate 21 and the scanning line 2. The insulating layer 23 is formed of an insulating film such as a silicon oxide film (SiO ₂ ), for example, and has optical transparency. The TFT 24 is provided on the insulating layer 23. The TFT 24 is a switching element that drives the pixel electrode 28. Although not shown, the TFT 24 includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode.

  The semiconductor layer is made of, for example, a polycrystalline silicon film and is formed in an island shape. Impurity ions are implanted into the semiconductor layer to form a source region, a channel region, and a drain region. An LDD (Lightly Doped Drain) region may be formed between the channel region and the source region or between the channel region and the drain region.

  The gate electrode is formed on the element substrate 20 in a region overlapping with the channel region of the semiconductor layer in plan view via a part (gate insulating film) of the insulating layer 25. Although not shown, the gate electrode is electrically connected to the scanning line 2 arranged on the lower layer side through a contact hole, and the TFT 24 is on / off controlled by applying a scanning signal. .

  The structure of the TFT 24 is not limited to such a so-called top gate structure, but a so-called bottom gate structure in which the portion of the scanning line 2 that overlaps the channel region of the semiconductor layer via the insulating layer 23 functions as a gate electrode. It may be adopted.

The insulating layer 25 is provided so as to cover the insulating layer 23 and the TFT 24. The insulating layer 25 is formed of an insulating film such as a silicon oxide film (SiO ₂ ), for example, and has optical transparency. The insulating layer 25 includes a gate insulating film that insulates between the semiconductor layer of the TFT 24 and the gate electrode. The insulating layer 25 relieves surface irregularities caused by the TFT 24.

  A data line 3 is provided on the insulating layer 25. The data line 3 is formed of the same material as the scanning line 2 and has a light shielding property. The TFT 24 is disposed so as to be sandwiched between the scanning line 2 and the data line 3 having light shielding properties. This suppresses the switching operation from becoming unstable due to light entering the semiconductor layer of the TFT 24. In addition to the scanning lines 2 and the data lines 3, a light shielding layer formed of a light shielding material may be separately provided as at least one of the lower layer and the upper layer of the TFT 24 as the light shielding portion.

Although not shown, the capacitor line 4 is provided on the insulating layer 25 with the data line 3 and the wiring layer being different. An insulating layer 27 is provided so as to cover the insulating layer 25, the data line 3, and the capacitor line 4. The insulating layer 27 is formed of an insulating film such as a silicon oxide film (SiO ₂ ), for example, and has optical transparency.

  The pixel electrode 28 is provided on the insulating layer 27 corresponding to the pixel P. The pixel electrode 28 is disposed so as to overlap the opening region D1 in a planar manner. The pixel electrode 28 is made of a light-transmitting conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The pixel electrode 28 is electrically connected to the drain region in the semiconductor layer of the TFT 24 through a contact hole (not shown) provided in the insulating layer 25 and the insulating layer 27. The alignment film 29 is provided so as to cover the pixel electrode 28.

  As described above, the counter substrate 30 includes the prism substrate 10, the light shielding layer 32 (see FIG. 1B), the planarization layer 33, the common electrode 34, and the alignment film 35. The configuration of the prism substrate 10 included in the counter substrate 30 will be described below.

<Electro-optical device substrate>
A prism substrate 10 as a substrate for an electro-optical device includes a substrate body 11 as a substrate, a prism (reflecting portion) 15 provided on the first surface 11a side as a main surface of the substrate body 11, and a first surface 11a. It has the 1st sealing layer 13 and the 2nd sealing layer 14 which were laminated | stacked on it. The substrate body 11 is made of a light transmissive material such as glass or quartz.

  The prism 15 has a groove 12 formed on the first surface 11 a side of the substrate body 11. The groove 12 is formed in a V shape in sectional view so as to open toward the liquid crystal layer 40. The cross section of the groove 12 has a substantially isosceles triangular shape with the opening 12c opening in the first surface 11a as a base and two V-shaped inclined surfaces 12a as two sides. The inside of the groove 12 is a hollow portion 12b in a hollow state.

  The groove 12 is formed so as to overlap the non-opening region D2 in plan view. That is, the grooves 12 are formed in a lattice shape, and are arranged so as to overlap the scanning lines 2 (see FIG. 2) in the X direction and to overlap the data lines 3 (see FIG. 2) in the Y direction.

  The apex of the substantially isosceles triangle shape of the groove 12 is located at the center in the width direction of the non-opening region D2. The width of the groove 12 (the length of the base of the approximately isosceles triangle shape) is set to be the same as or slightly wider than the width of the non-opening region D2. In the present embodiment, the width of the groove 12 is, for example, about 1 μm to 2 μm. The depth (length in the Z direction) of the groove 12 is, for example, about 20 μm to 30 μm.

  The first sealing layer 13 is formed so as to cover the first surface 11 a of the substrate body 11 and close the opening 12 c of the groove 12. The first sealing layer 13 is in an overhanging state with respect to the groove 12, and is formed so as not to enter the inside from the opening 12 c of the groove 12, for example. The first sealing layer 13 may be formed so as to enter the inside of the groove 12 slightly (for example, up to about 1 μm) from the opening 12c.

  The first sealing layer 13 is provided with a through-hole 13a that communicates with the hollow portion 12b with an opening area smaller than the opening 12c at a position overlapping the opening 12c of the groove 12. The through holes 13a are arranged at the intersections of the lattice-shaped non-opening regions D2 in plan view (see FIG. 3). The planar shape of the through-hole 13a is, for example, a circle, but may be another shape. The second sealing layer 14 is formed to cover the first sealing layer 13 and closes the through hole 13a. The first sealing layer 13 and the second sealing layer 14 are formed of an insulating film such as a silicon oxide film and have light transmittance.

  The groove 12 is sealed by the first sealing layer 13 and the second sealing layer 14, and forms a hollow portion 12 b in the hollow state inside the groove 12. The hollow part 12b is in a state close to a vacuum, for example. The prism 15 directs light incident from the second surface 11 b opposite to the first surface 11 a of the substrate body 11 toward the liquid crystal layer 40 side at the boundary surface (inclined surface 12 a) between the substrate body 11 and the groove 12. Reflect. The hollow portion 12b may be an air layer.

  Here, the first sealing layer 13 is formed so as not to enter the inside of the groove 12 from the opening 12c, or is slightly formed so as to enter the inside of the groove 12. Compared with the electro-optical device substrate, the inclined surface 12a functioning as the reflecting surface of the prism 15 can be made larger.

<Operation of Electro-Optical Device Substrate>
Next, how the light incident on the liquid crystal device 1 is collected and emitted will be described with reference to FIG. In the liquid crystal device 1, light incident from the counter substrate 30 (prism substrate 10) side is light-modulated for each pixel P by the liquid crystal layer 40 and then emitted to the element substrate 20 side. Here, light having various incident angles is incident on the liquid crystal device 1. For example, incident light L1 incident along the optical axis passing through the planar center of the pixel P region (opening region D1) travels straight in the pixel P region, passes through the liquid crystal layer 40, and passes through the element substrate. 20 side is injected.

  On the other hand, when the incident light L2 incident from the outside of the incident light L1 travels straight as it is, it deviates from the region of the pixel P (opening region D1) and is shielded by the light shielding portion (data line 3). In the liquid crystal device 1, such incident light L <b> 2 is reflected by the prism 15 to be directed toward the region of the pixel P. As described above, in the liquid crystal device 1, the incident light is efficiently guided toward the area of the pixel P by the prism 15, so that the utilization efficiency of the incident light can be increased.

  The prism 15 has a function of totally reflecting incident light at the boundary surface (inclined surface 12 a) between the substrate body 11 and the groove 12. In order to totally reflect incident light, the optical conditions of the prism 15 are as follows: the refractive index of the substrate body 11 is R1, the refractive index of the hollow portion 12b is R2, and the incident angle of the incident light with respect to the normal of the inclined surface 12a is θ. In this case, it is necessary to satisfy R1> R2 and sin θ> R2 / R1.

  For example, when quartz is used as the material of the substrate body 11, the refractive index R1 of the substrate body 11 is 1.46, so the refractive index R2 of the hollow portion 12b may be 1.4 or less, for example. In this embodiment, since the hollow part 12b is in a state close to a vacuum, the refractive index R2 of the hollow part 12b is extremely small with respect to the refractive index R1 of the substrate body 11. Therefore, the incident light can be totally reflected by the inclined surface 12a over a wide angle range of the incident angle θ.

  Regarding the design of the angle formed by the inclined surface 12a of the prism 15 and the normal direction of the second surface 11b of the substrate body 11, the incident light angle distribution and the projection lens 117 (see FIG. 12) of the projector 100 described later are captured. It is determined based on an angle (F value) or the like. In the present embodiment, the angle formed by the inclined surface 12a and the normal direction of the second surface 11b of the substrate body 11 is, for example, about 1 ° to 3 °.

  The element substrate 20 and the counter substrate 30 in the liquid crystal device 1 have insulating films and conductive films having different refractive indexes, and incident light passes through these insulating films and conductive films and the liquid crystal layer 40. Therefore, it is desirable to find an optical condition in which the light use efficiency is highest in the configuration of the liquid crystal device 1 as the optical condition of the prism 15. Further, it is desirable that the depth of the groove 12, the width of the opening 12c, and the angle of the inclined surface 12a in the prism 15 are determined based on optical conditions that maximize light utilization efficiency.

<Method for Manufacturing Electro-Optical Device Substrate>
Next, a method for manufacturing the prism substrate 10 as the electro-optical device substrate according to the first embodiment will be described with reference to FIGS. 5, 6, 7, 8, 9, and 10. 5, 6, 7, 8, 9, and 10 are schematic cross-sectional views illustrating a method for manufacturing a substrate for an electro-optical device according to the first embodiment. In addition, each figure of FIG.5, FIG.6, FIG.7, FIG.8, FIG.9 and FIG.10 is corresponded in the schematic sectional drawing along the AA 'line of FIG.

  Although not shown, in the manufacturing process of the prism substrate 10, processing is performed with a large substrate (mother substrate) that can take a plurality of prism substrates 10, and the mother substrate is finally cut into individual pieces. Thus, a plurality of prism substrates 10 are obtained. Accordingly, in each step described below, processing is performed in the state of the mother substrate before being singulated, but here, processing for individual prism substrates 10 in the mother substrate will be described.

  First, as shown in FIG. 5A, a mask layer 71 is formed on the first surface 11a of the substrate body 11 having optical transparency. In the present embodiment, quartz is used as the material of the substrate body 11. As the mask layer 71, for example, a hard mask made of a metal material such as W (tungsten) or WSi (tungsten silicide) is preferably used in order to deeply form the groove 12 formed in the next step. Then, an opening 71 a is formed in a region corresponding to the display region E of the mask layer 71 using a photolithography technique. The opening 71a is formed corresponding to the non-opening region D2 shown in FIG. 3 in plan view.

  Next, an etching process is performed on the substrate body 11 through the opening 71 a of the mask layer 71. As a result, as shown in FIG. 5B, the groove 12 having the opening 12c and the inclined surface 12a is formed in the display area E of the first surface 11a of the substrate body 11. As the etching process, for example, dry etching using an ICP (ICP-RIE / Inductive Coupled Plasma-RIE) dry etching apparatus capable of forming high-density plasma is used.

  As an etching gas, for example, a gas in which oxygen, carbon monoxide, or the like is mixed with a fluorine-based gas is used. For example, when the etching selectivity between the substrate body 11 and the mask layer 71 is 4 or more: 1, the groove 12 having a V-shaped cross section having a depth four times or more the thickness of the mask layer 71 can be formed. After forming the groove 12, the mask layer 71 is removed from the substrate body 11.

  Next, as shown in FIG. 5C, the material of the sacrificial layer 72 is deposited on the first surface 11 a of the substrate body 11 to cover the first surface 11 a and fill the inside of the groove 12 to close the opening 12 c. A sacrificial layer 72 is formed. As a material of the sacrificial layer 72, for example, silicon can be used. As a method for forming the sacrificial layer 72, for example, a CVD (Chemical Vapor Deposition) method can be used. The sacrificial layer 72 may be formed by using a resin material as the material of the sacrificial layer 72 and applying it by a spin coating method or the like.

  Next, as shown in FIGS. 6A to 6C, the first surface 11 a side of the substrate body 11 is polished to remove a portion of the sacrificial layer 72 outside the groove 12. (First polishing step). FIGS. 6A to 6C schematically show states according to the progress of the polishing process in the first polishing step. Examples of the polishing method include chemical mechanical polishing (CMP). In the CMP process, a polishing apparatus (not shown) provided with a polishing pad and a chemical polishing agent are used to perform a process of removing unevenness on the surface and flattening by a combined action of chemical action and mechanical polishing.

  First, as shown in FIG. 6A, a portion of the sacrificial layer 72 above the first surface 11a is removed. As a result, a portion of the sacrificial layer 72 above the first surface 11a is removed, and a portion that fills the inside of the groove 12 is left.

  Although not shown in FIG. 6A, in this state, there are many irregularities due to the sacrificial layer 72 and the grooves 12 remaining on the first surface 11 a on the first surface 11 a side of the substrate body 11. Further, if even a small amount of the sacrificial layer 72 remains on the first surface 11a, the transmittance of light transmitted through the substrate body 11 is lowered. Therefore, the polishing of the first surface 11a is further continued from this state.

  Here, the hardness of silicon that is the material of the sacrificial layer 72 is lower than the hardness of quartz that is the material of the substrate body 11. Therefore, by continuing the polishing of the first surface 11a, as shown in FIG. 6B, the sacrificial layer 72 is polished more than the substrate body 11, and the sacrificial layer 72 is removed from the first surface 11a to the groove 12. It will be in the state dug inside. In the state as shown in FIG. 6B, only the substrate body 11 is temporarily polished.

  The polishing load in the CMP process depends on the pressure for pressing the substrate body 11 and the contact area of the polishing pad. If the pressure for pressing the substrate body 11 is constant, the contact area between the substrate body 11 and the polishing pad is The smaller the size, the larger. Since the groove 12 is provided in the display area E, the ratio of the substrate material to the unit area is smaller in the display area E than in the non-display area F in which the groove 12 is not provided.

  Therefore, the polishing load on the substrate body 11 is not uniform over the entire surface to be polished, and is larger in the display area E than in the non-display area F. Therefore, the polishing rate in the display area E is higher than the polishing rate in the non-display area F. As a result, as shown in FIG. 6C, the substrate body 11 is polished more in the display area E than in the non-display area F, so that the display area E is recessed in the non-display area F. It becomes. That is, a step is generated between the display area E and the non-display area F.

  FIG. 7A schematically shows the level difference at the initial stage of the first polishing process, and FIG. 7B schematically shows the level difference at the end of the first polishing process. As shown in FIG. 7A, in the initial stage of the first polishing process, there are many irregularities in the display area E and the non-display area F. By continuing the polishing, as shown in FIG. 7B, many of these irregularities are relaxed, but a large step is generated between the display area E and the non-display area F.

  When the level difference between the display area E and the non-display area F is large, the level difference is reflected on the surface of each layer formed on the upper layer of the substrate body 11 in the subsequent steps. And even if the surface of the planarization layer 33 formed on the substrate body 11 is polished in a second polishing step described later, the step cannot be sufficiently relaxed and a good flat surface may not be obtained. Therefore, in the present embodiment, before the second polishing step, processing for relaxing the step between the display area E and the non-display area F is performed.

  In addition, when removing the upper part of the sacrificial layer 72 in a 1st grinding | polishing process, it is good also as performing dry etching in addition to CMP process. Further, when the first polishing step is completed, the upper surface of the sacrificial layer 72 filling the inside of the groove 12 may be recessed slightly lower than the first surface 11a. If the upper surface of the sacrificial layer 72 is recessed from the first surface 11a in this way, the groove 12 can be easily seen in plan view. For example, the counter substrate 30 having the prism substrate 10 and the element substrate 20 are bonded together. The groove 12 can be used as a reference for alignment in a process or the like.

Next, as shown in FIG. 8A, the first sealing layer 13 is formed so as to cover the first surface 11 a of the substrate body 11 and the sacrificial layer 72 inside the groove 12. The first sealing layer 13 is formed by, for example, a low pressure CVD method using TEOS (tetraethoxysilane: Si (OC ₂ H ₅ ) ₄ ) or a plasma CVD method using tetraethoxysilane and oxygen gas. It is composed of a silicon oxide film such as SiO ₂ .

  Next, as illustrated in FIG. 8B, a resist layer 73 is formed on the first sealing layer 13. The resist layer 73 is first formed so as to cover the first sealing layer 13 as indicated by a dotted line in FIG. Then, an opening 73 a is formed at a position overlapping the sacrificial layer 72 (groove 12) in the display area E. The opening 73 a is formed so that the opening area is smaller than the opening 12 c of the groove 12. More specifically, the through hole 13a is formed such that the diameter of the opening of the through hole 13a is smaller than the width of the opening 12c of the groove 12 in the Y direction. In the non-display area F, an opening 73b is formed.

  Next, as shown in FIG. 8C, a through hole 13a reaching the sacrificial layer 72 is formed at a position overlapping the sacrificial layer 72 (groove 12) of the first sealing layer 13 (through hole forming step). . In the through hole forming step, the through hole 13a is formed in the first sealing layer 13, and the portion corresponding to the non-display area F of the first sealing layer 13 is removed, so that the first surface 11a of the substrate body 11 is removed. A recess 11c is formed in the non-display area F on the side. For example, the recess 11c is formed in a frame shape so as to surround the periphery of the display area E shown in FIG.

In the through hole forming step, for example, CF ₄ , C ₄ F ₈ or the like is formed on the first sealing layer 13 and the substrate body 11 through the opening 73a and the opening 73b of the resist layer 73 shown in FIG. A dry etching process using the fluorocarbon-based gas as an etching gas is performed. The dry etching process is desirably performed under such a condition that the etching rate of etching performed through the opening 73b is smaller than the etching rate of etching performed through the opening 73a. For example, it is preferable to set the pressure lower and set the gas flow rate lower.

  As a result, as shown in FIG. 8C, in the display region E, a through hole 13a having an opening area smaller than the opening 12c of the groove 12 is formed in the first sealing layer 13, and the through hole 13a is formed in the through hole 13a. The sacrificial layer 72 is exposed. On the other hand, in the non-display area F, the first sealing layer 13 is removed, and a recess 11 c is formed in the substrate body 11. By forming the recess 11c in the non-display area F, the step between the display area E and the non-display area F is relaxed and becomes smaller. Moreover, since the recessed part 11c is formed in frame shape, the level | step difference with the non-display area | region F can be eased over the circumference | surroundings of the display area E. FIG.

  In the present embodiment, since the concave portion 11c is formed in the substrate body 11 in the through hole forming step in this way, a step of forming the concave portion 11c is not required separately. Therefore, productivity in the manufacture of the substrate for the electro-optical device can be improved as compared with the case where a step of forming the recess 11c is separately required.

Next, as shown in FIG. 9A, the sacrificial layer 72 embedded in the trench 12 is removed. In the sacrificial layer removal step, dry etching using, as an etching gas, a fluorine-based gas such as chlorine trifluoride (ClF ₃ ) or xenon difluoride (XeF ₂ ) through the through hole 13 a of the first sealing layer 13. Etching is performed. Thereby, the sacrificial layer 72 is selectively etched and removed from the inside of the groove 12.

  Next, as shown in FIG. 9B, a second sealing layer 14 that covers the recess 11c of the substrate body 11 and the first sealing layer 13 and closes the through hole 13a is formed. The second sealing layer 14 is formed of, for example, a silicon oxide film using a low pressure CVD method or the like, similarly to the step of forming the first sealing layer. Thereby, the through-hole 13a of the 1st sealing layer 13 is block | closed, the inside of the groove | channel 12 is sealed in a hollow state, and the hollow part 12b is formed. As a result, the prism 15 is formed on the substrate body 11.

  In the present embodiment, since the recess 11c is formed in the through-hole forming step, the step between the display area E and the non-display area F on the upper surface of the second sealing layer 14 is relaxed. Note that there are some irregularities on the upper surface of the second sealing layer 14 due to the through holes 13 a of the first sealing layer 13.

  In the present embodiment, since the formation of the second sealing layer 14 is performed in an atmosphere reduced in pressure close to a vacuum, when the second sealing layer 14 is formed so as to cover the through hole 13a, the prism is formed. The 15 hollow portions 12b are sealed in a state close to vacuum. Thus, since the hollow portion 12b of the prism 15 is in the same state as the atmosphere for forming the second sealing layer 14, if the second sealing layer 14 is formed in the air, the hollow portion 12b becomes an air layer. .

  Furthermore, in this embodiment, compared with the method for manufacturing the substrate for an electro-optical device described in Patent Document 1, the inside of the groove 12 is made a hollow portion 12b in a hollow state while the opening 12c of the groove 12 is more reliably closed. Therefore, the inclined surface 12a that functions as the reflecting surface of the prism 15 can be made larger. Thus, the prism substrate 10 is completed.

  Next, as illustrated in FIG. 9C, the light shielding layer 32 is formed in a region (non-display region F) that overlaps the concave portion 11 c in plan view on the second sealing layer 14 of the prism substrate 10. In addition, an alignment mark 16 as a mark is formed in a region (non-display region F) overlapping the concave portion 11 c on the second sealing layer 14. The alignment mark 16 is obtained by patterning a part of the light shielding film as the alignment mark 16 when a light shielding film for forming the light shielding layer 32 is formed and patterned.

  The alignment mark 16 is used, for example, as a reference for alignment so that positional displacement does not occur in the process of bonding the element substrate 20 and the counter substrate 30 together. The alignment marks 16 are illustrated in the cut surface of FIG. 9C, but may be disposed at the four corners of the substrate body 11.

  Next, as shown in FIG. 10A, the planarization layer 33 is formed so as to cover the second sealing layer 14, the light shielding layer 32, and the alignment mark 16. The planarization layer 33 is formed of a silicon oxide film using a low pressure CVD method or the like, for example, similarly to the step of forming the first sealing layer 13. The surface of the planarization layer 33 after film formation reflects the unevenness on the upper surface of the second sealing layer 14 and the unevenness caused by the alignment mark 16 and the light shielding layer 32.

  Next, as shown in FIG. 10B, the first surface 11a side of the substrate body 11, that is, the surface of the planarizing layer 33 is polished and planarized (second polishing step). In the second polishing process, for example, a CMP process is used as in the first polishing process. Thereby, the unevenness of the surface of the planarization layer 33 is alleviated, and the step between the display area E and the non-display area F is further relaxed, and the surface of the planarization layer 33 is planarized.

  Here, consider a case where the recess 11c is not formed in the substrate body 11 in the through hole forming step. That is, suppose that the first sealing layer 13 and the first sealing layer 13 and the first sealing layer 13 are not formed on the substrate body 11 with a step between the display area E and the non-display area F before the recess 11c shown in FIG. It is assumed that the two sealing layers 14 are stacked and the alignment mark 16 is formed on the second sealing layer 14.

  In this case, the position of the alignment mark 16 in the Z direction is higher than the position shown in FIG. 9C (on the −Z direction side) with respect to the first surface 11a of the substrate body 11 in the display area E. . Then, in the second polishing step, since the non-display area F must be polished more than the display area E, the step between the display area E and the non-display area F cannot be easily relaxed. The mark 16 may be removed.

  Note that it is possible to reduce the step between the display area E and the non-display area F by forming a recess in the non-display area F immediately before the second polishing step. However, in that case, the step of forming the recesses is added as compared with the present embodiment, leading to a decrease in productivity. Then, by forming a recess in the non-display area F after the alignment mark 16 is formed in the non-display area F, the possibility that the alignment mark 16 is removed increases. In order to avoid this, it is necessary to form the planarization layer 33 thick so that the step between the display area E and the non-display area F can be absorbed.

  In the present embodiment, the step between the display region E and the non-display region F is relaxed before the second sealing layer 14, the alignment mark 16, and the planarization layer 33 are formed. Accordingly, not only can the surface of the planarization layer 33 be more easily and better planarized in the second polishing step, but also the remaining thickness of the planarization layer 33 on the alignment mark 16 can be easily secured. It is possible to suppress disappearance and removal of a part of the alignment mark 16.

  Even in the second polishing step, a step may occur due to non-uniform polishing load between the non-display area F and the display area E. In the present embodiment, when a step is generated in the second polishing step, the step generated in the second polishing step is expected and reflected in the shape of the recess 11c formed in the non-display area F in the through hole forming step. Can do. Thereby, the shape of the substrate body 11 can be corrected in advance so that no step is generated in the second polishing step.

  Next, as shown in FIG. 10C, the common electrode 34 is formed on the planarization layer 33, and the alignment film 35 is formed so as to cover the common electrode 34. Thereby, the counter substrate 30 is completed.

  As described above, according to the first embodiment, the following effects can be obtained.

  (1) Since the recess 11c is formed in the non-display area F of the substrate body 11, the polishing amount of the display area E is polished in the non-display area F when the first surface 11a of the substrate body 11 is polished in the first polishing process. The level difference between the display area E and the non-display area F caused by the increase in amount can be reduced. Since the second polishing step is performed after the level difference between the display area E and the non-display area F is relaxed, the surface of the flattening layer 33 can be easily flattened and the flatness can be improved in the second polishing process. Can be made.

  (2) Since the second sealing layer 14 is formed so as to cover the display area E and the non-display area F after the level difference between the display area E and the non-display area F is relaxed, The surface can be a surface with few steps. Thereby, in the second polishing step, the flatness of the surface of the planarizing layer 33 formed on the second sealing layer 14 can be further improved.

  (3) Since not only the through hole 13a but also the recess 11c is formed in the step of forming the through hole 13a in the first sealing layer 13, a step of forming the recess 11c is not required. Thereby, the productivity of the counter substrate 30 (prism substrate 10) can be improved as compared with a case where a step of forming the recess 11c is separately required.

  (4) Since the recess 11c is formed so as to surround the outside of the display area E, the step with the non-display area F can be relaxed around the display area E. Thereby, the flatness of the surface of the planarization layer 33 can be further improved.

  (5) Since the recess 11c is formed in the non-display area F and the alignment mark 16 is formed in the area overlapping the recess 11c in a plane, the alignment mark 16 and the display area E are compared with the case where the recess 11c is not formed. The step can be reduced. Therefore, when the surface of the planarization layer 33 is polished in the second polishing step, the remaining thickness of the planarization layer 33 on the alignment mark 16 can be easily ensured as compared with the case where the recess 11c is not formed. It can be suppressed that 16 disappears or a part of alignment mark 16 is removed.

(Second Embodiment)
<Method for Manufacturing Electro-Optical Device Substrate>
Next, a method for manufacturing the electro-optical device substrate according to the second embodiment will be described with reference to FIG. FIG. 11 is a schematic view illustrating a method for manufacturing a substrate for an electro-optical device according to the second embodiment. FIG. 11A is a schematic plan view of the prism substrate 10 as viewed from the first surface 11a side of the substrate body 11, and FIG. 11B is along the line BB ′ in FIG. FIG.

  The method for manufacturing the electro-optical device substrate according to the second embodiment is a method for manufacturing the prism substrate 10 having the same configuration as that of the first embodiment, and a plurality of recesses 11c are formed with respect to the first embodiment. However, the other configurations are almost the same. In addition, about the component which is common in 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  As shown in FIGS. 11A and 11B, in the second embodiment, a plurality of recesses 11c are formed with a predetermined interval. For example, the recess 11c is formed in a frame shape in the non-display area F shown in FIG. 11A in plan view, and is formed so that the outer recess 11c surrounds the inner recess 11c.

  The plurality of recesses 11c are formed with the same width W1 in the extending direction. In addition, a predetermined interval W2 is provided between the adjacent recesses 11c. In addition, between the adjacent recessed parts 11c is a part which remained convexly on the 1st surface 11a side by forming the recessed part 11c among the board | substrate main bodies 11. FIG.

  As described above, the polishing load in the CMP process of the polishing process depends on the pressure for pressing the substrate body 11 and the contact area of the polishing pad. If the pressure for pressing the substrate body 11 is constant, The smaller the contact area of the polishing pad, the larger. Therefore, when one or both of the width W1 of the recess 11c and the interval W2 between the recesses 11c are changed, the contact area between the substrate body 11 and the polishing pad changes. Thereby, the grinding | polishing load with respect to the board | substrate body 11 can be adjusted in a grinding | polishing process. That is, the difference between the polishing rate of the non-display area F and the polishing rate of the display area E can be controlled.

  Such a plurality of recesses 11c can be formed, for example, before the first polishing step. In this case, a step of forming the recess 11c is separately required. However, by forming the plurality of recesses 11c in advance, the polishing load between the non-display area F and the display area E in the first polishing process can be adjusted. Therefore, the step between the non-display area F and the display area E that occurs in the first polishing process can be suppressed.

  In addition, when a new level difference occurs in the processes after the first polishing process, the level difference occurring later is corrected by adjusting the balance of the polishing load between the non-display area F and the display area E in the first polishing process. It is also possible to form an uneven step in the first polishing process. As a result, the flatness of the surface of the counter substrate 30 (prism substrate 10) obtained in the second polishing step can be further improved.

  In the case where the counter substrate 30 does not include the alignment mark 16 or the light shielding layer 32, a plurality of steps are formed in the through hole forming step after the step is generated in the first polishing step, as in the first embodiment. The recess 11c may be formed. In this case, by appropriately setting one or both of the width W1 of the recess 11c and the interval W2 between the recesses 11c, and adjusting the polishing load between the non-display area F and the display area E in the second polishing step, Finally, the surface of the planarization layer 33 can be easily planarized.

  According to the second embodiment, the following effects can be obtained in addition to the effects of the first embodiment.

  (1) A plurality of recesses 11c are formed with a predetermined interval W2 between adjacent recesses 11c. If the pressure which pressurizes the substrate main body 11 is constant, the polishing load in the polishing step increases as the contact area between the substrate main body 11 and the polishing pad decreases. Accordingly, the contact area between the substrate body 11 and the polishing pad in the second polishing step is adjusted by appropriately setting the interval W2 between the adjacent recesses 11c, so that the polishing rate of the display region E and the polishing rate of the non-display region F are adjusted. And the difference can be controlled. Thereby, the flatness of the planarization layer 33 can be further improved.

(Third embodiment)
<Electronic equipment>
Next, an electronic apparatus according to a third embodiment will be described with reference to FIG. FIG. 12 is a schematic diagram illustrating a configuration of a projector as an electronic apparatus according to the third embodiment.

  As shown in FIG. 12, a projector (projection display device) 100 as an electronic apparatus according to the third embodiment includes a polarization illumination device 110, two dichroic mirrors 104 and 105 as light separation elements, and three Reflection mirrors 106, 107, 108, five relay lenses 111, 112, 113, 114, 115, three liquid crystal light valves 121, 122, 123, a cross dichroic prism 116 as a light combining element, and a projection lens 117 It has.

  The polarization illumination device 110 includes a lamp unit 101 as a light source composed of a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 102, and a polarization conversion element 103. The lamp unit 101, the integrator lens 102, and the polarization conversion element 103 are arranged along the system optical axis L.

  The dichroic mirror 104 reflects red light (R) and transmits green light (G) and blue light (B) among the polarized light beams emitted from the polarization illumination device 110. Another dichroic mirror 105 reflects the green light (G) transmitted through the dichroic mirror 104 and transmits the blue light (B).

  The red light (R) reflected by the dichroic mirror 104 is reflected by the reflection mirror 106 and then enters the liquid crystal light valve 121 via the relay lens 115. The green light (G) reflected by the dichroic mirror 105 enters the liquid crystal light valve 122 via the relay lens 114. The blue light (B) transmitted through the dichroic mirror 105 is incident on the liquid crystal light valve 123 via a light guide system composed of three relay lenses 111, 112, 113 and two reflection mirrors 107, 108.

  The transmissive liquid crystal light valves 121, 122, and 123 as light modulation elements are disposed to face the incident surfaces of the cross dichroic prism 116 for each color light. The color light incident on the liquid crystal light valves 121, 122, 123 is modulated based on video information (video signal) and emitted toward the cross dichroic prism 116.

  The cross dichroic prism 116 is formed by bonding four right-angle prisms, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. Yes. The three color lights are synthesized by these dielectric multilayer films, and the light representing the color image is synthesized. The synthesized light is projected onto the screen 130 by the projection lens 117 which is a projection optical system, and the image is enlarged and displayed.

  The liquid crystal light valve 121 is applied with the liquid crystal device 1 having the prism substrate 10 of the above-described embodiment. The liquid crystal light valve 121 is arranged with a gap between a pair of polarizing elements arranged in crossed Nicols on the incident side and emission side of colored light. The same applies to the other liquid crystal light valves 122 and 123.

  According to the configuration of the projector 100 according to the third embodiment, the liquid crystal device 1 including the prism substrate 10 having excellent display quality and cost competitiveness is provided even if the plurality of pixels P are arranged with high definition. Therefore, it is possible to provide the projector 100 with high quality and brightness.

  The above-described embodiments merely show one aspect of the present invention, and can be arbitrarily modified and applied within the scope of the present invention. As modifications, for example, the following can be considered.

(Modification 1)
In the method for manufacturing the substrate for an electro-optical device according to the above embodiment, the concave portion 11c is formed in a frame shape in plan view, but the present invention is not limited to such a form. The planar shape of the recess 11c is not limited to a frame shape, and may be formed by being divided into an island shape, for example. As described above, the polishing load in the CMP process of the polishing process depends on the contact area between the substrate body 11 and the polishing pad. Therefore, since the polishing load can be adjusted by adjusting the area ratio between the recess 11c occupying the unit area and the remaining portion of the substrate body 11, the surface of the counter substrate 30 can be easily and satisfactorily the same as in the above embodiment. It can be flattened.

(Modification 2)
In the above embodiment, the liquid crystal device 1 has the configuration in which the counter substrate 30 includes the prism substrate 10, but the present invention is not limited to such a configuration. Even if the liquid crystal device 1 has a configuration in which the element substrate 20 includes the prism substrate 10, the same effect can be obtained by applying the method for manufacturing the electro-optical device substrate according to the above-described embodiment.

(Modification 3)
The liquid crystal device 1 according to the above embodiment is a transmissive liquid crystal device in which the pixel electrode 28 and the common electrode 34 are formed of a light-transmitting conductive film, but the present invention is not limited to such a form. The pixel electrode 28 or the common electrode 34 of the liquid crystal device 1 may be formed of a light-reflective conductive film such as aluminum to form a reflective liquid crystal device. If the pixel electrode 28 is formed of a light-reflective conductive film, light incident from the counter substrate 30 side is light-modulated while being reflected on the element substrate 20 side (pixel electrode 28) and emitted from the counter substrate 30 side. The If the common electrode 34 is formed of a light-reflective conductive film, light incident from the element substrate 20 side is light-modulated while being reflected on the counter substrate 30 side (common electrode 34) and emitted from the element substrate 20 side. The

(Modification 4)
The electronic apparatus (projector 100) of the above embodiment includes the three liquid crystal light valves 121, 122, 123 to which the liquid crystal device 1 is applied, but the present invention is not limited to such a form. The electronic device may have a configuration including two or less liquid crystal light valves (liquid crystal device 1), or may have a configuration including four or more liquid crystal light valves (liquid crystal device 1).

(Modification 5)
An electronic apparatus to which the liquid crystal device 1 according to the above embodiment can be applied is not limited to the projector 100. The liquid crystal device 1 is, for example, a projection type HUD (head-up display), a direct-view type HMD (head-mounted display), an electronic book, a personal computer, a digital still camera, a liquid crystal television, a viewfinder type, or a monitor direct-view type video. It can be suitably used as a display unit for information terminal devices such as recorders, car navigation systems, electronic notebooks, and POS.

(Modification 6)
In the above embodiment, the liquid crystal device has been described as an example of the electro-optical device including the electro-optical device substrate (prism substrate 10), but the present invention is not limited to such a form. For example, the electrophoretic display device may include an electro-optical device substrate (prism substrate 10) for the purpose of increasing the amount of display light. Further, an electro-optical device having a self-light-emitting element such as an organic electroluminescence device may be configured to include an electro-optical device substrate (prism substrate 10) for the purpose of preventing color mixing and the like.

  DESCRIPTION OF SYMBOLS 1 ... Liquid crystal device (electro-optical device), 10 ... Prism substrate (substrate for electro-optical device), 11 ... Substrate body (substrate), 11a ... First surface (main surface), 11b ... Second surface, 11c ... Recessed portion, DESCRIPTION OF SYMBOLS 12 ... Groove, 13 ... 1st sealing layer, 13a ... Through-hole, 14 ... 2nd sealing layer, 15 ... Prism (reflection part), 16 ... Alignment mark (mark), 20 ... Element board | substrate (1st board | substrate) 24 ... TFT (switching element), 28 ... pixel electrode, 30 ... counter substrate (second substrate), 33 ... flattening layer, 40 ... liquid crystal layer (electro-optic material layer), 72 ... sacrificial layer, E ... display area (First area), F ... non-display area (second area), 100 ... projector (electronic device).

Claims (6)

A method for manufacturing a substrate for an electro-optical device having, on a main surface, a first region in which a reflecting portion including a groove is disposed, and a second region surrounding the outside of the first region,
Forming the groove in the first region of the substrate having optical transparency;
Depositing a sacrificial layer on the side of the main surface and filling the inside of the trench with the sacrificial layer;
A first polishing step of polishing a side of the main surface of the substrate to remove a portion of the sacrificial layer located outside the groove;
Forming a first sealing layer covering the main surface and the sacrificial layer inside the groove;
A through hole forming step of forming a through hole at a position overlapping the sacrificial layer inside the groove of the first sealing layer;
Removing the sacrificial layer inside the groove through the through hole;
A second sealing layer forming step of forming a second sealing layer covering the first sealing layer and closing the through hole;
A second polishing step for polishing the main surface side of the substrate,
In the through-hole forming step, a concave portion is formed in the second region on the main surface side. A method for manufacturing a substrate for an electro-optical device according to claim 1,
The method of manufacturing a substrate for an electro-optical device, wherein the recess is formed so as to surround an outer side of the first region. A method for manufacturing a substrate for an electro-optical device according to claim 1,
A method of manufacturing a substrate for an electro-optical device, wherein a plurality of the recesses are formed at a predetermined interval. A method for manufacturing a substrate for an electro-optical device according to any one of claims 1 to 3,
Between the through hole forming step and the second polishing step,
Forming a mark in a region overlapping the recess in a plane,
And a step of forming a planarization layer covering the mark and the second sealing layer. A first substrate provided with a plurality of pixel electrodes and a switching element corresponding to each of the plurality of pixel electrodes;
A second substrate disposed opposite the first substrate;
An electro-optic material layer provided between the first substrate and the second substrate,
5. The electro-optical device, wherein either the first substrate or the second substrate is manufactured by the method for manufacturing a substrate for an electro-optical device according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 5.

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