JP6303283B2 - Semiconductor device, electro-optical device, semiconductor device manufacturing method, and electronic apparatus - Google Patents

Description

  The present invention relates to a semiconductor device, an electro-optical device, a method for manufacturing a semiconductor device, a method for manufacturing an electro-optical device, an electronic apparatus, and the like.

  As one of the electro-optical devices, for example, an active drive type liquid crystal device including a transistor (semiconductor device) for each pixel as an element for switching control of a pixel electrode is known. Liquid crystal devices are used in, for example, direct-view displays and projector light valves.

  The transistor is generally provided such that the semiconductor layer is substantially parallel to the surface of the substrate. The area where the transistor is provided needs to be a light-shielding area, and if this area is large, the aperture ratio decreases. Therefore, for the purpose of further improving the aperture ratio, for example, in the method described in Patent Document 1, the semiconductor layer is arranged in a direction substantially perpendicular to the surface of the substrate, whereby the transistor region can be reduced in a plane. Thus, the light shielding area can be reduced.

JP 2011-221072 A

  However, the method described in Patent Document 1 has a problem that it is difficult to form a source / drain region in a semiconductor layer. In other words, since the ion implantation method to the semiconductor layer is difficult, there is a demand for simplification of the manufacturing method.

  An aspect of the present invention has been made to solve at least a part of the above problems, and can be realized as the following forms or application examples.

  Application Example 1 A semiconductor device according to this application example includes a semiconductor layer including one of a source region and a drain region, the other of the source region and the drain region, and a channel region, and gate insulation covering the channel region. A first electrode that is one of a source electrode and a drain electrode, and a second electrode that is one of the source electrode and the drain electrode, and a gate electrode disposed so as to face the channel region with the gate insulating layer interposed therebetween. And one of the source region and the drain region is disposed so as to cover at least a part of the second surface of the first insulating layer, and the other of the source region and the drain region is at least a part of the second electrode. Is disposed so as to cover the third surface of the first insulating layer, and the channel region is a small fourth surface disposed between the second surface and the third surface of the first insulating layer. The first insulating layer has a first surface opposite to the second surface and the third surface, and is disposed between the first surface and the second surface. Is smaller than the distance between the first surface and the third surface, and the first electrode and the second electrode are electrically connected to the semiconductor layer.

  According to this application example, the convex portion configured by the second surface, the fourth surface, and the third surface of the first insulating layer is provided, and in particular, the semiconductor along the fourth surface serving as the side surface of the convex portion. Since the layer, the gate insulating layer, and the gate electrode are provided, the width of the gate electrode is shortened when viewed from the direction from the second surface to the first surface (in plan view) without shortening the gate length. be able to. Thereby, it becomes possible to make a light-shielding area small and to improve an aperture ratio. In addition, since a semiconductor layer can be ion-implanted using a known manufacturing method, a transistor can be formed relatively easily.

  Application Example 2 A semiconductor device according to this application example includes a semiconductor layer including one of a source region and a drain region, the other of the source region and the drain region, and a channel region, and gate insulation covering the channel region. A first electrode that is one of a source electrode and a drain electrode, and a second electrode that is one of the source electrode and the drain electrode, and a gate electrode disposed so as to face the channel region with the gate insulating layer interposed therebetween. A second electrode, and the semiconductor layer is disposed to cover the first insulating layer, and the first insulating layer is disposed to cover a gate wiring electrically connected to the gate electrode, The gate wiring includes a first surface, second and third surfaces facing the first surface, and a fourth surface disposed between the second surface and the third surface. , The first surface and the second surface The distance between the first and third surfaces is smaller than the distance between the first surface and the third surface, and at least one of the source region and the drain region faces the second surface through the first insulating layer. The other of the source region and the drain region is disposed so that at least a part thereof is opposed to the third surface through the first insulating layer, and at least a part of the channel region is disposed in the first insulation. It arrange | positions so that the said 4th surface may be opposed through a layer, The said 1st electrode and the said 2nd electrode are electrically connected to the said semiconductor layer, It is characterized by the above-mentioned.

  According to this application example, the convex portion including the second surface, the fourth surface, and the third surface of the gate wiring is provided, and in particular, the semiconductor layer along the fourth surface serving as the side surface of the convex portion, Since the gate insulating layer and the gate electrode are provided, the width of the gate electrode can be shortened when viewed from the direction from the second surface to the first surface (in plan view) without shortening the gate length. it can. Thereby, it becomes possible to make a light-shielding area small and to improve an aperture ratio. In addition, since a semiconductor layer can be ion-implanted using a known manufacturing method, a transistor can be formed relatively easily. In addition, since the convex portion is formed in the gate wiring, the convex portion and the semiconductor layer can be brought close to each other, and the gate electrode and the gate wiring (back gate) can function as a double gate electrode. Thereby, the ON / OFF characteristic of the transistor can be improved.

  Application Example 3 A semiconductor device according to this application example includes a semiconductor layer including one of a source region and a drain region, the other of the source region and the drain region, and a channel region, and gate insulation covering the channel region. A first electrode that is one of a source electrode and a drain electrode, and a second electrode that is one of the source electrode and the drain electrode, and a gate electrode disposed so as to face the channel region with the gate insulating layer interposed therebetween. A second electrode, wherein one of the source region and the drain region is disposed so as to cover at least a part of the second surface of the first insulating layer, and the other of the source region and the drain region is at least A portion is disposed so as to cover the third surface of the first insulating layer, and at least a portion of the channel region is formed between the second surface and the third surface of the first insulating layer. The first insulating layer is disposed so as to cover the gate wiring electrically connected to the gate electrode, and the gate wiring covers the base layer. The underlayer includes a fifth surface on the substrate side, a sixth surface on the gate wiring side, a seventh surface on the gate wiring side, and the sixth surface and the seventh surface. And the distance between the fifth surface and the sixth surface is smaller than the distance between the fifth surface and the seventh surface. The second surface is disposed so as to be opposed, the third surface is disposed so as to be opposed to the seventh surface, and the fourth surface is disposed so as to be opposed to the eighth surface. And

  According to this application example, since the convex portion including the sixth surface, the seventh surface, and the eighth surface is provided on the base layer, the gate wiring arranged thereon is along the undulation of the base layer. What is necessary is just to form. Therefore, it is possible to reduce the material used for the gate wiring compared to the case where the gate wiring is provided with a convex portion, and the gate wiring can be formed relatively easily.

  Application Example 4 A semiconductor device according to this application example includes a semiconductor layer including one of a source region and a drain region, the other of the source region and the drain region, and a channel region, and gate insulation covering the channel region. A first electrode that is one of a source electrode and a drain electrode, and a second electrode that is one of the source electrode and the drain electrode, and a gate electrode disposed so as to face the channel region with the gate insulating layer interposed therebetween. A second electrode, wherein one of the source region and the drain region is disposed so as to cover at least a part of the second surface of the first insulating layer, and the other of the source region and the drain region is at least A portion is disposed so as to cover the third surface of the first insulating layer, and at least a portion of the channel region is formed between the second surface and the third surface of the first insulating layer. The first insulating layer is arranged to cover a gate wiring electrically connected to the gate electrode, and the gate wiring covers the surface of the substrate. The surface of the substrate includes a ninth surface, a tenth surface protruding from the ninth surface, and an eleventh surface disposed between the ninth surface and the tenth surface. The second surface is disposed to face the ninth surface, the third surface is disposed to face the tenth surface, and the fourth surface is disposed to face the eleventh surface. Is arranged.

  According to this application example, since the gate wiring is arranged so as to cover the surface of the substrate having the convex portion, it is possible to reduce the material used for the gate wiring compared to the case where the convex portion is provided in the gate wiring. Therefore, the gate wiring can be formed relatively easily.

  Application Example 5 In the semiconductor device according to the application example, the first electrode is disposed inside a first contact hole that is disposed so as to penetrate the second insulating layer that covers the semiconductor layer and the gate electrode. It is preferable that the second electrode is disposed inside a second contact hole disposed so as to penetrate the second insulating layer.

  According to this application example, since the first electrode and the second electrode are provided on the second insulating layer side, compared with the case where the first electrode and the second electrode are provided closer to the substrate side, the first electrode and the second electrode are provided. It is possible to suppress damage such as heat from being applied to the wiring connected to the two electrodes. Therefore, reliability can be improved.

  Application Example 6 An electro-optical device according to this application example includes the above-described semiconductor device, a pixel electrode electrically connected to the semiconductor device, an element substrate including the semiconductor device and the pixel electrode, A counter substrate disposed opposite to the element substrate, and an electro-optic layer sandwiched between the element substrate and the counter substrate.

  According to this application example, since the size of the planar semiconductor device is suppressed, the aperture ratio can be improved.

  Application Example 7 In the electro-optical device according to the application example described above, the semiconductor device described above, a pixel electrode electrically connected to the semiconductor device, an element substrate including the semiconductor device and the pixel electrode, A counter substrate disposed opposite to the element substrate, and an electro-optic layer sandwiched between the element substrate and the counter substrate, wherein the semiconductor device is disposed so as to overlap the gate wiring in a plan view. Preferably it is.

  According to this application example, since the semiconductor device and the gate wiring are arranged so as to overlap in a plan view, it is possible to prevent the aperture ratio from decreasing without expanding the light shielding region.

  Application Example 8 A method of manufacturing a semiconductor device according to this application example includes a gate wiring forming step of forming a gate wiring on a substrate, and a first insulating layer formed on the gate wiring and the substrate. An insulating layer forming step; a second surface facing the first surface on the substrate side; a third surface having a distance from the first surface longer than the second surface; A convex portion forming step for forming a second surface between the second surface and the third surface, the second surface in the first insulating layer, and the second surface of the first insulating layer, A semiconductor layer forming step of forming a semiconductor layer so as to cover the third surface and the fourth surface; and an ion implantation step of implanting impurity ions into the semiconductor layer to form a channel region, a source region, and a drain region; Forming a gate insulating layer on the semiconductor layer; And forming step, on the gate insulating layer, and having a gate electrode forming step of forming a gate electrode so as to face the fourth surface.

  According to this application example, the convex portion constituted by the second surface, the fourth surface, and the third surface of the first insulating layer is formed, and in particular, the semiconductor layer along the fourth surface that is the side surface of the convex portion, Since the gate insulating layer and the gate electrode are formed, the width of the gate electrode can be shortened when viewed from the second surface toward the first surface (in plan view) without shortening the gate length. Thereby, it becomes possible to make a light-shielding area small and to improve an aperture ratio. In addition, since a semiconductor layer can be ion-implanted using a known manufacturing method, a transistor can be formed relatively easily.

  Application Example 9 A semiconductor device manufacturing method according to this application example includes a gate wiring precursor film forming step of forming a gate wiring precursor film for forming a gate wiring on a substrate, and the gate wiring precursor. Etching the film, a second surface facing the first surface on the substrate side, a third surface having a distance from the first surface longer than the second surface, the second surface and the first surface A gate wiring forming step of forming a gate wiring having a fourth surface disposed between the first and second surfaces; and a first insulation for forming a first insulating layer on the substrate so as to cover the gate wiring. A semiconductor layer is formed on the first insulating layer so as to overlap the gate wiring in a plan view and to cover the second surface, the third surface, and the fourth surface of the gate wiring in a layer forming step A semiconductor layer forming step and implanting impurity ions into the semiconductor layer; An ion implantation step for forming a channel region, a source region, and a drain region, a gate insulating layer forming step for forming a gate insulating layer on the semiconductor layer, and a fourth surface on the gate insulating layer. And a gate electrode forming step of forming a gate electrode so as to face each other.

  According to this application example, a convex portion including the second surface, the fourth surface, and the third surface is formed on the gate wiring, and in particular, the semiconductor layer and the gate insulation along the fourth surface that is the side surface of the convex portion. Since the layer and the gate electrode are formed, the width of the gate electrode can be shortened when viewed from the direction from the second surface to the first surface (in plan view) without shortening the gate length. Thereby, it becomes possible to make a light-shielding area small and to improve an aperture ratio. In addition, since a semiconductor layer can be ion-implanted using a known manufacturing method, a transistor can be formed relatively easily. In addition, since the convex portion is formed in the gate wiring, the convex portion and the semiconductor layer can be brought close to each other, and the gate electrode and the semiconductor layer (back gate) can function as a double gate electrode. Thereby, the ON / OFF characteristic of the transistor can be improved.

  Application Example 10 In the method of manufacturing a semiconductor device according to this application example, a base layer is formed on a substrate, a second surface facing the first surface on the substrate side is formed on the base layer, the second surface. An underlayer forming step of forming a third surface having a distance from the first surface that is longer than the surface, and a fourth surface disposed between the second surface and the third surface; A gate wiring forming step for forming a gate wiring thereon; a first insulating layer forming step for forming a first insulating layer on the gate wiring and the underlying layer; and the gate wiring overlapping the gate wiring in a plan view. Forming a semiconductor layer on the first insulating layer so as to cover the second surface, the third surface, and the fourth surface; and implanting impurity ions into the semiconductor layer to form a channel region An ion implantation process for forming a source region and a drain region, and on the semiconductor layer A gate insulating layer forming step of forming a gate insulating layer, on the gate insulating layer, characterized in that it comprises a gate electrode forming step of forming a gate electrode so as to face the fourth surface.

  According to this application example, since the convex portion including the second surface, the fourth surface, and the third surface is formed in the base layer, the gate wiring may be formed along the undulation of the base layer. Therefore, it is possible to reduce the material used for the gate wiring compared to the case where the convex portion is formed on the gate wiring, and the gate wiring can be formed relatively easily.

  Application Example 11 In the method of manufacturing a semiconductor device according to this application example, the second surface on the surface of the substrate, the third surface protruding from the second surface, and between the second surface and the third surface. Forming a fourth surface disposed on the substrate, forming a gate wiring on the surface of the substrate, and forming a first insulating layer on the surface of the gate wiring and the substrate. A semiconductor layer that forms a semiconductor layer on the first insulating layer so as to overlap the gate wiring in plan view and to cover the second surface, the third surface, and the fourth surface in a layer forming step A step of forming, an ion implantation step of implanting impurity ions into the semiconductor layer to form a channel region, a source region, and a drain region, and a gate insulating layer forming step of forming a gate insulating layer on the semiconductor layer , On the gate insulating layer, against the fourth surface. A gate electrode forming step of forming a gate electrode so as to, characterized in that it comprises a.

  According to this application example, the convex portions are formed on the substrate, and further, the first insulating layer and the gate wiring are formed. Therefore, the effects described in the application example 10 are achieved.

  Application Example 12 A method for manufacturing an electro-optical device according to this application example includes electrically connecting the semiconductor device and the pixel electrode through a contact hole with the steps including the semiconductor device manufacturing method described above. And a step of forming an electro-optic layer on the pixel electrode.

  According to this application example, since the size of the planar semiconductor device is suppressed, the aperture ratio can be improved.

  Application Example 13 An electronic apparatus according to this application example includes the above-described electro-optical device.

  According to this application example, since the electro-optical device is provided, an electronic apparatus with high display quality can be provided.

1 is a schematic plan view illustrating a configuration of a liquid crystal device as an electro-optical device according to a first embodiment. FIG. 2 is a schematic cross-sectional view taken along the line H-H ′ of the liquid crystal device illustrated in FIG. 1. FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device. FIG. 6 is a schematic cross-sectional view illustrating structures of a liquid crystal device and a semiconductor device. The schematic plan view which looked at the semiconductor device from the upper part among the liquid crystal devices shown in FIG. 5 is a flowchart showing a method for manufacturing a liquid crystal device in the order of steps. FIG. 6 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device among methods for manufacturing a liquid crystal device. FIG. 6 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device among methods for manufacturing a liquid crystal device. Schematic which shows the structure of the projection type display apparatus provided with the liquid crystal device. FIG. 9 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. FIG. 9 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. FIG. 9 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment. FIG. 9 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. Note that the drawings to be used are appropriately enlarged or reduced so that the part to be described can be recognized.

  In the following embodiments, for example, when “on the substrate” is described, the substrate is disposed so as to be in contact with the substrate, or is disposed on the substrate via another component, or the substrate. It is assumed that a part is arranged so as to be in contact with each other and a part is arranged via another component.

  In this embodiment, an active matrix liquid crystal device including a thin film transistor (TFT) as a pixel switching element will be described as an example of the liquid crystal device. This liquid crystal device can be suitably used, for example, as a light modulation element (liquid crystal light valve) of a projection display device (liquid crystal projector).

(First embodiment)
<Configuration of liquid crystal device as electro-optical device>
FIG. 1 is a schematic plan view showing a configuration of a liquid crystal device as an electro-optical device. 2 is a schematic cross-sectional view taken along the line HH ′ of the liquid crystal device shown in FIG. FIG. 3 is an equivalent circuit diagram showing an electrical configuration of the liquid crystal device. Hereinafter, the configuration of the liquid crystal device will be described with reference to FIGS.

  As shown in FIGS. 1 and 2, the liquid crystal device 100 according to the present embodiment includes an element substrate 10 and a counter substrate 20 which are disposed to face each other, and a liquid crystal layer 15 as an electro-optical layer sandwiched between the pair of substrates. Have. As the first base material 10a as the substrate constituting the element substrate 10 and the second base material 20a constituting the counter substrate 20, for example, a transparent substrate such as a glass substrate or a quartz substrate is used.

  The element substrate 10 is larger than the counter substrate 20, and both the substrates are bonded via a sealing material 14 disposed along the outer periphery of the counter substrate 20. In the element substrate 10, liquid crystal having positive or negative dielectric anisotropy is sealed between the opposing substrates 20 inside the sealing material 14 provided in an annular shape in plan view, thereby forming a liquid crystal layer 15. For the sealing material 14, for example, an adhesive such as a thermosetting or ultraviolet curable epoxy resin is employed. Spacers (not shown) are mixed in the sealing material 14 to keep the distance between the pair of substrates constant.

  A display area E in which a plurality of pixels P are arranged is provided inside the inner edge of the sealing material 14. The display area E may include dummy pixels arranged so as to surround the plurality of pixels P in addition to the plurality of pixels P contributing to display. Although not shown in FIGS. 1 and 2, a light shielding film (black matrix: BM) for planarly dividing the plurality of pixels P in the display area E is provided on the counter substrate 20.

  A data line driving circuit 22 is provided between the sealing material 14 along one side of the element substrate 10 and the one side. Further, an inspection circuit 25 is provided between the sealing material 14 and the display area E along the other one side facing the one side. Further, a scanning line driving circuit 24 is provided between the sealing material 14 and the display area E along the other two sides that are orthogonal to the one side and face each other. A plurality of wirings 29 connecting the two scanning line driving circuits 24 are provided between the sealing material 14 and the inspection circuit 25 along the other one side facing the one side.

  A light shielding film 18 (parting portion) is provided between the sealing material 14 arranged in an annular shape on the counter substrate 20 and the display region E. The light shielding film 18 is made of, for example, a light shielding metal or metal oxide, and the inside of the light shielding film 18 is a display area E having a plurality of pixels P. Although not shown in FIG. 1, a light shielding film that divides a plurality of pixels P in a plane is also provided in the display area E.

  Wirings connected to the data line driving circuit 22 and the scanning line driving circuit 24 are connected to a plurality of external connection terminals 65 arranged along the one side. Hereinafter, the direction along the one side will be referred to as the X direction, and the direction along the other two sides orthogonal to the one side and facing each other will be described as the Y direction.

  As shown in FIG. 2, on the surface of the first base material 10a on the liquid crystal layer 15 side, a transparent pixel electrode 27 provided for each pixel P and a thin film transistor (TFT: Thin Film Transistor, which is a switching element) are provided. Hereinafter, it is referred to as “TFT 30”), signal wirings, and an alignment film 28 covering them.

  In addition, a light shielding structure is employed that prevents light from entering the semiconductor layer (active layer) in the TFT 30 to make the switching operation unstable. The element substrate 10 in the present invention includes at least the pixel electrode 27, the TFT 30, and the alignment film 28.

  On the surface of the counter substrate 20 on the liquid crystal layer 15 side, a light shielding film 18, a planarizing layer 33 formed so as to cover the light shielding film 18, a counter electrode 31 provided so as to cover the planarizing layer 33, An alignment film 32 that covers the electrode 31 is provided. The counter substrate 20 in the present invention includes at least the counter electrode 31 and the alignment film 32.

  As shown in FIG. 1, the light shielding film 18 surrounds the display area E and is provided at a position where the scanning line driving circuit 24 and the inspection circuit 25 overlap in a plan view (illustration is simplified). Thus, the light incident on the peripheral circuit including these drive circuits from the counter substrate 20 side is shielded, and the peripheral circuit is prevented from malfunctioning due to the light. Further, unnecessary stray light is shielded from entering the display area E, and high contrast in the display of the display area E is ensured.

  The planarizing layer 33 is made of an inorganic material such as silicon oxide, for example, and is provided so as to cover the light shielding film 18 with optical transparency. As a method for forming such a planarization layer 33, for example, a method of forming a film by using a plasma CVD (Chemical Vapor Deposition) method or the like can be cited.

  The counter electrode 31 is made of a transparent conductive film such as ITO (Indium Tin Oxide), for example, covers the planarization layer 33, and includes an element substrate by vertical conduction portions 26 provided at the four corners of the counter substrate 20 as shown in FIG. It is electrically connected to the wiring on the 10 side.

  The alignment film 28 covering the pixel electrode 27 and the alignment film 32 covering the counter electrode 31 are selected based on the optical design of the liquid crystal device 100. For example, an inorganic alignment film formed by depositing an inorganic material such as SiOx (silicon oxide) using a vapor deposition method and substantially vertically aligning with liquid crystal molecules having negative dielectric anisotropy can be given.

  Such a liquid crystal device 100 is a transmission type, and the transmittance of the pixel P when the voltage is not applied is normally white larger than the transmittance when the voltage is applied, or the transmittance of the pixel P when the voltage is not applied. A normally black mode optical design is employed, which is smaller than the transmittance when a voltage is applied. Polarizing elements are arranged and used according to the optical design on the light incident side and the light exit side, respectively.

  As shown in FIG. 3, the liquid crystal device 100 includes a plurality of scanning lines 3a and a plurality of data lines 6a that are insulated from each other and orthogonal to each other at least in the display region E, and a capacitor line 3b as a common potential wiring. The direction in which the scanning line 3a extends is the X direction, and the direction in which the data line 6a extends is the Y direction.

  A pixel electrode 27, a TFT 30, and a storage capacitor 16 are provided in a region divided by the scanning line 3a, the data line 6a, the capacitor line 3b, and these signal lines, and these constitute a pixel circuit of the pixel P. doing.

  The scanning line 3 a is electrically connected to the gate of the TFT 30, and the data line 6 a is electrically connected to the data line side source / drain region (source region) of the TFT 30. The pixel electrode 27 is electrically connected to the pixel electrode side source / drain region (drain region) of the TFT 30.

  The data line 6a is connected to the data line driving circuit 22 (see FIG. 1), and supplies image signals D1, D2,..., Dn supplied from the data line driving circuit 22 to the pixels P. The scanning line 3a is connected to the scanning line driving circuit 24 (see FIG. 1), and supplies the scanning signals SC1, SC2,..., SCm supplied from the scanning line driving circuit 24 to each pixel P.

  The image signals D1 to Dn supplied from the data line driving circuit 22 to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each of a plurality of adjacent data lines 6a for each group. Good. The scanning line driving circuit 24 supplies the scanning signals SC1 to SCm to the scanning line 3a at a predetermined timing.

  In the liquid crystal device 100, the TFT 30 as a switching element is turned on for a certain period by the input of the scanning signals SC1 to SCm, so that the image signals D1 to Dn supplied from the data line 6a are supplied to the pixel electrode 27 at a predetermined timing. It is the structure written in. The predetermined level of the image signals D1 to Dn written to the liquid crystal layer 15 through the pixel electrode 27 is held for a certain period between the pixel electrode 27 and the counter electrode 31 disposed to face the liquid crystal layer 15. The

  In order to prevent the retained image signals D1 to Dn from leaking, a storage capacitor 16 is connected in parallel with a liquid crystal capacitor formed between the pixel electrode 27 and the counter electrode 31. The storage capacitor 16 is provided between the pixel electrode side source / drain region of the TFT 30 and the capacitor line 3b.

<Configuration of liquid crystal device and semiconductor device>
FIG. 4 is a schematic cross-sectional view showing the structure of a liquid crystal device and a TFT as a semiconductor device. FIG. 5 is a schematic plan view of the semiconductor device portion of the liquid crystal device shown in FIG. 4 as viewed from above. Hereinafter, the structures of the liquid crystal device and the semiconductor device will be described with reference to FIGS. 4 and 5 show cross-sectional positional relationships among the constituent elements, and are expressed on an expressible scale.

  As shown in FIG. 4, the liquid crystal device 100 includes an element substrate 10 that is one of a pair of substrates, and a counter substrate 20 (not shown) that is the other substrate disposed to face the element substrate 10. Yes. As described above, the first base material 10a configuring the element substrate 10 is configured by, for example, a quartz substrate.

  As shown in FIGS. 4 and 5, on the first base material 10a, for example, a lower light-shielding film 3c containing a material such as Al (aluminum), Ti (titanium), Cr (chromium), or W (tungsten). (Gate wiring) is formed. The lower light-shielding film 3c is planarly patterned in a lattice shape and defines an opening area of each pixel P. Note that the lower light-shielding film 3c may have conductivity and function as part of the scanning line 3a.

  A first interlayer insulating layer 11a (first insulating layer) made of a silicon oxide film or the like is provided on the lower light-shielding film (scanning line) 3c. The first interlayer insulating layer 11a is provided with a convex portion 12 in which a part of a region where the TFT 30 is provided projects to the liquid crystal layer 15 side. Specifically, a surface on the first base material 10a side in the first interlayer insulating layer 11a is defined as a first surface 12a, and a surface facing the first surface 12a is defined as a second surface 12b. The top surface of the convex portion 12 is a third surface 12c. A slope between the second surface 12b and the third surface 12c in the convex portion 12 is defined as a fourth surface 12d. That is, the convex portion 12 is provided in which the distance from the first surface 12a to the third surface 12c is longer than the distance from the first surface 12a to the second surface 12b.

  A TFT 30 as a semiconductor device is formed on the first interlayer insulating layer 11a. In the TFT 30, for example, a semiconductor layer 30a made of polysilicon (high-purity polycrystalline silicon) or the like is provided across the second surface 12b, the fourth surface 12d, and the third surface 12c of the first interlayer insulating layer 11a. Yes. Further, the TFT 30 includes a gate insulating layer 11g formed on the semiconductor layer 30a, and a gate electrode 30g made of a polysilicon film or the like formed on a surface facing the fourth surface 12d on the gate insulating layer 11g. The gate electrode 30g is electrically connected to the lower light-shielding film 3c (scanning line) through the contact hole CNT1.

  The semiconductor layer 30a is formed as an N-type TFT 30 by implanting N-type impurity ions such as phosphorus (P) ions. Specifically, the semiconductor layer 30a includes, for example, a channel region 30c, a data line side source / drain region 30s, and a pixel electrode side source / drain region 30d.

  The channel region 30c is doped with P-type impurity ions such as boron (B) ions. The other regions (30s, 30d) are doped with N-type impurity ions such as phosphorus (P) ions. Thus, the TFT 30 is formed as an N-type TFT.

  In the semiconductor layer 30a, for example, a data line side source / drain region (source region) 30s is arranged at a position corresponding to the second surface 12b in the first interlayer insulating layer 11a, and a pixel electrode side at a position corresponding to the third surface 12c. A source / drain region (drain region) 30d is disposed, and a channel region 30c is disposed at a position corresponding to the fourth surface 12d.

  A second interlayer insulating layer 11b made of a silicon oxide film or the like is formed on the gate electrode 30g and the gate insulating layer 11g. On the second interlayer insulating layer 11b, a conductive film is formed using a light-shielding conductive part material such as Al (aluminum) and patterned to form a data line side source / drain via the contact hole CNT2. A relay electrode 51 and a data line 6a connected to the region 30s are formed. At the same time, a relay electrode 52 connected to the pixel electrode side source / drain region 30d through the contact hole CNT3 is formed.

  Next, a third interlayer insulating layer 11c is formed covering the data line 6a, the relay electrodes 51 and 52, and the second interlayer insulating layer 11b. The third interlayer insulating layer 11c is made of, for example, silicon oxide or nitride, and is subjected to a flattening process for flattening the surface unevenness caused by covering the region where the TFT 30 is provided. Examples of the planarization method include chemical mechanical polishing (CMP) and spin coating. Thereafter, a contact hole CNT4 penetrating the third interlayer insulating layer 11c is formed.

  On the third interlayer insulating layer 11c, a capacitor line 3b (COM potential) constituting a part of the storage capacitor 16 is formed. For example, the capacitor line 3b has a laminated structure in which an aluminum (Al) film is disposed in a lower layer and a titanium nitride (TiN) film is disposed in an upper layer.

  A capacitive insulating film 16b made of alumina, a silicon nitride film or the like is formed on the capacitive line 3b so as to cover the capacitive line 3b. Further, a stopper film 16c1 made of a silicon oxide film or the like is formed on the capacitive insulating film 16b in the vicinity of the region overlapping the contact hole CNT5 region in plan view. The stopper film 16c1 may be formed before the capacitor insulating film 16b is formed, that is, between the capacitor line 3b and the capacitor insulating film 16b.

  On the stopper film 16c1, the capacitor insulating film 16b, and the third interlayer insulating layer 11c, a light-shielding conductive material such as Al (aluminum) is filled so as to fill the contact hole CNT4 and cover the third interlayer insulating layer 11c. The conductive electrode is formed into a film and patterned to form a relay electrode 53 connected to the pixel electrode side source / drain region 30d through the contact hole CNT4, and a capacitor electrode as a pixel electrode potential layer constituting the storage capacitor 16 16c is formed. Note that the capacitor electrode 16c and the capacitor electrode 16c adjacent to each other are patterned on the stopper film 16c1 described above.

  A fourth interlayer insulating layer 11d made of a silicon oxide film or the like is formed on the capacitor electrode 16c. A contact hole CNT5 that penetrates the fourth interlayer insulating layer 11d is formed. A planarization process may be performed on the fourth interlayer insulating layer 11d in the same manner as the third interlayer insulating layer 11c.

  The contact hole CNT5 that penetrates the fourth interlayer insulating layer 11d is formed, for example, at a position that overlaps the stopper film 16c1 in plan view in the capacitive electrode 16c. A transparent conductive film such as ITO is formed on the fourth interlayer insulating layer 11d so as to fill the contact hole CNT5. Then, by patterning the transparent conductive film, the pixel electrode 27 connected to the capacitor electrode 16c through the contact hole CNT5 is formed.

  The capacitor electrode 16c is electrically connected to the pixel electrode side source / drain region 30d of the TFT 30 via the relay electrode 53, the contact hole CNT4, the relay electrode 52, and the contact hole CNT3, and is connected to the pixel electrode via the contact hole CNT5. 27 is electrically connected.

On the pixel electrode 27 and the fourth interlayer insulating layer 11d, an alignment film 28 (see FIG. 2) obtained by obliquely depositing an inorganic material such as silicon oxide (SiO ₂ ) is provided. On the alignment film 28, a liquid crystal layer 15 in which liquid crystal or the like is sealed in a space surrounded by the sealing material 14 (see FIGS. 1 and 2) is provided.

On the other hand, the counter electrode 31 is provided over the entire surface of the second base material 20a (the liquid crystal layer 15 side) (see FIG. 2). On the counter electrode 31, an alignment film 32 is formed by obliquely depositing an inorganic material such as silicon oxide (SiO ₂ ). The counter electrode 31 is made of a transparent conductive film such as an ITO film, for example, like the pixel electrode 27 described above.

  The liquid crystal layer 15 takes a predetermined alignment state by the alignment films 28 and 32 in a state where no electric field is generated between the pixel electrode 27 and the counter electrode 31. The sealing material 14 is an adhesive made of, for example, a photocurable resin or a thermosetting resin, for bonding the element substrate 10 and the counter substrate 20 around them, and a distance between the two substrates is set to a predetermined value. Spacers such as glass fiber or glass beads are mixed. Hereinafter, a method for manufacturing the liquid crystal device 100 will be described.

<Liquid Crystal Device and Semiconductor Device Manufacturing Method>
FIG. 6 is a flowchart showing a manufacturing method of the liquid crystal device in the order of steps. 7 and 8 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device among the methods for manufacturing a liquid crystal device. Hereinafter, a method for manufacturing a liquid crystal device and a method for manufacturing a semiconductor device will be described with reference to FIGS.

  First, a manufacturing method on the element substrate 10 side will be described. First, in step S11 (scanning line forming process, first insulating layer forming process), a TFT 30 as a semiconductor device is formed on a first base material 10a made of a quartz substrate or the like. Specifically, as shown in FIG. 7A, a lower light-shielding film 3c made of aluminum or the like is formed on the first base material 10a using a well-known film forming technique. Next, a first interlayer insulating layer 11a made of a silicon oxide film or the like is formed on the lower light shielding film 3c. Hereinafter, a specific method for manufacturing the TFT 30 will be described with reference to FIGS.

  In the step (projection forming step) shown in FIG. 7B, the projection 12 is formed on the first interlayer insulating layer 11a. Specifically, the convex portion 12 is formed in a region where the TFT 30 is formed by using a photolithography technique and an etching technique. More specifically, the surface on the first base material 10a side of the first interlayer insulating layer 11a is the first surface 12a, the second surface 12b facing the first surface 12a, the upper surface of the convex portion 12 is the third surface 12c, and the convex portion 12, the convex part 12 which makes the slope between the 2nd surface 12b and the 3rd surface 12c the 4th surface 12d is formed. Note that the distance from the first surface 12a to the third surface 12c is longer than the distance from the first surface 12a to the second surface 12b.

  In the step (semiconductor layer forming step) shown in FIG. 7C, the semiconductor layer 30a is formed on the first interlayer insulating layer 11a. Specifically, the semiconductor layer 30a made of polysilicon or the like is formed over the second surface 12b, the fourth surface 12d, and the third surface 12c by using a well-known film formation technique, a photography technique, and an etching technique. To do.

  In the step (ion implantation step) shown in FIG. 7D, impurity ions are implanted into the semiconductor layer 30a. Specifically, when an N-type TFT is formed, a region to be the channel region 30c is doped with P-type impurity ions such as boron (B) ions. N-type impurity ions such as phosphorus (P) ions are doped into the data line side source / drain region 30s and the pixel electrode side source / drain region 30d.

  Thereby, the data line side source / drain region (source region) 30s is arranged at a position corresponding to the second surface 12b in the first interlayer insulating layer 11a, and the pixel electrode side source / drain region (source region) at a position corresponding to the third surface 12c. Drain region) 30d is disposed, and a channel region 30c is disposed at a position corresponding to the fourth surface 12d.

  Thus, since the pixel electrode side source / drain region 30d is disposed on the uppermost surface of the convex portion 12 which is the third surface 12c, the pixel electrode side source / drain region 30d and the pixel electrode 27 are connected at a short distance. Can do.

  In the step shown in FIG. 8E (gate insulating layer forming step, gate electrode forming step), the gate electrode 30g is formed. Specifically, first, the gate insulating layer 11g is formed on the semiconductor layer 30a and the first interlayer insulating layer 11a. Next, contact holes CNT1 are formed in the gate insulating layer 11g and the first interlayer insulating layer 11a. Thereafter, the contact hole CNT1 is filled, polysilicon is formed on the gate insulating layer 11g, and the polysilicon is patterned, so that the gate electrode 30g is located at a position corresponding to at least the fourth surface 12d on the gate insulating layer 11g. Form. As a result, the gate electrode 30g is electrically connected to the lower light-shielding film 3c (scanning line) through the contact hole CNT1.

  In the step shown in FIG. 8F, a second interlayer insulating layer 11b made of a silicon oxide film or the like is formed on the gate electrode 30g and the gate insulating layer 11g.

  In the step shown in FIG. 8G, the relay electrodes 51 and 52 are formed on the second interlayer insulating layer 11b. Specifically, first, contact holes CNT2 and 3 are formed in the second interlayer insulating layer 11b and the gate insulating layer 11g by using a photolithography technique and an etching technique. Next, the contact holes CNT2 and 3 are filled, and a light-shielding conductive member such as aluminum is formed on the second interlayer insulating layer 11b, and the conductive member is patterned. Thereby, the relay electrode 51 electrically connected to the contact hole CNT2 and the relay electrode 52 electrically connected to the contact hole CNT3 are formed on the second interlayer insulating layer 11b. Thus, the TFT 30 is formed.

  Next, referring to FIG. 6, in step S12, a pixel electrode 27 is formed. Specifically, a third interlayer insulating layer 11c, a storage capacitor 16, and a fourth interlayer insulating layer 11d are formed on the TFT 30, and a pixel is formed on the fourth interlayer insulating layer 11d by using a photolithography technique and an etching technique. An electrode 27 is formed.

  In step S13, the alignment film 28 is formed. Specifically, an alignment material 28 having a columnar structure is formed by obliquely vapor-depositing an inorganic material such as silicon oxide on the fourth interlayer insulating layer 11d provided with the pixel electrode 27.

  Next, a manufacturing method on the counter substrate 20 side will be described. First, in step S21, the counter electrode 31 is formed on the second base material 20a made of a translucent material such as a quartz substrate by using a well-known film forming technique.

In step S <b> 22, the alignment film 32 is formed on the counter electrode 31. As a manufacturing method of the alignment film 32, for example, an oblique deposition method in which an inorganic material such as silicon oxide (SiO ₂ ) is obliquely deposited is used. Thus, the counter substrate 20 is completed. Next, a method for bonding the element substrate 10 and the counter substrate 20 will be described.

  In step S <b> 31, the sealing material 14 is applied on the element substrate 10. Specifically, for example, the relative positional relationship between the element substrate 10 and a dispenser (also possible with a discharge device) is changed, so that the periphery of the display area E in the element substrate 10 (so as to surround the display area E). The sealing material 14 is applied.

  In step S32, the element substrate 10 and the counter substrate 20 are bonded together. Specifically, the element substrate 10 and the counter substrate 20 are bonded to the element substrate 10 through the applied sealing material 14.

  In step S33, liquid crystal is injected into the structure from the liquid crystal injection port, and then the liquid crystal injection port is sealed with a sealing material. Thus, the liquid crystal device 100 is completed.

<Configuration of electronic equipment>
Next, a projection display device as an electronic apparatus according to the present embodiment will be described with reference to FIG. FIG. 9 is a schematic diagram showing a configuration of a projection display device including the above-described liquid crystal device.

  As shown in FIG. 9, the projection display apparatus 1000 of the present embodiment includes a polarization illumination device 1100 arranged along the system optical axis L, two dichroic mirrors 1104 and 1105 as light separation elements, and three Reflective mirrors 1106, 1107, 1108, five relay lenses 1201, 1202, 1203, 1204, 1205, three transmissive liquid crystal light valves 1210, 1220, 1230 as light modulation means, and a cross dichroic as a light combiner A prism 1206 and a projection lens 1207 are provided.

  The polarized light illumination device 1100 is generally configured by a lamp unit 1101 as a light source composed of a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 1102, and a polarization conversion element 1103.

  The dichroic mirror 1104 reflects red light (R) and transmits green light (G) and blue light (B) among the polarized light beams emitted from the polarization illumination device 1100. Another dichroic mirror 1105 reflects the green light (G) transmitted through the dichroic mirror 1104 and transmits the blue light (B).

  The red light (R) reflected by the dichroic mirror 1104 is reflected by the reflection mirror 1106 and then enters the liquid crystal light valve 1210 via the relay lens 1205. Green light (G) reflected by the dichroic mirror 1105 enters the liquid crystal light valve 1220 via the relay lens 1204. The blue light (B) transmitted through the dichroic mirror 1105 enters the liquid crystal light valve 1230 via a light guide system including three relay lenses 1201, 1202, 1203 and two reflection mirrors 1107, 1108.

  The liquid crystal light valves 1210, 1220, and 1230 are disposed to face the incident surfaces of the cross dichroic prism 1206 for each color light. The color light incident on the liquid crystal light valves 1210, 1220, and 1230 is modulated based on video information (video signal) and emitted toward the cross dichroic prism 1206.

  In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. The three color lights are synthesized by these dielectric multilayer films, and the light representing the color image is synthesized. The synthesized light is projected on the screen 1300 by the projection lens 1207 which is a projection optical system, and the image is enlarged and displayed.

  The liquid crystal light valve 1210 is the one to which the liquid crystal device 100 described above is applied. The liquid crystal device 100 is arranged with a gap between a pair of polarizing elements arranged in crossed Nicols on the incident side and the emission side of colored light. The same applies to the other liquid crystal light valves 1220 and 1230.

  According to such a projection display apparatus 1000, since the liquid crystal light valves 1210, 1220, and 1230 are used, high reliability can be obtained.

  The electronic device on which the liquid crystal device 100 is mounted includes a projection display device 1000, a head-up display, a smartphone, an EVF (Electrical View Finder), a mobile mini projector, a mobile phone, a mobile computer, a digital camera, and a digital video. It can be used for various electronic devices such as cameras, displays, in-vehicle devices, audio devices, exposure devices, and lighting devices.

  As described above in detail, according to the TFT 30, the liquid crystal device 100, the manufacturing method of the TFT 30, the manufacturing method of the liquid crystal device 100, and the electronic apparatus of the first embodiment, the following effects can be obtained.

  (1) According to the TFT 30, the liquid crystal device 100, the manufacturing method of the TFT 30, and the manufacturing method of the liquid crystal device 100 of the first embodiment, the second surface 12b, the fourth surface 12d, and the third surface of the first interlayer insulating layer 11a Since the convex portion 12 composed of 12c is formed, in particular, the semiconductor layer 30a, the gate insulating layer 11g, and the gate electrode 30g are formed along the fourth surface 12d which is the side surface of the convex portion 12, so that the gate The width of the gate electrode 30g can be shortened when viewed from the direction from the second surface 12b toward the first surface 12a (in plan view) without shortening the length. As a result, it is possible to maintain the light shielding property, reduce the light shielding region, and improve the aperture ratio. In addition, since the ions can be implanted into the semiconductor layer 30a by a known manufacturing method, the TFT 30 can be formed relatively easily.

  (2) According to the electronic device of the first embodiment, since the above-described liquid crystal device 100 is provided, an electronic device with high display quality can be provided.

(Second Embodiment)
<Liquid Crystal Device and Semiconductor Device Manufacturing Method>
10 and 11 are schematic cross-sectional views illustrating a method for manufacturing a liquid crystal device according to the second embodiment, particularly a method for manufacturing a semiconductor device (TFT). Hereinafter, a manufacturing method of the TFT will be described with reference to FIGS.

  The manufacturing method of the TFT 130 of the second embodiment is different from the first embodiment in the formation method of the lower light-shielding film 103c (scanning line) and the first interlayer insulating layer 111a, and the other methods are substantially the same. It is. Therefore, in the second embodiment, portions different from the first embodiment will be described in detail, and descriptions of other overlapping portions will be omitted as appropriate.

  In the manufacturing method of the TFT 130 as the semiconductor device according to the second embodiment, first, in the step shown in FIG. 10A (scanning line precursor film forming step), a well-known film forming technique is applied on the first base material 10a. A lower light-shielding film precursor film 103c1 (scanning line precursor film) before being used as the lower light-shielding film 103c made of aluminum or the like is formed.

  In the step shown in FIG. 10B (scanning line forming step), the convex portion 12 is formed on the lower light-shielding film precursor film 103c1. Specifically, using the photolithography technique and the etching technique, the convex portion 12 is formed in the region where the TFT 130 is formed, and the lower light shielding film 103c is formed. As in the first embodiment, the surface of the lower light-shielding film 103c on the first base material 10a side is the first surface 12a, the surface facing the first surface 12a is the second surface 12b, and the convex portion 12 The upper surface is the third surface 12c, and the slope between the second surface 12b and the third surface 12c of the convex portion 12 is the fourth surface 12d.

  In the step shown in FIG. 10C (first insulating layer forming step), a first interlayer insulating layer 111a made of a silicon oxide film or the like is formed on the lower light-shielding film 103c. The first interlayer insulating layer 111a is formed following the undulation of the convex portion 12 of the lower light-shielding film 103c, and has the first surface 12a to the fourth surface 12d similarly to the lower light-shielding film 103c.

  In the step (ion implantation step) shown in FIG. 10D, the semiconductor layer 30a is formed on the first interlayer insulating layer 111a. Specifically, the semiconductor layer 30a made of polysilicon or the like is formed over the second surface 12b, the fourth surface 12d, and the third surface 12c by using a well-known film formation technique, a photography technique, and an etching technique. To do. Next, as in the first embodiment, impurity ions are implanted into the semiconductor layer 30a.

  Thus, the data line side source / drain region (source region) 30s is disposed at a position corresponding to the second surface 12b in the first interlayer insulating layer 111a, and the pixel electrode side source / drain region (source region) is disposed at a position corresponding to the third surface 12c. Drain region) 30d is disposed, and a channel region 30c is disposed at a position corresponding to the fourth surface 12d.

  In the step shown in FIG. 11E (gate insulating layer forming step, gate electrode forming step), the gate insulating layer 11g and the gate electrode 30g are formed. The manufacturing method is the same as in the first embodiment. In the step shown in FIG. 11F, the relay electrodes 51 and 52 are formed on the second interlayer insulating layer 11b. Thus, the TFT 130 is formed.

  As described above in detail, according to the TFT 130, the liquid crystal device 100, the manufacturing method of the TFT 130, and the manufacturing method of the liquid crystal device 100 of the second embodiment, in addition to the effect (1) described above, the following effects can be obtained. It is done.

  (3) According to the TFT 130, the liquid crystal device 100, the manufacturing method of the TFT 130, and the manufacturing method of the liquid crystal device 100 of the second embodiment, the convex portion 12 is formed on the lower light-shielding film 103c, so the convex portion 12 and the semiconductor layer 30a. The gate electrode 30g and the lower light-shielding film 103c (back gate) can function as a double gate electrode. Thereby, the ON / OFF characteristic of the TFT 130 can be improved.

(Third embodiment)
<Liquid Crystal Device and Semiconductor Device Manufacturing Method>
12 and 13 are schematic cross-sectional views illustrating a method for manufacturing a liquid crystal device according to the third embodiment, particularly a method for manufacturing a semiconductor device (TFT). Hereinafter, a manufacturing method of the TFT will be described with reference to FIGS.

  The manufacturing method of the TFT 230 of the third embodiment is different from the above-described second embodiment in the formation method of the lower light-shielding film 203c (scanning line), and the other methods are generally the same. For this reason, in 3rd Embodiment, a different part from 2nd Embodiment is demonstrated in detail, and description is abbreviate | omitted suitably about another overlapping part.

  In the manufacturing method of the TFT 230 as the semiconductor device of the third embodiment, first, in the step shown in FIG. 12A, the convex portion 12 is formed on the first base material 10a or the base layer 11z on the first base material 10a. To do. When forming the convex part 12 in the 1st base material 10a, it forms by giving grinding, a grinding | polishing process, etc. to the 1st base material 10a, for example. When forming the convex part 12 in the base layer 11z, it forms using the photolithographic technique and the etching technique, for example.

  As with the other protrusions 12, the bottom surface of the first base material 10a or the base layer 11z is the first surface 12a (fifth surface), and the surface facing the first surface 12a is the second surface 12b (sixth surface). Surface, the ninth surface), the upper surface of the convex portion 12 is the third surface 12c (seventh surface, tenth surface), and the slope between the second surface 12b and the third surface 12c in the convex portion 12 is the fourth surface. Let it be surface 12d (8th surface, 11th surface).

  In the step shown in FIG. 12B, the lower light-shielding film 203 c (scanning line) is formed on the first base material 10 a having the convex portions 12 or on the base layer 11 z having the convex portions 12. The lower light-shielding film 203c is formed following the undulations of the convex portions 12 of the first base material 10a or the base layer 11z.

  In the step shown in FIG. 12C, a first interlayer insulating layer 111a made of a silicon oxide film or the like is formed on the lower light shielding film 203c. The first interlayer insulating layer 111a is formed following the undulation of the convex portion 12 of the lower light-shielding film 103c, and has the first surface 12a to the fourth surface 12d similarly to the lower light-shielding film 103c.

  In the step shown in FIG. 12D, the semiconductor layer 30a is formed on the first interlayer insulating layer 111a. Specifically, this is the same as in the second embodiment. Next, impurity ions are implanted into the semiconductor layer 30a.

  Thus, the data line side source / drain region (source region) 30s is disposed at a position corresponding to the second surface 12b in the first interlayer insulating layer 111a, and the pixel electrode side source / drain region (source region) is disposed at a position corresponding to the third surface 12c. Drain region) 30d is disposed, and a channel region 30c is disposed at a position corresponding to the fourth surface 12d.

  In the step shown in FIG. 13E, the gate insulating layer 11g and the gate electrode 30g are formed. The manufacturing method is the same as in the first embodiment. In the step shown in FIG. 11F, the relay electrodes 51 and 52 are formed on the second interlayer insulating layer 11b. Thus, the TFT 230 is formed.

  As described above in detail, according to the TFT 230, the liquid crystal device 100, the manufacturing method of the TFT 230, and the manufacturing method of the liquid crystal device 100 of the third embodiment, in addition to the effects (1) and (3) described above, The effect shown is obtained.

  (4) According to the TFT 230, the liquid crystal device 100, the manufacturing method of the TFT 230, and the manufacturing method of the liquid crystal device 100 according to the third embodiment, the convex portion 12 is formed on the first base material 10a or the base layer 11z. As in the embodiment, the material of the lower light-shielding film 103c, such as aluminum, titanium, chromium, and tungsten, can be reduced. Thereby, the convex part 12 can be formed more easily than 2nd Embodiment.

  The aspect of the present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification. It is included in the range. Moreover, it can also implement with the following forms.

(Modification 1)
As in the second embodiment described above, the method for forming the convex portion 12 on the lower light-shielding film 103c is not limited to using a photolithography technique and an etching technique. For example, the convex portion is formed using a mask. It may be laminated (film formation). Further, a transfer method may be used.

(Modification 2)
As described above, the semiconductor layer 30a is not limited to the provision of the data line side source / drain region 30s and the pixel electrode side source / drain region 30d. May be provided.

(Modification 3)
As described above, the electro-optical device is not limited to being applied to the liquid crystal device 100, and may be applied to, for example, an organic EL device, a plasma display, electronic paper, or the like.

  3a ... scanning line, 3b ... capacitance line, 3c, 103c, 203c ... lower light shielding film (gate wiring), CNT1, 2, 3, 4, 5 ... contact hole, 6a ... data line, 10 ... element substrate, 10a ... 1st base material, 11a, 111a ... 1st interlayer insulation layer (1st insulation layer), 11b ... 2nd interlayer insulation layer, 11c ... 3rd interlayer insulation layer, 11d ... 4th interlayer insulation layer, 11g ... Gate insulation layer 11z: Underlayer, 12: Projection, 12a: First surface, 12b: Second surface, 12c: Third surface, 12d: Fourth surface, 14: Sealing material, 15: Liquid crystal layer as an electro-optic layer, DESCRIPTION OF SYMBOLS 16 ... Accumulation capacity | capacitance, 16b ... Capacitance insulating film, 16c ... Capacitance electrode, 18 ... Light shielding film, 20 ... Opposite substrate, 20a ... 2nd base material, 22 ... Data line drive circuit, 24 ... Scanning line drive circuit, 25 ... Inspection Circuit 26 ... Vertical conduction part 27 ... Pixel electrode 28, 32 ... Directional film, 29 ... wiring, 30, 130, 230 ... TFT, 30a ... semiconductor layer, 30c ... channel region, 30d ... pixel electrode side source / drain region, 30g ... gate electrode, 30s ... data line side source / drain region, 31 ... Counter electrode 33 ... Flattening layer 51, 52, 53 ... Relay electrode 65 ... External connection terminal 100 ... Liquid crystal device 1000 ... Projection type display device 1100 ... Polarized illumination device 1101 ... Lamp unit 1102 ... Integrator lens 1103. Polarization conversion element 1104 1105 Dichroic mirror 1106 1107 1108 Reflection mirror 1201 1202 1203 1204 1205 Relay lens 1206 Cross dichroic prism 1207 Projection lens 1210 , 1220, 1230 ... Liquid crystal Tobarubu, 1300 ... screen.

Claims (5)

A semiconductor layer including one of a source region and a drain region, the other of the source region and the drain region, and a channel region;
A gate insulating layer covering the channel region;
A gate electrode disposed to face the channel region via the gate insulating layer;
A first electrode that is one of a source electrode and a drain electrode;
A second electrode which is the other of the source electrode and the drain electrode;
Including
The semiconductor layer is disposed to cover the first insulating layer;
The first insulating layer is disposed to cover a gate wiring electrically connected to the gate electrode;
The gate wiring includes a first surface, second and third surfaces facing the first surface, and a fourth surface disposed between the second surface and the third surface. A distance between the first surface and the second surface is smaller than a distance between the first surface and the third surface;
One of the source region and the drain region is disposed so that at least a part thereof faces the second surface through the first insulating layer,
The other of the source region and the drain region is disposed so that at least a part thereof faces the third surface through the first insulating layer,
The channel region is disposed so that at least a part thereof faces the fourth surface through the first insulating layer,
The semiconductor device, wherein the first electrode and the second electrode are electrically connected to the semiconductor layer. The semiconductor device according to claim 1,
The first electrode is disposed inside a first contact hole disposed so as to penetrate the semiconductor layer and the second insulating layer covering the gate electrode, and is disposed so as to penetrate the second insulating layer. 2. A semiconductor device, wherein the second electrode is disposed inside a two contact hole. A semiconductor device according to claim 1 or 2 ,
A pixel electrode electrically connected to the semiconductor device;
An element substrate including the semiconductor device and the pixel electrode;
A counter substrate disposed opposite to the element substrate;
An electro-optic layer sandwiched between the element substrate and the counter substrate;
An electro-optical device comprising: A gate wiring precursor film forming step of forming a gate wiring precursor film for forming a gate wiring on the substrate;
Etching the gate wiring precursor film, a second surface facing the first surface on the substrate side, a third surface having a longer distance from the first surface than the second surface; A gate wiring forming step of forming a gate wiring having a second surface disposed between the second surface and the third surface;
A first insulating layer forming step of forming a first insulating layer on the substrate so as to cover the gate wiring;
A semiconductor layer forming step of forming a semiconductor layer on the first insulating layer so as to overlap the gate wiring in plan view and to cover the second surface, the third surface, and the fourth surface of the gate wiring; ,
An ion implantation step of implanting impurity ions into the semiconductor layer to form a channel region, a source region, and a drain region;
A gate insulating layer forming step of forming a gate insulating layer on the semiconductor layer;
Forming a gate electrode on the gate insulating layer so as to face the fourth surface; and
A method for manufacturing a semiconductor device, comprising: An electronic apparatus comprising the electro-optical device according to claim 3 .

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