JP2013073032A - Liquid crystal device, method of manufacturing liquid crystal device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display high-quality images on a liquid crystal device.SOLUTION: A liquid crystal device 100 includes: a liquid crystal layer that is held between an element substrate and an opposing substrate; a TFT 30 that is provided on the element substrate; and a capacitive element 16 that has a capacitive electrode 16a, a dielectric layer 16b, and pixel electrodes 16c that are electrically connected with the TFT 30. The capacitive electrode 16a has a depression 55 in an area between the pixel electrodes 16c that are planarly adjacent to each other.

Description

  The present invention relates to a liquid crystal device, a method for manufacturing a liquid crystal device, and an electronic apparatus.

  As the liquid crystal device, an active drive type liquid crystal device in which a switching element such as a thin film transistor is provided for each pixel is known. An active drive type liquid crystal device has a liquid crystal layer between a pair of electrodes, and an image signal written for each pixel is temporarily held in an electric capacity composed of the pair of electrodes and the liquid crystal layer.

  In addition to this, in order to electrically hold an image signal for each pixel for a predetermined period, for example, as described in Patent Document 1, a dielectric is provided between a capacitor electrode and a pixel electrode arranged in a solid shape. A technique is disclosed in which a capacitive element with layers sandwiched is provided.

  Further, as disclosed in Patent Document 2, a technique is disclosed in which a capacitor element having a dielectric layer sandwiched between a capacitor electrode having a slit between pixel electrodes in a plane and a pixel electrode is disclosed. .

JP 2010-176119 A JP 2002-221732 A

  However, in the capacitor element described in Patent Document 1, since the capacitor electrode is exposed between the pixel electrodes when seen in a plan view, electric field leakage occurs between the pixel electrodes. As a result, the alignment of the liquid crystal is disturbed, and light leakage and azimuth angle deviation occur. As a result, there is a problem that the brightness to be displayed is lowered.

  Further, the capacitor element described in Patent Document 2 requires a step of forming a slit in the capacitor electrode, or the resistance of the capacitor electrode increases because the slit is provided. Further, since the capacitor electrodes are connected at the outer periphery of the display region, the resistance changes between the outer periphery and the center of the display region, and a potential gradient is generated. Accordingly, there is a problem that display unevenness occurs.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 A liquid crystal device according to this application example includes a pair of substrates, a liquid crystal layer sandwiched between the pair of substrates, a transistor provided on one of the pair of substrates, the transistor, An electrically connected capacitor element having a pixel electrode, a capacitor electrode, and a dielectric layer sandwiched between the pixel electrode and the capacitor electrode, wherein the capacitor electrode is adjacent in a plane. It is characterized by having a depression in the region between the matching pixel electrodes.

  According to this configuration, since the depression is provided on the surface of the capacitive electrode corresponding to the pixel electrodes adjacent in plan, the distance from the pixel electrode provided in the upper layer to the bottom of the depression of the capacitive electrode is Compared to the case where no depression is provided, the length can be increased. Therefore, the electric field generated between the pixel electrode and the capacitor electrode can be weakened, and the electric field can be prevented from leaking from between the pixel electrodes to the liquid crystal layer. As a result, it is possible to prevent the alignment of the liquid crystal layer from being affected by the electric field.

  Application Example 2 In the liquid crystal device according to the application example described above, it is preferable that the liquid crystal device includes an insulating film that planarly overlaps with an outer edge of the adjacent pixel electrodes and fills between the adjacent pixel electrodes and the recesses.

  According to this configuration, since the outer edge of the pixel electrode and the capacitor electrode are arranged with the insulating film interposed therebetween, the distance from the outer edge of the pixel electrode where the pixel electrodes are separated to the capacitor electrode is determined by the thickness of the insulating film. It is possible to keep away. Therefore, the electric field can be prevented from leaking from between the pixel electrodes.

  Application Example 3 In the liquid crystal device according to the application example described above, it is preferable that the depression is arranged along at least one of the data line and the scanning line in a plan view.

  According to this configuration, since the depression is arranged in the non-opening region between the pixel electrodes provided with the data line and the scanning line, the transmitted light passing through the opening region is given to the liquid crystal layer without being affected by the depression. The influence of the electric field can be suppressed.

  Application Example 4 In the liquid crystal device according to the application example described above, it is preferable that the capacitor electrode has a portion without the depression in a region between the adjacent pixel electrodes in plan view.

  According to this configuration, since there is a non-depressed portion on the surface of the capacitor electrode in a region that overlaps between the pixel electrodes, the length is shortened compared to the length of the capacitor electrode film in the depressed portion. Thus, the resistance of the capacitor electrode can be prevented from significantly increasing.

  Application Example 5 In the liquid crystal device according to the application example described above, it is preferable that a width of the bottom of the depression is wider than a gap between the pixel electrodes.

  According to this configuration, since the width of the bottom of the depression is wider than the gap between the pixel electrodes (the width between the end portions of the adjacent pixel electrodes), the distance from the end portion of the pixel electrode to the capacitor electrode is increased. Can be separated. Therefore, it is possible to weaken the electric field generated between the pixel electrode and the capacitor electrode, and to prevent the electric field from leaking between the pixel electrodes.

  Application Example 6 In the liquid crystal device according to the application example described above, it is preferable that the gap between the pixel electrodes has a length equal to or less than a length obtained by adding the thickness of the insulating film to the thickness of the pixel electrode.

  According to this configuration, by setting the gap between the pixel electrodes as described above, it is possible to weaken the electric field generated between the pixel electrode and the capacitor electrode, and to suppress leakage of the electric field from between the pixel electrodes. Can do.

  Application Example 7 A method for manufacturing a liquid crystal device according to this application example includes a pair of substrates, a liquid crystal layer sandwiched between the pair of substrates, a transistor provided on one of the pair of substrates, A method of manufacturing a liquid crystal device, comprising: a capacitor element having a pixel electrode, a capacitor electrode, and a dielectric layer sandwiched between the pixel electrode and the capacitor electrode, connected to the transistor, A recess forming step of forming a recess in a surface of the capacitor electrode in a region overlapping with the region between the pixel electrodes in a plane; an insulating film forming step of forming an insulating film so as to fill at least the recess; and the insulating film And a dielectric layer forming step of forming the dielectric layer so as to cover the capacitor electrode, and a pixel electrode forming step of forming the pixel electrode so as to cover the dielectric layer.

  According to this method, a depression is formed on the surface of the capacitor electrode between two adjacent pixel electrodes in a plane, and the insulating film is formed so as to fill at least the depression. Therefore, the bottom of the depression is formed from the pixel electrode formed on the upper layer. The distance up to can be made longer than in the case where no depression is provided. Therefore, the electric field generated between the pixel electrode and the capacitor electrode can be weakened, and the electric field can be prevented from leaking from between the pixel electrodes to the liquid crystal layer. As a result, it is possible to prevent the alignment of the liquid crystal layer from being affected by the electric field.

  Application Example 8 In the method of manufacturing a liquid crystal device according to the application example, in the insulating film forming step, an insulating film precursor to be the insulating film is formed so as to cover the capacitor electrode, and then an etch back process is performed. Preferably, the insulating film is formed in the at least the recess by any one of a method, a CMP process, and an etching process.

  According to this method, since the insulating film is formed by any one of the methods described above, it is possible to form an insulating film having a flat upper surface even in a portion where a recess is formed.

  Application Example 9 An electronic apparatus according to this application example includes the liquid crystal device described above.

  According to this configuration, since the liquid crystal device described above is provided, it is possible to provide an electronic device capable of suppressing the alignment of the liquid crystal layer from being affected by an electric field and preventing the display quality from being deteriorated. can do.

1 is a schematic plan view illustrating a configuration of a liquid crystal device according to a first embodiment. FIG. 2 is a schematic cross-sectional view taken along the line H-H ′ of the liquid crystal device illustrated in FIG. 1. FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device. FIG. 3 is a schematic plan view illustrating a configuration of a pixel in a liquid crystal device. FIG. 3 is a schematic plan view illustrating a configuration of a part of a pixel. FIG. 3 is a schematic plan view illustrating a configuration of a part of a pixel. FIG. 7A is a schematic cross-sectional view taken along line A-A ′ of the pixel shown in FIGS. 4 to 6, and FIG. 7B is an enlarged cross-sectional view taken along line B-B ′ of the pixel shown in FIG. 6. 5 is a flowchart showing a method for manufacturing a liquid crystal device in the order of steps. FIG. 6 is a schematic cross-sectional view showing a part of a method for manufacturing a liquid crystal device. FIG. 6 is a schematic cross-sectional view showing a part of a method for manufacturing a liquid crystal device. Schematic which shows the structure of the projection type display apparatus (projector) as an electronic device provided with the liquid crystal device. The schematic plan view which shows the structure of the liquid crystal device of 2nd Embodiment. FIG. 4 is an enlarged cross-sectional view illustrating a structure of a capacitive element between pixels P. FIG. 4 is an enlarged cross-sectional view illustrating a structure of a capacitive element between pixels P.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. Note that the drawings to be used are appropriately enlarged or reduced so that the part to be described can be recognized.

  In the following embodiments, for example, when “on the substrate” is described, the substrate is disposed so as to be in contact with the substrate, or is disposed on the substrate via another component, or the substrate. It is assumed that a part is arranged so as to be in contact with each other and a part is arranged via another component.

  In the present embodiment, an active matrix liquid crystal device including a thin film transistor (TFT) as a pixel switching element will be described as an example. This liquid crystal device can be suitably used as, for example, a light modulation element (liquid crystal light valve) of a projection display device (liquid crystal projector) described later.

(First embodiment)
<Configuration of liquid crystal device>
FIG. 1 is a schematic plan view showing the configuration of the liquid crystal device. 2 is a schematic cross-sectional view taken along the line HH ′ of the liquid crystal device shown in FIG. FIG. 3 is an equivalent circuit diagram showing an electrical configuration of the liquid crystal device. Hereinafter, the structure of the liquid crystal device will be described with reference to FIGS.

  As shown in FIGS. 1 and 2, the liquid crystal device 100 according to the present embodiment includes an element substrate 10 and a counter substrate 20 that are disposed to face each other, and a liquid crystal layer 15 that is sandwiched between the pair of substrates. As the first substrate 11 constituting the element substrate 10 and the second substrate 12 constituting the counter substrate 20, for example, a transparent substrate such as a glass substrate or a silicon substrate is used.

  The element substrate 10 is slightly larger than the counter substrate 20, and both substrates are bonded via a seal material 14 arranged in a frame shape, and liquid crystal having positive or negative dielectric anisotropy is sealed in the gap. A liquid crystal layer 15 is formed. For example, an adhesive such as a thermosetting or ultraviolet curable epoxy resin is employed as the sealing material 14. A gap material for keeping the distance between the pair of substrates constant is mixed in the seal material 14.

  A light shielding layer 18 is similarly provided in a frame shape inside the sealing material 14 arranged in a frame shape on the counter substrate 20 side. The light shielding layer 18 is made of, for example, a light shielding metal or metal oxide, and the inside of the light shielding layer 18 is a display region E having a plurality of pixels P. Although not shown in FIG. 1, the display area E is also provided with a light-shielding portion that divides a plurality of pixels P in a plane.

  A data line driving circuit 22 is provided between one side of the first substrate 11 and the sealing material 14 along the one side. Further, an inspection circuit 25 is provided inside the sealing material 14 along the other one side facing the one side. Further, a scanning line driving circuit 24 is provided inside the sealing material 14 along the other two sides orthogonal to the one side and facing each other. A plurality of wirings (not shown) that connect the two scanning line driving circuits 24 are provided inside the sealing material 14 on the other side facing the one side.

  Wirings connected to the data line driving circuit 22 and the scanning line driving circuit 24 are connected to a plurality of external connection terminals 61 arranged along the one side. Hereinafter, the direction along the one side will be referred to as the X direction, and the direction along the other two sides orthogonal to the one side and facing each other will be described as the Y direction. The arrangement of the inspection circuit 25 is not limited to this, and the inspection circuit 25 may be provided at a position along the inner side of the seal material 14 between the data line driving circuit 22 and the display area E.

  As shown in FIG. 2, on the surface of the first substrate 11 on the liquid crystal layer 15 side, a light-transmissive pixel electrode 16c provided for each pixel P and a thin film transistor 30 (hereinafter referred to as “TFT 30”) as a switching element. ), Signal wirings, and an alignment film 28 covering them. In addition, a light shielding structure is employed that prevents light from entering the semiconductor layer in the TFT 30 to make the switching operation unstable.

  On the surface of the second substrate 12 on the liquid crystal layer 15 side, a light shielding layer 18, an interlayer insulating layer (not shown) formed to cover the light shielding layer 18, and a common electrode provided to cover the interlayer insulating layer 31 and an alignment film 32 covering the common electrode 31 are provided.

  As shown in FIG. 1, the light shielding layer 18 is provided in a frame shape at a position overlapping the scanning line driving circuit 24 and the inspection circuit 25 in plan view. Thus, the light incident from the counter substrate 20 side is shielded, and the malfunction of the peripheral circuits including these drive circuits due to the light is prevented. Further, unnecessary stray light is shielded from entering the display area E, and high contrast in the display of the display area E is ensured.

  The interlayer insulating layer is made of an inorganic material such as silicon oxide, for example, and is provided so as to cover the light shielding layer 18 with light transmittance. As a method of forming such an interlayer insulating layer, for example, a method of forming a film using a plasma CVD (Chemical Vapor Deposition) method or the like can be given.

  The common electrode 31 is made of, for example, a transparent conductive film such as ITO (Indium Tin Oxide), covers the interlayer insulating layer, and includes the element substrate 10 by the vertical conduction portions 26 provided at the four corners of the counter substrate 20 as shown in FIG. It is electrically connected to the side wiring.

  The alignment film 28 covering the pixel electrode 16 c and the alignment film 32 covering the common electrode 31 are selected based on the optical design of the liquid crystal device 100. For example, an organic material such as polyimide is formed, and the surface thereof is rubbed so that liquid crystal molecules are subjected to a substantially horizontal alignment treatment, or an inorganic material such as SiOx (silicon oxide) is vapor-phase grown. And a film formed by a method and aligned substantially perpendicularly to liquid crystal molecules.

  As shown in FIG. 3, the liquid crystal device 100 includes a plurality of scanning lines 3 a and a plurality of data lines 6 a that are insulated from each other and orthogonal to each other at least in the display region E, and capacitance lines 3 b. The direction in which the scanning line 3a extends is the X direction, and the direction in which the data line 6a extends is the Y direction.

  A pixel electrode 16c, a TFT 30, and a capacitor element 16 are provided in a region divided by the scanning line 3a, the data line 6a, the capacitor line 3b, and these signal lines, and these constitute a pixel circuit of the pixel P. doing.

  The scanning line 3a is electrically connected to the gate of the TFT 30, and the data line 6a is electrically connected to the data line side source / drain region of the TFT 30. The pixel electrode 16 c is electrically connected to the pixel electrode side source / drain region of the TFT 30.

  The data line 6a is connected to the data line driving circuit 22 (see FIG. 1), and supplies image signals D1, D2,..., Dn supplied from the data line driving circuit 22 to the pixels P. The scanning line 3a is connected to the scanning line driving circuit 24 (see FIG. 1), and supplies the scanning signals SC1, SC2,..., SCm supplied from the scanning line driving circuit 24 to each pixel P.

  The image signals D1 to Dn supplied from the data line driving circuit 22 to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each of a plurality of adjacent data lines 6a for each group. Good. The scanning line driving circuit 24 supplies the scanning signals SC1 to SCm to the scanning line 3a in a pulse-sequential manner at a predetermined timing.

  In the liquid crystal device 100, the TFT 30 as a switching element is turned on for a certain period by the input of the scanning signals SC1 to SCm, so that the image signals D1 to Dn supplied from the data line 6a are supplied to the pixel electrode 16c at a predetermined timing. It is the structure written in. The image signals D1 to Dn of a predetermined level written in the liquid crystal layer 15 through the pixel electrode 16c are held for a certain period between the pixel electrode 16c and the common electrode 31 arranged to face each other through the liquid crystal layer 15. The

  In order to prevent the held image signals D1 to Dn from leaking, the capacitive element 16 is connected in parallel with the liquid crystal capacitance formed between the pixel electrode 16c and the common electrode 31. The capacitive element 16 is provided between the pixel electrode side source / drain region of the TFT 30 and the capacitive line 3b. The capacitive element 16 has a dielectric layer between the capacitive electrode made of a transparent conductive film and the pixel electrode 16c.

  Such a liquid crystal device 100 is, for example, a transmissive type, and adopts an optical design of a normally white mode in which the pixel P is brightly displayed when not driven and a normally black mode in which the pixel P is darkly displayed when not driven. Polarizing elements are arranged and used according to the optical design on the light incident side and the light exit side, respectively.

  FIG. 4 is a schematic plan view showing a configuration of a pixel in the liquid crystal device. 5 and 6 are schematic plan views showing the configuration of a part of the pixel. FIG. 7A is a schematic cross-sectional view taken along the line A-A ′ of the pixel shown in FIGS. 4 to 6. FIG. 7B is an enlarged sectional view taken along line B-B ′ of the pixel shown in FIG. 6. Hereinafter, the planar structure and cross-sectional structure of the pixel will be described with reference to FIGS.

  FIG. 5 is a schematic plan view showing layers from the data line 6a to the capacitor electrode 16a in the pixel P. FIG. 6 is a schematic plan view showing a layer of the pixel electrode 16c.

  As shown in FIG. 4, the pixel P in the liquid crystal device 100 has, for example, a substantially rectangular opening area in a plan view. The opening area is surrounded by a light-shielding non-opening area extending in the X direction and the Y direction and provided in a lattice shape.

  A scanning line 3a is provided in a non-opening region extending in the X direction. The scanning line 3a uses a light-shielding conductive member, and at least a part of the non-opening region is configured by the scanning line 3a. Examples of the light-shielding conductive material include W (tungsten), Ti (titanium), TiN (titanium nitride), and the like.

  Similarly, a data line 6a is provided in the non-opening region extending in the Y direction. The data line 6a also uses a light-shielding conductive member, and at least a part of the non-opening region is constituted by these.

  The non-opening region is not only constituted by the signal lines provided on the element substrate 10 side, but also constituted by a light shielding layer 18 (see FIG. 1) patterned in a lattice shape on the counter substrate 20 side. Can do.

  The TFT 30 shown in FIG. 3 is provided near the intersection of the non-opening region (intersection of the scanning line 3a and the data line 6a). By providing the TFT 30 in the vicinity of the intersection of the non-opening region having the light shielding property, the optical malfunction of the TFT 30 is prevented and the aperture ratio in the opening region is secured.

  Specifically, as shown in FIG. 4, the TFT 30 includes a semiconductor layer 30a having a data line side source / drain region 30s, a pixel electrode side source / drain region 30d, and a channel region 30c. The semiconductor layer 30a is disposed along the scanning line 3a through the intersection.

  The data line side source / drain region 30s is electrically connected to the data line 6a through a contact hole CNT41 provided in a portion protruding in the X direction. The pixel electrode side source / drain region 30d is electrically connected to the relay layer 51 through a contact hole CNT42 provided in a portion protruding in the X direction.

  Further, the TFT 30 is provided with a gate electrode 30g along the data line 6a at the intersection. In the gate electrode 30g, the portion extending in the Y direction overlaps the channel region 30c in a plane. The gate electrode 30g is electrically connected to the scanning line 3a through a contact hole CNT43 provided between a part extending in the Y direction and the scanning line 3a (not shown).

  Since the scanning line 3a is disposed on the lower layer side than the semiconductor layer 30a, the scanning line 3a is formed wider than the semiconductor layer 30a of the TFT 30, so that the channel region 30c of the TFT 30 with respect to light from a liquid crystal projector or the like. Can be shielded almost or completely. As a result, when the liquid crystal device 100 is operated, the light leakage current in the TFT 30 is reduced, the contrast ratio can be improved, and high-quality image display is possible.

  The data line 6a and the scanning line 3a extend in the Y direction and the X direction, respectively. Each pixel P is divided by the data line 6a and the scanning line 3a.

  The pixel electrode 16c is formed in an island shape for each pixel P, and is provided so that the scanning line 3a or the data line 6a and the outer edge overlap in a plane. Each pixel P is divided into a matrix by the data lines 6a and the scanning lines 3a, and the end portions of the respective pixels P are formed so as to partially overlap the data lines 6a and the scanning lines 3a.

  As shown in FIGS. 5 and 6, the capacitive element 16 is formed in a region where the capacitive electrode 16a and the pixel electrode 16c overlap each other. The capacitive electrode 16a is made of, for example, a transparent conductive material such as ITO, and constitutes a pair of capacitive electrodes in the capacitive element 16 together with the pixel electrode 16c. The capacitive electrode 16a is disposed so as to overlap substantially the entire display area E.

  The capacitor electrode 16 a is formed on the lower layer side than the pixel electrode 16 c and has an opening 52 for each pixel P. A contact hole for electrically connecting the pixel electrode 16c and the pixel electrode side source / drain region 30d (see FIG. 7) is formed inside the opening 52.

  Next, the structure of the pixel P will be described in more detail with reference to FIG. As shown in FIG. 7, the scanning line 3 a is provided on the first substrate 11. The scanning line 3a has a light shielding property, for example, at least one of metals such as Al (aluminum), Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). It is possible to use a single metal containing one metal, an alloy, a metal silicide, a polysilicide, a nitride, or a laminate of these.

  On the scanning line 3a, a base insulating layer 11a made of, for example, silicon oxide is provided so as to cover the first substrate 11 and the scanning line 3a. Further, an island-shaped semiconductor layer 30a is provided on the base insulating layer 11a.

  The semiconductor layer 30a is made of, for example, a polycrystalline silicon film and is implanted with impurity ions to have a data line side source / drain region 30s, a channel region 30c, and a pixel electrode side source / drain region 30d.

  A first interlayer insulating layer (gate insulating layer) 11b is formed on the semiconductor layer 30a so as to cover the semiconductor layer 30a and the base insulating layer 11a. Further, a gate electrode 30g is provided at a position facing the channel region 30c with the first interlayer insulating layer 11b interposed therebetween.

  A second interlayer insulating layer 11c is provided on the gate electrode 30g so as to cover the gate electrode 30g and the first interlayer insulating layer 11b. Further, two contact holes CNT41 and CNT42 penetrating the first interlayer insulating layer 11b and the second interlayer insulating layer 11c are provided at positions that overlap the end portion of the semiconductor layer 30a in plan view.

  Specifically, a conductive film is formed by using a light-shielding conductive part material such as Al (aluminum) so as to fill the contact hole CNT41 and the contact hole CNT42 and cover the second interlayer insulating layer 11c, and patterning this. Thus, the contact hole CNT41, the contact hole CNT42, and the relay layer 51 connected to the pixel electrode side source / drain region 30d through the contact hole CNT42 are formed.

  The relay layer 51 shields the TFT 30 together with the data line 6a. Furthermore, the relay layer 51 electrically connects a part between the TFT 30 and the pixel electrode 16c.

  On the relay layer 51, a third interlayer insulating layer 11d is provided so as to cover the relay layer 51 and the second interlayer insulating layer 11c. In the third interlayer insulating layer 11d, a contact hole CNT43 is provided so as to overlap a part of the contact hole CNT41 in a plan view, and further, a contact hole CNT44 is provided so as to overlap a part of the relay layer 51.

  Specifically, a conductive film is formed using a light-shielding conductive part material such as Al (aluminum) so as to fill the contact holes CNT43 and CNT44 and cover the third interlayer insulating layer 11d, and patterning the conductive film. As a result, the data line 6a and the contact holes CNT43 and CNT44 are formed.

  A fourth interlayer insulating layer 11e is provided on the data line 6a so as to cover the data line 6a and the third interlayer insulating layer 11d. The fourth interlayer insulating layer 11e is made of, for example, silicon oxide or nitride, and is subjected to a flattening process for flattening surface irregularities caused by covering the TFT 30 and the like.

  Examples of the planarization method include chemical mechanical polishing (CMP) and spin coating. The fourth interlayer insulating layer 11e is provided with a contact hole CNT45 so as to overlap a part of the contact hole CNT44 in plan view. In addition, a depression 55 is provided on the surface of a part of the fourth interlayer insulating layer 11e (part of the non-opening region).

  As shown in FIG. 5, the recess 55 is formed in a substantially cross shape between the pixels P in plan view. In other words, a plurality of substantially cross-shaped depressions 55 are formed so as to surround the pixel P. Details of the depression 55 will be described later. On the fourth interlayer insulating layer 11e, a capacitive electrode 16a constituting the capacitive element 16 is provided.

  Specifically, a contact hole CNT45 and a capacitor electrode 16a are formed by forming a transparent conductive film such as ITO so as to fill the contact hole CNT45 and cover the fourth interlayer insulating layer 11e and patterning the film. .

  A fifth interlayer insulating layer 11f is formed on the capacitor electrode 16a so as to cover the capacitor electrode 16a and the fourth interlayer insulating layer 11e, and is patterned to form a fifth interlayer insulating layer 11f in the display region E. Remove. On the fifth interlayer insulating layer 11f, a dielectric layer 16b constituting the capacitive element 70 is provided so as to cover the fifth interlayer insulating layer 11f and the exposed capacitor electrode 16a.

  The dielectric layer 16b is made of, for example, alumina whose dielectric constant is relatively higher than that of other dielectric layers. In the display area E, the dielectric layer 16b constitutes the capacitive element 16 together with the capacitive electrode 16a and the pixel electrode 16c. Since alumina has a relatively high dielectric constant compared to other dielectric materials, it is possible to increase the settable capacitance value when the size of the capacitive element 16 is constant. In addition, in order to raise the capacitance value of the capacitive element 16, it is more preferable that the film thickness of the dielectric layer 16b is thin.

  In the fifth interlayer insulating layer 11f and the dielectric layer 16b, a contact hole CNT46 is provided in a region overlapping with a part of the contact hole CNT45 in a plan view. Further, a pixel electrode 16c is provided on the dielectric layer 16b.

  Specifically, a contact hole CNT 46 and a pixel electrode 16 c are formed by forming a transparent conductive film such as ITO so as to fill the contact hole CNT 46 and cover the dielectric layer 16 b and patterning it.

  The pixel electrode 16c is electrically connected to the pixel electrode side source / drain region 30d through the contact holes CNT46, CNT45, CNT44, the relay layer 51, and the contact hole CNT42.

  Since each of the capacitive elements 16 is composed of a transparent capacitive electrode 16a, a dielectric layer 16b, and a pixel electrode 16c, the opening area is a ratio occupied by the display area E in the pixel P without narrowing the opening area. It does not reduce the rate.

  Next, as shown in FIG. 7B, the configuration of the capacitor 116 between the pixel electrodes 16c will be described. The capacitor 116 between the pixel electrodes 16c has a recess 55 on the surface of the fourth interlayer insulating layer 11e, and the capacitor electrode 16a is provided so as to cover the recess 55 and the fourth interlayer insulating layer 11e. Further, the fifth interlayer insulating layer 11f is patterned and provided so that the inside of the depression 55 and the upper part thereof are raised. Hereinafter, this portion of the fifth interlayer insulating layer 11f (insulating film) is referred to as an “insulating portion 11f1”.

  A dielectric layer 16b is provided on the insulating portion 11f1 so as to cover the insulating portion 11f1 and the capacitor electrode 16a. A pixel electrode 16c is provided on the dielectric layer 16b, and the pixel electrode 16c1 and the pixel electrode 16c2 are provided separately between adjacent pixel electrodes.

  Specifically, the depth H1 of the recess 55 is, for example, 100 nm to 400 nm. The raised height H2 of the insulating part 11f1 is, for example, 150 nm.

  Further, the gap L1 between the pixel electrode 16c1 and the pixel electrode 16c2 is, for example, 0.7 μm. The width L2 of the bottom surface (bottom portion) of the capacitive electrode 16a formed in the recess 55 is, for example, 0.8 μm. The raised width L3 of the pixel electrodes 16c1 and 16c2 is, for example, 0.25 μm.

  As described above, the depression 55 is provided on the surface of the capacitor electrode 16a in a region overlapping with the pixel electrode 16c in a plan view, and the distance between the pixel electrode 16c and the capacitor electrode 16a is increased, whereby the pixel electrode 16c1 and the pixel electrode 16c2 It is possible to suppress the leakage of the electric field generated between the pixel electrode 16c and the capacitor electrode 16a. Therefore, it is possible to suppress the alignment of the liquid crystal layer 15 from being affected by the electric field.

  In addition, the gap L1 between the pixel electrode 16c1 and the pixel electrode 16c2 is preferably equal to or shorter than the length obtained by adding the thickness of the insulating portion 11f1 to the thickness of the pixel electrode 16c. According to this, the electric field generated between the pixel electrode 16c and the capacitor electrode 16a can be weakened, and the leakage of the electric field from between the pixel electrode 16c1 and the pixel electrode 16c2 can be suppressed.

<Method for manufacturing liquid crystal device>
FIG. 8 is a flowchart showing a method of manufacturing the liquid crystal device in the order of steps. 9 and 10 are schematic cross-sectional views illustrating a part of the manufacturing method of the liquid crystal device. Hereinafter, a method for manufacturing the liquid crystal device will be described with reference to FIGS. The layers provided on the element substrate may be referred to as an element substrate. In addition, the layers provided on the counter substrate may be referred to as a counter substrate including the layers.

  First, a manufacturing method on the element substrate 10 side will be described. In step S11, the TFT 30 and the like are formed on the first substrate 11 made of a glass substrate or the like. Specifically, the TFT 30 and the like are formed on the first substrate 11 using a well-known film formation technique, photolithography technique, and etching technique.

  In step S <b> 12 (recess formation step), a recess 55 is formed on the surface of the fourth interlayer insulating layer 11 e on the first substrate 11. Specifically, as shown in FIG. 9A, for example, an etching process is performed on the surface of the fourth interlayer insulating layer 11 e to form a recess 55.

  In step S13, the capacitor electrode 16a is formed so as to cover the fourth interlayer insulating layer 11e having the recess 55 (see FIG. 9A). The thickness of the capacitive electrode 16a is, for example, 50 nm to 140 nm.

  In step S14 (insulating film forming step), the insulating portion 11f1 is formed in and above the recess 55. Specifically, first, as shown in FIG. 9B, a fifth interlayer insulating layer 11f (insulating film precursor) is formed so as to cover the capacitor electrode 16a. As a manufacturing method of the fifth interlayer insulating layer 11f, for example, a CVD (Chemical Vapor Deposition) method can be used. The thickness of the fifth interlayer insulating layer 11f at this time is, for example, 800 nm.

    Next, as shown in FIG. 9C, the upper surface of the fifth interlayer insulating layer 11f is planarized. Examples of the planarization method include an etch back method, a chemical mechanical polishing (CMP) method, an etching method, and the like. The thickness of the fifth interlayer insulating layer 11f at this time is, for example, 150 nm as described above.

  Next, as shown in FIG. 10D, the fifth interlayer insulating layer 11f is patterned to form an insulating portion 11f1. Thereby, the upper part of the hollow 55 and its periphery can be raised by the insulating part 11f1.

  In step S15 (dielectric layer forming step), the dielectric layer 16b is formed. Specifically, as shown in FIG. 10D, the dielectric layer 16b is formed so as to cover the insulating portion 11f1 and the capacitor electrode 16a.

  In step S16 (pixel electrode formation step), the pixel electrode 16c is formed. Specifically, as shown in FIG. 10E, the pixel electrode 16c is formed so as to cover the dielectric layer 16b. The thickness of the pixel electrode 16c is, for example, 50 nm to 140 nm. Thereafter, as shown in FIG. 10F, the pixel electrodes 16c are patterned to divide the pixels P from each other. That is, the pixel electrode 16c1 and the pixel electrode 16c2 are formed above the recess 55 formed between the pixels P so as to cover the dielectric layer 16b.

  As described above, the depression 55 is provided between the pixels P, and the pixel electrode 16c and the capacitor electrode 16a are separated from each other, thereby generating the pixel electrode 16c1 and the pixel electrode 16c2 between the pixel electrode 16c and the capacitor electrode 16a. It is possible to suppress electric field leakage. Therefore, it is possible to suppress the alignment of the liquid crystal layer 15 from being affected by the electric field.

  As shown in FIG. 7B, when the width L2 at the bottom of the depression 55 is larger than the gap L1 between the pixel electrodes (between the pixel electrodes 16c1 and 16c2), the influence of the electric field leakage is small. When the depression 55 is filled with the fifth interlayer insulating layer 11f, a depression is easily formed on the surface. Further, when the gap L1 is increased, the influence of the electric field leakage increases. Therefore, it is desirable to determine the gap L1 and the width L2 from the influence of the electric field leakage and the film formation state of the fifth interlayer insulating layer 11f.

In step S17, the alignment film 28 is formed above the pixel electrode 16c. As a manufacturing method of the alignment film 28, for example, an oblique deposition method in which an inorganic material such as silicon oxide (SiO ₂ ) is obliquely deposited is used. Thus, the element substrate 10 side is completed.

  Next, a manufacturing method on the counter substrate 20 side will be described. First, in step S21, the common electrode 31 is formed on the second substrate 12 made of a light-transmitting material such as a glass substrate by using a well-known film forming technique, photolithography technique, and etching technique.

  In step S <b> 22, the alignment film 32 is formed on the common electrode 31. The method of manufacturing the alignment film 32 is the same as that of the alignment film 28, and is formed by using, for example, oblique vapor deposition. Thus, the counter substrate 20 side is completed. Next, a method for bonding the element substrate 10 and the counter substrate 20 will be described.

  In step S <b> 31, the sealing material 14 is applied on the element substrate 10. Specifically, the relative positional relationship between the element substrate 10 and the dispenser (which may be a discharge device) is changed, and the sealing material 14 is placed on the periphery of the display area E on the element substrate 10 (so as to surround the display area E). Apply.

  In step S32, the element substrate 10 and the counter substrate 20 are bonded together. Specifically, the element substrate 10 and the counter substrate 20 are bonded together via the sealing material 14 applied to the element substrate 10. More specifically, it is performed while ensuring the positional accuracy in the vertical and horizontal directions of the substrates 10 and 20.

  In step S33, liquid crystal is injected into the structure from a liquid crystal injection port (not shown), and then the liquid crystal injection port is sealed. For the sealing, for example, a sealing material such as a resin is used. Thus, the liquid crystal device 100 is completed.

<Configuration of electronic equipment>
FIG. 11 is a schematic diagram illustrating a configuration of a projection display device as an electronic apparatus including the liquid crystal device described above. Hereinafter, the configuration of a projection display device including a liquid crystal device will be described with reference to FIG.

  As shown in FIG. 11, a projection display apparatus 1000 as an electronic apparatus according to the present embodiment includes a polarized illumination apparatus 1100 arranged along the system optical axis L, and two dichroic mirrors 1104 and 1105 as light separation elements. Three reflection mirrors 1106, 1107, 1108, five relay lenses 1201, 1202, 1203, 1204, 1205, three transmissive liquid crystal light valves 1210, 1220, 1230 as light modulation means, and a light combining element As a cross dichroic prism 1206 and a projection lens 1207.

  The polarized light illumination device 1100 is generally configured by a lamp unit 1101 as a light source composed of a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 1102, and a polarization conversion element 1103.

  The dichroic mirror 1104 reflects red light (R) and transmits green light (G) and blue light (B) among the polarized light beams emitted from the polarization illumination device 1100. Another dichroic mirror 1105 reflects the green light (G) transmitted through the dichroic mirror 1104 and transmits the blue light (B).

  The red light (R) reflected by the dichroic mirror 1104 is reflected by the reflection mirror 1106 and then enters the liquid crystal light valve 1210 via the relay lens 1205. Green light (G) reflected by the dichroic mirror 1105 enters the liquid crystal light valve 1220 via the relay lens 1204. The blue light (B) transmitted through the dichroic mirror 1105 enters the liquid crystal light valve 1230 via a light guide system including three relay lenses 1201, 1202, 1203 and two reflection mirrors 1107, 1108.

  The liquid crystal light valves 1210, 1220, and 1230 are disposed to face the incident surfaces of the cross dichroic prism 1206 for each color light. The color light incident on the liquid crystal light valves 1210, 1220, and 1230 is modulated based on video information (video signal) and emitted toward the cross dichroic prism 1206. In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. The three color lights are synthesized by these dielectric multilayer films, and the light representing the color image is synthesized. The synthesized light is projected on the screen 1300 by the projection lens 1207 which is a projection optical system, and the image is enlarged and displayed.

  The liquid crystal light valve 1210 is the one to which the liquid crystal device 100 described above is applied. The liquid crystal device 100 is arranged with a gap between a pair of polarizing elements arranged in crossed Nicols on the incident side and the emission side of colored light. The same applies to the other liquid crystal light valves 1220 and 1230.

  According to such a projection type display apparatus 1000, an electronic apparatus capable of improving display quality can be provided through the liquid crystal module in which the liquid crystal apparatus 100 described above is employed.

  As described above in detail, according to the liquid crystal device 100, the method for manufacturing the liquid crystal device 100, and the electronic apparatus of the present embodiment, the following effects can be obtained.

  (1) According to the liquid crystal device 100 of the present embodiment, the depression 55 is provided on the surface of the fourth interlayer insulating layer 11e in the region corresponding to the planarly adjacent pixel electrodes 16c1 and 16c2, and the insulating portion 11f1 is interposed therebetween. Since the dielectric layer 16b and the pixel electrode 16c are provided, the distance from the pixel electrodes 16c1 and 16c2 in the upper layer to the bottom of the depression 55 can be made longer than in the case where the depression 55 is not provided. Therefore, it is possible to weaken the electric field generated between the pixel electrodes 16c1 and 16c2 and the capacitor electrode 16a, and it is possible to suppress the electric field from leaking to the liquid crystal layer 15 between the pixel electrodes 16c1 and 16c2. As a result, it is possible to suppress the alignment of the liquid crystal layer 15 from being affected by the electric field.

  (2) According to the liquid crystal device 100 of the present embodiment, the width L2 at the bottom of the recess 55 is larger than the gap L1 between the pixel electrodes 16c (the width between the end portions of the adjacent pixel electrodes 16c1 and 16c2). Since it is wide, the distance from the end of the pixel electrode 16c to the capacitor electrode 16a can be increased. Therefore, the electric field generated between the pixel electrode 16c and the capacitor electrode 16a can be weakened, and the electric field can be prevented from leaking to the liquid crystal layer 15 from between the pixel electrodes 16c1 and 16c2.

  (3) According to the method for manufacturing the liquid crystal device 100 of the present embodiment, the depression 55 is formed on the surface of the fourth interlayer insulating layer 11e in the region corresponding to the area between the pixel electrodes 16c1 and 16c2 adjacent in plan, and the insulating portion Since the dielectric layer 16b and the pixel electrode 16c are formed across 11f1, the distance from the pixel electrodes 16c1 and 16c2 on the upper layer to the bottom of the recess 55 can be made longer than when the recess 55 is not provided. it can. Therefore, it is possible to weaken the electric field generated between the pixel electrodes 16c1 and 16c2 and the capacitor electrode 16a, and it is possible to suppress the electric field from leaking to the liquid crystal layer 15 between the pixel electrodes 16c1 and 16c2. As a result, it is possible to suppress the alignment of the liquid crystal layer 15 from being affected by the electric field.

  (4) According to the electronic apparatus of the present embodiment, since the liquid crystal device 100 described above is provided, the liquid crystal layer 15 can be prevented from being disturbed by the influence of an electric field and the display quality can be improved. Possible electronic devices can be provided.

(Second Embodiment)
<Configuration of liquid crystal device>
FIG. 12 is a schematic cross-sectional view illustrating a partial structure of the liquid crystal device according to the second embodiment. Hereinafter, the structure of the liquid crystal device of the second embodiment will be described with reference to FIG.

  The liquid crystal device 200 of the second embodiment is different from the first embodiment in the structure of the capacitive element 216, and the other configurations are generally the same. Therefore, in the second embodiment, portions different from the first embodiment will be described in detail, and descriptions of other overlapping portions will be omitted as appropriate.

  As shown in FIG. 12, the liquid crystal device 200 of the second embodiment is provided with a capacitor element 216 having a depression 55 between the pixels P, as in the first embodiment. The capacitive element 216 between the pixels P has a recess 55 in the fourth interlayer insulating layer 11e, and a capacitor electrode 16a is provided so as to cover the recess 55 and the fourth interlayer insulating layer 11e.

  In the second embodiment, the insulating portion 211 f 1 is provided only in the recess 55. A dielectric layer 216b is provided on the insulating portion 211f1 so as to cover the insulating portion 211f1 and the capacitor electrode 16a. A pixel electrode 216c is provided on the dielectric layer 216b, and the pixel electrode 216c1 and the pixel electrode 216c2 are separately provided with a boundary between adjacent pixel electrodes.

  The manufacturing method of the liquid crystal device 200 of the second embodiment is substantially the same as the manufacturing method of the first embodiment. As a different part, after the capacitor electrode 16 a is formed in the recess 55, the insulating portion 211 f 1 is formed only in the recess 55.

  Specifically, a fifth interlayer insulating layer 211f is formed so as to cover the capacitor electrode 16a. Next, the upper surface of the fifth interlayer insulating layer 11f is planarized. Examples of the planarization treatment method include an etch back method and a CMP treatment. Further, wet etching may be performed to remove the surface of the capacitor electrode 16a. At this time, the height of the insulating portion 211f1 is set to the height of the surface of the capacitive electrode 16a.

  Next, the dielectric layer 216b is formed so as to cover the insulating portion 211f1 and the capacitor electrode 16a. Thereafter, the pixel electrode 216c1 and the pixel electrode 216c2 are formed by patterning so as to cover the dielectric layer 216b.

  As described above in detail, according to the liquid crystal device 200 of the second embodiment, the following effects can be obtained.

  (5) According to the liquid crystal device 200 of the second embodiment, since the height of the upper surface of the capacitor electrode 16a and the upper surface of the insulating portion 211f1 are matched, the dielectric layer 216b and the pixel electrode 216c ( 216c1, 216c2) can be formed flat. Therefore, it is possible to prevent the liquid crystal alignment in the liquid crystal layer 15 from being disturbed.

  Note that the present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification, and is included in the technical scope of the present invention. Is. Moreover, it can also implement with the following forms.

(Modification 1)
As in the first embodiment described above, the structure above the depression 55 is not limited to the structure in which the dielectric layer 16b is formed via the insulating portion 11f1, and may be as shown in FIG. 13, for example. FIG. 13 is an enlarged cross-sectional view showing the structure of the capacitive element between the pixels P. As in the liquid crystal device 500 shown in FIG. 13, a dielectric layer 516b is provided on the capacitor electrode 16a formed in the recess 55 so as to cover the capacitor electrode 16a. An insulating portion 11f1 is provided above the recess 55 on the dielectric layer 516b.

  Also in this case, the distance between the pixel electrodes 16c1 and 16c2 and the capacitor electrode 16a can be increased, and an electric field generated between the pixel electrode 16c and the capacitor electrode 16a from between the pixel electrode 16c1 and the pixel electrode 16c2 is a liquid crystal layer. 15 can be prevented from leaking. Therefore, it is possible to suppress the alignment of the liquid crystal layer 15 from being affected by the electric field.

(Modification 2)
As in the second embodiment described above, the structure above the depression 55 is not limited to the structure in which the dielectric layer 216b is formed via the insulating portion 211f1, and may be as shown in FIG. 14, for example. FIG. 14 is an enlarged cross-sectional view showing the structure of the capacitive element between the pixels P. As in the liquid crystal device 600 shown in FIG. 14, a dielectric layer 616b is provided on the capacitor electrode 16a formed in the recess 55 so as to cover the capacitor electrode 16a. An insulating portion 211f1 is provided above the recess 55 on the dielectric layer 616b.

  Also in this case, the distance between the pixel electrodes 216c1 and 216c2 and the capacitor electrode 16a can be increased, and an electric field generated between the pixel electrode 216c and the capacitor electrode 16a is generated between the pixel electrode 216c1 and the pixel electrode 216c2. 15 can be prevented from leaking. Therefore, it is possible to suppress the alignment of the liquid crystal layer 15 from being affected by the electric field.

(Modification 3)
As described above, the shape of the recess 55 is not limited to being formed in a cross shape between the pixels P. For example, the recess 55 is provided between the pixels P so as to extend in a direction along the scanning line 3a in a plane. Also good. Further, it may be provided to extend between the pixels P in a direction along the data line 6a in a plane.

(Modification 4)
As described above, the capacitor electrode 16a is not limited to be formed on the depression 55 formed in the fourth interlayer insulating layer 11e. For example, a hygroscopic BSG film is formed on the depression 55, and A capacitor electrode 16a may be formed thereon. Specifically, the thickness of the BSG film is, for example, 50 nm to 75 nm.

(Modification 5)
As described above, the projection display apparatus 1000 (projector) has been described as an example of the electronic apparatus. However, the present invention is not limited to this. For example, the present invention may be applied to a viewer, a viewfinder, a head mounted display, and the like. Various electronic devices such as LCD TVs, mobile phones, electronic notebooks, word processors, viewfinder type or monitor direct-view type video tape recorders, workstations, mobile personal computers, video phones, POS terminals, pagers, calculators, touch panels, etc. Further, the present invention may be applied to an electrophoretic device such as electronic paper, a car navigation device, and the like.

  3a ... scanning line, 3b ... capacitance line, 6a ... data line, 10 ... element substrate, 11 ... first substrate, 11a ... underlying insulating layer, 11b ... gate insulating layer, 11c ... second interlayer insulating layer, 11d ... third Interlayer insulating layer, 11e ... fourth interlayer insulating layer, 11f ... fifth interlayer insulating layer (insulating film), 11f1, 211f1 ... insulating portion (insulating film), 12 ... second substrate, 14 ... sealing material, 15 ... liquid crystal layer 16, 116, 216 ... capacitance element, 16a ... capacitance electrode, 16b, 216b, 516b, 616b ... dielectric layer, 16c, 216c ... pixel electrode, 18 ... light shielding layer, 20 ... counter substrate, 22 ... data line driving circuit 24 ... Scanning line drive circuit, 25 ... Inspection circuit, 26 ... Vertical conduction part, 28 ... Alignment film, 30 ... TFT, 30a ... Semiconductor layer, 30c ... Channel region, 30d ... Source / drain region on the pixel electrode side, 30g ... Gate Electrode, 30 s ... data line side source / drain region, 31 ... common electrode, 32 ... alignment film, 41, 42, 43, 44, 45, 46 ... contact hole CNT, 51 ... relay layer, 52 ... opening, 61 ... external Connection terminal, 70 ... capacitance element, 100,200 ... liquid crystal device, 1000 ... projection type display device, 1100 ... polarization illumination device, 1101 ... lamp unit, 1102 ... integrator lens, 1103 ... polarization conversion element, 1104,1105 ... dichroic mirror 1106, 1107, 1108 ... reflective mirror, 1201, 1202, 1203, 1204, 1205 ... relay lens, 1206 ... cross dichroic prism, 1207 ... projection lens, 1210 ... liquid crystal light valve, 1210, 1220, 1230 ... liquid crystal light valve, 1300: Screen.

Claims (9)

A pair of substrates;
A liquid crystal layer sandwiched between the pair of substrates;
A transistor provided on one of the pair of substrates;
A capacitor element electrically connected to the transistor, including a pixel electrode, a capacitor electrode, and a dielectric layer sandwiched between the pixel electrode and the capacitor electrode;
With
The liquid crystal device, wherein the capacitor electrode has a depression in a region between pixel electrodes adjacent in plan. The liquid crystal device according to claim 1,
A liquid crystal device comprising an insulating film that overlaps with an outer edge of the adjacent pixel electrodes in a plan view and fills between the adjacent pixel electrodes and the recesses. The liquid crystal device according to claim 1 or 2,
The liquid crystal device according to claim 1, wherein the recess is arranged along at least one of the data line and the scanning line in a plan view. The liquid crystal device according to claim 3,
2. The liquid crystal device according to claim 1, wherein the capacitor electrode has a portion without the depression in a region between the adjacent pixel electrodes in plan view. The liquid crystal device according to claim 1, wherein the liquid crystal device is a liquid crystal device according to claim 1.
The liquid crystal device according to claim 1, wherein a width of the bottom of the depression is wider than a gap between the pixel electrodes. The liquid crystal device according to claim 5,
The liquid crystal device according to claim 1, wherein the gap between the pixel electrodes has a length equal to or shorter than a length obtained by adding a thickness of the insulating film to a thickness of the pixel electrode. A pair of substrates;
A liquid crystal layer sandwiched between the pair of substrates;
A transistor provided on one of the pair of substrates;
A capacitive element having a pixel electrode connected to the transistor, a capacitive electrode, and a dielectric layer sandwiched between the pixel electrode and the capacitive electrode;
A method of manufacturing a liquid crystal device comprising:
A recess forming step for forming a recess on the surface of the capacitor electrode in a region overlapping the region between the pixel electrodes in a plane;
An insulating film forming step of forming an insulating film so as to fill at least the depression;
A dielectric layer forming step of forming the dielectric layer so as to cover the insulating film and the capacitive electrode;
A pixel electrode forming step of forming the pixel electrode so as to cover the dielectric layer;
A method for manufacturing a liquid crystal device, comprising: It is a manufacturing method of the liquid crystal device according to claim 7,
In the insulating film forming step, an insulating film precursor to be the insulating film is formed so as to cover the capacitor electrode, and thereafter, by any one of an etch back processing method, a CMP processing method, and an etching processing method, A method of manufacturing a liquid crystal device, wherein the insulating film is formed at least in the recess.   An electronic apparatus comprising the liquid crystal device according to any one of claims 1 to 6.

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