JP2000214482A - Electro-optic device and electronic apparatus using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the differences in level occurring in the presence of various kinds of wiring layers and elements in an image display region by using a relatively simple constitution in an electro-optic device. SOLUTION: The electro-optic device has an electro-optic material layer 11 which is held between a pair of substrates and pixel electrodes 9a disposed in a matrix-form formed on a TFT array substrate 2. The TFT array substrate is formed with recessed parts 50 on the lower layer side of data lines 6a, scanning lines 3a, capacitor lines 3b and TFTs 30 and, therefore, the flat formation of aligned films 18 is made possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method of a thin film transistor (hereinafter referred to as a TFT (Thin Film Transistor)) and a thin film diode (hereinafter referred to as a TFD).
de). The present invention relates to an electro-optical device of an active matrix driving system by driving and the like, and a display device using the same.

[0002]

2. Description of the Related Art Among the electro-optical devices used for various display devices, in the most typical liquid crystal device, a pixel electrode and a counter electrode are formed on the surface of a pair of substrates. An alignment film subjected to a rubbing process in each direction is formed. Therefore, when an electro-optical material such as liquid crystal is sealed between a pair of substrates, the electro-optical material such as liquid crystal is aligned in a predetermined state between these alignment films.
Then, when an electric field is applied to the electro-optical substance from both electrodes during operation of the liquid crystal device, the orientation state of the electro-optical substance changes for each pixel, and display is performed in the image display area of the electro-optical device.

Accordingly, in this type of electro-optical device,
Wiring layers such as data lines, scanning lines, capacitance lines, and TF
This is due to the presence or absence of a film forming the wiring layer or the pixel switching element between the region where the pixel switching element such as T or TFD is formed and the region where these wiring layers and the pixel switching element are not formed. If there is unevenness and the unevenness remains on the surface (alignment film) in contact with the electro-optical material as it is, poor alignment (disclination) occurs in the electro-optical material depending on the degree of the unevenness, and each pixel Leads to deterioration of the image. That is, when a polyimide film or the like is subjected to a rubbing treatment to form an alignment film, if the polyimide film has unevenness, the unevenness of the alignment at the alignment film surface due to the unevenness causes a variation in the electro-optical material. Poor alignment occurs. When such poor orientation of the electro-optical material occurs, for example, in a normally white mode in which white display is performed when no voltage is applied to the electro-optical material, a white spot phenomenon occurs at a position of poor orientation, and contrast is reduced. The resolution decreases as well as the definition. Such deterioration of the image is remarkable when the unevenness is formed near the opening area of each pixel through which the incident light for image display passes.

In order to avoid such a situation, the distance between the alignment films (the thickness of the electro-optical material) between the substrates must be uniform and
It is necessary to maintain a predetermined value and to perform a rubbing process on the alignment film uniformly and appropriately over the entire surface of the substrate. For this purpose, it is important to flatten the image display area.

[0005]

However, in order to flatten the image display area with the conventional structure, for example, the thin films constituting the TFT or the wiring layers formed in multiple layers are insulated and separated. For this purpose, it is necessary to eliminate unevenness by using one or more layers of a plurality of interlayer insulating films formed. That is, it is necessary to form the interlayer insulating film in the region where the wiring layer and the pixel switching element and the like are formed thinner than the interlayer insulating film in the region where the wiring layer and the pixel switching device and the like are not formed. In addition, the upper surface of the insulating film formed on the uppermost side is formed by CMP (Chem).
ical Mechanical Polishing) process,
Alternatively, SOG (Spin On Glas
It is necessary to planarize by forming s). However, any of these methods has a problem that the manufacturing process is considerably complicated, which results in a decrease in yield and an increase in cost.

Further, even if the thickness of the interlayer insulating film is changed for each region, the thickness of the interlayer insulating film is excessively large (for example, 10
If the thickness is reduced to about 000 angstroms), cracks are likely to occur. On the other hand, the interlayer insulating film is too thin (for example, about several hundred Angstroms).
In this case, the electric field interacts between the two conductive films insulated through the interlayer insulating film. For example, if the interlayer insulating film formed on the side opposite to the gate insulating film with respect to the channel region of the TFT having the light-shielding layer is thin, the interlayer insulating film acts as a gate insulating film, and a back channel is formed in the channel region. Or the capacity is added. In addition, it is basically difficult to form a thin insulating film in a defect-free state by itself, which reduces the yield of electro-optical devices. Furthermore, forming the interlayer insulating film thicker in one part and thinner in the other part also reduces the degree of freedom in designing the electro-optical device.

Further, in this type of electro-optical device, even if the duty ratio when supplying an image signal to each pixel electrode is small, a predetermined capacitance (capacity) is applied to each pixel electrode so that flicker and crosstalk do not occur. In some cases, a capacitor for providing the storage capacitor is provided. In this case, the total thickness of the specific region is increased by the thickness of the electrode forming the capacitor or the thickness of the capacitor line. Therefore, the level difference in the image display area increases. In particular, if such a storage capacitor is formed in a lower layer of the data line or in a region along the scanning line, the total film thickness of this portion is further increased and a considerably large step is generated in the image display region. For example, when a storage capacitor is formed below the data line, only the thickness of the storage capacitor (the total thickness of the first storage capacitor electrode, the insulating film, and the second storage capacitor electrode) and the thickness of the data line do not exist. It will be higher than the pixel part, and the level difference is about 1
It can be as high as 0000 angstroms. Therefore, in this case, there is a problem that the flattening process for eliminating the step in the image display area is difficult and costly.

Further, in an electro-optical device having a TFT for each pixel, particularly when used in a projector, when the projection light transmitted through the electro-optical device is incident on the back surface as return light and is irradiated on the channel region of the TFT. Since light leakage occurs in the TFT, a light-shielding film may be provided below the TFT in order to prevent the light leakage. Also in this case, the total thickness of the region where the TFT is formed is larger than that of the other regions by the thickness of the light-shielding film, and the above-described step is increased.
Therefore, also in this case, there is a problem that the flattening processing for eliminating the step in the image display area is difficult and costly.

In view of the above problems, an object of the present invention is to
With a relatively simple configuration, it is possible to improve display quality without reducing reliability and productivity by reducing steps due to the presence of wiring layers and pixel switching elements in the image display area. An object is to provide an electro-optical device and a display device.

[0010]

In order to solve the above-mentioned problems, according to the present invention, the pixel switching elements are arranged on an upper layer side of pixel switching elements arranged in a matrix and on an upper layer side of a wiring layer for the pixel switching elements. A first substrate having a pixel electrode connected thereto, a second substrate having a counter electrode facing the pixel electrode, and an electro-optical device sandwiched between the first and second substrates. In the electro-optical device having a substance, at least a part of the pixel switching element and the wiring layer is formed in a concave portion that is recessed below the pixel switching element and the wiring layer.

In the present invention, in the first substrate, at least a part of various wiring layers such as a data line, a scanning line, and a capacitance line, or at least a part of a pixel switching element is formed in a recess formed in a lower layer side. Between the region where these wiring layers or pixel switching elements are formed and the region where these wiring layers or pixel switching elements are not formed. Even if there is a difference in the total thickness, such a difference is absorbed and reduced by the concave portion. Also, if the region where the total thickness is the largest due to the overlapping of the wiring layers is reduced by the recess by the difference from the total thickness of the other regions, a step is prevented from being formed between these regions. it can. Further, in the opening region where the pixel electrode is formed but the wiring layer and the pixel switching element are not formed, the sum of the film thickness is considerably smaller than that in the non-opening region where the wiring layer and the pixel switching element are formed. However, if the non-opening region where the wiring layer and the pixel switching element are formed is lowered by the concave portion, it is possible to prevent a step from being formed between these regions. Therefore, according to the present invention, the first
Since the uppermost layer side of the substrate can be flattened, a polyimide film or the like for forming an alignment film can be formed flat on the surface. Therefore, the rubbing process can be properly performed on each of the first and second substrates. After the first and second substrates are bonded together, an electro-optical material such as a liquid crystal is interposed between the substrates. Encapsulating the electro-optic material is properly oriented. Therefore, it is possible to improve the contrast and achieve high definition display.

Further, since the concave portion is formed only below the wiring layer and the pixel switching element, if the concave portion is formed at an early stage of the manufacturing process, the CVD process,
Various processes such as a sputtering process, a photolithography process, and an etching process can be performed under substantially the same or exactly the same conditions as before, and it is necessary to add a new process to form a wiring layer and a pixel switching element. There is no need to complicate the process. Further, since it is not necessary to perform a troublesome process of changing the thickness of the interlayer insulating film in each region, productivity does not decrease. Furthermore, if the thickness of the interlayer insulating film is constant, there is no problem that cracks occur due to the thick interlayer insulating film and no problem that a back channel is generated due to the thin interlayer insulating film, so that reliability is improved. Does not decrease.

In the present invention, the depth of the concave portion is, for example, in a range from 0.1 μm to 2.0 μm.

In the present invention, the recess may have a side wall rising at an angle of about 90 ° from the bottom, but with such a shape, the recess may have a tapered surface rising at an angle of 45 ° or more from the bottom. It is preferable to provide a side wall portion made of: With this configuration, when removing the polysilicon film, the resist, and the like formed in the concave portion, the side wall portion is tapered, so that the polysilicon film, the resist, and the like can be reliably removed from the side wall portion. No foreign matter remains inside. Further, even when the wiring layer is drawn out of the concave portion to the outside of the concave portion, if the side wall portion has a tapered surface, the wiring layer does not break at this side wall portion.

In the present invention, the opening edge of the concave portion preferably has a curved cross-sectional shape. That is, it is preferable that the opening edge of the concave portion is gentle rather than angular. With such a shape, it is possible to prevent the polysilicon film, the resist, and the like from remaining in the recess as a shadow of the opening edge when the polysilicon film, the resist, and the like formed in the recess are removed. Even when the wiring layer is pulled out of the recess to the outside of the recess, if the opening edge is not angular, the wiring layer does not break at the opening edge.

In the present invention, the concave portion may be formed directly on the surface of the transparent substrate serving as the base of the first substrate, or may be formed on the surface of the transparent substrate serving as the base of the first substrate. Any of the configurations formed on the surface of the formed insulating film may be used.

In any of these configurations, an insulating film is formed so as to cover the bottom and side walls of the recess, and at least a part of the pixel switching element and the wiring layer is formed on the insulating film. It is preferred that According to such a configuration, even if the inner surface of the concave portion is rough when the concave portion is formed by etching, since the surface is covered with the insulating film, the TFT is directly formed on the inner surface of the rough concave portion.
As compared with the case where an active layer or the like is formed, the surface condition of the inner surface of the concave portion can be prevented from adversely affecting the active layer of the TFT. For example, deterioration of transistor characteristics such as drift of threshold voltage (Vth), deterioration of mobility in the active layer, and deterioration of characteristics such as increase of off-leakage can be prevented.

In the present invention, the pixel switching element is, for example, a thin film transistor. In this case, the wiring layer includes a scanning line and a data line connected to the thin-film transistor.

In the present invention, the recess is preferably formed in a region overlapping with the entire region of the wiring layer in the image display region of the first substrate on which the plurality of pixel electrodes are formed. preferable. With this configuration, the step between the region where the wiring layer is formed and the region where the wiring layer is not formed can be completely eliminated by the concave portion.

In this case, the width dimension of the wiring layer forming area in the image display area is determined from the opening width of the concave portion formed on the lower layer side of the wiring layer to the lower layer side of the wiring layer in the concave portion. It is preferable that the width is smaller than a value obtained by subtracting a dimension corresponding to twice the thickness of the formed interlayer insulating film. With this configuration, when the side wall of the recess is a taper surface of about 45 degrees, the wiring layer is formed on the bottom in the recess formed in the interlayer insulating film, and the end of the wiring layer is formed on the side wall formed of the tapered surface. Do not overlap. Therefore, it is possible to prevent the formation of useless irregularities on the upper layer side.

In the present invention, the width of the wiring layer forming area in the image display area is substantially equal to the opening width of the recess formed below the wiring layer, or the width of the recess is smaller. The dimension may be narrower by 10 μm or less than the opening width. With this configuration, it is possible to prevent a step from being formed near the edge of the concave portion on the upper layer side.

In the present invention, it is preferable that the recess is formed in a region overlapping with a whole region of a semiconductor film forming an active region of the thin film transistor.
With this configuration, a step between the region where the active region of the thin film transistor is formed and the region where the semiconductor film is not formed can be completely eliminated by the concave portion.

In this case, the width of the formation region of the semiconductor film is formed in the lower portion of the semiconductor film in the recess from the width of the bottom of the recess formed in the lower portion of the semiconductor film. It is preferable that the width is smaller than a value obtained by subtracting a dimension corresponding to twice the thickness of the interlayer insulating film. With such a configuration, when the side wall of the recess is a taper surface of about 45 degrees, the semiconductor film is formed at the bottom in the recess formed in the interlayer insulating film, and the end of the semiconductor film is formed on the side wall formed of the tapered surface. The parts do not overlap. Therefore, it is possible to prevent the formation of useless irregularities on the upper layer side.

In the present invention, the width dimension of the semiconductor film formation region is substantially equal to the opening width of the recess formed below the semiconductor film, or is larger than the opening width of the recess. The dimensions may be as narrow as 10 μm or less. With this configuration, it is possible to prevent a step from being formed near the edge of the concave portion on the upper layer side.

In the present invention, it is preferable that a capacitance element for providing a storage capacitance to the pixel electrode is formed on the first substrate. With such a configuration, since the potential of the pixel electrode can be held by the capacitor, flicker and crosstalk do not occur even when the duty ratio when supplying the image signal to each pixel electrode is small.

In this case, it is preferable that the wiring layer includes a capacitance line forming an electrode of the capacitance element. With this structure, even when the quality of an image is improved by adding a capacitor, unevenness due to the capacitor line is not formed on the uppermost layer of the first substrate. Therefore, even if a capacitance line is added, the alignment film can be formed flat, and the electro-optical material can be properly oriented.

[0027] In the present invention, the recessed portion is located 4 mm from the bottom.
There may be a case where a side wall portion formed of a tapered surface rising at an angle of 5 ° or more is provided. In this case, a part of the electrode constituting the capacitive element is formed in a portion corresponding to the side wall portion of the concave portion. Is preferred. As described above, when the capacitive element is formed by using the side wall portion having the tapered surface,
Even within the same projected area, a capacitor with a large electrode facing area can be formed, so that a capacitor with a large capacitance can be formed.

In the present invention, it is preferable that the recess is formed in a region overlapping with the entire region of the formation region of the capacitor. According to this structure, the step between the region where the capacitor is formed and the region where the capacitor is not formed can be completely eliminated by the concave portion.

In this case, the width dimension of the electrode forming the capacitive element is substantially equal to the opening width of the concave portion in which the electrode is formed, or is smaller than the opening width of the concave portion by one.
It is preferred that the dimensions be as narrow as 0 μm or less. With this configuration, it is possible to prevent a step from being formed near the edge of the concave portion on the upper layer side.

[0030] In the present invention, at least a portion of the first substrate in the region where the concave portion is formed is provided on the front surface side of the first substrate.
It is preferable that a light shielding film is formed in a region covering the channel region of the thin film transistor as viewed from the substrate. With this configuration, even if light transmitted through the first substrate is reflected and enters from the back side of the first substrate, the light is blocked by the light shielding film and enters the channel region of the TFT. There is no. Therefore, it is possible to prevent light leakage from occurring in the TFT.

In this case, the light-shielding film may have either a configuration formed in the concave portion or a configuration formed below the layer in which the concave portion is formed.

When the light-shielding film is formed in the recess, the light-shielding film is formed in an area of the recess overlapping with the bottom and the side wall of the recess. May be. With this configuration,
Even when light enters obliquely from the back side of the first substrate,
The light-shielding film formed in the region overlapping the side wall blocks this light.

In the present invention, it is preferable that an alignment concave portion is formed on the first substrate simultaneously with the concave portion.

In the display device using the electro-optical device to which the present invention is applied, since the surface of the first substrate in contact with the electro-optical material is flat, the entire surface is uniform and
Rubbing can be performed properly. Therefore, the first and second
Since the electro-optical material is appropriately oriented between the substrates, high-quality display can be performed in various display devices. In particular, in the projection type display device, since the contrast reduction and the like due to the disorder of the alignment state of the electro-optical material are enlarged and displayed as it is, it is strongly required to properly align the liquid crystal. This is effective in improving the contrast and increasing the definition of the display in the device.

[0035]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] (Configuration of Image Display Area in Electro-Optical Device) With reference to FIGS. 1 to 4, a configuration in an image display area of an electro-optical device to which the present invention is applied will be described together with its operation. I do. FIG. 1 is an equivalent circuit of various elements, wiring layers, and the like in a plurality of pixels formed in a matrix forming an image display area of the electro-optical device. FIG. 2 is a plan view showing a part of a plurality of adjacent pixel groups of a TFT array substrate on which data lines, scanning lines, pixel electrodes, etc. are formed, and FIGS. AA 'in FIG.
It is sectional drawing, BB 'sectional drawing and CC' sectional drawing.
In FIGS. 2, 3, 4 and 5, in order to make each layer and each member large enough to be recognized on the drawings,
The scale is different for each layer and each member.

In FIG. 1, a plurality of pixels formed in a matrix and constituting an image display area of the electro-optical device 1 according to the present embodiment are composed of a pixel electrode 9a and a pixel electrode 9a.
a, and a data line 6a to which an image signal is supplied is electrically connected to a source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. good. TFT
The scanning line 3a is electrically connected to the gate 30. The scanning signals G1, G2,..., Gm are applied in a pulsed manner to the scanning line 3a in this order at a predetermined timing. It is configured. The pixel electrode 9a is a TFT 30
Of the TFT 30 which is a switching element, which is electrically connected to the drain of the data line 6a.
1, S2,..., Sn are written at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the electro-optical material via the pixel electrodes 9a are constant with respect to a counter electrode (described later) formed on a counter substrate (described below). Retained for a period. In this embodiment, the electro-optical material is a liquid crystal, and the orientation or order of the molecular assembly changes for each pixel depending on the applied voltage level, thereby modulating light and enabling a gradation display. In the normally white mode, the incident light cannot pass through the electro-optical material portion according to the applied voltage. In the normally black mode, the incident light does not pass through the electro-optical material according to the applied voltage. It can pass through the optical material portion. Therefore, light having a contrast corresponding to the image signal is emitted from the electro-optical device 1.

Here, the held image signals S1, S2,
... In order to prevent Sn from leaking, a capacitance element 15 is added to each pixel in parallel with an electro-optical material capacitance (liquid crystal capacitance) formed between the pixel electrode 9a and the counter electrode. For example, the voltage of the pixel electrode 9a is held by the capacitor 15 for a time that is three orders of magnitude longer than the time during which the source voltage is applied. Thereby, the holding characteristics are further improved, and the electro-optical device 1 having a high contrast ratio can be realized.

(Configuration of Pixel) In FIGS. 2 and 3,
On the TFT array substrate 2 of the electro-optical device 1, a plurality of transparent pixel electrodes 9a are formed in a matrix on a transparent substrate 20 made of a quartz substrate, which is a base thereof. Along each, a data line 6a made of an aluminum film, and a scanning line 3a and a capacitor line 3b made of a conductive semiconductor film are formed. Also, T
The pixel switching TFT 30 is formed on the FT array substrate 2 using the island-shaped semiconductor film 30a. The data line 6a is a semiconductor film 30 made of a polysilicon film or the like.
a of the pixel switching TFT 30 is electrically connected to the source region 31a of the pixel switching TFT 30 through the contact hole 5,
The pixel electrode 9a is electrically connected to the drain region 32a of the semiconductor film 30a via the contact hole 8. The scanning line 3a is arranged in the semiconductor film 30a so as to face the channel region 33a of the pixel switching TFT 30, and the scanning line 3a functions as a gate electrode of the pixel switching TFT 30.

In the present embodiment, the capacitance element 15 is formed using the capacitance line 3b, and the capacitance line 3b intersects with the data line 6a and a linear portion extending substantially linearly along the scanning line 3a. And a protruding portion protruding forward (upward with respect to FIG. 2) from the location along the data line 6a.

(Configuration of TFT Array Substrate) In this embodiment,
In the region surrounded by the thick line L1 shown in FIG. The configuration of the recess 50 will be described later in detail with reference to FIGS. 3, 4, and 5, and the configuration of the pixel switching TFT 30 will be described with reference to FIG.

In FIG. 3, the TFT array substrate 2 has
As shown in FIG. 3, a pixel switching TFT 30 for controlling the switching of each pixel electrode 9a is provided at a position adjacent to the pixel electrode 9a made of a transparent conductive thin film such as an ITO film (Indium Tin Oxide film). The pixel switching TFT 30 is an LDD (Lightly Doped Draid).
n) Scan line 3 having a structure and serving as a gate electrode
a, a channel region 33a where a channel is formed by an electric field from the scanning line 3a, the scanning line 3a and the semiconductor film 30a.
A gate insulating film 41, a data line 6a as a source electrode, a lightly doped source region 31b formed in the semiconductor film 30a and a lightly doped source region 31a formed of the heavily doped source region 31c, and a lightly doped region formed in the semiconductor film 30a. A drain region 32a including a drain region 32b and a high-concentration drain region 32c is provided. A corresponding one of the plurality of pixel electrodes 9a is connected to the high-concentration drain region 32c. As described later, the source region 31a and the drain region 32a are
It is formed by doping a predetermined concentration of an n-type or p-type dopant depending on whether an n-type or p-type channel is formed. In this embodiment, the pixel switching TFT 30 is an n-channel TFT, and since this n-channel TFT has an advantage of a high operating speed, it is often used as a pixel switching element.

In this embodiment, the data line 6a is formed of a light-shielding thin film such as a low-resistance metal film such as Al or an alloy film such as metal silicide. In addition, the contact hole 5 leading to the high-concentration source region 31c and the high-concentration drain region 3
An interlayer insulating film 14 in which contact holes 8 each leading to 2c are formed is formed. Data line 6a is electrically connected to high-concentration source region 31c via contact hole 5 to source region 31a. Further, on the data line 6a and the interlayer insulating film 14, an interlayer insulating film 17 in which a contact hole 8 to the high-concentration drain region 32c is formed is formed. The pixel electrode 9a formed in the upper layer of the interlayer insulating film 17 is electrically connected to the high-concentration drain region 32c via the contact hole 8 to the high-concentration drain region 32c. The pixel electrode 9
a and the high-concentration drain region 32c may be electrically connected to each other by relaying an Al film or the like formed simultaneously with the data line 6a.

The pixel switching TFT 30 preferably has an LDD structure as described above, but has an offset structure in which impurity ions are not implanted into regions corresponding to the low concentration source region 31b and the low concentration drain region 32b. Alternatively, a self-aligned structure in which high-concentration source and high-concentration drain regions are formed in a self-aligned manner with respect to the scanning line 3a by implanting high-concentration impurity ions into the semiconductor film 30a using the scanning line 3a as a mask. You may have.

In this embodiment, the pixel switching T
Although the FT 30 has a single gate structure in which only one gate electrode (scanning line 3a) is arranged between the source and the drain,
Two or more gate electrodes may be arranged between them.
At this time, the same signal is applied to each gate electrode. If a TFT is constituted by a dual gate or triple gate or more as described above, the channel and the source-
Leakage current at the junction of the drain region can be prevented, and current during off-state can be reduced. If at least one of these gate electrodes has an LDD structure or an offset structure,
Further, the off current can be reduced, and a stable switching element can be obtained.

In the TFT array substrate 2 thus configured, generally, the channel region 33 of the semiconductor film 30a is formed.
a, When strong light enters the polysilicon layers such as the low-concentration source region 31b and the low-concentration drain region 32b, a photocurrent is generated due to the photoelectric conversion effect of the polysilicon, and the transistor characteristics of the pixel switching TFT 30 deteriorate. . Therefore, in the present embodiment, the data line 6a made of a light-shielding metal film such as an aluminum film is formed so as to cover the scanning line 3a from above.
At least the channel region 33a and the low concentration source region 31
Intense light does not enter from the counter substrate 7 into the b and the low concentration drain region 32b.

(Configuration of Capacitive Element) In the present embodiment, when forming the capacitive element 15 for adding a storage capacitor to the pixel electrode 9a, the gate insulating film 41 is extended from a position facing the scanning line 3a to form a dielectric film. The semiconductor film 30a is extended to form a first storage capacitor electrode 15a, and a capacitor line 3b is formed to face the first storage capacitor electrode 15a. More specifically,
A high-concentration drain region 32c of the semiconductor film 30a is extended under the data line 6a, and a gate insulating film 41 is formed on the capacitance line 3b which also extends along the data line 6a and the scanning line 3a.
And the first storage capacitor electrode 15a. Here, the insulating film as a dielectric of the capacitive element 15 is formed on a polysilicon film by high-temperature oxidation.
Since it is nothing but the gate insulating film 41 of the FT 30, it is thin,
In addition, since the insulating film has a high withstand voltage, the capacitor 15 has a relatively small area and a large capacitance.

As described above, in the present embodiment, the capacity line 3b is formed in the region below the data line 6a and in the region where the electro-optical material is likely to undergo disclination along the scanning line 3a, so that the opening region is deviated. The capacitance element 15 is formed by effectively utilizing the space, and a storage capacitance is added to the pixel electrode 9a. Therefore, the electro-optical device 1 of the present embodiment
Can perform high-definition and bright display while having a small size, and have a high contrast ratio.

The capacitance line 3b and the scanning line 3a are made of the same polysilicon film. The dielectric film of the capacitor 15 and the gate insulating film 4 of the pixel switching TFT 30 are used.
1 is made of the same insulating film such as an oxide film or a nitride film. Further, the first storage capacitor electrode 15a, the channel region 33a of the pixel switching TFT 30, the source region 3
1a, the drain region 32a, etc.
a. For this reason, even though the capacitor 15 is formed, the laminated structure formed on the TFT array substrate 2 can be simplified. Further, in manufacturing the electro-optical device 1 of the present embodiment, the capacitive element 15 can be formed with the help of the step of forming the TFT 30.

In the TFT array substrate 2 on which the TFT 30 and the capacitor 15 are formed as described above, an alignment film 18 is formed on the surface of the pixel electrode 9a and the interlayer insulating film 17. This alignment film 18 is formed by performing a rubbing process on an organic thin film transparent conductive thin film such as a polyimide film formed on the surface of the pixel electrode 9 and the interlayer insulating film 17.

(Structure of the opposing substrate)
The FT array substrate 2 is made of a transparent substrate 7 such as a glass plate or quartz.
0 is disposed opposite to a counter substrate 7 having a base of 0. In the counter substrate 7, a second mask called a black mask or a black matrix is formed in a region other than an opening region of each pixel (a region where incident light is actually transmitted and effectively contributes to display in the image display region). A light-shielding film 72 is provided. Therefore, light incident from the counter substrate 7 does not enter the channel region 33a of the pixel switching TFT 30 or the like. Further, the second light-shielding film 72 has a function of improving contrast, preventing color mixture of color materials, and the like.

On the opposing substrate 7, a transparent opposing electrode 71 made of an ITO film (transparent conductive thin film) is formed on the upper layer side of the light shielding film 72, and an alignment film 73 is formed on the upper layer side of the opposing electrode 71. Is formed. The alignment film 73 is also formed by performing a rubbing process on an organic thin film such as a polyimide film formed on the surface of the counter electrode 71.

(Structure of Laminating Substrates) The opposing substrate 7 and the TFT array substrate 2 configured as described above are
a and the opposing electrode 71 are arranged so as to face each other, and then an electro-optical material (liquid crystal) is sealed in a space surrounded by a sealing material containing a spacer to be described later, and the electro-optical material layer 11 is formed. . The electro-optical material layer 11 has an alignment film 18 in a state where no electric field is applied from the pixel electrode 9a.
By 73, a predetermined orientation state is obtained. Electro-optical material layer 11
Is composed of, for example, an electro-optic material obtained by mixing one or several kinds of nematic electro-optic materials.

(Flattening Structure on TFT Array Substrate)
In the electro-optical device 1 configured as described above, the region surrounded by the thick line L1 in FIG. 2 is recessed on the side of the transparent substrate 20 of the TFT array substrate 2, as shown in FIG. A recess 50 is formed. For this reason, the BB 'cross section and the CC' cross section of FIG. 2 are represented as shown in FIGS. 4 and 5, respectively.

In FIGS. 3, 4 and 5, the recess 50 is used.
In an image display area where a large number of pixel electrodes 9a are formed on the TFT array substrate 2, a pixel switching TFT 30 is formed, or a wiring layer is formed such as a scanning line 3a, a data line 6a, and a capacitor line 3b.
As long as it is a region that can offset a step that tends to be formed on the surface of the alignment film 18, it may be formed only in a region that planarly overlaps only a part of the pixel switching TFT 30 or a part of the wiring layer. As is clear from FIG. 2, a region where the semiconductor film 30a for forming the pixel switching TFT 30 and the capacitor 15 is formed, and wiring layers such as the scanning line 3a, the data line 6a, and the capacitor line 3b are formed. It is formed in a region overlapping with all of the regions.

That is, in this embodiment, on the surface of the transparent substrate 20, which is the base of the TFT array substrate 2, the region where the semiconductor film 30a for forming the pixel switching TFT 30 and the capacitor 15 is formed, and the scanning line 3a A recess 50 is formed in a region overlapping with all regions where wiring layers such as data lines 6a and capacitance lines 3b are formed. For this reason, on the surface of the transparent substrate 20, a region corresponding to an opening region where the semiconductor film 30a and the wiring layer are not formed in each pixel is a region that is one step higher than the region where the concave portion 50 is formed. I have.

However, the semiconductor film 30a, the gate insulating film 41, the scanning line 3a, the capacitance line 3b,
The interlayer insulating films 14 and 17 are formed, and the concave portion 50 is filled with these films. Moreover, the semiconductor film 30
a, the gate insulating film 41, the scanning line 3a, the capacitor line 3b, etc. are formed only inside the concave portion 50, and the total thickness of the region where the concave portion 50 is formed is the film thickness in the opening region. Is larger than the sum of Moreover, the depth of the recess 50 is determined by the difference between the sum of the film thicknesses in the regions where the semiconductor film 30a and the wiring layers are formed and the sum of the film thicknesses in the regions where the semiconductor films 30a and the wiring layers are not formed. The optimum value is set based on the sum of these film thicknesses so that the step caused by the difference can be eliminated. In the present embodiment, the depth of the concave portion 50 is from about 0.1 μm to about 2.
It is set in a range up to 0 μm. Therefore, in the TFT array substrate 2, the uppermost layer (the surface of the alignment film 18)
Has no large steps.

In the present embodiment, the concave portion 50 has a side wall portion 52 formed of a tapered surface rising from the bottom portion 51 at an angle of 45 ° or more. In addition, the opening edge 5 of the concave portion 50
No. 3 has a curved cross-sectional shape and is not an angular shape. Therefore, even when the wiring layers such as the scanning lines 3a, the data lines 6a, and the capacitance lines 3b are drawn out from the inside of the concave portion 50, the side wall portions 52 of the concave portion 50 are formed.
There is no disconnection at the opening edge 53. Further, since such a wiring layer is formed by patterning a conductive film formed on the entire surface of the TFT array substrate 2 in a manufacturing process of the TFT array substrate 2, the conductive film remains in an unnecessary region. Causes short circuit. However, in the present embodiment, since the side wall 52 of the concave portion 50 has a tapered surface obliquely upward and the opening edge 53 is not angular, the conductive film which is unnecessary for the side wall 52 and the like as a shadow of the opening edge 53 is formed. Will not remain.

In this embodiment, as shown in FIGS. 4 and 5, the first storage capacitor electrode 15
a is formed over the bottom portion 51 of the recess 50 and the tapered side wall portion 52.
The capacitance line 3b is formed wider than 5a. Therefore, when compared with the same projection area, the first storage capacitor electrode 15a and the capacitor line 3b are compared with the configuration in which the first storage capacitor electrode 15a and the capacitor line 3b face each other only at the bottom 51 of the concave portion 50. Have a large opposing area. Therefore, the capacitance element 15 has a large capacitance despite being formed in a small area in the pixel.

As described above, in the electro-optical device 1 of the present embodiment, the data lines 6a, the scanning lines 3a, the capacitance lines 3b, and the TF
A recess 5 having a predetermined depth is formed below the region where T30 is formed.
Since 0 is formed, the uppermost side (the surface of the alignment film 18) of the region where these wiring layers and the like are formed is flat with respect to the uppermost side (the surface of the alignment film 18) in the opening region of the pixel. Be transformed into Moreover, in the present embodiment, the data line 6
a, the scanning line 3a, the capacitance line 3b, and the TFT 30 are overlapped with each other, so that a concave portion 50 having a depth equal to the sum of the film thicknesses is formed in a region where the stacked body composed of these various wiring layers and the TFT 30 is thickest. Therefore, the thickest region is almost completely flattened with respect to the opening region. As a result, on the uppermost layer side of the TFT array substrate 2, there is no step between the region where the TFT 30 and various wiring layers are formed and the opening region where these thin films are not formed, and the entire surface is flat. Therefore, a polyimide film for forming the alignment film 18 can be formed flat on the uppermost layer side of the TFT array substrate 2. Therefore, T
Since the rubbing process can be properly performed on the FT array substrate 2, after the TFT array substrate 2 and the opposing substrate 7 are bonded to each other, an electro-optical material such as liquid crystal is sealed between the substrates. Are properly oriented. Therefore, disclination of the electro-optical material does not occur, so that the image quality does not deteriorate due to the disclination. Further, it is not necessary to narrow the opening area in order to prevent the influence of disc clination from affecting the opening area, so that a bright display can be performed. Therefore,
In the display device using the electro-optical device 1 of the present embodiment, high-quality display can be performed, such as improvement in contrast and high definition of display.

Although the method of manufacturing the electro-optical device 1 according to the present embodiment will be described later, since the concave portion 50 is formed only below the wiring layer and the pixel switching TFT 30, the concave portion 50 is formed at an early stage of the manufacturing process. After that, various processes such as a CVD process, a sputtering process, a photolithography process, and an etching process can be performed under substantially the same or exactly the same conditions as in the past. Therefore, the wiring layer and the pixel switching TFT
There is no need to add a new step to form 30;
Further, there is no need to complicate the process. Further, since it is not necessary to perform a troublesome process of changing the thickness of the interlayer insulating film in each region, productivity does not decrease. further,
Unlike the configuration in which the thickness of the interlayer insulating film is increased or reduced in each region, the interlayer insulating films 14, 1
If the film thickness of 7 is constant in the entire region, the problem that cracks occur due to the thick interlayer insulating film and the problem that the back channel occurs due to the thin interlayer insulating film do not occur, so that the reliability is low. It does not drop.

In this embodiment, the side wall 52 of the recess 50 formed in the TFT array substrate 1 is formed in a tapered shape, and the opening edge 53 is not square. Therefore, as will be described later, the pixel switching TF is formed on the concave portion as
Even when T30 or each wiring layer is formed, unlike the case where the side wall portion 52 has a concave portion without a taper or the side wall portion 52 has a concave portion with an inverse taper, even if the wiring layer is routed across the side wall portion 52, No disconnection or the like occurs and the recess 5
No foreign matter such as a polysilicon film or a resist remains inside the zero. For this reason, the uppermost layer side of the TFT array substrate 2 can be reliably flattened, and no trouble or the like due to foreign matter remaining inside the concave portion 50 occurs.

Since the region where the TFT 30 and the wiring layer are formed has some irregularities, the height of the alignment film 18 in any of these regions is adjusted to the height of the alignment film 18 in the opening region. Is optional. For example,
The height of the alignment film 18 above the capacitor 15 may be adjusted to the height of the alignment film 18 in the opening region, or the alignment film in the upper layer of the scanning line 3a or the capacitor line 3b outside the region where the TFT 30 is formed. The height of 18 may be adjusted. Furthermore, it is arbitrary which region of the TFT array substrate 2 is concavely recessed.
The recess may be formed only in the region facing the TFT a, or the recess may be formed only in the region facing the TFT 30. In any case, if at least a recess is formed in a region deviating from the opening region, an effect of flattening according to the formation region and the depth of the recess can be obtained. Therefore, the depth of the depression to be formed in which region is determined by the required pixel aperture ratio (the ratio of the pixel opening region to the non-opening region), the definition, and the yield. It is set to the optimum condition taking into account.

(Method of Manufacturing Electro-Optical Device) A method of manufacturing the electro-optical device 1 according to the present embodiment will be described with reference to FIGS. 6 to 9 show TFs according to the present embodiment.
FIG. 3 is a process sectional view illustrating a method for manufacturing a T-array substrate, and FIG.
2 corresponds to the section taken along the line AA ′ in FIG.

First, as shown in FIG. 6A, a transparent substrate 20 made of a quartz substrate serving as a base of the TFT array substrate 2 is formed.
Is prepared, a resist mask 55 is formed on the surface of the transparent substrate 20.

Next, dry etching such as reactive etching or reactive ion beam etching is performed on the surface of the transparent substrate 20 through the opening of the resist mask 55 to form each wiring layer and TFT in the image display area. For a predetermined non-opening area (see FIGS. 2, 3, 4 and 5), a recess 5 having no taper or having a small taper.
0 is formed.

Here, the transparent substrate 20 is 1 mm, for example.
It has a thickness of the order of magnitude, and no problem arises even if the recess 50 of about several microns is formed for planarization.
At this time, according to the experiment of the present inventor, for example, SF ₆ /
In the case of performing dry etching using CHF ₃ gas, if the mixing ratio is 14/112, the etching rate is 5290 Å / min (Å / Å).
), The etching rate is 5169 angstroms / min when the mixing ratio is 17/90, and the etching rate is 4297 angstroms / min when the mixing ratio is 23/67. That is, SF ₆ / CHF
By adjusting the mixing ratio of the _three gases, a desired etching rate can be obtained, so that the concave portion 50 having a desired depth can be formed. In particular, when the recess 50 is formed by performing anisotropic etching such as reactive etching or reactive ion beam etching,
Can be formed in the same shape as the above pattern.

After the concave portion 50 having no taper is formed by the dry etching process as described above, the concave portion 50 is subsequently subjected to wet etching at a low etching rate of, for example, about 780 angstroms / min, as shown in FIG. The side wall portion 52 of 50 is tapered. At this time, the opening edge 53 of the concave portion 50 is also gently etched, so that there is no corner. By forming the recess 50 in which the side wall 52 is tapered, the recess 50 is formed.
After forming a polysilicon film and resist in the post process,
When these are removed, the polysilicon film and the resist do not remain as foreign matter in the recess 50 without being etched or peeled off. Therefore, the yield of the TFT array substrate 2 is not reduced, and unnecessary unevenness is not formed later.

In order to form the side wall portion 52 of the concave portion 50 into a tapered shape only by dry etching, the resist mask 55 may be retreated during etching and dry etching may be performed again.

Preferably, the transparent substrate 20 is annealed in an inert gas atmosphere such as N ₂ (nitrogen) and at a high temperature of about 900 to 1300 ° C., and the transparent substrate 20 is subjected to a high-temperature process performed later. Pre-processing is performed so that the generated distortion is reduced. That is, before forming the concave portion 50, the transparent substrate 20 is heat-treated at the same temperature or at a temperature higher than the highest temperature in the manufacturing process.

The TFT array substrate 2 may be formed by subjecting a silicon substrate, hard glass, or the like to the above-described etching process or annealing process instead of the transparent substrate 20 made of quartz.

Further, the alignment (alignment) of the transparent substrate 20 in a masking step or the like performed thereafter.
For example, in this step, simultaneously with the concave portion 50, a concave portion for alignment (a concave portion for alignment) is formed at a predetermined position on the transparent substrate 20 on the TFT array substrate 2 side, and the concave portion is recognized by interference of light or the like. It can be performed by:

Next, as shown in FIG.
0 to about 450-550 ° C., preferably about 500 ° C.
Flow rate of about 400 to 600 cc /
The semiconductor film 30a made of an amorphous silicon film is formed by low-pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa) using a monosilane gas, a disilane gas, or the like.
To form Then, in a nitrogen atmosphere, about 600 to 70
By performing an annealing process at 0 ° C. for about 1 to 10 hours, preferably 4 to 6 hours, the polysilicon film 1 is
The solid phase is grown to a thickness of 00 to 2000 angstroms, preferably about 1000 angstroms.

At this time, when an n-channel TFT is formed as the pixel switching TFT 30 described with reference to FIG. 3, the semiconductor film 30a is formed in order to perform channel doping on at least a region corresponding to the channel region. Sb (antimony), As (arsenic), P (phosphorus)
, Etc., is slightly doped by ion implantation or the like. In addition, a TF for pixel switching
When T30 is a p-channel type, B (boron),
A dopant of a group III element such as Ga (gallium) or In (indium) may be slightly doped by ion implantation or the like. Note that the semiconductor film 30 made of a polysilicon film is formed without using an amorphous silicon film by a low pressure CVD method or the like.
a may be directly formed. Alternatively, a semiconductor film 30a made of a polysilicon film is formed by implanting silicon ions into a polysilicon film deposited by a low-pressure CVD method or the like to make the film amorphous once (amorphization), and then recrystallizing the film by annealing or the like. May be. As a method for solid phase growth, annealing treatment using RTA (Rapid Thermal Anneal) or laser annealing such as excimer laser may be used.

Next, as shown in FIG. 6D, the semiconductor film 30 is formed by a photolithography process, an etching process, and the like.
a is patterned in an island shape. Here, as described with reference to FIG. 2, the semiconductor film 30a extends to the region where the capacitance line 3b is formed below the data line 6a and the region where the capacitance line 3b is formed along the scanning line 3a. And a first storage capacitor electrode 15a is formed.

Next, as shown in FIG. 7A, the entire semiconductor film 30a constituting the pixel switching TFT 30 is thermally oxidized at a temperature of about 900 to 1300.degree. C., preferably at a temperature of about 1000.degree. Forming a relatively thin 300 Å thick thermal oxide silicon film;
Furthermore, a high-temperature silicon oxide film (HTO
Gate insulating film 4 having a multilayer structure by depositing a relatively thin film of about 500 Å or silicon nitride film.
Form one. When this gate insulating film 41 is formed,
The insulating film formed on the surface of the first storage capacitor electrode 15a is used as a dielectric film of the capacitor 15. When the gate insulating film 41 is formed in this manner, the thickness of the semiconductor film 30a is about 300 to 1500 angstroms, preferably about 350 to 500 angstroms, and the thickness of the gate insulating film 41 is About 200 to 1500 angstroms thickness, preferably about 300 to 1000
Angstrom thick. By shortening the high-temperature thermal oxidation time in this way, warpage due to heat can be prevented particularly when a large substrate of about 8 inches is used. However, the gate insulating film 41 having a single-layer structure may be formed only by thermally oxidizing the semiconductor film 30a made of a polysilicon film.

The timing of the introduction is not particularly limited. For example, a portion of the semiconductor film 30a to be the first storage capacitor electrode 15a is doped with P ions at a dose of about 3 × 10 ¹⁴ / cm ^2. Therefore, the resistance may be reduced.

Next, as shown in FIG.
After depositing the polysilicon layer 300 (semiconductor film) by a method or the like, phosphorus (P) is thermally diffused to make the polysilicon film 300 conductive. Alternatively, a doped silicon film may be formed by introducing an impurity at the same time as forming the polysilicon film 300 with P ions.

Next, as shown in FIG. 7C, a capacitor line 3b is formed together with the scanning line 3a having the pattern shown in FIG. 2 by a photolithography process using a resist mask, an etching process, and the like. In this etching step, in this embodiment, as shown in FIGS. 2 to 5, the capacitance line 3b is formed to be slightly wider than the semiconductor film 3a. The layer thickness of these capacitance lines 3b (scanning lines 3a) is
For example, about 3500 angstroms.

Next, as shown in FIG. 7D, when the pixel switching TFT 30 is an n-channel TFT having an LDD structure, a scanning line is first formed in the semiconductor film 30a to form a low concentration region. A dopant of a group V element such as P is doped at a low concentration (for example, P ions at a dose of 1 to 3 × 10 ¹³ / cm ² ) using 3a (gate electrode) as a diffusion mask. Thus, the semiconductor film 30a below the scanning line 3a becomes the channel region 33a. The resistance of the capacitance line 3b and the scanning line 3a is also reduced by the impurity doping.

Subsequently, as shown in FIG. 7E, in order to form a high-concentration source / drain region constituting the pixel switching TFT 30, a resist mask 56 wider than the scanning line 3a is used to form the scanning line 3a. After being formed so as to cover, a dopant 61 of a group V element such as P is also doped at a high concentration (for example, P ions at a dose of 1 to 3 × 10 ¹⁵ / cm ² ). The resistance of the capacitance line 3b and the scanning line 3a is further reduced by the doping of the impurity.
Here, when the pixel switching TFT 30 is a p-channel type, a dopant of a group III element such as B is added to the semiconductor film 30a in order to form a low concentration source / drain region and a high concentration source / drain region. And dope. Note that a TFT having an offset structure may be used without performing low-concentration doping, or a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, or the like using the scanning line 3a as a mask.

In parallel with these steps, an n-channel type T
Circuits such as a data line driving circuit and a scanning line driving circuit having a complementary structure composed of an FT and a p-channel TFT are formed in a peripheral portion on the TFT array substrate 2. As described above, in the present embodiment, since the semiconductor film 30a of the pixel switching TFT 30 is formed of polysilicon, the data line driving circuit and the scanning line driving circuit can be formed in substantially the same steps when forming the pixel switching TFT 30. This is advantageous in manufacturing.

Next, as shown in FIG. 8A, an NSG (North-Semiconductor Transistor) is applied to cover the pixel switching TFT 30, the scanning line 3a, and the capacitance line 3b by using, for example, normal pressure or low pressure CVD or TEOS gas. A non-doped silicate glass), a silicate glass film such as a PSG (phosphorus silicate glass), a BSG (boron silicate glass), a BPSG (boron phosphorus silicate glass), an interlayer insulating film 14 made of a silicon nitride film, a silicon oxide film, or the like is formed. . The thickness of the interlayer insulating film 14 is about 5,000 to 15,000.
Angstrom is preferred.

Next, an annealing process at about 1000 ° C. is performed for about 20 minutes to activate the high-concentration source region 31c and the high-concentration drain region 32c. Then, as shown in FIG. Contact hole 5
It is formed by dry etching such as reactive etching or reactive ion beam etching or by wet etching. In addition, contact holes for connecting the scanning lines 3a and the capacitance lines 3b to a wiring layer (not shown) are also formed in the interlayer insulating film 14 in the same process as the contact holes 5.

Next, as shown in FIG. 8C, a low-resistance metal such as Al or a metal silicide having a light-shielding property is formed on the interlayer insulating film 14 by sputtering or the like to form a metal film 6.
After deposition to a thickness of 000-5000 angstroms, preferably about 3000 angstroms, FIG.
As shown in FIG. 7, the data line 6a is formed by a photolithography process, an etching process, and the like.

Next, as shown in FIG.
a, NSG, PSG, BSG, BSG
An interlayer insulating film 17 made of a silicate glass film such as PSG, a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the interlayer insulating film 17 is preferably about 5,000 to 15,000 angstroms.

Next, as shown in FIG. 9B, the high-concentration drain region 32c of the Is formed in a region corresponding to the above.

Next, as shown in FIG. 9C, a transparent conductive thin film 9 such as an ITO film is deposited on the interlayer insulating film 17 by sputtering or the like to a thickness of about 500 to 2,000 angstroms. Thereafter, as shown in FIG. 9D, a pixel electrode 9a is formed by a photolithography step, an etching step, or the like. When forming the reflection type electro-optical device 1, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.

Subsequently, after applying a coating liquid for a polyimide-based alignment film on the pixel electrode 9a, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction, thereby obtaining a structure shown in FIG. The alignment film 18 is formed as shown in FIG. Thus, the TFT array substrate 2 is formed.

As described above, in the present embodiment, when forming the TFT array substrate 2, the uppermost layer is formed flat, but the recess 50 is formed only below the wiring layer and the pixel switching TFT 30. So
If the concave portion 50 is formed at an early stage of the manufacturing process, thereafter, various processes such as a CVD process, a sputtering process, a photolithography process, and an etching process are performed under substantially the same or exactly the same conditions as the conventional process. Can be. Therefore, it is not necessary to add a new process for forming the wiring layer and the pixel switching TFT 30, and
There are advantages that there is no need to complicate the process and that productivity does not decrease.

On the other hand, in order to form the counter substrate 7 shown in FIG. 3, first, a transparent substrate 30 such as a glass substrate or a quartz substrate is prepared. Next, with respect to the transparent substrate 30,
For example, after a metal chromium film is formed by sputtering, a light-shielding film 72 corresponding to each pixel is formed in a matrix by a photolithography process, an etching process, and the like, and a light-shielding film for parting-off as a peripheral parting for an image display area is formed. Form. The light-shielding film 72 is not limited to a metal chromium film, but may be a metal material such as Ni (nickel) or Al (aluminum), or a resin black obtained by dispersing Si (silicon), carbon or Ti (titanium) in a photoresist. Or the like.

Next, a transparent conductive thin film of ITO or the like is applied to the entire surface of
The counter electrode 71 is formed by depositing to a thickness of 00 Å. Further, after applying a coating liquid for a polyimide-based alignment film on the entire surface of the counter electrode 71, a rubbing treatment is performed so as to have a predetermined pretilt angle and in a predetermined direction, thereby forming an alignment film 73. Thus, the opposing substrate 7 is formed.

Thereafter, the TFT array substrate 2 and the opposing substrate 7 are pasted together with a sealing material so that the alignment films 18 and 73 face each other, and a plurality of types of, for example, a plurality of types are placed in the gap between the substrates by vacuum suction or the like. The electro-optical material obtained by mixing the above-mentioned nematic electro-optical material is decompressed and injected to form the electro-optical material layer 11.

In the above-described manufacturing method, the surface of the interlayer insulating film 17 may be more completely flattened by performing a CMP process or a spin coating process (SOG) on the surface of the interlayer insulating film 17. With such planarization, disclination (poor alignment) of the electro-optical material caused by unevenness of the surface of the interlayer insulating film 17 can be more completely prevented according to the degree of the planarization. Even when such processing is performed, in the electro-optical device 1 of the present embodiment, T
Since the steps on the upper surface of the interlayer insulating film 17 are considerably reduced by the concave portions 50 formed in the FT array substrate 2, such a step of achieving more complete global planarization (CMP)
There is an advantage that processing or spin coating processing can be performed under simple processing conditions.

[Embodiment 2] FIGS. 10 and 11 are cross-sectional views showing the configuration of an electro-optical device according to this embodiment. Here, the basic configuration of the electro-optical device of the present embodiment is as follows.
Since the configuration is the same as that of the electro-optical device according to the first embodiment, the basic configuration is as shown in FIGS. 1, 2, and 3. Therefore, only the characteristic portions of this embodiment will be described with reference to FIGS. 10 and 11, and the common portions will be denoted by the same reference numerals and shown in FIGS. Omitted. FIGS. 10 and 11 correspond to cross-sectional views taken along line BB ′ and line CC ′ in FIG. 2, respectively, of the cross section of the electro-optical device of the present embodiment.

As shown in FIGS. 10 and 11, in this embodiment, as in the first embodiment, when forming the capacitance element 15 for adding a storage capacitor to the pixel electrode 9a, the gate insulating film 41 is connected to the scanning line 3a. A first storage capacitor electrode 15a is formed by extending a semiconductor film 30a to extend from a position opposite to the first storage capacitor electrode 15a, and a capacitance line 3b is formed to face the first storage capacitor electrode 15a. Also in this embodiment, since the uppermost layer side of the TFT array substrate 2 is flattened, the transparent substrate 20
A concave portion 50 is formed on the surface of the substrate, and the scanning line 3a, the capacitor line 3b, and the pixel switching TF are formed inside the concave portion 50.
A semiconductor film 30a for forming T30 and the first storage capacitor electrode 15a of the capacitor 15 is formed. Further, also in the present embodiment, the concave portion 50 has the bottom portion 51 and the bottom portion 51 to 4.
A tapered side wall 52 is provided that rises obliquely at an angle of 5 °.

In this embodiment, the width dimension of the capacitance line 3b is
It is slightly narrower than the width dimension of the first storage capacitor electrode 15a, and does not protrude from both sides of the first storage capacitor electrode 15a. Nevertheless, also in the present embodiment, the first storage capacitor electrode 15a constituting the capacitance element 15 is formed over the bottom 51 of the recess 50 and the tapered side wall 52, and the capacitance line 3 is also formed on the bottom 51 of the recess 50 and the tapered portion. Is formed over the side wall portion 52 of FIG. That is, the capacitance element 15 is formed using the tapered side wall 52 of the recess 50. Therefore, also in the present embodiment, as in the first embodiment, when compared with the same projected area, compared with the configuration in which the first storage capacitor electrode 15a and the capacitor line 3b are opposed only by the bottom 51 of the concave portion 50, The facing area between the first storage capacitor electrode 15a and the capacitor line 3b is large. Therefore, the capacitance element 15 has a large capacitance despite being formed in a small area in the pixel.

[Third Embodiment] In the first embodiment, the surface of the transparent substrate 20, which is the base of the TFT array substrate 2, is directly etched to form a lower layer of the pixel switching TFT 30 and a data line. 6a, scanning line 3
Although the concave portion 50 is formed on the lower layer side of the wiring layer such as the capacitor line 3a and the capacitor line 3b, the concave portion may be formed on the insulating film formed on the surface of the transparent substrate 20 as described below.

FIG. 12 is a cross-sectional view of the electro-optical device according to the present embodiment when cut at a position corresponding to line BB 'in FIG. Note that the basic configuration of the electro-optical device of the present embodiment is the same as that of the electro-optical device according to the first embodiment, and the basic configuration is as shown in FIGS. 1, 2, and 3. . Therefore, only the characteristic portions of the present embodiment will be described with reference to FIG. 12, and the common portions will be denoted by the same reference numerals and shown in FIG. 12, and the description thereof will be omitted.

As shown in FIG. 12, in this embodiment, the TFT
A thick base insulating film 200 is formed on the surface of the transparent substrate 20, which is the base of the array substrate 2, and the pixel switching TFT 30 (see FIGS. 2 and 3) and the capacitive element are formed on the surface of the base insulating film 200. The recess 50 is formed on the lower layer side of the semiconductor film 30a for forming the semiconductor layer 15 and on the lower layer side of the wiring layer such as the data line 6a, the scanning line 3a, and the capacitor line 3b. As the base insulating film 200, a highly insulating glass such as NSG, PSG, BSG, or BPSG, a silicon oxide film, a silicon nitride film, or the like can be used. Other configurations are the same as those in the first and second embodiments, and thus description thereof is omitted.

In the electro-optical device using the TFT array substrate 2 configured as described above, the data lines 6a, the scanning lines 3a, the capacitance lines 3b and the TF
Since the concave portion 50 having a predetermined depth is formed below the region where the T30 and the like are formed, the uppermost side (the surface of the alignment film 18) of the region where these wiring layers and the like are formed is a pixel. Uppermost layer side of opening region (surface of alignment film 18)
The height is equivalent to that of, and there is no large step. Therefore, TF
Since the uppermost layer side of the T array substrate 2 is entirely flat, the uppermost layer side of the TFT array substrate 2
A polyimide film for forming the alignment film 18 can be formed flat. Therefore, since the rubbing process can be properly performed on the TFT array substrate 2, when the TFT array substrate 2 is bonded to the counter substrate 7 and an electro-optical material such as a liquid crystal is sealed between the substrates, The electro-optic material is properly oriented. For this reason, no disclination of the electro-optical material occurs, so that the same effects as those of the first embodiment can be obtained, for example, there is no deterioration in image quality caused by the disclination.

In this embodiment, the pixel switching T
Although the FT 30 is formed inside the concave portion 50, since the underlying insulating film 200 is interposed between the lower substrate and the transparent substrate 20, impurities from the transparent substrate 20 are removed from the pixel switching TFT 30. Has no effect on

In order to manufacture the TFT array substrate 2 having such a configuration, one of the methods of manufacturing the TFT array substrate 2 according to the first embodiment described with reference to FIGS. 12B, a thick base insulating film 200 is formed on the surface of the transparent substrate 20 as shown in FIG. 12 and then the same as the resist mask 55 shown in FIG. A resist mask having a pattern is formed, and then the surface of the base insulating film 200 is etched under predetermined conditions to form a concave portion 50. Thereafter, the steps after the step described with reference to FIG. 6C may be performed.

[Embodiment 4] FIG. 13 is a cross-sectional view of the electro-optical device of the present embodiment, taken along a line corresponding to line BB 'in FIG. Note that the basic configuration of the electro-optical device of the present embodiment is the same as that of the electro-optical device according to the first embodiment, and the basic configuration is as shown in FIGS. 1, 2, and 3. . Accordingly, only the characteristic portions of the present embodiment will be described with reference to FIG. 13, and the common portions will be denoted by the same reference numerals and shown in FIG.

In the first and third embodiments, the recess 50 is formed in the TFT array substrate 2 below the pixel switching TFT 30 and below the wiring layer such as the data line 6a, the scanning line 3a, and the capacitor line 3b. After this, this recess 5
Although the semiconductor film 30a and the scanning line 3a are formed directly inside the substrate 0, in this embodiment, as shown in FIG. A thin insulating film 201 is formed, and thereafter, a semiconductor film 30a, a scanning line 3a, and the like are formed on the surface of the insulating film 201.

Therefore, in the present embodiment, the bottom 51 of the recess 50 is formed.
The semiconductor film 30a, the scanning line 3a, and the like are formed in the concave portion 50 in a state where the side wall portion 52 is covered with the thin insulating film 201. For this reason, even if the inner surface of the concave portion 50 is rough when the surface of the transparent substrate 2 is etched to form the concave portion 50, since the surface is covered with the insulating film 201, the semiconductor is directly formed on the inner surface of the rough concave portion 50. Unlike the case where the film 30a (the active layer of the pixel switching TFT 30) and the like are formed, the surface state of the inner surface of the concave portion 50 is changed to the pixel switching TFT 30.
It does not affect the transistor characteristics of the FT 30, for example, the threshold voltage (Vth). Therefore, in the TFT array substrate 2 of the present embodiment, there is no deterioration in characteristics such as drift of the threshold voltage of the TFT, decrease in mobility in the active layer, increase in off-leak, and the like.
The reliability is not reduced even if the pits are formed.

In this embodiment, the pixel switching T
Although the FT 30 is formed inside the concave portion 50, since the underlying insulating film 200 is interposed between the lower substrate and the transparent substrate 20, impurities from the transparent substrate 20 are removed from the pixel switching TFT 30. Has no effect on

[Embodiment 5] FIG. 14 is a cross-sectional view of the electro-optical device according to the present embodiment, taken along a line corresponding to line BB 'in FIG. Note that the basic configuration of the electro-optical device of the present embodiment is the same as that of the electro-optical device according to the first embodiment, and the basic configuration is as shown in FIGS. 1, 2, and 3. . Accordingly, only the characteristic portions of the present embodiment will be described with reference to FIG. 13, and the common portions will be denoted by the same reference numerals and shown in FIG.

Although the fourth embodiment has a configuration corresponding to an improved example of the first embodiment, a similar improvement is made in the third embodiment.
It can also be applied to That is, as shown in FIG. 14, in the present embodiment, in the TFT array substrate 2, after a thick insulating film 200 is formed on the surface of the transparent substrate 20, the TFT for pixel switching is formed on the surface of the insulating film 200.
After forming the concave portion 50 on the lower layer side of the wiring layer such as the data line 6a, the scanning line 3a, and the capacitor line 3b,
Forming a thin insulating film 201 on the entire surface of the transparent substrate 20;
Thereafter, the semiconductor film 30a and the scanning lines 3a are formed on the surface of the insulating film 201.

Therefore, in the present embodiment, the bottom 51 of the recess 50 is formed.
The semiconductor film 30a, the scanning line 3a, and the like are formed in the concave portion 50 in a state where the side wall portion 52 is covered with the thin insulating film 201. For this reason, even if the inner surface of the concave portion 50 is rough when the surface of the transparent substrate 2 is etched to form the concave portion 50, since the surface is covered with the insulating film 201, the semiconductor is directly formed on the inner surface of the rough concave portion 50. Unlike the case where the film 30a (the active layer of the pixel switching TFT 30) and the like are formed, the surface state of the inner surface of the concave portion 50 is changed to the pixel switching TFT 30.
It does not affect the transistor characteristics of the FT 30, for example, the threshold voltage (Vth). Therefore, in the TFT array substrate 2 of the present embodiment, there is no deterioration in characteristics such as drift of the threshold voltage of the TFT, decrease in mobility in the active layer, increase in off-leak, and the like.
The reliability is not reduced even if the pits are formed.

Sixth Embodiment An electro-optical device according to a sixth embodiment of the present invention will be described with reference to FIGS. FIG. 15 is a plan view showing a part of a plurality of adjacent pixel groups of a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in the electro-optical device of the present embodiment. FIG. 16 is a sectional view taken along the line DD ′ of FIG. Since the basic configuration of the electro-optical device according to the present embodiment is the same as that of the electro-optical device according to the first embodiment, only the characteristic portions of the present embodiment will be described with reference to FIGS. 15 and FIG. 16 are denoted by the same reference numerals, and the description thereof is omitted.

In the first to fifth embodiments described above,
In forming the capacitive element 15 that adds a storage capacitor to the pixel electrode 9a, the semiconductor film 30a is extended to form the first storage capacitor electrode 15a, and the first storage capacitor electrode 1a is formed.
Although the capacitor line 3b is formed so as to face the semiconductor film 30a, as shown in FIGS.
The high-concentration drain region 32c of a extends along the data line 6a toward the preceding scanning line 3a, and a region overlapping the lower layer of the preceding scanning line 3a is the first storage capacitor electrode 15a. Even with such a configuration, the first storage capacitor electrode 15
The capacitive element 14 is formed so as to oppose the portion a where the gate insulating film 41 extends to this region as a dielectric film and the scanning line 3a in the preceding stage.

Also in this embodiment, in the TFT array substrate 2, in the region surrounded by the thick line L 1 in FIG. 15, a concave portion 50 recessed on the side of the transparent substrate 20 of the TFT array substrate 2 as shown in FIG. Is formed. This recess 50 also
As in the first embodiment, in the image display area where a large number of pixel electrodes 9a are formed on the TFT array substrate 2, the area where the pixel switching TFT 30 is formed, and the wiring layers such as the scanning lines 3a and the data lines 6a are formed. The semiconductor film 30a and the gate insulating film 4 are formed in a region overlapping with all the
1. The scanning line 3a and the interlayer insulating films 14 and 17 are formed, and the concave portion 50 is filled with these films. Moreover, the semiconductor film 30a, the gate insulating film 41, the scanning line 3a,
The capacitance line 3b and the like are formed only inside the concave portion 50, and the total thickness of the region where the concave portion 50 is formed is larger than the total thickness of the opening region. For example, it has a configuration similar to that of the first embodiment.

Therefore, also in the electro-optical device 1 of this embodiment, the data lines 6a and the scanning lines 3 are provided on the TFT array substrate 2.
Since a concave portion 50 having a predetermined depth is formed below the region where the TFT 30 is formed, the uppermost side (the surface of the alignment film 18) of the region where these wiring layers and the like are formed is a pixel. (The alignment film 1)
8 surface). Therefore, a polyimide film for forming the alignment film 18 can be formed flat on the uppermost layer side of the TFT array substrate 2. Therefore, T
Since the rubbing process can be properly performed on the FT array substrate 2, after the TFT array substrate 2 and the opposing substrate 7 are bonded to each other, an electro-optical material such as liquid crystal is sealed between the substrates. Are properly oriented. Therefore, since the disclination of the electro-optical material does not occur, the same effect as that of the first embodiment can be obtained, for example, the image quality does not deteriorate due to the disclination.

In this embodiment, as shown in FIG.
Regarding the first storage capacitor electrode 15 a constituting the capacitor 15, the bottom 51 of the recess 50 and the tapered side wall 52
And the scanning line 3a is formed wider than the first storage capacitor electrode 15a. For this reason, when compared with the same projection area, the first portion is only at the bottom 51 of the concave portion 50.
The opposed area between the first storage capacitor electrode 15a and the scanning line 3a is larger than that in the configuration in which the storage capacitor electrode 15a and the scanning line 3a are opposed. Therefore, the capacitance element 15 has a large capacitance despite being formed in a small area in the pixel.

Seventh Embodiment An electro-optical device according to a seventh embodiment of the present invention will be described with reference to FIGS. FIG. 17 is a plan view showing a part of a plurality of adjacent pixel groups of a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in the electro-optical device according to the present embodiment. , FIG. 19 and FIG.
AA 'sectional view, BB' sectional view, and C-
It is C 'sectional drawing. Since the basic configuration of the electro-optical device according to this embodiment is the same as that of the electro-optical device according to Embodiment 1, only the characteristic portions of this embodiment will be described with reference to FIGS. The common parts are denoted by the same reference numerals and are shown in FIGS. 17 to 20, and the description thereof will be omitted.

As shown in FIGS. 17 to 20, in this embodiment, as in Embodiment 3, a thick base insulating film 200 is formed on the surface of the transparent substrate 20 which is the base of the TFT array substrate 2, and On the surface of the insulating film 200, the lower side of the semiconductor film 30a for forming the pixel switching TFT 30 and the capacitor 15 and the data lines 6a,
A concave portion 50 is formed below the wiring layer such as the scanning line 3a and the capacitor line 3b. Other configurations are the same as those in the first and second embodiments, and thus description thereof is omitted.

In the electro-optical device using the TFT array substrate 2 configured as described above, the data lines 6a, the scanning lines 3a, the capacitance lines 3b and the TF
Since the concave portion 50 having a predetermined depth is formed below the region where the T30 and the like are formed, the uppermost layer of the TFT array substrate 2 is entirely flat. For this reason, in the TFT array substrate 2, a polyimide film for forming the alignment film 18 can be formed flat on the uppermost layer side. Therefore, since the rubbing process can be properly performed on the TFT array substrate 2, when the TFT array substrate 2 is bonded to the counter substrate 7 and an electro-optical material such as a liquid crystal is sealed between the substrates, The electro-optic material is properly oriented.
For this reason, no disclination of the electro-optical material occurs, so that the same effects as those of the first embodiment can be obtained, for example, there is no deterioration in image quality caused by the disclination.

In this embodiment, opaque refractory metals such as Ti and C are formed between the transparent substrate 20 and the base insulating film 200 over the entire region substantially overlapping the concave portion 50.
A light shielding film 16 made of a single metal, alloy, metal silicide, or the like containing at least one of r, W, Ta, Mo, and Pd or Si is formed.
The pixel switching TFTs 30 are opposed to each other. Therefore, the channel region 33a of the pixel switching TFT 30 is covered with the light shielding film 16 when viewed from the back surface side of the TFT array substrate 2. For this reason, in the present embodiment, it is possible to prevent a situation in which return light from the back surface side of the TFT array substrate 2 is incident on the channel region 33a of the pixel switching TFT 30 or the like, and the generation of photocurrent causes the pixel switching TFT 30 The characteristics do not deteriorate.

In this embodiment, the light-shielding film 16 is formed of a high heat-resistant material such as an opaque refractory metal. For this reason, after forming the light-shielding film 16, even if high-temperature processing is performed to form the pixel switching TFT 30, the light-shielding film 16 does not break or melt. Note that a polysilin film may be used as the light shielding film 16. Further, as the light-shielding film 16, a film obtained by forming a polysilicon film on the upper layer of the high melting point metal and performing an anti-reflection treatment may be used.

Further, the base insulating film 200 is formed by forming the semiconductor film 30a constituting the pixel switching TFT 30 as an interlayer insulating film for electrically insulating the light shielding film 16 from the light. The pixel switching TF is formed on the entire surface of the substrate 2.
It also has a function as a base film for T30. That is,
It has a function of preventing deterioration of the characteristics of the pixel switching TFT 30 due to roughening of the surface of the TFT array substrate 2 during polishing, dirt remaining after cleaning, and the like. Also, the base insulating film 1
6 can prevent the light shielding film 16 from contaminating the pixel switching TFT 30 and the like.

In manufacturing the TFT array substrate 2 having such a configuration, one of the methods for manufacturing the TFT array substrate 2 according to the first embodiment described with reference to FIGS. , (B), the transparent substrate 20 is replaced with a transparent substrate 20 as shown in FIGS.
A metal such as Ti, Cr, W, Ta, Mo and Pd, or a metal alloy film such as metal silicide, by sputtering, to a layer thickness of about 1000 to 5000 angstroms;
After forming a layer having a thickness of preferably about 2,000 angstroms, the layer is patterned by a photolithography step, an etching step or the like to form a light shielding film 16. Here, if a polysilicon film is used as the light-shielding film 16, it is possible to prevent the underlying insulating film 16 formed on the upper layer from being broken by the stress received from the light-shielding film 16.
Next, after forming a thick base insulating film 200 on the surface side of the light shielding film 16, a resist mask having the same pattern as the resist mask 55 shown in FIG. 6A is formed, and then the base insulating film 200 is formed under predetermined conditions. Is etched to form a concave portion 50. Thereafter, the steps after the step described with reference to FIG. 6C may be performed.

In the present embodiment, the light-shielding film 16 is formed over a wide area substantially overlapping with the concave portion 50. The formed structure may be used. With such a configuration, the area of the part where the light-shielding film 16 is integrally formed is much smaller than the case of the light-shielding film provided in a lattice shape or a stripe shape. The stress generated in the light-shielding film 16 due to the difference in physical properties between the light-shielding film and the light-shielding film can be greatly reduced. As a result, film peeling, film deformation, or cracks in the light shielding film 16 can be prevented. In addition, the pixel switching TFT 3 is generated by the stress of the light shielding film 16 itself.
It is possible to prevent a situation where the characteristic of 0 is deteriorated.

Further, the light shielding film 16 may be electrically connected to the constant potential source or the capacitance element 15. For example, the light-shielding film 16 may be electrically connected to the capacitor line 3b at a constant potential via a contact hole. With this configuration, the potential change of the light-shielding film 16 does not adversely affect the pixel switching TFT 30 that is disposed to face the light-shielding film 16. In addition, by setting the capacitance line 3b to a constant potential, the capacitor line 15 can function well as a second storage capacitor electrode. In this case, as the constant potential source, a constant potential source such as a negative power supply or a positive power supply supplied to a peripheral circuit (for example, a scanning line driving circuit, a data line driving circuit, or the like) for driving the electro-optical device, or a ground. A power source, a constant potential source supplied to the counter electrode 71, and the like can be given.

[Eighth Embodiment] An electro-optical device according to an eighth embodiment of the present invention will be described with reference to FIG. FIG.
0 is a cross-sectional view of the TFT array substrate used in the electro-optical device of the present embodiment. Since the basic configuration of the electro-optical device according to the present embodiment is the same as that of the electro-optical device according to Embodiment 7, only the characteristic portions of the present embodiment will be described with reference to FIG. Are assigned the same reference numerals as in FIG.
And their descriptions are omitted. FIG. 21 corresponds to a cross section taken along line BB ′ of FIG.

As shown in FIG. 21, in the present embodiment, as in the first embodiment, on the surface of the transparent substrate 20, which is the base of the TFT array substrate 2, the pixel switching TFT 30 and the capacitor 15 are formed. Concave portions 50 are formed below the semiconductor film 30a and below the wiring layers such as the data lines 6a, the scanning lines 3a, and the capacitor lines 3b. Further, an interlayer insulating film 220 is provided on the surface side of the transparent substrate 20.
Are formed. On the surface of the interlayer insulating film 220,
The shape of the concave portion 50 formed on the surface of the transparent substrate 20 is reflected, and the pixel switching TFT is placed in the reflected concave portion.
30 and semiconductor film 30 for forming capacitive element 15
a and wiring layers such as the scanning lines 3a and the capacitance lines 3b.

In this embodiment, opaque refractory metals such as Ti and C are provided between the transparent substrate 20 and the interlayer insulating film 220 over the entire region substantially overlapping the concave portion 50.
A light-shielding film 16 made of a single metal, alloy, metal silicide, or the like containing at least one of r, W, Ta, Mo, and Pd or Si is formed.
The pixel switching TFTs 30 are opposed to each other. Therefore, the channel region 33a of the pixel switching TFT 30 is covered with the light shielding film 16 when viewed from the back surface side of the TFT array substrate 2. For this reason, also in the present embodiment, it is possible to prevent a situation in which return light from the back surface side of the TFT array substrate 2 is incident on the channel region 33a of the pixel switching TFT 30 or the like, and the generation of a photocurrent causes the pixel switching TFT 30 An effect similar to that of the seventh embodiment is obtained, for example, the characteristics are not deteriorated.

Ninth Embodiment Referring to FIGS. 22 and 23, an electro-optical device according to a ninth embodiment of the present invention will be described. 22 and 23 are cross-sectional views of the TFT array substrate used in the electro-optical device according to the embodiment. Since the basic configuration of the electro-optical device according to the present embodiment is the same as that of the electro-optical device according to the seventh embodiment, only the characteristic portions of the present embodiment will be described with reference to FIGS. The same reference numerals are given to the same parts as those shown in FIGS. 22 and 23, and the description thereof will be omitted. FIGS. 22 and 23 are respectively BB ′ of FIG.
This corresponds to a cross section taken along line C-C '.

As shown in FIGS. 22 and 23, in the present embodiment, the pixel switching TFT 30 and the capacitor 15 are formed on the surface of the transparent substrate 20, which is the base of the TFT array substrate 2, as in the first embodiment. And the data line 6a, the scanning line 3a,
A concave portion 50 is formed below the wiring layer such as the capacitor line 3b.

Here, an interlayer insulating film 230 is formed on the surface of the transparent substrate 20. On the upper layer side of the interlayer insulating film 230, a semiconductor film 30a for forming the pixel switching TFT 30 and the capacitor 15 and wiring layers such as the scanning line 3a and the capacitor line 3b are formed inside the recess 50. . In addition, on the upper layer side of the interlayer insulating film 230, the interlayer insulating film 14 for insulating and separating the scanning line 3a or the capacitance line 3b from the data line 6a is also formed inside the recess 50. For this reason, as shown in FIG. 23, the surface of the interlayer insulating film 14 is considerably flattened in the portion where the capacitive element 15 is formed, and the data line 6a is formed there. Therefore, in this embodiment, the recess 5
0 is closed by the data line 6a, and the capacitor 15 and the like are formed inside the data line 6a.

As shown in FIG. 23, data line 6a
Is defined as LL1 where the opening width of the recess 50 formed on the lower layer side is LL1, and the thicknesses of the interlayer insulating films 230 and 14 formed on the lower layer side of the data line 6a in the recess 50 are ta and t.
b, the following expression is satisfied: W2 <{(LL1-2 · (ta + tb)}. That is, since the side wall 52 of the recess 50 is a tapered surface of about 45 degrees, near the opening of the recess 50, The dimensions occupied by the interlayer insulating films 230 and 14 in the width direction are the same for both sides of the data line 6a.
14 is twice the sum of the thicknesses ta and tb of
From the opening width LL1 of the interlayer insulating films 230 and 14,
When the width dimension W2 of the data line 6a is set to a value equal to or less than a value obtained by subtracting a value obtained by doubling the sum of a and tb, the data line 6a is located at the bottom in the recess formed in the interlayer insulating film 14. , Do not overlap with the tapered side wall. Therefore, on the upper layer side, useless unevenness due to the overlap between the data line 6a and the side wall of the recess does not occur.

Further, the width dimension W1 of the semiconductor film 30a is
The width of the bottom portion 51 of the concave portion 50 formed on the lower layer side is LL.
2, and the thickness of the interlayer insulating film 230 formed below the semiconductor film 30a in the concave portion 50 is ta, and the following expression W1 <(LL2-2 · ta) is satisfied. That is, since the side wall portion 52 of the concave portion 50 is a taper surface of about 45 degrees, the dimension occupied by the interlayer insulating film 230 in the width direction near the bottom of the concave portion 50 is equal to the both sides of the semiconductor film 30a. Film thickness ta
, The width dimension LL2 of the bottom 51 of the recess 50
When the width dimension W1 of the semiconductor film 30a is set to be equal to or less than a value obtained by subtracting a value obtained by doubling the thickness ta of the interlayer insulating film 230 from the above, the semiconductor film 30a is positioned at the bottom in the recess formed in the interlayer insulating film 230. Therefore, it does not overlap with the tapered side wall portion. Therefore, on the upper layer side, useless unevenness due to the overlap between the semiconductor film 30a and the side wall of the recess does not occur.

Therefore, in the TFT array substrate 2 of the present embodiment, since the uppermost layer has almost no irregularities, the polyimide film for forming the alignment film 18 can be formed flat. Therefore, since the rubbing process can be properly performed on the TFT array substrate 2, when the TFT array substrate 2 is bonded to the counter substrate 7 and an electro-optical material such as a liquid crystal is sealed between the substrates, The electro-optic material is properly oriented. For this reason, no disclination of the electro-optical material occurs, so that the same effects as those of the first embodiment can be obtained, for example, there is no deterioration in image quality caused by the disclination.

In this embodiment, opaque refractory metals such as Ti, Cr, W, and the like are formed between the transparent substrate 20 and the interlayer insulating film 230 from the bottom 51 to the side wall 52 inside the recess 50. A light-shielding film 16 made of a single metal, an alloy, a metal silicide, or the like containing at least one of Ta, Mo, and Pd or Si is formed. The light-shielding film 16 faces the pixel switching TFT 30. is there. Therefore, the pixel switching TFT
The 30 channel regions 33a are covered with the light-shielding film 16 when viewed from the back surface side of the TFT array substrate 2. Therefore, also in the present embodiment, the return light from the back side of the TFT array substrate 2 is applied to the channel region 3 of the pixel switching TFT 30.
The same effect as in the seventh embodiment can be obtained, for example, it is possible to prevent the incident light on 3a or the like from occurring, and the characteristics of the pixel switching TFT 30 are not deteriorated by the generation of the photocurrent. In particular, in the present embodiment, since the light-shielding film 16 is formed from the bottom 51 to the side wall 52, even if light is obliquely incident from the back side of the TFT array substrate 2 as shown by an arrow Q in FIG. , Can block such light.

In this embodiment, when the side wall 52 of the recess 50 is not a tapered surface, the width of the semiconductor film 30a, the width of the capacitor line 3b, and the data It is preferable that the width of each of the lines 6a is substantially equal to or smaller than the opening width LL of the recess 50 by 10 μm or less than the opening LL of the recess 50. With this configuration, since the formation regions of the semiconductor film 30a, the capacitance line 3b, and the data line 6a almost completely overlap with the formation region of the recess 50, the side wall 52 of the recess 50 and both ends of the semiconductor film 30a. There is no wide gap between the side wall 52 of the recess 50 and both ends of the capacitor line 3b, and there is no unnecessary overlap between both ends of the data line 6a and the surface of the transparent substrate 20.

[Overall Configuration of Electro-Optical Device] The overall configuration of each embodiment of the electro-optical device configured as described above will be described with reference to FIG. 24 and FIG. Incidentally, FIG.
FIG. 25 is a plan view of the TFT array substrate 2 together with the components formed thereon viewed from the counter substrate 7 side.
FIG. 25 is a cross-sectional view taken along the line HH ′ of FIG. 24 including the counter substrate 7.

In FIG. 24, on the TFT array substrate 2, a sealing material 152 is provided along the edge thereof, and a light shielding film 153 for, for example, peripheral parting is formed in parallel with the inside of the sealing material 152. . The sealing material 152 is a TFT
An adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the array substrate 2 and the opposing substrate 7 around the periphery thereof, and a glass fiber or a glass fiber for setting a distance between the two substrates to a predetermined value. Spacers such as glass beads are mixed. In a region outside the sealing material 152, a data line driving circuit 101 and mounting terminals 102 are provided along one side of the TFT array substrate 2, and a scanning line driving circuit 104 extends along two sides adjacent to this one side. It is provided. If the delay of the scanning signal supplied to the scanning line 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuits 101 may be arranged on both sides along the side of the image display area. For example, the odd-numbered data lines 6a supply an image signal from a data line driving circuit arranged along one side of the image display area, and the even-numbered data lines extend along the opposite side of the image display area. The image signal may be supplied from a data line driving circuit disposed in the same manner. If the data lines 6a are driven in a comb-tooth shape in this manner, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be formed. Further, the TFT array substrate 2
The remaining side has a plurality of wiring layers 105 for connecting between the scanning line driving circuits 104 provided on both sides of the image display area.
Is provided. In at least one of the corners of the counter substrate 7, a vertical conductive material 10 for establishing electrical continuity between the TFT array substrate 2 and the counter substrate 7 is provided.
6 are provided. Then, as shown in FIG. 25, the counter substrate 7 having substantially the same contour as the sealing material 152 shown in FIG.
It is stuck to.

Here, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 2, for example, a TF is mounted on a driving LSI mounted on a TAB (tape automated bonding substrate).
The connection may be made electrically and mechanically via an anisotropic conductive film provided on the peripheral portion of the T array substrate 2. Further, the side of the opposite substrate 7 on which the projected light is incident and T
For example, a TN (twisted nematic) mode, ST
N (super TN) mode, D-STN (double-ST
A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as an N) mode or a normally white mode / normally black mode.

Since the electro-optical device 1 in each of the embodiments described above is applied to a color electro-optical material projector, three electro-optical devices are used as RGB light valves, and each panel has The light of each color separated via the dichroic mirror for RGB color separation is respectively incident as projection light. Therefore, in each of the embodiments, the opposing substrate 7 is not provided with a color filter. However, an RGB color filter may be formed on the opposing substrate 7 in a predetermined region facing the pixel electrode 9a where the light-shielding film 72 is not formed, together with the protective film. In this way, the electro-optical device according to each embodiment can be applied to a color electro-optical device such as a direct-view or reflection-type color electro-optical material television other than the electro-optical material projector. Further, a micro lens may be formed on the counter substrate 7 so as to correspond to one pixel. With this configuration, a bright electro-optical device can be realized by improving the efficiency of collecting incident light. Furthermore, the counter substrate 7
A dichroic filter that produces RGB colors using light interference may be formed by depositing a number of interference layers having different refractive indices thereon. According to the counter substrate with the dichroic filter, a brighter color electro-optical device can be realized.

In the electro-optical device 1 according to each of the embodiments described above, incident light is made to enter from the side of the counter substrate 7 as in the related art, but the light shielding film 16 is formed on the side of the TFT array substrate 2. In this case, the TFT array substrate 2
May be made to enter from the side, and to exit from the side of the counter substrate 7. That is, even if the electro-optical device 1 is attached to the projector in this manner, light can be prevented from being incident on the channel region 33a of the semiconductor film 30a, and a high-quality image can be displayed. Here, conventionally, in order to prevent reflection on the back surface side of the TFT array substrate 2, it has been necessary to separately arrange a polarizing plate coated with an AR coating for antireflection or attach an AR film. However, the back surface of the TFT array substrate 2 and the semiconductor film 30
a at least between the channel region 33a and the like.
When 6 is formed, it is not necessary to use such an AR-coated polarizing plate or AR film, or to use a substrate obtained by performing an AR treatment on the TFT array substrate 2 itself. In addition, since light resistance is excellent, even if a bright light source is used or polarization conversion is performed by a polarizing beam splitter to improve light use efficiency, image quality deterioration such as crosstalk due to light does not occur.

The switching element provided in each pixel has been described as a normal stagger type or coplanar type polysilicon TFT.
The embodiments are also effective for other types of TFTs such as TFTs and amorphous silicon TFTs.

Further, as a switching element of each pixel of the electro-optical device, a two-terminal non-linear element such as a TFD may be used instead of the TFT. In this case, one of the scanning lines and the data lines is provided on a counter substrate to form a stripe-shaped counter electrode, and the other is provided on an element array substrate, and each of the T and T lines is provided.
What is necessary is just to comprise so that it may connect to each pixel electrode via FD element etc.

[Electronic Apparatus] Next, an embodiment of an electronic apparatus including the liquid crystal device 100 described in detail above will be described with reference to FIGS.

First, in FIG. 26, the electro-optical device 1
1 shows a schematic configuration of an electronic device provided with. In FIG.
The electronic device includes a display information output source 1000, a display information processing circuit 1002, a drive circuit 1004, a liquid crystal device 100, a clock generation circuit 1008, and a power supply circuit 1010. The display information output source 1000 is a ROM
(Read Only Memory), RAM (Random Access Memor)
y), a clock generation circuit 100 including a memory such as an optical disk device, a tuning circuit for tuning and outputting an image signal, and the like.
The display information such as an image signal in a predetermined format is output to the display information processing circuit 1002 based on the clock signal from the control unit 8. The display information processing circuit 1002 includes various known processing circuits such as an amplification / polarity inversion circuit, a serial-parallel conversion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and is input based on a clock signal. Digital signals are sequentially generated from the displayed information,
The signal is output to the driving circuit 1004 together with the clock signal CLK.
The drive circuit 1004 drives the liquid crystal device 100. The power supply circuit 1010 supplies a predetermined power to each of the above-described circuits.
Note that the driving circuit 1004 may be mounted on the TFT array substrate constituting the electro-optical device 1, and in addition, the display information processing circuit 1002 may be mounted.

Next, FIGS. 27 to 28 show specific examples of the electronic apparatus configured as described above.

In FIG. 27, a liquid crystal projector 1100, which is an example of an electronic apparatus, prepares three liquid crystal display modules including the electro-optical device 1 in which the above-described drive circuit 1004 is mounted on a TFT array substrate, and each of the modules has an RGB component. It is configured as a projector used as the light valves 100R, 100G, and 100B. In the liquid crystal projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, 3
Light components R, G, and B corresponding to the three primary colors of RGB are divided by the mirrors 1106 and the dichroic mirrors 1108, and the light valve 1 corresponding to each color is separated.
00R, 100G and 100B respectively. At this time, in particular, the B light is guided through a relay lens system 1121 including an entrance lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss due to a long optical path. Then, light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B, respectively, are recombined by the dichroic prism 1112, and then are transmitted to the screen 1 via the projection lens 1114.
120 is projected as a color image.

In FIG. 28, a laptop personal computer (PC) 1200 for multimedia, which is another example of electronic equipment, has the above-described electro-optical device 1 provided in a top cover case, and further includes a CPU,
The keyboard 1202 accommodates a memory, a modem, and the like.
Is provided.

In addition to the electronic devices described with reference to FIGS. 27 to 28, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic organizer, a calculator, a word processor, an engineering machine, etc. A workstation (EWS), a mobile phone, a videophone, a POS terminal, a device having a touch panel, and the like are examples of the electronic device illustrated in FIG.

[0149]

As described above, according to the electro-optical device of the present invention, it is possible to achieve flattening in the image display area using a relatively simple structure, thereby improving productivity and reliability. Without lowering, the occurrence of disclination of the electro-optical material can be reduced, and the pixel opening area can be increased. Therefore, an electro-optical device capable of displaying a bright and high-quality image can be realized.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements and wiring layers provided in a plurality of pixels in a matrix forming an image display area in an electro-optical device according to a first embodiment of the present invention.

FIG. 2 shows a data line,
FIG. 3 is a plan view illustrating a configuration of a pixel on a TFT array substrate on which a scanning line, a pixel electrode, and the like are formed.

FIG. 3 is a sectional view taken along line AA ′ of FIG. 2;

FIG. 4 is a sectional view taken along line BB 'of FIG. 2;

FIG. 5 is a sectional view taken along the line CC ′ of FIG. 2;

FIG. 6 is a process sectional view illustrating the method for manufacturing the electro-optical device illustrated in FIG.

7 is a process cross-sectional view showing each process performed after the process shown in FIG. 6 in the method of manufacturing the electro-optical device shown in FIG.

8 is a process cross-sectional view showing each process performed after the process shown in FIG. 7 in the method of manufacturing the electro-optical device shown in FIG.

9 is a process cross-sectional view showing each process performed after the process shown in FIG. 8 in the method of manufacturing the electro-optical device shown in FIG.

FIG. 10 is a cross-sectional view of the electro-optical device according to the second embodiment of the present invention at a position corresponding to line BB ′ in FIG.

11 is a cross-sectional view of the electro-optical device according to the second embodiment of the present invention at a position corresponding to line CC ′ in FIG.

FIG. 12 is a cross-sectional view of the electro-optical device according to Embodiment 3 of the present invention at a position corresponding to line BB ′ in FIG.

FIG. 13 is a cross-sectional view of the electro-optical device according to Embodiment 4 of the present invention at a position corresponding to line BB ′ in FIG.

FIG. 14 is a cross-sectional view of the electro-optical device according to Embodiment 5 of the present invention at a position corresponding to line BB ′ in FIG. 2;

FIG. 15 is a sectional view of a T-type optical device according to a sixth embodiment of the present invention, in which data lines, scanning lines, pixel electrodes, and the like are formed.
FIG. 3 is a plan view illustrating a configuration of a pixel on the FT array substrate.

FIG. 16 is a sectional view taken along the line DD ′ of FIG. 15;

FIG. 17 is a cross-sectional view of the electro-optical device according to Embodiment 7 of the present invention, in which a data line, a scanning line, a pixel electrode, and the like are formed.
FIG. 3 is a plan view illustrating a configuration of a pixel on the FT array substrate.

18 is a sectional view taken along line AA 'of FIG.

19 is a sectional view taken along the line BB 'of FIG.

20 is a sectional view taken along the line CC 'of FIG.

FIG. 21 is a cross-sectional view of the electro-optical device according to Embodiment 8 of the present invention at a position corresponding to line BB ′ in FIG. 17;

FIG. 22 is a cross-sectional view of the electro-optical device according to Embodiment 9 of the present invention at a position corresponding to line AA ′ in FIG.

FIG. 23 is a cross-sectional view of the electro-optical device according to Embodiment 9 of the present invention at a position corresponding to line CC ′ in FIG. 17;

FIG. 24 is a plan view of a TFT array substrate of an electro-optical device to which the present invention is applied, together with components formed thereon, viewed from a counter substrate side.

25 is a sectional view taken along the line H-H 'of FIG.

FIG. 26 is a block diagram illustrating a schematic configuration of an electronic apparatus using the electro-optical device to which the invention is applied.

FIG. 27 is a cross-sectional view showing a liquid crystal projector as an example of the electronic apparatus shown in FIG.

28 is a front view showing a personal computer as another example of the electronic apparatus shown in FIG.

[Explanation of symbols]

 Reference Signs List 1 electro-optical device 2 TFT array substrate 3a scanning line 3b capacitance line (second storage capacitance electrode) 5, 8 contact hole 6a data line 7 counter substrate 9a pixel electrode 11 electro-optical material layer 14, 17, 230 interlayer insulating film 15 accumulation Capacitor 15a First storage capacitor electrode 16 Light-shielding film formed on TFT array substrate 18, 71 Alignment film 30 Pixel switching TFT 30a Semiconductor film 31a Source region 31b Low-concentration source region 31c High-concentration source region 32a Drain region 32b Low-concentration drain region 32c High-concentration drain region 33a Channel region 41 Gate insulating film 51 Bottom portion of concave portion 52 Side wall portion of concave portion 53 Opening edge of concave portion 71 Counter electrode 73 Alignment film 72 Light shielding film formed on opposing substrate 101 Data line drive circuit 103 Sampling circuit 104 Scanning Line drive circuit 1 2 the sealing member 153 light-shielding film for parting

Claims (25)

[Claims] A first substrate on which pixel electrodes connected to the pixel switching elements are respectively formed on an upper layer side of the pixel switching elements arranged in a matrix and on an upper layer side of a wiring layer for the pixel switching elements; An electro-optical device, comprising: a second substrate on which a counter electrode facing the pixel electrode is formed; and an electro-optical material sandwiched between the first and second substrates, wherein the pixel switching element and the wiring An electro-optical device, wherein at least a part of the layer is formed in a concave portion that is recessed below the pixel switching element and the wiring layer. 2. The method according to claim 1, wherein the depth of the concave portion is
An electro-optical device having a range of 0.1 μm to 2.0 μm. 3. The electro-optical device according to claim 1, wherein the recess has a side wall formed of a tapered surface rising from the bottom at an angle of 45 ° or more. 4. The method according to claim 1, wherein
The opening edge of the concave portion has a curved cross-sectional shape. 5. The method according to claim 1, wherein
The electro-optical device according to claim 1, wherein the concave portion is formed on a surface of a transparent substrate serving as a base of the first substrate. 6. The method according to claim 1, wherein
The electro-optical device according to claim 1, wherein the concave portion is formed on a surface of an insulating film formed on a surface of a transparent substrate serving as a base of the first substrate. 7. The method according to claim 1, wherein
Furthermore, an electro-optical device is characterized in that an insulating film is formed so as to cover a bottom portion and a side wall portion of the concave portion, and at least a part of the pixel switching element and the wiring layer is formed on an upper layer side of the insulating film. apparatus. 8. The method according to claim 1, wherein
The pixel switching element is a thin film transistor,
An electro-optical device, wherein the wiring layer includes a scanning line and a data line connected to the thin-film transistor. 9. The image forming apparatus according to claim 8, wherein the recess is formed in a region overlapping the entire region of the wiring layer in the image display region of the first substrate on which the plurality of pixel electrodes are formed. An electro-optical device, comprising: 10. The wiring layer according to claim 9, wherein a width dimension of the wiring layer forming area in the image display area is determined based on an opening width of the concave section formed below the wiring layer in the concave section. The thickness of the interlayer insulating film formed on the lower layer side is 2
An electro-optical device characterized by being narrower than a value obtained by subtracting a dimension corresponding to twice. 11. The method according to claim 9, wherein a width dimension of the wiring layer forming area in the image display area is substantially equal to an opening width of the concave section formed below the wiring layer. An electro-optical device having a size smaller than the opening width by 10 μm or less. 12. The electro-optical device according to claim 8, wherein the concave portion is formed in a region overlapping an entire region of a semiconductor film forming an active region of the thin film transistor. 13. The semiconductor device according to claim 12, wherein a width of the formation region of the semiconductor film is from a width of a bottom of the recess formed on a lower layer side of the semiconductor film to a lower layer side of the semiconductor film in the recess. An electro-optical device characterized by being smaller than a value obtained by subtracting a dimension corresponding to twice the thickness of the formed interlayer insulating film. 14. The semiconductor device according to claim 12, wherein a width of the formation region of the semiconductor film is substantially equal to an opening width of the recess formed below the wiring layer, or is larger than an opening width of the recess. An electro-optical device having a size narrower than 10 μm. 15. The electro-optical device according to claim 8, wherein a capacitance element for providing a storage capacitance to the pixel electrode is formed on the first substrate. apparatus. 16. The electro-optical device according to claim 15, wherein the wiring layer includes a capacitance line forming an electrode of the capacitance element. 17. The concave portion according to claim 15, wherein the concave portion has a side wall portion formed of a tapered surface rising at an angle of 45 ° or more from a bottom portion, and a part of an electrode constituting the capacitive element is a side wall of the concave portion. An electro-optical device formed at a portion corresponding to a portion. 18. The electro-optical device according to claim 15, wherein the concave portion is formed in a region overlapping with a whole region of the capacitor element. 19. The device according to claim 18, wherein a width dimension of an electrode forming the capacitance element is substantially equal to an opening width of the concave portion in which the electrode is formed, or 10 μm or less than an opening width of the concave portion. An electro-optical device having a narrow dimension. 20. The region according to claim 8, wherein, on the surface side of the first substrate, at least a region that covers a channel region of the thin film transistor when viewed from the first substrate, in a region where the concave portion is formed. An electro-optical device, wherein a light-shielding film is formed on the electro-optical device. 21. The light-shielding film according to claim 20, wherein
An electro-optical device, wherein the electro-optical device is formed below a layer in which the concave portion is formed. 22. The light-shielding film according to claim 20, wherein
An electro-optical device formed in the recess. 23. The light-shielding film according to claim 22,
An electro-optical device, wherein the electro-optical device is formed in a region of the recess that overlaps a bottom portion and a side wall portion of the recess. 24. The electro-optical device according to claim 1, wherein the first substrate has an alignment concave portion formed simultaneously with the concave portion. 25. A display device comprising the electro-optical device defined in claim 1. Description: