JPH11183934A - Liquid crystal panel and manufacture thereof and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently flatten a picture element part by utilizing a constitution in which a shielding layer is provided under TFT in a liquid crystal panel of an active matrix drive method by a TFT drive. SOLUTION: A liquid crystal panel 100 is provided with a liquid crystal layer 50 held between a couple of substrates and picture element electrodes formed in a matrix form on a TFT array substrate 10. The shielding layer is arranged so as to overlap a TFT 30 and the scanning lines looking at them from the bottom. In 1st interlayer insulating layers 12, 13, which are formed on the shielding layer in an area where the shielding layer 11a is formed, and are formed on a TFT array substrate in an area where the shielding layer is not formed, a part opposed to TFT, data lines, scanning lines, etc., is formed in a recessed form looking at it from the side of the opposed substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of an active matrix driving type liquid crystal panel driven by a thin film transistor (hereinafter, referred to as TFT) and a method of manufacturing the same, and an electronic apparatus using the same. It belongs to the technical field of a liquid crystal panel in which a light-shielding layer is provided below a TFT, and an electronic device using the same, which is used for the like.

[0002]

2. Description of the Related Art Conventionally, when a liquid crystal panel of this type is used as a light valve in a liquid crystal projector or the like, generally, projection light is incident from the side of a counter substrate which is disposed opposite to a TFT array substrate with a liquid crystal layer interposed therebetween. You. Here, the projected light is an a-Si (amorphous silicon) film or a p-
When the light enters a region for channel formation made of a Si (polysilicon) film, a photoelectric current is generated in this region due to a photoelectric conversion effect, and the transistor characteristics of the TFT deteriorate. Therefore, a light-shielding layer called a second light-shielding layer is generally formed on the opposing substrate from a metal material such as Cr (chrome), resin black, or the like, at a position facing each TFT.

Further, in this type of liquid crystal panel, a regular staggered or coplanar type amorphous silicon or polycrystalline silicon having a top gate structure (ie, a structure in which a gate electrode is provided above a channel on a TFT array substrate) is used. In the case of using a silicon TFT, it is necessary to prevent a part of the projection light from entering the TFT channel from the TFT array substrate side as return light by the projection optical system in the liquid crystal projector. Similarly, the reflected light from the surface of the TFT array substrate when the projected light passes therethrough, or when it is emitted from another liquid crystal panel when a plurality of liquid crystal panels are used in combination for color, passes through the projection optical system after being emitted. It is also necessary to prevent some of the incoming projection light from entering the TFT channel from the TFT array substrate side as return light. For this reason, Japanese Patent Application Laid-Open No. 9-127497, Japanese Patent Publication No. 3-52611, Japanese Patent Application Laid-Open No. 3-125123, and Japanese Patent Application Laid-Open No. 8-171101 disclose TFTs on a TFT array substrate composed of a quartz substrate or the like. For example, a liquid crystal panel in which a light-shielding layer is formed of an opaque high-melting point metal at an opposing position (that is, below the TFT) has been proposed.

When the light shielding layer is provided below the TFT as described above, the light shielding layer and the TFT are electrically insulated, and an interlayer insulating layer is formed on the light shielding layer to prevent contamination of the TFT from the light shielding layer. A layer is formed, and a TFT is formed thereon. That is, when the light shielding layer is provided below the TFT,
Along with this, an interlayer insulating layer between the light shielding layer and the TFT is an essential component.

As described above, conventionally, a light-shielding layer is provided to improve the image quality of a liquid crystal panel. In addition to this, there are the following various techniques for improving the image quality.

That is, first, in this type of liquid crystal panel,
On a TFT array substrate, a region where wiring such as TFTs, data lines, scanning lines, and capacitance lines are formed, and a region where these TFTs and the like are not formed (particularly, an opening region through which projected light for image display passes). If the unevenness due to the difference in the total layer thickness is left as it is on the surface (alignment film) in contact with the liquid crystal, poor alignment (disclination) occurs in the liquid crystal depending on the degree of the unevenness, and each pixel has This leads to image deterioration. More specifically, if the rubbing process is performed on the alignment film formed on the uneven surface in which each opening region is depressed, a region that is not aligned according to the unevenness occurs, and poor alignment of the liquid crystal occurs. The contrast changes. Therefore, conventionally, a flattening film such as an organic film is further applied by spin coating or the like on an interlayer insulating layer formed for electrical insulation on these TFTs and various wirings, or this insulating layer is formed by SOG. (Spin-on glass: spun glass) or the like. By forming a pixel electrode and an alignment film on the flattened surface, the above-described poor alignment of the liquid crystal is suppressed.

In this type of liquid crystal panel, even if the duty ratio when supplying an image signal to each pixel electrode is small, a predetermined capacitance is applied to each pixel electrode in order to prevent flicker and crosstalk from occurring. Or a storage capacity for providing the storage capacity. More specifically, a storage capacitor is provided to the pixel electrode by forming a capacitor structure by opposing a capacitor electrode to a part of the pixel electrode, and arranging the capacitor line on the TFT array substrate in parallel with the scanning line. By taking this storage capacity sufficiently, high-definition image display is possible.

[0008]

In a liquid crystal panel, there is a strong demand for an improvement in image quality, an improvement in manufacturing efficiency, and a reduction in manufacturing cost.

However, when the pixel portion in contact with the liquid crystal is flattened as described above, the manufacturing efficiency and cost deteriorate. In particular, as described above, when a light-shielding layer is formed below the TFT to planarize the pixel portion, the TFT including the light-shielding layer and an interlayer insulating layer necessary to accompany the light-shielding layer is stacked.
Since the total layer thickness of the portion is increased, the burden on the planarization process is increased, and there is a problem that manufacturing efficiency and cost are significantly deteriorated.

Further, when the unevenness is flattened with the above-mentioned organic film, SOG, or the like near the uppermost layer located above the light-shielding layer or the interlayer insulating layer necessary for the light-shielding layer, the flattening film itself becomes thick. . There is a problem that it is difficult to connect a pixel electrode formed above such a thick flattening film to a source or drain region of a semiconductor layer formed below. That is, it is extremely difficult in practice to open a thick layer having a total thickness of about 2 μm as a contact hole for directly connecting the two. Therefore, in order to connect them electrically by relaying the Al layer forming the data line, it is necessary to use Al (indium.
(Tin oxide) and poor compatibility (especially, the contact resistance between them is high, and they corrode).
It becomes necessary to further interpose an interlayer insulating layer between the layers and electrically connect the Al layer and the ITO film with another conductive layer such as Ti. For this purpose, for example, 1
A mask of the order of several sheets is required for the thin film forming process,
As a result, there is a problem that the production becomes difficult and the production cost increases.

The present invention has been made in view of the above-mentioned problems, and a liquid crystal panel capable of efficiently flattening a pixel portion by utilizing a configuration in which a light-shielding layer is provided below a TFT and a specialty in its manufacturing process. Another object of the present invention is to provide an electronic device including the liquid crystal panel and a manufacturing method thereof.

[0012]

According to a first aspect of the present invention, there is provided a liquid crystal panel comprising a liquid crystal sealed between a pair of substrates, wherein a plurality of substrates are provided on one of the substrates. Data lines, a plurality of scanning lines intersecting the plurality of data lines, a plurality of thin film transistors connected to the plurality of data lines and the scanning lines, a plurality of thin film transistors connected to the plurality of thin film transistors, A first interlayer insulating film having a concave portion when viewed from the side of the other substrate of the pair of substrates, wherein at least a part of the thin film transistor, the data line, and the scanning line is concave in the concave shape. It is characterized in that it is formed on the lip.

According to the liquid crystal panel of the first aspect, the first interlayer insulating layer is formed such that a portion facing at least one of a TFT, a data line and a scanning line is concavely concave when viewed from the other substrate side. In comparison with the conventional case where the first interlayer insulating layer is formed flat and the TFTs and the like are formed thereon, the first interlayer insulating layer is formed in accordance with the depth of the concave portion. The difference in the total layer thickness between the region where the TFT or the like is formed and the region where the TFT or the like is not formed is reduced, and flattening in the pixel portion is promoted. For example, if the depth of the concave portion is set so that the difference in the total layer thickness becomes substantially zero, the subsequent flattening process can be omitted, or the difference in the total layer thickness can be reduced to some extent. If the depth of the concave portion is set so as to reduce it at all, the load of the subsequent flattening process can be reduced. In other words, the above-described conventional steps of applying a flattening film by spin coating or the like and forming a flattened insulating layer can be omitted or simplified.

In a liquid crystal panel according to a second aspect of the present invention, a liquid crystal is sealed between a pair of substrates, and a plurality of data lines intersect with the plurality of data lines on one of the pair of substrates. A plurality of scan lines, a plurality of thin film transistors connected to the plurality of data lines and scan lines, a plurality of pixel electrodes connected to the plurality of thin film transistors, and at least a channel formation region of the plurality of thin film transistors, A light-shielding layer provided at a position to cover each as viewed from the substrate side, and a first interlayer insulating film having a concave portion formed on the light-shielding layer, the thin film transistor, the data line, At least a part of the scanning line is formed on the concave portion.

According to the liquid crystal panel of the present invention, the light-shielding layer is provided on one of the substrates at a position covering at least a channel forming region of the plurality of TFTs when viewed from the side of the one substrate. Therefore, it is possible to prevent the return light or the like from the one substrate side from being incident on the channel forming region, and to prevent the TFT characteristics from deteriorating due to generation of a photocurrent. The first interlayer insulating layer is provided on the light shielding layer in a region where the light shielding layer is formed on one substrate, and is provided on the one substrate in a region where the light shielding layer is not formed. ing. Therefore, the TFT and the like can be electrically insulated from the light shielding layer, and the situation where the light shielding layer contaminates the TFT and the like can be prevented.
Here, in particular, the first interlayer insulating layer has a portion facing at least one of the TFT, the data line, and the scanning line, which is formed in a concave shape when viewed from the other substrate side. In comparison with the case where the first interlayer insulating layer is formed flat and these TFTs and the like are formed thereon, the region where these TFTs and the like are formed is formed in accordance with the depth of the concave portion. The difference in the total layer thickness from the unexposed region is reduced, and flattening in the pixel portion is promoted. For example, if the depth of the concave portion is set so that the difference in the total layer thickness becomes substantially zero, the subsequent flattening process can be omitted, or the difference in the total layer thickness can be reduced to some extent. If the depth of the concave portion is set so as to reduce it at all, the load of the subsequent flattening process can be reduced. In other words, the above-described conventional steps of applying a flattening film by spin coating or the like and forming a flattened insulating layer can be omitted or simplified.

According to a third aspect of the present invention, there is provided a liquid crystal panel according to the first or second aspect, wherein the first interlayer insulating layer is formed of a single layer. I do.

According to the liquid crystal panel of the present invention, since the first interlayer insulating layer may be constituted by a single layer, it is not necessary to increase the number of layers as compared with the conventional case, and the first interlayer insulating layer has a concave shape. The first interlayer insulating layer can be obtained by controlling the thickness of the depressed portion and the other portion.

According to a fourth aspect of the present invention, there is provided a liquid crystal panel according to the first or second aspect, wherein the first interlayer insulating layer comprises a single layer portion and a multilayer portion. The single-layer portion is the concave portion, and the multilayer portion is the non-concave portion.

According to the liquid crystal panel of the present invention, since the single layer portion is formed as a concave portion, the layer thickness of the first interlayer insulating layer in the concave portion is reduced. The layer thickness can be relatively easily controlled reliably and with high precision. Therefore, the thickness of the first interlayer insulating layer in the concave portion can be extremely reduced.

According to a fifth aspect of the present invention, there is provided a liquid crystal panel according to any one of the first to fourth aspects, wherein the one substrate is provided on the one substrate in parallel with the plurality of scanning lines. A plurality of capacitance lines that are provided and respectively provide a predetermined capacitance to the plurality of pixel electrodes.
The first interlayer insulating layer may be formed so that a portion facing the capacitance line is also depressed in the concave shape.

According to the liquid crystal panel of the present invention, since the first interlayer insulating layer is also formed so as to have a concave portion facing the capacitor line, the capacitor line is formed above the first interlayer insulating layer. Even in the case of wiring, the region where the capacitor line is wired can be flattened. Then, it is also possible to make the layer thickness of the first interlayer insulating layer in the portion facing the capacitance line extremely small.

According to a sixth aspect of the present invention, there is provided a liquid crystal panel according to the fifth aspect, wherein:
The light shielding layer is provided on the one substrate even at a position where the capacitance line overlaps when viewed from the one substrate side.

According to the liquid crystal panel of the present invention, when the thickness of the first interlayer insulating layer in the portion facing the capacitance line is reduced, the light-shielding layer overlaps the capacitance line when viewed from one substrate side. Because it is provided on one substrate at the position,
Without increasing the surface area of the capacitance line, the capacitance between the light-shielding layer opposed to the semiconductor layer forming the TFT via the insulating layer can be increased. That is, the storage capacitance of the pixel electrode can be increased as a whole.

According to a seventh aspect of the present invention, there is provided a liquid crystal panel according to the fifth or sixth aspect, wherein the first interlayer insulating layer includes the light shielding layer, the semiconductor layer, and the capacitor line. Characterized in that it is formed so as to be depressed in the concave shape at a depth corresponding to the total layer thickness.

According to the liquid crystal panel of the present invention, the first interlayer insulating layer is formed so as to be concave in a depth corresponding to the total thickness of the light shielding layer, the semiconductor layer of the TFT, and the capacitance line. Therefore, it is possible to reduce the level difference between the region where the light-shielding layer and the like are formed and the other region, and the flattening of the pixel portion is promoted.

In order to solve the above-mentioned problems, the liquid crystal panel according to claim 8 is the liquid crystal panel according to claim 5 or 6, wherein the first interlayer insulating layer is formed of the light shielding layer, the semiconductor layer, and the capacitor line. And a concave portion having a depth corresponding to a total layer thickness of the data lines.

According to the liquid crystal panel of the present invention, the first interlayer insulating layer is formed so as to be concave in a depth corresponding to the total layer thickness of the light shielding layer, the semiconductor layer of the TFT, the capacitance line and the data line. Therefore, the step between the region where the light-shielding layer and the like are formed and the other region can be reduced, and the flattening of the pixel portion is promoted.

According to a ninth aspect of the present invention, there is provided a liquid crystal panel according to any one of the first to eighth aspects, wherein the semiconductor layer forming the TFT is arranged along the data line. The light shielding layer is provided on the one substrate even at a position where the data line overlaps when the data line is viewed from the one substrate side.

According to the liquid crystal panel of the ninth aspect, between the semiconductor layer extended along the data line and the light shielding layer provided at a position where the data line overlaps when viewed from one substrate side. Thus, a capacitor is formed via the first interlayer insulating layer. As a result, the storage capacity of the pixel electrode can be increased by effectively utilizing the space below the data line and outside the opening region.

According to a tenth aspect of the present invention, there is provided a liquid crystal panel according to the first aspect, wherein the first interlayer insulating layer is made of a silicon oxide film or a silicon nitride film. It is characterized by being composed of a film.

According to the liquid crystal panel of the tenth aspect,
With the eleventh interlayer insulating layer made of a silicon oxide film or a silicon nitride film, TFTs and the like can be electrically insulated from the light-shielding layer and contamination from the light-shielding layer can be prevented. In addition, the first interlayer insulating layer configured as described above is suitable for a TFT underlayer.

[0032] In order to solve the above-mentioned problems, the liquid crystal panel according to the eleventh aspect is the liquid crystal panel according to any one of the first to tenth aspects, wherein the light shielding layer is made of Ti (titanium), Cr (chromium). , W (tungsten), Ta (tantalum), Mo (molybdenum), and Pd (lead).

According to the liquid crystal panel of the eleventh aspect,
The light shielding layer is made of an opaque refractory metal such as Ti, Cr, W,
Since it includes at least one of Ta, Mo, and Pd, for example, a metal simple substance, an alloy, a metal silicide, or the like, a high-temperature process in the TFT forming process performed after the light shielding layer forming process on the TFT array substrate is performed. In addition, the light shielding layer can be prevented from being broken or melted.

According to a twelfth aspect of the present invention, there is provided a liquid crystal panel according to the first aspect, wherein the light shielding layer is connected to a constant potential source. It is characterized by.

According to the liquid crystal panel of the twelfth aspect,
Since the light shielding layer is connected to a constant potential source, the light shielding layer is set to a constant potential. Therefore, the potential fluctuation of the light-shielding layer does not adversely affect the TFT disposed opposite to the light-shielding layer.

According to a thirteenth aspect of the present invention, there is provided a liquid crystal panel according to the twelfth aspect, wherein the first interlayer insulating layer connects the light shielding layer and the constant potential source. At the position, the hole is formed in the concave shape and is opened.

According to the liquid crystal panel of the thirteenth aspect,
Since the first interlayer insulating layer is formed in a concave shape at a position where the light shielding layer and the constant potential source are connected, in the manufacturing process, after the first interlayer insulating layer is formed, the concave portion is formed. The step of opening this position is facilitated according to the depth of the hole.

According to a fourteenth aspect of the present invention, there is provided a method of manufacturing a liquid crystal panel according to the second aspect, wherein the light shielding layer is formed in a predetermined region on the one substrate. Forming, depositing an insulating layer on the one substrate and the light-shielding layer, forming a resist pattern corresponding to the concave portion on the insulating layer by photolithography, Forming a recessed portion by performing dry etching for a predetermined time through the step.

According to the method for manufacturing a liquid crystal panel of the present invention, first, a light-shielding layer is formed in a predetermined region on one substrate, and an insulating layer is deposited on the one substrate and the light-shielding layer. Next, a resist pattern corresponding to the concave portion in the insulating layer is formed by photolithography, and then dry etching is performed for a predetermined time through the resist pattern, and the concave portion is formed. It is formed. Therefore, by controlling the time of the dry etching, the depth and the layer thickness of the concave portion can be controlled.

According to a fifteenth aspect of the present invention, there is provided a method of manufacturing a liquid crystal panel according to the third aspect, wherein the light shielding layer is provided on a predetermined region on the one substrate. Forming, a step of depositing a first insulating layer on the one substrate and the light-shielding layer, and a step of forming a resist pattern corresponding to the concave portion in the first insulating layer by photolithography, Removing the first insulating layer corresponding to the concave portion by performing etching through the resist pattern; and depositing a second insulating layer on the one substrate and the first insulating layer. It is characterized by having.

According to a fifteenth aspect of the present invention, first, a light-shielding layer is formed in a predetermined region on one substrate, and a first insulating layer is deposited on the one substrate and the light-shielding layer. You. Next, a resist pattern corresponding to the concave portion is formed on the first insulating layer by photolithography. Thereafter, etching is performed through the resist pattern to correspond to the concave portion. First
The insulating layer is removed. Then, one of the substrates and the first
A second insulating layer is deposited on the insulating layer. As a result, the thickness of the first interlayer insulating layer in the concave portion can be controlled relatively easily, reliably, and accurately by managing the thickness of the second insulating layer.

A method of manufacturing a liquid crystal panel according to a sixteenth aspect is characterized in that in order to solve the above problems, at least dry etching is performed as the etching method.

According to the liquid crystal panel manufacturing method of the present invention, since the etching is performed at least by dry etching, the insulating layer on the light-shielding layer having no resist pattern can be removed anisotropically. As a result, it is possible to form a concave portion with a high accuracy as substantially designed.

A method of manufacturing a liquid crystal panel according to a seventeenth aspect is characterized in that in order to solve the above-mentioned problem, at least wet etching is used as the etching method.

According to the method for manufacturing a liquid crystal panel of the present invention, since the etching is performed at least by wet etching, the side wall of the concave portion formed in the insulating layer on the light shielding layer can be formed in a tapered shape. This allows
Wiring films and resists formed on the side wall in a later step can be easily and reliably removed. Therefore, no unnecessary film remains, and the yield does not decrease.

A liquid crystal panel manufacturing method according to claim 18 is a method for manufacturing a liquid crystal panel according to claim 12, wherein the light shielding layer is provided in a predetermined region on the one substrate. Forming the first interlayer insulating layer on the one substrate and the light-shielding layer such that a portion facing the TFT and a portion corresponding to the connection position are depressed in a concave shape; A step of forming the TFT on one interlayer insulating layer, a step of forming a second interlayer insulating layer on the TFT and the first interlayer insulating layer, and connecting the light-shielding layer and a wiring from the constant potential source A contact hole for connecting the TFT and the data line at the same time as opening the second and first interlayer insulating layers up to the light shielding layer at the connection position. And, also the source of the semiconductor layer forming the TFT is characterized in that a step of opening the second interlayer insulating layer until reaching the semiconductor layer at a position facing the drain region.

According to the liquid crystal panel manufacturing method of the eighteenth aspect, the light-shielding layer is formed in the predetermined region on the one substrate, and the portion facing the TFT and the position where the light-shielding layer and the constant potential source are connected. A first interlayer insulating layer is formed on one of the substrates and the light-shielding layer so that a portion corresponding to the first layer is depressed.
Thereafter, a TFT is formed on the first interlayer insulating layer, and
A second interlayer insulating layer is formed on the FT and the first interlayer insulating layer. This second interlayer insulating layer is provided for electrical insulation of TFTs, data lines, scanning lines, and the like. Here, the second and first interlayer insulating layers are opened as contact holes for connecting the light-shielding layer and the wiring from the constant potential source to the light-shielding layer, and at the same time, connect the TFT and the data line. The second interlayer insulating layer is opened up to the semiconductor layer as a contact hole. Therefore, these two types of contact holes can be opened collectively.

According to a nineteenth aspect of the present invention, there is provided an electronic apparatus comprising the liquid crystal panel according to the first to twelfth aspects.

According to the electronic apparatus of the present invention, the electronic apparatus includes the above-described liquid crystal panel of the present invention, and the liquid crystal panel capable of efficiently flattening the pixel portion enables high-quality image display. Become.

The operation and other advantages of the present invention will become more apparent from the embodiments explained below.

[0051]

Embodiments of the present invention will be described below with reference to the drawings.

(Configuration and Operation of Liquid Crystal Panel) The configuration and operation of the embodiment of the liquid crystal panel according to the present invention will be described with reference to FIG.
Will be described based on FIG.

First, the basic structure of the liquid crystal panel will be described with reference to FIGS. FIG. 1 is a plan view of an adjacent pixel group on a TFT array substrate on which a data line, a scanning line, a pixel electrode, a light shielding layer, and the like are formed. FIG. 2 is a plan view of a connection portion between the light shielding layer and the constant potential line. FIG. 3 shows FIG.
FIG. 4 is a cross-sectional view of an embodiment of a liquid crystal panel showing an AA ′ cross-section along with a counter substrate and the like, and FIG. 4 is a cross-sectional view of a modification of the liquid crystal panel of FIG. FIG. 5 is a cross-sectional view of the liquid crystal panel showing a cross section taken along line BB ′ of FIG. 1 together with a counter substrate and the like.
FIG. 6 is a cross-sectional view of the liquid crystal panel showing a cross section taken along line CC ′ of FIG. 1 together with a counter substrate and the like. FIG. 7 is a cross-sectional view taken along the line DD ′ in FIG.
FIG. 3 is a cross-sectional view of a liquid crystal panel showing a cross section together with a counter substrate and the like. In FIGS. 3 to 7, the scale of each layer and each member is different in order to make each layer and each member have a size recognizable in the drawings.

In FIG. 1, a plurality of transparent pixel electrodes 9a are arranged in a matrix on a TFT array substrate of a liquid crystal panel.
(Indicated by a dotted line portion 9a '), and a data line 6a (source electrode), a scanning line 3a (gate electrode), and a capacitor line 3b are respectively provided along the vertical and horizontal boundaries of the pixel electrode 9a. Is provided. The data line 6a is electrically connected to a later-described source region of the semiconductor layer 1a made of a polysilicon film via the contact hole 5a, and the pixel electrode 9a is connected to a later-described source region of the semiconductor layer 1a via the contact hole 8. Is electrically connected to the drain region. Further, the scanning line 3a (gate electrode) is arranged so as to face a channel forming region 1a '(a region indicated by oblique lines at the lower right in the figure) of the semiconductor layer 1a which will be described later. The light-shielding layer 11a in the pixel portion is provided in a region indicated by oblique lines rising to the right in the drawing. That is, the light shielding layer 11a
In the pixel portion, the channel forming region 1 of the semiconductor layer 1a
The TFT including a ′, the data line 6a, the scanning line 3a, and the capacitor line 3b are provided at positions overlapping each other when viewed from the TFT array substrate side.

In FIG. 1, in particular, in a mesh-like (matrix-like) region surrounded by a thick line including the data line 6a, the scanning line 3a, and the capacitor line 3b, a first interlayer insulating layer described later is depressed. Other pixel electrodes 9
In a region substantially corresponding to a, the first interlayer insulating layer is formed in a relatively convex shape (in a planar shape).

In FIG. 2, on the TFT array substrate of the liquid crystal panel, a constant potential line 6b formed of the same conductive layer made of Al or the like as the data line 6a is provided. Light shielding layer (light shielding wiring) 1
1b. In particular, in FIG. 2, in a region surrounded by a thick line including the contact hole 5 b, a first interlayer insulating layer described later is formed so as to be concave, and in other regions, the first interlayer insulating layer is not formed. It is formed in a relatively convex shape (in a planar shape).

As shown in FIGS. 3 to 6, the liquid crystal panel 1
Reference numeral 00 includes a TFT array substrate 10 which constitutes an example of one transparent substrate, and an opposing substrate 20 which constitutes an example of the other transparent substrate disposed to face the TFT array substrate 10. TFT
The array substrate 10 is made of, for example, a quartz substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate. TFT
The array substrate 10 is provided with a pixel electrode 9a,
On the upper side, an alignment film 19 that has been subjected to a predetermined alignment process such as a rubbing process is provided. The pixel electrode 9a is made of, for example, a transparent conductive thin film such as an ITO film (indium tin oxide film). The alignment film 19 is made of, for example, an organic thin film such as a polyimide thin film.

On the other hand, a common electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the common electrode 21. I have. The common electrode 21 is made of, for example, a transparent conductive thin film such as an ITO film. The alignment film 22 is made of an organic thin film such as a polyimide thin film.

As shown in FIG. 3, each pixel electrode 9a is provided on the TFT array substrate 10 at a position adjacent to each pixel electrode 9a.
A TFT 30 for switching control of a is provided.

As shown in FIGS. 3 to 7, the second light shielding layer 2 is formed on the opposite substrate 20 in a region other than the opening region of each pixel.
3 are provided. For this reason, the projection light does not irradiate the channel forming region 1 a ′ and the LDD (Lightly Doped Drain) regions 1 b and 1 c of the semiconductor layer 1 a of the TFT 30 from the side of the counter substrate 20. Further, the second light shielding layer 23
It has functions such as improvement of contrast and prevention of color mixing of coloring materials.

A sealing material 52 (to be described later) is provided between the TFT array substrate 10 and the opposing substrate 20, which are configured as described above and in which the pixel electrode 9a and the common electrode 21 are arranged to face each other.
Liquid crystal is sealed in a space surrounded by (see FIGS. 8 and 9), and a liquid crystal layer 50 is formed. The liquid crystal layer 50 has the alignment film 19 in a state where no electric field is applied from the pixel electrode 9a.
A predetermined orientation state is taken by (2) and (2). The liquid crystal layer 50
For example, it is composed of a liquid crystal in which one or several kinds of nematic liquid crystals are mixed. The sealing material 52 includes two substrates 10 and 20.
Is an adhesive made of, for example, a photocurable resin or a thermosetting resin, and a spacer such as glass fiber or glass beads for setting a distance between the two substrates to a predetermined value is mixed. ing.

As shown in FIG. 3, the TFT array substrate 10 and each TFT 30
Between, for example, WSi (tungsten silicide)
Are provided, respectively. Light shielding layer 1
1a is Ti, C, preferably an opaque refractory metal
It is composed of a single metal, an alloy, a metal silicide or the like containing at least one of r, W, Ta, Mo and Pd. With such a material, the TFT formed after the step of forming the light shielding layer 11a on the TFT array substrate 10 is formed.
The light-shielding layer 11a
Is not broken or melted. Light shielding layer 11a
Is formed, it is possible to prevent light returning from the side of the TFT array substrate 10 from entering the channel forming region 1a 'and the LDD regions 1b and 1c of the TFT 30 beforehand. The characteristics of the TFT 30 do not deteriorate.

Further, between the light-shielding layer 11a and the plurality of TFTs 30, there is provided a first interlayer insulating layer 12 'composed of a first insulating layer 12 and a second insulating layer 13. The first interlayer insulating layer 12 ′ is a semiconductor layer 1 a forming the TFT 30.
Is provided to electrically insulate from the light shielding layer 11a. Further, the first interlayer insulating layer 12 ′ is formed on the entire surface of the TFT array substrate 10 so that the TFT 30
It also has a function as a base film for the purpose. That is, TFT
It has a function of preventing the characteristics of the TFT 30 from deteriorating due to roughness at the time of polishing the surface of the array substrate 10 or contamination remaining after cleaning.

Here, as particularly shown in FIGS. 3 to 7, the first interlayer insulating layer 12 'is formed on the light shielding layer 1 on the TFT array substrate.
The region where the light shielding layer 11a is formed is formed on the light shielding layer 11a, and the region where the light shielding layer 11a is not formed is provided on the TFT array substrate 10.
A portion facing the TFT 30, the data line 6 a, the scanning line 3 a, and the capacitor line 3 b is formed in a concave shape when viewed from the counter substrate 20 side. In the present embodiment, in particular, the first interlayer insulating layer 12 ′ is composed of a single-layer portion and a two-layer portion, and the single-layer portion of the second insulating layer 13 is formed as a thin and concave portion. And the first and second insulating layers 12
And 13 are thicker portions that are not concavely concave. As described above, when the first interlayer insulating layer 12 ′ is configured, the layer thickness of the first interlayer insulating layer 12 ′ in the concave portion is relatively easily set as the layer thickness of the second insulating layer 13, so that it is reliable and reliable. Can be controlled with high precision. Therefore, the layer thickness of the first interlayer insulating layer 12 '(that is, the layer thickness of the second insulating layer 13) in the concave portion can be made extremely thin.

The first interlayer insulating layer 1 configured as described above
By 2 ′, the TFT 30 and the like can be electrically insulated from the light shielding layer 11a, and the situation where the light shielding layer 11a contaminates the TFT 30 and the like can be prevented. Here, in particular, the first interlayer insulating layer 1
2 'is formed by recessing the portion facing the TFT 30, the data line 6a, the scanning line 3a, and the capacitor line 3b in a concave shape, so that the first interlayer insulating layer is formed flat and the When compared with the case where these TFTs and the like are formed,
Depending on the depth of the concave portion, the difference in the total layer thickness between the region where the TFTs and the like are formed and the region where the TFTs and the like are not formed is reduced, and flattening in the pixel portion is promoted.

For example, if the depth of the concave portion is set so that the difference in the total layer thickness becomes substantially zero, the subsequent flattening process can be omitted. Alternatively, if the depth of the concave portion is set so as to reduce the difference in the total layer thickness at all, the load of the subsequent flattening process can be reduced. More preferably, the first interlayer insulating layer 12 ′ includes the light-shielding layer 11 a, the semiconductor layer 1 a, the capacitor line 3 b, and the data line 3 a.
Is formed in a concave shape at a depth corresponding to the total layer thickness.
By configuring the first interlayer insulating layer 12 'in this manner, the upper surface of the data line 6a and the upper surface of the second interlayer insulating layer 4 adjacent to the data line 6a can be almost aligned, and the pixel before forming the pixel electrode 9a can be formed. The flattening of the part is promoted. However, the first interlayer insulating layer 12 'may be formed to be concave in a depth corresponding to the total layer thickness of the light shielding layer 11a, the semiconductor layer 1a, and the capacitor line 3b. By configuring the first interlayer insulating layer 12 'in this manner, the upper surface of the second interlayer insulating layer 4 can be made substantially flat, and flattening in the pixel portion before forming the pixel electrode 9a is promoted.

As described above, since the predetermined region of the first interlayer insulating layer 12 ′ required by providing the light shielding layer 11 a is formed in a concave shape, according to the present embodiment, according to this embodiment, Steps such as application of a flattening film by spin coating or the like, CMP treatment, and formation of a flattened insulating layer can be omitted or simplified.

As shown in FIG. 4, the first interlayer insulating layer 12 "may be formed of a single layer instead of the first interlayer insulating layer 12 'of FIG. In this case, it is not necessary to increase the number of layers as compared with the conventional case. By controlling, the first interlayer insulating layer 12 ″ is obtained.

Referring again to FIG. 3, the first interlayer insulating layer 12 '
Is made of a highly insulating glass such as NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphor silicate glass), or a silicon oxide film, a silicon nitride film, or the like. Become.

In this embodiment, as shown in FIGS. 1 and 5, the high-concentration drain region 1e of the semiconductor layer 1a extends along the data line 6a, and the light-shielding layer 11a is connected to the data line 6a. Since it is also provided below, the first storage capacitor electrode (polysilicon layer) extending along the data line 6a
A capacitor is formed between 1 f and the light shielding layer (third storage capacitor electrode) 11 a via the second insulating layer 13. As a result, the storage capacity of the pixel electrode 9a can be increased by effectively utilizing the space below the opening area below the data line 6a. In addition, a capacitance is formed between the capacitance line (second storage capacitance electrode) 3b and the first storage capacitance electrode 1f using an insulating film formed in the same step as the gate insulating film 2 as a dielectric.
Thereby, above and below the first storage capacitor electrode 1f,
Since a capacitor can be formed and a storage capacitor can be effectively added with a limited area, the pixel size can be reduced. Alternatively, since a high aperture ratio can be realized, a bright liquid crystal panel can be provided.

In the present embodiment, as shown in FIGS. 1 and 6, the first interlayer insulating layer 12 'is also formed so that the portion opposing the capacitor line (second storage capacitor electrode) 3b is recessed. Therefore, even if the capacitance line 3b is wired above the first interlayer insulating layer 12 ', the region where the capacitance line 3b is wired can be flattened. The layer thickness of the first interlayer insulating layer 12 ′ at the portion facing the capacitor line 3 b is extremely thin (for example, about 1000 to 2000 °), and the light-shielding layer (third storage capacitor electrode) 11 a Is also provided below the capacitance line 3b, so that it extends from the light-shielding layer 11a and the high-concentration drain region 1e of the semiconductor layer 1a that are opposed to each other via the second insulating layer 13 without increasing the surface area of the capacitance line 3b. It is possible to increase the storage capacitance 70 between the provided first storage capacitance electrode 1f. That is, the storage capacitance 70 of the pixel electrode 9a can be increased as a whole.
As described above, the storage capacity can be increased so that the opening area of each pixel is not narrowed particularly in a limited area in the screen display area, which is very advantageous. The capacitance line 3b
, A storage capacitor may be formed with the preceding scanning line 3a. If a constant potential line for supplying a constant potential to the capacitor line 3b is connected to a constant potential source such as a negative power source or a positive power source of a peripheral driving circuit (a data line driving circuit, a scanning line driving circuit, etc., which will be described later), externally The mounting terminal for inputting the above signal and the signal wiring provided from the mounting terminal can be omitted, which is very advantageous when the size of the liquid crystal panel is reduced.

In this embodiment, as shown in FIGS. 2 and 7, the light-shielding layer 11b of the light-shielding wiring portion (and the light-shielding layer 11a in the pixel portion connected thereto) is electrically connected to the constant potential line 6b. Therefore, the light shielding layer 11a is set at a constant potential.
Therefore, the potential fluctuation of the light-shielding layer 11a does not adversely affect the TFT 30 that is disposed to face the light-shielding layer 11a. In this case, the constant potential of the constant potential line 6b may be equal to the ground potential, or may be equal to the potential of the common electrode 21. Further, the constant potential line 6b may be connected to a constant potential source such as a negative power supply or a positive power supply of a peripheral driving circuit for driving the liquid crystal panel 100. Further, there is no problem even if the light shielding layer 11b and the above-mentioned capacitance line 3b are electrically connected. In this case, since the constant potential line can be shared, signal wiring can be reduced, effective use of space can be achieved, and this is very advantageous when the size of the liquid crystal panel is reduced.

Further, as shown in FIGS. 2 and 7, the first interlayer insulating layer 12 'is formed in a concave shape at the position where the light-shielding layer 11b and the constant potential line 6b are connected. As described above, the step of opening the contact hole 5b by etching after the formation of the first interlayer insulating layer 12 'is facilitated according to the depth of the concave portion, and the contact holes 5a and 5b are simultaneously opened. Can make holes. Therefore, it is possible to omit the step of opening the contact hole 5b, and it is possible to reduce the cost and improve the yield by reducing the number of steps.

Referring again to FIG. 3, the TFT 30 has an LD
A channel forming region 1 of a semiconductor layer 1a having a D (Lightly Doped Drain) structure and having a channel formed by an electric field from the scanning line 3a (gate electrode) and the scanning line 3a.
a ′, the gate insulating layer 2 that insulates the scanning line 3a from the semiconductor layer 1a, and the lightly doped source region (source side L) of the semiconductor layer 1a.
DD region) 1b, data line 6a (source electrode), low-concentration drain region (drain-side LDD region) of semiconductor layer 1a
1c, a high-concentration source region 1d and a high-concentration drain region 1e of the semiconductor layer 1a. High concentration drain region 1
A corresponding one of the plurality of pixel electrodes 9a is connected to e. As described later, the source regions 1b and 1d and the drain regions 1c and 1e are provided with a predetermined concentration of n-type or p-type dopants for the semiconductor layer 1a depending on whether an n-type or p-type channel is formed. It is formed by doping. An n-type channel TFT has the advantage of a high operating speed, and is often used as the TFT 30 as a pixel switching element. In the present embodiment, in particular, the data line 6a (source electrode) is formed of a light-shielding thin film such as a metal film such as Al or an alloy film such as metal silicide. In addition, a contact hole 5 leading to the high-concentration source region 1d is formed on the scanning line 3a (gate electrode), the gate insulating layer 2, and the first interlayer insulating layer 12 '.
The second interlayer insulating layer 4 in which the contact holes 8 leading to the high-concentration drain region 1e are formed. The data line 6a (source electrode) is electrically connected to the high-concentration source region 1d via the contact hole 5a to the source region 1b. Further, a third contact hole 8 to the high-concentration drain region 1e is formed on the data line 6a (source electrode) and the second interlayer insulating layer 4.
An interlayer insulating layer 7 is formed. The pixel electrode 9a is formed through the contact hole 8 to the high-concentration drain region 1e.
Is electrically connected to the high-concentration drain region 1e. The above-described pixel electrode 9a is provided on the upper surface of the third interlayer insulating layer 7 configured as described above.

The TFT 30 preferably has an L level as described above.
Although it has a DD structure, it may have an offset structure in which impurity ions are not implanted in the low-concentration source region 1b and the low-concentration drain region 1c, or implant high-concentration impurity ions using the gate electrode 3a as a mask to achieve self-alignment. A self-aligned TFT that forms the high concentration source region 1d and the drain region 1e may be used. Further, as shown in FIG. 3, in the present embodiment, two gate electrodes to which the same scanning signal is supplied via the gate insulating film 2 between the high concentration source region 1d and the high concentration drain region 1b of the TFT 30. By providing 3a, a TFT having a dual gate (double gate) structure may be provided. Thereby, TFT3
0 leakage current can be reduced. Further, when the dual gate structure TFT has the above-described LDD structure or offset structure, the leakage current of the TFT 30 can be further reduced, and a high contrast ratio can be realized. Further, with the dual gate structure, redundancy can be provided, and not only pixel defects can be significantly reduced, but also a high-contrast image quality can be realized due to a low leak current even during high-temperature operation. It goes without saying that the number of gate electrodes 3a provided between the high-concentration source region 1d and the high-concentration drain region 1b of the TFT 30 may be three or more.

Here, in general, the polysilicon layers such as the channel formation region of the semiconductor layer 1a, the low-concentration source region 1b, and the low-concentration drain region 1c have a photocurrent due to the photoelectric conversion effect of the polysilicon when light enters. However, in the present embodiment, the data line 6a (source electrode) is formed of a light-shielding metal thin film such as Al so as to cover the scanning line 3a (gate electrode) from above. Since it is formed, at least the channel forming region 1 a ′ of the semiconductor layer 1 a and the LDD region 1
It is possible to effectively prevent the projection light (that is, light from the upper side in FIG. 3) from being incident on b and 1c. Also, as mentioned above,
Since the light shielding layer 11a is provided below the TFT 30, at least the channel forming region 1 of the semiconductor layer 1a is provided.
a ′ and the return light to the LDD regions 1b and 1c (that is, FIG.
Thus, the incidence of light from below can be effectively prevented.

As shown in FIG. 6, a storage capacitor 70 is provided in each of the pixel electrodes 9a. This storage capacity 70
More specifically, the first storage capacitor electrode 1 is formed by the same process as that of the semiconductor layer 1a, and is formed of a polysilicon film extending from the high-concentration drain region 1e of the semiconductor layer 1a.
f, an insulating layer 2 ′ formed via the gate insulating layer 2, a capacitor line 3 b (second storage capacitor electrode) formed in the same process as the scanning line 3 a (gate electrode), a second and third interlayer insulating layer 4 and 7, and a part of the pixel electrode 9a facing the capacitor line 3b via the second and third interlayer insulating layers 4 and 7. Since the storage capacitor 70 is provided as described above, the duty ratio is small, and high-definition display without flicker is possible. As shown in FIG. 1, the capacitor line 3b (second storage capacitor electrode) is provided on the surface of the TFT array substrate 10 in parallel with the scanning line 3a (gate electrode). Further, in the present embodiment, the first storage capacitor electrode 1
Since the first interlayer insulating layer 12 ′ below f can be made thinner, the storage capacity can be increased, and a liquid crystal panel with high image quality can be realized.

In the present embodiment, the first interlayer insulating layer in the formation region including all of the semiconductor layer 1a, the data line 6a, the scanning line 3a, and the capacitance line 3b shown in FIG. 1 is thinned. When it is considered that the signal delay of the signal or the scanning signal becomes an unacceptable level or affects the transistor characteristics of the pixel switching TFT 30, the semiconductor layer 1a, the data line 6a, the scanning line 3a, and the capacitance line The thickness of the first interlayer insulating layer in at least one region of 3b may be reduced.

The liquid crystal panel 100 configured as described above
Will be described with reference to FIGS. 8 and 9. FIG. FIG. 8 is a plan view of the TFT array substrate 10 together with the components formed thereon as viewed from the counter substrate 20 side.
FIG. 9 is a cross-sectional view taken along the line HH ′ of FIG. 8 including the counter substrate 20.

In FIG. 8, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof.
In parallel to the inside, a light-shielding peripheral partition 53 made of the same or different material as the second light-shielding layer 23 such as a black matrix is provided. The data line driving circuit 101 and the mounting terminals 10 are provided outside the sealing material 52.
2 are provided along one side of the TFT array substrate 10, and the scanning line drive circuit 104 is provided along two sides adjacent to the one side. Further, on one remaining side of the TFT array substrate 10, a plurality of wirings 105 for electrically connecting the scanning line driving circuits 104 provided on both sides of the screen display area are provided. Further, at least one of the corners of the opposing substrate 20, the TFT array substrate 1
A silver point 106 made of a conductive material for providing electrical continuity between 0 and the counter substrate 20 is provided. And FIG.
As shown in FIG. 8, the counter substrate 20 having substantially the same contour as the sealing material 52 shown in FIG.
It is fixed to the array substrate 10.

The data line driving circuit 101 and the scanning line driving circuit 104 are electrically connected to the data line 6a (source electrode) and the scanning line 3a (gate electrode) by wiring. An image signal converted into a format that can be immediately displayed from a control circuit (not shown) is input to the data line driving circuit 101, and the scanning line driving circuit 104 sequentially sends a gate voltage to the scanning line 3a in a pulsed manner. Then, the data line driving circuit 101 sends a signal voltage corresponding to the image signal to the data line 6a (source electrode). In the present embodiment, in particular, the TFT 30
Since is a p-Si (polysilicon) type TFT, the data line driving circuit 101 and the scanning line driving circuit 104 can be formed in the same step when the TFT 30 is formed, which is advantageous in manufacturing.

FIG. 10 shows a two-dimensional layout on the TFT array substrate 100 of the light shielding layer 11b forming the light shielding wiring portion.

As shown in FIG. 10, the light-shielding layer 11a has the scanning lines 3a,
The capacitor line 3b and the data line 6a (not shown) are routed so as to overlap each other, and are routed outside the screen display area so as to pass under the peripheral partition 53 on the counter substrate 20,
It is connected to a constant potential line as shown in FIG. With such wiring, the dead space below the peripheral partition 53 can be used effectively, and the area for curing the sealing material can be increased. Further, the peripheral partition 53 provided on the opposite substrate 20 is formed on the TFT array substrate 10 by using the light shielding layer 11a.
And the same material as above, so as to be electrically connected to the light shielding layers 11a and 11b. Thus, the peripheral parting 53
Since the second light-shielding layer on the opposing substrate 20 is not required by incorporating the liquid crystal panel, the precision at the time of bonding the TF array substrate 10 and the opposing substrate 20 can be neglected, and a bright liquid crystal device with a uniform transmittance can be obtained. realizable. Further, the light-shielding layer 11a may be provided only along the scanning line 3a and below it, or may be provided only below the data line 6a. Light-shielding layer 11 described above
The arrangement method a is selected in consideration of the layer thickness of the step portion and the yield.

8 to 10, on the TFT array substrate 10, a precharge circuit for supplying a precharge signal of a predetermined voltage level to the plurality of data lines 6a prior to the image signal, respectively, A sampling circuit for sampling and supplying each to the plurality of data lines 6a,
An inspection circuit or the like for inspecting the quality, defect, or the like of the liquid crystal device during manufacturing or shipping may be formed. Instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, a driving LSI mounted on a TAB (tape automated bonding substrate) is provided around the TFT array substrate 10. The connection may be made electrically and mechanically via an anisotropic conductive film provided in the portion.

Although not shown in FIGS. 1 to 10, the side of the opposite substrate 20 on which the projected light is incident and the side of the TFT array substrate 10 on which the emitted light is emitted are, for example, T
Depending on operation modes such as N (twisted nematic) mode, STN (super TN) mode, D-STN (double-STN) mode, and normally white mode / normally black mode, a polarizing film,
A retardation film, a polarizing plate and the like are arranged in a predetermined direction.

Next, the operation of the present embodiment configured as described above will be described with reference to FIG. 3 and FIGS.

First, the data line driving circuit 101 receiving the image signal from the control circuit applies the signal voltage to the data line 6a (source electrode) at the timing and magnitude corresponding to the image signal.
, And in parallel with this, the scanning line driving circuit 104
A gate voltage is sequentially applied to the scanning line 3a (gate electrode) in a pulsed manner at a predetermined timing, and the TFT 30 is driven.
Thereby, in the TFT 30 to which the source voltage is applied at the time when the gate voltage is turned on, the source regions 1d and 1b of the semiconductor layer 1a, the channel formed in the channel forming region 1a ', and the drain regions 1c and 1e are formed. A voltage is applied to the pixel electrode 9a through the gate. The voltage of the pixel electrode 9a is held by the storage capacitor 70 (see FIG. 6) for a time longer than the time when the source voltage is applied, for example, by three digits.

As described above, when a voltage is applied to the pixel electrode 9a, the alignment state of the liquid crystal in the portion of the liquid crystal layer 50 between the pixel electrode 9a and the common electrode 21 changes, and the normally white mode In this case, the projection light cannot pass through the liquid crystal portion according to the applied voltage.In the normally black mode, the projection light can pass through the liquid crystal portion according to the applied voltage. As a whole, light having a contrast according to the image signal is emitted from the liquid crystal panel 100.

In particular, in the present embodiment, the TFT 30 is excellent in light-shielding properties and the adverse effect of the return light is reduced, so that the transistor characteristics of the TFT 30 are improved, and the first interlayer insulating layer 12 ′ is formed of the TFT 30. And various wirings are formed in a concave shape at a position facing the wiring, so that defective alignment of liquid crystal is reduced, and finally, a high-contrast, high-quality image can be displayed by the liquid crystal panel 100. It becomes possible.

Since the liquid crystal panel 100 described above is applied to a color liquid crystal projector, three liquid crystal panels 100 are used as light valves for RGB, respectively.
The light of each color separated through the dichroic mirror for RGB color separation is incident on each panel as projection light. Therefore, in each embodiment, the counter substrate 20 is not provided with a color filter. However, even in the liquid crystal panel 100, an RGB color filter and a protective film thereof are provided in a predetermined area facing the pixel electrode 9 a where the black matrix 23 is not formed.
It may be formed on the counter substrate 20. If you do this,
The liquid crystal panel of the present embodiment can be applied to a color liquid crystal device such as a direct-view type or reflection type color liquid crystal television other than the liquid crystal projector. Further, a micro lens may be formed on the counter substrate 20 so as to correspond to one pixel. In this case, a bright liquid crystal panel can be realized by improving the efficiency of collecting incident light. Furthermore, a dichroic filter that produces RGB colors using light interference may be formed by depositing a number of interference layers having different refractive indexes on the counter substrate 20. According to the counter substrate with a dichroic filter, a brighter color liquid crystal panel can be realized.

In the liquid crystal panel 100, the projection light is made incident from the side of the counter substrate 20 as in the conventional case. However, since the light shielding layer 11a is present, the projection light is made incident from the side of the TFT array substrate 10 and The light may be emitted from the side of the substrate 20. That is, even if the liquid crystal panel 100 is attached to the liquid crystal projector in this manner, light can be prevented from being incident on the channel forming region 1a 'and the LDD regions 1b and 1c of the semiconductor layer 1a, and a high quality image can be displayed. It is possible to Here, conventionally, in order to prevent reflection on the back surface side of the TFT array substrate 10, it has been necessary to separately arrange a polarizing plate coated with an AR coating for antireflection or attach an AR film. However, in the present embodiment, at least the channel forming region 1a 'and the LDD region 1b of the surface of the TFT array substrate 10 and the semiconductor layer 1a are formed.
Since the light-shielding layer 11a is formed between the light-shielding layer 11a and the light-shielding layer 1c, it is not necessary to use such an AR-coated polarizing plate or AR film, or to use a substrate obtained by subjecting the TFT array substrate 10 itself to an AR treatment. Therefore, according to the present embodiment, the material cost can be reduced, and the yield is not significantly reduced due to dust, scratches or the like at the time of attaching the polarizing plate, which is very advantageous. In addition, since light resistance is excellent, even if a bright light source is used or polarization conversion is performed by a polarizing beam splitter to improve light use efficiency, image quality deterioration such as crosstalk due to light does not occur.

In the liquid crystal panel 100, a flattening film may be further applied on the third interlayer insulating layer 7 by spin coating or the like in order to further suppress poor alignment of liquid crystal molecules on the TFT array substrate 10 side. Alternatively, a CMP process may be performed. Alternatively, the third interlayer insulating layer 7 may be formed of a flattening film. In the present embodiment, as shown in FIGS. 3 to 7, the TF is reduced by the concave depression of the first interlayer insulating layer 12 '.
Since the portion where the T30 and various wirings are formed and the other portion have almost the same height, such a flattening process is not generally necessary. However, in order to display a higher quality image, This embodiment is very advantageous because even when the uppermost layer is further planarized, the planarization film can be made very thin or only a slight planarization process is required.

The switching element of the liquid crystal panel 100 is a regular stagger type or coplanar type polysilicon TF.
Although described as T, the present embodiment is also effective for other types of TFTs such as an inverted stagger type TFT and an amorphous silicon TFT.

Further, in the liquid crystal panel 100, the liquid crystal layer 50 is constituted by a nematic liquid crystal as an example.
The use of a polymer-dispersed liquid crystal in which liquid crystals are dispersed as fine particles in a polymer eliminates the need for the alignment films 19 and 22 and the above-described polarizing film and polarizing plate, and increases the light use efficiency, thereby increasing the efficiency of the liquid crystal panel. Advantages of high luminance and low power consumption can be obtained. Further, when the liquid crystal panel 10 is applied to a reflective liquid crystal device by forming the pixel electrode 9a from a metal film having a high reflectivity such as Al, the SH in which the liquid crystal molecules are almost vertically aligned in the state where no voltage is applied. (Super homeotropic) type liquid crystal may be used. Furthermore, in the liquid crystal panel 100, the common electrode 21 is provided on the side of the counter substrate 20 so as to apply a vertical electric field (vertical electric field) to the liquid crystal layer 50. Each pixel electrode 9a is composed of a pair of electrodes for generating a horizontal electric field so as to apply an electric field (i.e., without providing an electrode for generating a vertical electric field on the side of the counter substrate 20, the side of the TFT array substrate 10). It is also possible to provide an electrode for generating a horizontal electric field at the same time. The use of the horizontal electric field is advantageous in widening the viewing angle as compared with the case of using the vertical electric field. Others
The present embodiment can be applied to various liquid crystal materials (liquid crystal phases), operation modes, liquid crystal alignment, a driving method, and the like.

(Manufacturing Process) Next, a manufacturing process of the liquid crystal panel 100 having the above configuration will be described with reference to FIG.
This will be described with reference to FIG. 11 to 14.
In FIG. 3A, each layer on the TFT array substrate side in each process is shown.
FIG. 15 to FIG. 18 are process diagrams showing respective layers on the TFT array substrate side in respective processes corresponding to the BB ′ cross section of FIG.
9 to 22 are process diagrams showing respective layers on the TFT array substrate side in respective steps corresponding to the cross section taken along the line CC ′ in FIG. 6, and FIGS. 23 to 26 are diagrams showing each layer on the TFT array substrate side in each process. FIG. 7 is a process drawing corresponding to the DD ′ cross section of FIG. 7. The steps (1) to (20) shown in each figure are collectively performed as the same step in different portions on the TFT array substrate 1.

First, referring to FIGS. 11 to 14, FIG.
The manufacturing process of the portion including the TFT 30 corresponding to the AA ′ section of FIG.

As shown in step (1) of FIG. 11, a TFT array substrate 10 such as a quartz substrate or hard glass is prepared. Here, annealing is preferably performed in an inert gas atmosphere such as N ₂ (nitrogen) and at a high temperature of about 900 to 1300 ° C., and a pre-treatment is performed so that distortion generated in the TFT array substrate 10 in a high-temperature process performed later is reduced. Keep it. That is, the TFT array substrate 10 is preliminarily heat-treated at the same temperature or higher in accordance with the highest processing temperature at the highest temperature in the manufacturing process.

The TFT array substrate 1 thus processed
0, a metal film such as Ti, Cr, W, Ta, Mo and Pd, or a metal alloy film such as a metal silicide is formed by sputtering to a light-shielding film having a layer thickness of about 1000 to 3000 °, preferably about 2000 °. 11 is formed.

Subsequently, as shown in step (2), a resist mask corresponding to the pattern of the light shielding layer 11a is formed on the formed light shielding film 11 by photolithography.
The light-shielding film 11 is etched through the resist mask to form a light-shielding layer 11a.

Next, as shown in step (3), the light shielding layer 11
a, for example, by a normal pressure or reduced pressure CVD method or the like.
OS (tetra-ethyl-ortho-silicate) gas, T
EB (Tetra ethyl boat rate) gas, TMOP
(Tetramethyl oxyphosphate) gas or the like, a first insulating layer 12 (a two-layer first insulating layer) made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like. (Under the interlayer insulating layer 12 '). The layer thickness of the first insulating layer 12 is, for example, about 8000 to 12000 °.

Next, as shown in step (4), the TFT 3
Etching is performed on a region where the data line 6, the data line 6 a, the scanning line 3 a, and the capacitor line 3 b are to be formed above, and the first insulating layer 12 in this region is removed. Here, when the etching is performed by dry etching such as reactive etching or reactive ion beam etching, the first insulating layer 12 can be anisotropically removed in the same size as the resist mask formed by photolithography. There is an advantage that it can be easily controlled according to dimensions. On the other hand, when at least wet etching is used, the opening region of the first interlayer insulating layer 12 is widened due to isotropic properties. However, since the side wall surface of the opening portion can be formed in a tapered shape, for example, scanning in a later step is performed. The polysilicon film and the resist for forming the line 3a do not remain around the side wall of the opening without being etched or peeled off, and the yield does not decrease. In addition, as a method of forming the side wall surface of the opening portion of the first interlayer insulating layer 12 in a tapered shape, the resist pattern is recessed by etching once by dry etching.
Dry etching may be performed again.

Next, as shown in step (5), the light shielding layer 11
a and a second insulating layer 13 (a two-layer first interlayer insulating layer 12) made of a silicate glass film, a silicon nitride film, a silicon oxide film, or the like, like the first insulating layer 12. 'Upper layer). The layer thickness of the second insulating layer 13 is, for example, about 1000 to 2000 °. Second
By subjecting the insulating layer 13 to an annealing process at about 900 ° C., contamination may be prevented and planarization may be performed.

In the present embodiment, in particular, the layer thicknesses of the first insulating layer 12 and the second insulating layer 13 forming the first interlayer insulating layer are as follows:
The pixel region is set so as to be substantially flat before the pixel electrode 9a is formed later.

Next, as shown in step (6), a temperature of about 450 to 550 ° C., preferably about 500 ° C. is formed on the second insulating layer 13.
Flow rate of about 400 to 600 cc /
An amorphous silicon film is formed by low-pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa) using a monosilane gas, a disilane gas, or the like for min. Thereafter, in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours,
Preferably, the polysilicon film 1 is solid-phase grown to a thickness of about 500 to 2000 、, preferably about 1000 Å by performing an annealing process for 4 to 6 hours. At this time, when fabricating the n-channel TFT 30, a dopant of a group V element such as Sb (antimony), As (arsenic), or P (phosphorus) is slightly doped by ion implantation or the like. When the TFT 30 is of a p-channel type, B (boron), Ga (gallium), In
A dopant of a group III element such as (indium) is slightly doped by ion implantation or the like. The polysilicon film 1 may be directly formed by a low pressure CVD method or the like without passing through the amorphous silicon film. Alternatively, the polysilicon film 1 may be formed by implanting silicon ions into a polysilicon film deposited by a low-pressure CVD method or the like to make the polysilicon film once amorphous (amorphized), and then recrystallize by annealing or the like.

Next, as shown in step (7) of FIG. 12, a photolithography step, an etching step, etc.
A semiconductor layer 1a having a predetermined pattern as shown in FIG.

Next, as shown in step (8), the semiconductor layer 1
a at a temperature of about 900-1300 ° C., preferably about 100
By thermally oxidizing at a temperature of 0 ° C., a relatively thin thermal oxide film of about 300 ° is formed, and a high-temperature silicon oxide film (HTO film) or a nitride film of about 500 ° is formed by a low pressure CVD method or the like. The gate insulating layer 2 is deposited to a small thickness and has a multilayer structure. As a result, the thickness of the semiconductor layer 1a is about 300 to 1500 °, preferably about 35 °.
The thickness of the gate insulating layer 2 is 0 to 500 °.
Thickness of about 200-1500 °, preferably about 300-1
000 mm thick. By shortening the high-temperature thermal oxidation time in this way, warpage due to heat can be prevented particularly when a large substrate of about 8 inches is used. However, the gate insulating layer 2 having a single-layer structure may be formed only by thermally oxidizing the polysilicon layer 1.

Next, as shown in step (9), low pressure CVD
After depositing a polysilicon layer 3 by a method such as phosphorus (P)
Is thermally diffused to make the polysilicon film 3 conductive. Or P
A doped silicon film in which ions are introduced simultaneously with the formation of the polysilicon film 3 may be used. As shown in step (10), a scanning line 3a (gate electrode) having a predetermined pattern as shown in FIG. 1 is formed by a photolithography step using a mask, an etching step, or the like. The layer thickness of the scanning line 3a (gate electrode) is, for example, about 3500 °.

However, the scanning line 3a (gate electrode) may be formed of a refractory metal film such as W (tungsten) or Mo (molybdenum) or a metal silicide film instead of the polysilicon layer, or may be formed of these. The metal film or the metal silicide film and the polysilicon film may be combined to form a multilayer. In this case, if the scanning line 3a (gate electrode) is arranged as a light-shielding film corresponding to part or all of the area covered by the second light-shielding layer 23, the second light-shielding property of the metal film or the metal silicide film is obtained. Some or all of the layer 23 can be omitted. In this case, in particular, there is an advantage that the pixel aperture ratio can be prevented from lowering due to misalignment between the opposing substrate 20 and the TFT array substrate 10.

Next, as shown in step (11), the TFT 3
When 0 is an n-channel TFT having an LDD structure, first, a low-concentration source region 1b is formed in a p-type semiconductor layer 1a.
And to form a low-concentration drain region 1c, the scanning line 3a (gate electrode) as a diffusion mask, a dopant 200 of a group V element such as P low concentration (e.g., a P ion 1 to 3 × 10 ¹³ / (dose at a dose of cm ² ). As a result, the semiconductor layer 1a below the scanning line 3a (gate electrode) becomes a channel forming region 1a '.

Subsequently, as shown in step (12) of FIG. 13, the high-concentration source region 1b and the high-concentration drain region 1c
After forming a resist layer 202 on the scanning line 3a (gate electrode) using a mask wider than the scanning line 3a (gate electrode), a dopant 201 of a group V element such as P (For example, P ion is 1 to 3 ×
Doping (at a dose of 10 ¹⁵ / cm ² ). Also, T
When the FT 30 is a p-channel type, the n-type semiconductor layer 1
a, a lightly doped source region 1b and a lightly doped drain region 1
In order to form c and the high-concentration source region 1d and the high-concentration drain region 1e, doping is performed using a dopant of a group III element such as B. When the LDD structure is used as described above, an advantage that the short channel effect can be reduced can be obtained. Note that, for example, a TFT having an offset structure may be used without doping at a low concentration, and a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, or the like, using the scanning line 3a (gate electrode) as a mask. It may be.

In parallel with these steps, an n-channel polysilicon TFT and a p-channel polysilicon TFT
A data line driving circuit 101 and a scanning line driving circuit 104 having a CMOS (complementary MOS) structure
It is formed in the peripheral portion on the T array substrate 10. in this way,
Since the TFT 30 is a polysilicon TFT, the TFT 3
The data line driving circuit 101 and the scanning line driving circuit 104 can be formed in the same step when 0 is formed, which is advantageous in manufacturing.

Next, as shown in step (13), scan line 3
a (gate electrode) by using NSG, PSG,
A second interlayer insulating layer 4 made of a silicate glass film such as BSG or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The layer thickness of the second interlayer insulating layer 4 is about 5000 to 1
5000 ° is preferred.

Next, as shown in a step (14), an annealing process at about 1000 ° C. is performed for about 20 minutes to activate the high-concentration source region 1d and the high-concentration drain region 1e. The contact hole 5a for the electrode is formed by dry etching such as reactive etching or reactive ion beam etching. At this time, the contact holes 5 are formed by anisotropic etching such as reactive etching and reactive ion beam etching.
Opening a has the advantage that the opening shape can be made almost the same as the mask shape. However, if the opening is formed by a combination of dry etching and wet etching, the contact hole 5a can be formed into a tapered shape, so that there is an advantage that disconnection during wiring connection can be prevented. Further, a contact hole for connecting the scanning line 3a (gate electrode) to a wiring (not shown) is also formed in the second interlayer insulating layer 4 in the same process as the contact hole 5a.

Next, as shown in step (15), a low-resistance metal such as Al or a metal silicide having a light-shielding property is formed on the second interlayer insulating ~ 5000mm thick, preferably about 3
Then, as shown in step (16), a data line 6a (source electrode) is formed by a photolithography step, an etching step, or the like.

Next, as shown in step (17) of FIG.
To cover the data line 6a (source electrode), for example,
NS using normal pressure or low pressure CVD method, TEOS gas, etc.
A third interlayer insulating layer 7 made of a silicate glass film such as G, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the third interlayer insulating layer 7 is preferably about 5000-15000 °.

In the present embodiment, in particular, in steps (4) and (5) of FIG. 11, the first interlayer insulating layer is formed to be concave in the TFT 30 and various wiring portions. At the stage after step ()), the surface of the pixel region becomes substantially flat. In order to make the third interlayer insulating layer 7 flatter, an organic film or SOG (spin-on glass) is spin-coated, or a CMP process is performed instead of or in place of the silicate glass film constituting the third interlayer insulating layer 7. Alternatively, a flat film may be formed.

Next, as shown in step (18), a contact hole 8 for electrically connecting the pixel electrode 9a and the high-concentration drain region 1e is formed by dry etching such as reactive etching or reactive ion beam etching. Form. At this time, the advantage that the contact hole 8 can be made almost the same as the mask shape by opening the contact hole 8 by anisotropic etching such as reactive etching or reactive ion beam etching is obtained. However, if the dry etching and the wet etching are performed in combination, the contact holes 8 can be tapered, so that there is an advantage that disconnection during wiring connection can be prevented.

Next, as shown in a step (19), the ITO is formed on the third interlayer insulating layer 7 by sputtering or the like.
A transparent conductive thin film 9 such as a film is deposited to a thickness of about 500 to 2000 Å, and as shown in a step (20), a pixel electrode 9 is formed by a photolithography step, an etching step and the like.
a is formed. When the liquid crystal panel 100 is used for a reflection type liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.

Subsequently, a coating liquid for a polyimide-based alignment film was applied onto the pixel electrode 9a, and then rubbed in a predetermined direction so as to have a predetermined pretilt angle, as shown in FIG. An alignment film 19 is formed.

On the other hand, as for the counter substrate 20 shown in FIG. 3, a glass substrate, a quartz substrate, or the like is first prepared, and the second light-shielding layer 23 and the light-shielding peripheral partition 53 are formed by sputtering metal chromium, for example. Lithography process,
It is formed through an etching process. The second light shielding layer 23
The peripheral partition 53 may be formed of a material such as resin black in which carbon or Ti is dispersed in a photoresist, in addition to a metal material such as Cr, Ni, or Al.

Thereafter, a transparent conductive thin film of ITO or the like is deposited on the entire surface of the counter substrate 20 by sputtering or the like for about 5 minutes.
The common electrode 21 is formed by depositing to a thickness of 00 to 2000 °. Further, an alignment film 22 is formed by applying a coating liquid for a polyimide-based alignment film to the entire surface of the common electrode 21 and then performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle.

Finally, the T on which each layer is formed as described above
The FT array substrate 10 and the counter substrate 20 are bonded together by a sealing material 52 so that the alignment films 19 and 22 face each other, and a plurality of types of nematic liquid crystals are mixed in a space between the two substrates by vacuum suction or the like. The liquid crystal is sucked to form a liquid crystal layer 50 having a predetermined thickness.

Next, referring to FIGS. 15 to 18, FIG.
The manufacturing process of the portion including the data line corresponding to the BB ′ section of FIG.

Step (1) in FIG. 15 to step (2) in FIG.
0) is performed as the same manufacturing process as the above-described step (1) of FIG. 11 to step (20) of FIG.

That is, as shown in step (1) of FIG.
After forming the light-shielding film 11 on the entire surface of the TFT array substrate 10, as shown in step (2), a light-shielding layer 11a is formed by a photolithography step, an etching step, or the like.

Next, as shown in step (3), the light shielding layer 11
a on the first insulating layer 12 (two first interlayer insulating layers 1).
2 ′ is formed, and as shown in step (4), etching is performed on a region where the data line 6a is to be formed above, and the first insulating layer 12 in this region is removed. Here, when the etching is performed by dry etching such as reactive etching or reactive ion beam etching, the first insulating layer 12 can be anisotropically removed in the same size as the resist mask formed by photolithography. There is an advantage that it can be easily controlled according to dimensions. On the other hand, when at least wet etching is used, the opening region of the first interlayer insulating layer 12 is widened due to isotropic properties. However, since the side wall surface of the opening portion can be formed in a tapered shape, for example, the capacitance in a later step is reduced. The polysilicon film and the resist for forming the line 3b do not remain around the side wall of the opening without being etched or peeled off, and the yield does not decrease. In addition, as a method of forming the side wall surface of the opening portion of the first interlayer insulating layer 12 into a tapered shape, dry etching may be performed once, the resist pattern may be recessed, and dry etching may be performed again.

Next, as shown in step (5), the light shielding layer 1
The second insulating layer 13 (the upper layer of the two first interlayer insulating layers 12 ′) is formed on the first insulating layer 12 and the first insulating layer 12 a.

Next, as shown in step (6), after forming an amorphous silicon film on the second insulating layer 13, the polysilicon film 1 is grown by solid phase.

Next, as shown in step (7) of FIG. 16, a photolithography step, an etching step, etc.
A semiconductor layer 1a having a predetermined pattern as shown in FIG.

Next, as shown in a step (8), the first storage capacitor electrode 1f is thermally oxidized or the like to form the gate insulating layer 2f.
To form Although not particularly limited, the first storage capacitor electrode 1
For example, a dose of about 3 × 10 ¹² / cm of P ions is added to e ′.
^It may be doped with ² to lower the resistance. The first storage capacitor electrode 15 is formed by extending the semiconductor layer 1a made of the polysilicon film 1. Further, after a polysilicon layer 3 is deposited thereon as shown in step (9), a predetermined pattern as shown in FIG. 1 is formed by photolithography and etching as shown in step (10). The capacitance line 3b is formed from the same layer as the scanning line 3a. Therefore, the capacitance line 3b
Is, for example, about 3500 °, similar to the scanning line 3a (gate electrode).

Next, as shown in step (11) of FIG. 16 and step (12) of FIG.
To further reduce the resistance of the capacitance line 3b.

Next, as shown in step (13), the capacitance line 3
b, a second interlayer insulating layer 4 is formed so as to cover
As shown in 4), a contact hole for connecting the capacitance line 3b to a wiring (not shown) is opened in the second interlayer insulating layer 4.

Next, as shown in step (15), Al or the like is deposited as a metal film 6 on the second interlayer insulating layer 4 by sputtering or the like, and then, as shown in step (16), The data line 6a (source electrode) is formed by a lithography process, an etching process, or the like.

Next, as shown in step (17) of FIG.
The third interlayer insulating layer 7 is formed so as to cover the data line 6a (source electrode).

In the present embodiment, in particular, the steps (4) and (5) in FIG.
Since the first interlayer insulating layer is formed in a concave shape, the surface of the pixel region becomes almost flat at the stage after the step (17) is completed.

Next, in step (18) of FIG. 18, after waiting for the contact hole 8 to be opened, as shown in step (19), an ITO film or the like is formed on the third interlayer insulating layer 7. A transparent conductive thin film is deposited, and a pixel electrode 9a is formed by a photolithography step, an etching step, and the like, as shown in step (20).

Next, referring to FIGS. 19 to 22, FIG.
The manufacturing process of the portion including the scanning line and the capacitance line corresponding to the section taken along line CC ′ of FIG.

Step (1) in FIG. 19 to step (2) in FIG.
0) is performed as the same manufacturing process as the above-described step (1) of FIG. 11 to step (20) of FIG.

That is, as shown in step (1) of FIG.
After forming the light-shielding film 11 on the entire surface of the TFT array substrate 10, as shown in step (2), a light-shielding layer 11a is formed by a photolithography step, an etching step, or the like.

Next, as shown in step (3), the light shielding layer 11
a on the first insulating layer 12 (two first interlayer insulating layers 1).
2 ′), and as shown in step (4), etching is performed on a region where the scanning line 3a and the capacitor line 3b are to be formed above, and the first insulating layer 12 in this region is removed. Remove. Here, when the etching is performed by dry etching such as reactive etching or reactive ion beam etching, the first insulating layer 12 can be anisotropically removed in the same size as the resist mask formed by photolithography. There is an advantage that it can be easily controlled according to dimensions. On the other hand, when at least wet etching is used, the opening region of the first interlayer insulating layer 12 is widened due to isotropic properties. However, since the side wall surface of the opening portion can be formed in a tapered shape, for example, the capacitance in a later step is reduced. The polysilicon film and the resist for forming the line 3b do not remain around the side wall of the opening without being etched or peeled off, and the yield does not decrease. The first interlayer insulating layer 1
As a method of forming the side wall surface of the opening portion 2 in a tapered shape, dry etching may be performed once, then the resist pattern is retreated, and dry etching is performed again.

Next, as shown in step (5), the light shielding layer 1
The second insulating layer 13 (the upper layer of the two first interlayer insulating layers 12 ′) is formed on the first insulating layer 12 and the first insulating layer 12 a.

Next, as shown in step (6), after an amorphous silicon film is formed on the second insulating layer 13, the polysilicon film 1 is grown by solid phase.

Next, as shown in step (7) of FIG. 20, a photolithography step, an etching step, etc.
A first storage capacitor electrode 1f is formed by extending a semiconductor layer 1a made of a polysilicon film 1 having a predetermined pattern as shown in FIG.

Next, as shown in step (8), the first insulating capacitor electrode 1f is thermally oxidized to form the gate insulating layer 2f.
After a polysilicon layer 3 is deposited thereon as shown in step (9), a photolithography step, an etching step, and the like are carried out as shown in step (10), as shown in FIG. The scanning lines 3a and the capacitance lines 3b having a predetermined pattern as described above are formed.

Next, as shown in step (11) of FIG. 20 and step (12) of FIG.
To further lower the resistance of the scanning line 3a and the capacitance line 3b.

Next, as shown in step (13), scan line 3
a, and a second interlayer insulating layer 4 is formed so as to cover the capacitor line 3a and the capacitor line 3b, and as shown in a step (14), a contact hole for connecting the scanning line 3a and the capacitor line 3b to a wiring (not shown) is formed in the second layer. A hole is formed in the interlayer insulating layer 4.

Next, as shown in step (15), Al or the like is deposited as a metal film 6 on the second interlayer insulating layer 4 by sputtering or the like, and then, as shown in step (16), A data line 6a (source electrode) that does not exist on the cross section is formed by a lithography process, an etching process, or the like.

Next, as shown in step (17) of FIG.
The third interlayer insulating layer 7 is formed so as to cover the second interlayer insulating layer 4.

In the present embodiment, the first interlayer insulating layer is formed so as to be depressed in the scanning line 3a and the capacitor line 3b particularly by the steps (4) and (5) in FIG. At the stage after the step (17), the surface of the pixel region becomes substantially flat.

Next, in a step (18) of FIG. 22, after waiting for the contact hole 8 to be formed, as shown in a step (19), an ITO film or the like is formed on the third interlayer insulating layer 7. A transparent conductive thin film 9 is deposited, and a pixel electrode 9a is formed by a photolithography step, an etching step, and the like as shown in a step (20).

Next, referring to FIGS. 23 to 26, FIG.
The manufacturing process of the portion including the connection portion between the light-shielding layer and the constant potential line corresponding to the section DD ′ of FIG.

Step (1) in FIG. 23 to step (2) in FIG.
0) is performed as the same manufacturing process as the above-described step (1) of FIG. 11 to step (20) of FIG.

That is, as shown in step (1) of FIG.
After the light-shielding film 11 is formed on the entire surface of the TFT array substrate 10, as shown in step (2), the light-shielding layer 11b is formed by a photolithography step, an etching step, or the like.

Next, as shown in step (3), the light shielding layer 11
b, a first insulating layer 12 (two first interlayer insulating layers 1)
2 ′), and as shown in step (4), etching is performed on a region where a connection portion is to be formed upward, and the first insulating layer 12 in this region is removed. As shown in (5), the second insulating layer 13 (the upper layer of the two first interlayer insulating layers 12 ′) is formed on the light shielding layer 11b and the first insulating layer 12.

Next, as shown in step (6), after an amorphous silicon film is formed on the second insulating layer 13, the polysilicon film 1 is grown by solid phase.

Next, in steps (7) and (8) of FIG.
Waiting for the formation of the semiconductor layer 1a and the gate insulating layer 2 in the pixel portion, and then depositing the polysilicon layer 3 once as shown in step (9), and then in this step as shown in step (10) The polysilicon layer 3 is entirely removed.

Next, as shown in step (11) of FIG. 20 and step (12) of FIG. 21, doping of impurity ions 200 and 201 for semiconductor layer 1a is completed.

Next, as shown in step (13), a second interlayer insulating layer 4 is formed so as to cover the first insulating layer 13, and as shown in step (14), the light shielding layer 11b and the constant potential line are formed. A contact hole 5b for connecting to the second interlayer insulating layer 4 is formed in the second interlayer insulating layer 4. At this time, since only the second insulating layer 13 of the first interlayer insulating layer 12 'is formed under the second interlayer insulating layer 4, the high concentration source region 1d of the semiconductor layer 1a is formed.
Then, the second interlayer insulating layer 4 is opened, and a contact hole 5 is formed.
A hole can be formed at once by the same etching step as the step of forming a (step (14) in FIG. 13).

Next, as shown in step (15), Al or the like is deposited as a metal film 6 on the second interlayer insulating layer 4 by a sputtering process or the like, and then, as shown in step (16), The constant potential line 6b is formed from the same layer (such as Al) as the data line by a lithography process, an etching process, or the like.

Next, as shown in step (17) of FIG.
The third interlayer insulating layer 7 is formed so as to cover the constant potential line 6b and the second interlayer insulating layer 4.

Next, in step (18) of FIG. 26, after waiting for the contact hole 8 to be opened, as shown in step (19), an ITO film or the like is formed on the third interlayer insulating layer 7. The transparent conductive thin film 9 is once deposited, and further, as shown in a step (20), all of this portion is removed by a photolithography step, an etching step and the like.

As described above, according to the liquid crystal panel manufacturing method of the present embodiment, the light shielding layer 11b and the constant potential line 6b
The second interlayer insulating layer 4 and the first insulating layer 1 are provided as contact holes 5b for connecting to the light shielding layer 11b.
3 (the upper layer of the first interlayer insulating layer) was opened,
As a contact hole 5a for connecting T30 to the data line 6a, the second interlayer insulating layer 4 is opened up to the semiconductor layer 1a. Therefore, these two types of contact holes 5a and 5b can be opened collectively, which is advantageous in manufacturing. For example, it is possible to collectively open such two types of contact holes 5a and 5b to have a predetermined depth by wet etching with a selection ratio set to an appropriate value. In particular, the step of opening these contact holes is facilitated according to the depth of the concave portion of the first interlayer insulating layer. Since a contact hole opening step (photolithography step, etching step, etc.) for connecting the light-shielding layer and the constant potential line can be omitted, an increase in the number of steps does not lead to an increase in manufacturing cost or a decrease in yield.

As described above, according to the manufacturing process of the present embodiment, the first portion in the concave portion is formed.
By controlling the thickness of the second insulating layer 13, the thickness of the interlayer insulating layer 12 'can be controlled relatively easily, reliably, and accurately. Therefore, the thickness of the first interlayer insulating layer 12 'in the concave portion can be made extremely small.

As shown in FIG. 4, when the first interlayer insulating layer 12 ″ is formed of a single layer,
Steps (1) to (20) are performed by slightly modifying steps (3), (4) and (5) shown in FIGS. 19 and 23, respectively.
Should be performed. That is, in the step (3), the light shielding layer 11
For example, a slightly thick single-layer first interlayer insulating layer 12 ″ such as about 10,000 to 15000 ° is deposited on the TFT a, and in step (4), the TFT 30, the data line 6a,
Etching is performed on a region where the scanning line 3a and the capacitor line 3b are to be formed above, so that the first interlayer insulating layer 12 "in this region is left with a thickness of about 1000 to 2000 degrees. Also in this case, the layer thickness of the unetched portion and the layer thickness of the etched portion of the first interlayer insulating layer 12 ″ are substantially flat before the pixel electrode 9a is formed later. Is set to be If the first interlayer insulating layer 12 ″ is formed of a single layer in this manner, it is not necessary to increase the number of layers as compared with the conventional case, and the layer thickness of the concave portion and the non-concave portion is reduced. It is convenient to control by controlling the etching time because flattening can be achieved.

(Electronic Apparatus) Next, an embodiment of an electronic apparatus including the liquid crystal panel 100 described in detail above will be described with reference to FIGS.

First, FIG. 27 shows the liquid crystal panel 10
1 shows a schematic configuration of an electronic device provided with 0.

In FIG. 27, the electronic equipment includes a display information output source 1000, a display information processing circuit 1002, and a drive circuit 1.
004, liquid crystal panel 100, clock generation circuit 1008
And a power supply circuit 1010. The display information output source 1000 includes a ROM (Read Only Memory),
It includes a RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit for tuning and outputting an image signal, and displays display information such as an image signal in a predetermined format based on a clock signal from a clock generation circuit 1008. Output to the information processing circuit 1002. The display information processing circuit 1002 includes various known processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit. Digital signals are sequentially generated from the information and output to the driving circuit 1004 together with the clock signal CLK. The drive circuit 1004 drives the liquid crystal panel 100. The power supply circuit 1010 supplies a predetermined power to each of the above-described circuits. Note that the drive circuit 1004 may be mounted on a TFT array substrate constituting the liquid crystal panel 100,
In addition, a display information processing circuit 1002 may be mounted.

Next, FIGS. 28 to 31 show specific examples of the electronic apparatus having the above configuration.

In FIG. 28, a liquid crystal projector 1100, which is an example of an electronic device, prepares three liquid crystal display modules each including the liquid crystal panel 100 in which the above-described drive circuit 1004 is mounted on a TFT array substrate, and each of them has a light for RGB. The projector is used as the bulbs 100R, 100G, and 100B. In the liquid crystal projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, 3
Mirrors 1106 and two dichroic mirrors 1
108, light components R corresponding to the three primary colors of RGB,
Light valve 100 divided into G and B and corresponding to each color
R, 100G and 100B respectively. At this time, in particular, the B light is used to prevent light loss due to a long optical path, so that the input lens 1122, the relay lens 1123 and the output lens
24, through a relay lens system 1121. Then, the light valves 100R, 100G and 10
The light components corresponding to the three primary colors modulated by 0B respectively are:
After being recombined by the dichroic prism 1112, it is projected as a color image on the screen 1120 via the projection lens 1114.

In the present embodiment, in particular, since the light shielding layer is also provided below the TFT, the reflected light and the projected light by the projection optical system in the liquid crystal projector based on the light projected from the liquid crystal panel 100 pass through. The reflected light from the surface of the TFT array substrate at the time of light emission, a part of the projected light (a part of the R light and the G light) that passes through the dichroic prism 1112 after being emitted from another liquid crystal panel, and the like are returned as TF.
Even if the light enters from the side of the T array substrate, it is possible to sufficiently shield light from a channel region such as a switching TFT of a pixel electrode. For this reason, even if a prism suitable for miniaturization is used for the projection optical system, an AR film for preventing return light is adhered between the TFT array substrate and the prism of each liquid crystal panel, or an AR coating is applied to the polarizing plate. This is very advantageous in reducing the size and simplification of the configuration.

In FIG. 29, a laptop personal computer (PC) 1200 compatible with multimedia, which is another example of the electronic apparatus, is similar to the liquid crystal panel 100 described above.
Is provided in the top cover case, and the CP
U, memory, modem, etc.
02 is incorporated in the main body 1204.

In FIG. 30, a pager 1300, which is another example of the electronic equipment, includes a liquid crystal panel 100 in which a driving circuit 1004 is mounted on a TFT array substrate in a metal frame 1302 to form a liquid crystal display module. 1306 including the circuit board 1
308, first and second shield plates 1310 and 131
It is housed together with two or two elastic conductors 1314 and 1316 and a film carrier tape 1318.
In the case of this example, the display information processing circuit 1002 (FIG.
7) may be mounted on the circuit board 1308 or on the TFT array substrate of the liquid crystal panel 100.
Further, the above-described drive circuit 1004 can be mounted on a circuit board 1308.

Since the example shown in FIG. 30 is a pager, a circuit board 1308 and the like are provided. However, the driving circuit 1004 and further the display information processing circuit 1002
Liquid crystal panel 100 mounted with a liquid crystal display module
In the case of, the liquid crystal panel 10
It is also possible to produce, sell, use, or the like as a liquid crystal device in which 0 is fixed or as a backlight type liquid crystal device in which a light guide 1306 is incorporated in addition to this.

Also, as shown in FIG.
In the case of the liquid crystal panel 100 on which the display circuit 4 and the display information processing circuit 1002 are not mounted, the driving circuit 1004 and the IC 1324 including the display information processing circuit 1002
(Tape Carrier Package) implemented on 22
The liquid crystal device 1320 can be physically, electrically, and electrically connected to the TFT array substrate 1320 via an anisotropic conductive film provided on a peripheral portion of the TFT array substrate 10 to be produced, sold, used, and the like.

In addition to the electronic devices described above with reference to FIGS. 28 to 31, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic organizer, a calculator, a word processor, an engineering machine, etc. A workstation (EWS), a mobile phone, a video phone, a POS terminal, a device having a touch panel, and the like are examples of the electronic device illustrated in FIG.

As described above, according to the present embodiment, it is possible to realize various electronic devices including the liquid crystal panel 100 capable of displaying high-quality images with high manufacturing efficiency.

[0177]

According to the liquid crystal panel of the present invention, the first interlayer insulating layer is formed such that a portion facing at least one of the TFT, the data line and the scanning line is recessed when viewed from the other substrate side. Since it is formed, flattening in the pixel portion is promoted, and steps such as application of a flattening film by spin coating and formation of a flattened insulating layer can be omitted or simplified.

In a liquid crystal panel of a type in which a light-shielding layer is provided below the TFT, the specificity of the structure in which an interlayer insulating layer is required on the light-shielding layer is positively utilized, so that the efficiency and the comparison can be improved. The pixel portion can be easily flattened, and high-quality image display can be performed by suppressing the alignment defect of the liquid crystal with a relatively simple configuration.

[0179]

[Brief description of the drawings]

FIG. 1 is a plan view of an adjacent pixel group on a TFT array substrate on which a data line, a scanning line, a pixel electrode, a light shielding layer, and the like are formed, provided in an embodiment of a liquid crystal panel according to the present invention.

FIG. 2 shows a TFT showing a connection portion between a light shielding layer and a constant potential line.
FIG. 3 is a plan view of an array substrate.

FIG. 3 is a cross-sectional view of the embodiment of the liquid crystal panel showing a cross section taken along line AA ′ of FIG. 1 together with a counter substrate and the like.

FIG. 4 is a cross-sectional view of a modification of the liquid crystal panel, showing a cross section taken along line AA ′ of FIG. 1 together with a counter substrate and the like.

FIG. 5 is a cross-sectional view of the liquid crystal panel showing a cross section taken along line BB ′ of FIG. 1 together with a counter substrate and the like.

FIG. 6 is a cross-sectional view of the liquid crystal panel showing a cross section taken along line CC ′ of FIG. 1 together with a counter substrate and the like.

FIG. 7 is a sectional view of the liquid crystal panel showing a section taken along line DD ′ of FIG. 1 together with a counter substrate and the like.

FIG. 8 is a plan view showing the overall configuration of the liquid crystal device of FIG.

9 is a cross-sectional view illustrating the entire configuration of the liquid crystal device of FIG.

FIG. 10 is a plan view on a TFT array substrate showing a two-dimensional layout of a light shielding layer forming a light shielding wiring.

FIG. 11 is a process diagram (part 1) showing the manufacturing process of the embodiment of the liquid crystal panel in order for the portion shown in FIG. 3;

FIG. 12 is a process diagram (part 2) illustrating the manufacturing process of the embodiment of the liquid crystal panel in order for the portion illustrated in FIG. 3;

FIG. 13 is a process diagram (part 3) showing the manufacturing process of the embodiment of the liquid crystal panel in order for the portion shown in FIG. 3;

FIG. 14 is a process diagram (part 4) for sequentially illustrating the manufacturing process of the embodiment of the liquid crystal panel for the portion shown in FIG. 3;

FIG. 15 is a process view (1) showing the manufacturing process of the embodiment of the liquid crystal panel in order for the portion shown in FIG. 5;

FIG. 16 is a process view (2) showing the manufacturing process of the embodiment of the liquid crystal panel in order for the portion shown in FIG. 5;

FIG. 17 is a process view (part 3) for sequentially illustrating the manufacturing process of the liquid crystal panel according to the embodiment for the portion shown in FIG. 5;

FIG. 18 is a process diagram (part 4) for sequentially illustrating the manufacturing process of the liquid crystal panel according to the embodiment for the portion shown in FIG. 5;

FIG. 19 is a process view (1) showing the manufacturing process of the embodiment of the liquid crystal panel in order for the portion shown in FIG. 6;

FIG. 20 is a process view (2) showing the manufacturing process of the embodiment of the liquid crystal panel in order for the portion shown in FIG. 6;

FIG. 21 is a process diagram (part 3) showing the manufacturing process of the embodiment of the liquid crystal panel in order for the portion shown in FIG. 6;

FIG. 22 is a process diagram (part 4) for sequentially illustrating the manufacturing process of the liquid crystal panel according to the embodiment for the portion shown in FIG. 6;

FIG. 23 is a process view (1) showing the manufacturing process of the embodiment of the liquid crystal panel in order for the portion shown in FIG. 7;

FIG. 24 is a process view (2) showing the manufacturing process of the embodiment of the liquid crystal panel in order for the portion shown in FIG. 7;

FIG. 25 is a process view (3) showing the manufacturing process of the embodiment of the liquid crystal panel in order for the portion shown in FIG. 7;

FIG. 26 is a process view (part 4) of the manufacturing process of the embodiment of the liquid crystal panel in order for the portion shown in FIG. 7;

FIG. 27 is a block diagram illustrating a schematic configuration of an electronic device according to an embodiment of the present invention.

FIG. 28 is a cross-sectional view illustrating a liquid crystal projector as an example of an electronic apparatus.

FIG. 29 is a front view showing a personal computer as another example of the electronic apparatus.

FIG. 30 is an exploded perspective view showing a pager as an example of the electronic apparatus.

FIG. 31 is a perspective view illustrating a liquid crystal device using TCP as an example of an electronic apparatus.

[Explanation of symbols]

 1a: semiconductor layer 1a ': channel forming region 1b: low-concentration source region (source-side LDD region) 1c: low-concentration drain region (drain-side LDD region) 1d: high-concentration source region 1e: high-concentration drain region 1f: 1 storage capacitor electrode 2 gate insulating film 3a scanning line (gate electrode) 3b capacitor line (second storage capacitor electrode) 4 second interlayer insulating layer 5a, 5b contact hole 6a data line (source electrode) 6b ... constant potential line 7 ... third interlayer insulating layer 8 ... contact hole 9a ... pixel electrode 10 ... TFT array substrate 11a, 11b ... light shielding layer (third storage capacitor electrode) 12 ... first insulating layer (of first interlayer insulating layer) Lower layer) 12 ′, 12 ″ first interlayer insulating layer 13 second insulating layer (upper layer of first interlayer insulating layer) 19 alignment film 20 counter substrate 21 common electrode 22 alignment film 23 first Shielding layer 30 ... TFT 50 ... liquid crystal layer 52 ... sealing member 53 ... peripheral partition 70 ... storage capacitor 100 ... liquid crystal panel 101 ... the data line driving circuit 104 ... scan line driver circuit

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 619A

Claims (19)

[Claims] A liquid crystal sealed between a pair of substrates; a plurality of data lines; a plurality of scanning lines intersecting the plurality of data lines; A plurality of thin film transistors connected to the data lines and the scan lines, a plurality of thin film transistors connected to the plurality of thin film transistors, and a first portion having a concave portion when viewed from the other substrate side of the pair of substrates. A liquid crystal panel comprising: an interlayer insulating film, wherein at least a part of the thin film transistor, the data line, and the scanning line is formed in the concave portion. 2. A liquid crystal is sealed between a pair of substrates,
A plurality of data lines on one of the pair of substrates;
A plurality of scanning lines intersecting the plurality of data lines; a plurality of thin film transistors connected to the plurality of data lines and the scanning lines; a plurality of pixel electrodes connected to the plurality of thin film transistors; A light-shielding layer provided at a position to cover at least a channel formation region as viewed from the one substrate side; and a first interlayer insulating film having a concave portion formed on the light-shielding layer. ,
A liquid crystal panel, wherein at least a part of the thin film transistor, the data line, and the scanning line is formed on the concave portion. 3. The liquid crystal panel according to claim 1, wherein the first interlayer insulating layer is formed of a single layer. 4. The first interlayer insulating layer includes a single-layer portion and a multilayer portion, wherein the single-layer portion is a concave portion and the multilayer portion is a concave portion. The liquid crystal panel according to claim 1, wherein the liquid crystal panel is a portion that is not bent. 5. The semiconductor device according to claim 1, further comprising: a plurality of capacitance lines provided on the one substrate in parallel with the plurality of scanning lines, respectively, for applying a predetermined capacitance to the plurality of pixel electrodes. 5. The liquid crystal panel according to claim 1, wherein the layer is formed so that a portion facing the capacitance line is also depressed in the concave shape. 6. The liquid crystal panel according to claim 4, wherein the light shielding layer is provided on the one substrate even at a position where the capacitance line overlaps when viewed from the one substrate side. 7. The semiconductor device according to claim 5, wherein the first interlayer insulating layer is formed in the concave shape at a depth corresponding to a total layer thickness of the light shielding layer, the semiconductor layer, and the capacitance line.
Or the liquid crystal panel according to 6. 8. The method according to claim 1, wherein the first interlayer insulating layer is formed to be concave in a depth corresponding to a total layer thickness of the light shielding layer, the semiconductor layer, the capacitance line and the data line. The liquid crystal panel according to claim 5, wherein: 9. The semiconductor layer forming the thin film transistor extends along the data line, and the light-shielding layer is provided on the one side even at a position where the data line overlaps when viewed from the one substrate side. 9. The liquid crystal panel according to claim 1, wherein the liquid crystal panel is provided on a substrate. 10. The liquid crystal panel according to claim 1, wherein the first interlayer insulating layer is made of a silicon oxide film or a silicon nitride film. 11. The light shielding layer is made of Ti, Cr, W, T
The liquid crystal panel according to any one of claims 1 to 10, comprising at least one of a, Mo, and Pd. 12. The liquid crystal panel according to claim 1, wherein the light shielding layer is connected to a constant potential source. 13. The device according to claim 12, wherein the first interlayer insulating layer is formed in the concave shape and is opened at a position where the light shielding layer and the constant potential source are connected. The liquid crystal panel according to 1. 14. The method for manufacturing a liquid crystal panel according to claim 3, wherein the step of forming the light-shielding layer in a predetermined region on the one substrate, and the step of forming an insulating layer on the one substrate and the light-shielding layer. Depositing; forming a resist pattern on the insulating layer corresponding to the concave portion by photolithography; and performing dry etching for a predetermined time through the resist pattern to form the concave portion. And a method for manufacturing a liquid crystal panel. 15. The method for manufacturing a liquid crystal panel according to claim 3, wherein the step of forming the light shielding layer in a predetermined region on the one substrate, and the step of forming a first insulating layer on the one substrate and the light shielding layer. Depositing a layer, forming a resist pattern corresponding to the concave portion on the first insulating layer by photolithography, etching the resist pattern to correspond to the concave portion. Removing the first insulating layer; and depositing a second insulating layer on the one substrate and the first insulating layer. 16. The method according to claim 15, wherein the etching is performed by at least dry etching. 17. The method according to claim 15, wherein the etching is performed by at least wet etching. 18. The method for manufacturing a liquid crystal panel according to claim 13, wherein the step of forming the light shielding layer in a predetermined region on the one substrate, a portion facing the thin film transistor, and the connection position Forming the first interlayer insulating layer on the one substrate and the light-shielding layer so that a portion corresponding to the concave shape is formed in the concave shape; forming the thin film transistor on the first interlayer insulating layer; Forming a second interlayer insulating layer on the first interlayer insulating layer; and forming a contact hole for connecting the light-shielding layer and a wiring from the constant potential source to the light-shielding layer at the connection position. The second and first interlayer insulating layers are opened up to the same time, and at the same time, the thin film transistor is used as a contact hole for connecting the thin film transistor and the data line. Forming a hole in the second and first interlayer insulating layers up to the semiconductor layer at a position facing the source or drain region of the semiconductor layer forming the transistor. . 19. An electronic apparatus comprising the liquid crystal panel according to claim 1. Description: