JP2001075123A - Electrooptical device, its manufacture and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the display quality from being lowered due to a projecting and recessing region produced on an interlayer insulation layer and to obtain an electrooptical device capable of performing a picture display of high quality by arranging a light shielding layer placed along a data line so as to overlap the edge parts of pixel electrodes. SOLUTION: A data line 6a is provided between second and third interlayer insulation layers 4 and 7. A third light shielding layer 24 is formed along the data line 6a in an island-shaped, is arranged in a region between the pixel electrodes 9a adjacent to each other and holds the data lines 6a between the electrodes 9a and itself. The edge parts of the third light shielding layer 24 and the electrodes 9a are located so as to overlap with themselves in plan view. Also, the third light shielding layer 24 is placed opposite to a projecting and recessing region of an alignment layer 16. Consequently when an alignment defect is generated in a liquid crystal layer 50 by the electrodes 9a or the alignment layer 16 provided in the region, the light shielding layer 24 shields the alignment defect part. Namely, the lowering of the contrast due to a light leaking or the like is prevented and the display quality is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an electro-optical device of an active matrix drive system and a method of manufacturing the same.
In particular, the present invention relates to an electro-optical device in which at least a part of a pixel opening is defined by a light shielding film called a black matrix, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a thin film transistor (Thin Film Tr) has been used.
In an electro-optical device of an active matrix drive system using a switching element such as a TFT (hereinafter, appropriately referred to as TFT), a large number of scanning lines and data lines arranged vertically and horizontally, and a large number of TFs corresponding to their intersections.
T is provided on the TFT array substrate. Each TFT
Has a gate electrode connected to the scanning line, a source region of the semiconductor layer connected to the data line, and a drain region of the semiconductor layer connected to the pixel electrode. Here, in particular, the pixel electrode is T
Since it is provided on an interlayer insulating film for insulating the various layers constituting the FT and the wiring and the pixel electrode from each other, the TFT is provided through a contact hole opened in the interlayer insulating film.
Is connected to the drain region of the semiconductor layer.
When a scanning signal is supplied to the gate electrode of the TFT via a scanning line, the TFT is turned on, and an image signal supplied to the source region of the semiconductor layer via the data line is supplied to the source-drain of the TFT. It is supplied to the pixel electrode through the space. Supply of such an image signal is performed only for an extremely short time for each pixel electrode via each TFT. For this reason, in order to hold the voltage of the image signal supplied via the TFT which has been turned on for an extremely short time for a much longer time than the time which has been turned on, each pixel electrode is In general, a storage capacitor is formed in parallel with a liquid crystal capacitor. On the other hand, in this type of electro-optical device, TF
From the semiconductor layer formed on the T-array substrate, a source region and a drain region of the pixel switching TFT and a channel region therebetween are formed. The pixel electrode needs to be connected to the drain region of the semiconductor layer via wiring such as a scanning line, a capacitor line, and a data line having a laminated structure and a plurality of interlayer insulating films for electrically insulating these from each other. is there.

Here, a positive stagger type or coplanar type polysilicon TF having a top gate structure in which a gate electrode is provided on a semiconductor layer when viewed from the TFT array substrate side.
Particularly in the case of T and the like, when the interlayer distance from the semiconductor layer to the pixel electrode in the laminated structure is increased to, for example, about 1000 nm or more, it is difficult to form a contact hole for electrically connecting the two. More specifically, the etching accuracy is reduced as the etching is performed deeper, and there is a possibility that a hole may be formed through the target semiconductor layer. It is extremely difficult to open the holes. For this reason, when trying to reduce the interlayer distance, there is a problem that unevenness occurs on the surface of the interlayer insulating film due to the lower layer and the internal structure of the interlayer insulating film. If the surface of the interlayer insulating film has irregularities, poor alignment of the liquid crystal layer occurs, which causes problems such as a decrease in contrast and a decrease in display quality.

Therefore, recently, when a contact hole reaching a source region of a semiconductor layer is opened in an interlayer insulating film formed on a scanning line to make an electrical connection between a data line and a source region, a semiconductor layer is formed. A contact hole reaching the drain region of the layer is opened to form a relay conductive layer called a barrier layer made of the same layer as the data line on the interlayer insulating film. A technique has been developed for forming a contact hole from a pixel electrode to this barrier layer in an interlayer insulating film formed on the layer. In this way, if the electrical connection from the pixel electrode to the drain region is made by relaying the barrier layer made of the same layer as the data line, a contact hole from the pixel electrode to the semiconductor layer at once can be opened. In addition, the contact hole opening step and the like can be facilitated, and the diameter of each contact hole can be reduced.

[0005] However, even when such a conductive layer such as a barrier layer is formed, there is a problem that unevenness occurs on the surface of the interlayer insulating film due to the formed conductive layer. If the surface of the interlayer insulating film has irregularities, poor alignment of the liquid crystal layer occurs, which causes problems such as a decrease in contrast and a decrease in display quality.

As described above, the electro-optical device has a problem that the surface of the interlayer insulating film has irregularities due to the lower layer and the internal structure of the interlayer insulating film. If the surface of the interlayer insulating film has irregularities, poor alignment of the liquid crystal layer occurs, which causes problems such as a decrease in contrast and a decrease in display quality.

[0007]

In this type of electro-optical device, there is a strong demand for a higher quality display image, which is achieved by increasing the definition of the image display area or the pixel pitch. And a high pixel aperture ratio (ie, in each pixel, a non-pixel aperture region through which display light does not pass)
It is extremely important to increase the ratio of the pixel opening area through which the display light is transmitted.

However, as the pixel pitch becomes finer, the electrode size, the wiring width, the contact hole diameter, and the like are inherently limited due to the manufacturing technology.
Since the ratio of these wirings and electrodes occupying the image display area is relatively increased, there is a problem that the pixel aperture ratio is reduced.

Further, as the pixel pitch becomes finer as described above, it becomes difficult to make the above-mentioned storage capacitance, which must be formed in a limited area on the substrate, sufficiently large. Here, in particular, according to the technique using the barrier layer described above, the barrier layer is formed of the same conductive film made of Al or the like as the data line, and therefore, depending on the position and material of the barrier layer, the contact The degree of freedom in opening holes is poor, and it is extremely difficult to use the barrier layer for applications other than the relay function, for example, to increase the storage capacity. However, it is not possible to simplify the configuration of the apparatus and to improve the efficiency of the manufacturing process. Further, according to this technique, a chemical reaction occurs when the Al film forming the barrier layer comes into contact with the ITO film forming the pixel electrode, and the Al film which is easily ionized is corroded. As a result, the electrical connection between the barrier layer and the pixel electrode is impaired.
In addition to the barrier layer, it is necessary to use a refractory metal thin film such as a Ti (titanium) film capable of obtaining good electrical connection with the ITO film as the second barrier layer. There is also a problem that it is complicated.

Further, for example, barrier layers, data lines, TFTs
For example, when unevenness occurs in the interlayer insulating film, poor alignment of the liquid crystal layer occurs, which causes problems such as a decrease in contrast and a decrease in display quality.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an electro-optical device capable of preventing a deterioration in display quality due to unevenness generated in an interlayer insulating film and capable of displaying high-quality images. The task is to provide.

[0012]

According to another aspect of the present invention, there is provided an electro-optical device including a substrate, a semiconductor layer and a gate electrode disposed on the substrate, with a gate insulating film interposed therebetween. A thin film transistor, a first interlayer insulating film made of a flattening film arranged to cover the thin film transistor, and a contact hole formed on the first interlayer insulating film and formed in the first interlayer insulating film. A data line electrically connected to the semiconductor layer, and a second line disposed to cover the first interlayer insulating film including the data line.
An interlayer insulating film, and a pixel electrode disposed on the second interlayer insulating film and electrically connected to the semiconductor layer via contact holes formed in the first interlayer insulating film and the second interlayer insulating film. And a light-shielding film disposed along the data line and disposed so as to overlap an end of the pixel electrode.

According to such a configuration of the present invention, when applied to a liquid crystal device as an electro-optical device, poor alignment of liquid crystal generated in a region between pixel electrodes adjacent to each other with a data line interposed therebetween is hidden by a light shielding film. This has the effect that the display quality can be improved. For example, the light-shielding film is made of opaque refractory metals such as Ti (titanium) and Cr.
(Chrome), W (tungsten), Ta (tantalum),
It is composed of a metal simple substance, an alloy, a metal silicide or the like containing at least one of Mo (molybdenum) and Pb (lead).

Further, the data line is arranged in a concave portion formed on a surface of the first interlayer insulating film. With such a configuration, when the electro-optical device is used, unevenness due to data lines on the substrate surface can be reduced, and the degree of liquid crystal misalignment generated in a region between pixel electrodes adjacent to each other across the data line can be reduced. This has the effect of reducing the size and improving the display quality. Furthermore, when forming an alignment film for aligning liquid crystal so as to cover the pixel electrode, the rubbing treatment at the time of forming the alignment film increases the surface smoothness of the alignment film. Can be smaller.

The width of the light shielding film is wider than the width of the concave portion. With such a configuration, the alignment defect of the liquid crystal generated in the vicinity of the concave portion can be reliably hidden by the light shielding film, and the display quality can be further improved.

Further, the semiconductor device further includes a conductive layer interposed between the semiconductor layer and the pixel electrode, electrically connected to the semiconductor layer, and electrically connected to the pixel electrode, the conductive layer being made of the same film as the light shielding film. It is characterized by doing. According to such a configuration, by providing the conductive layer between the pixel electrode and the semiconductor layer, the semiconductor layer is formed at the time of forming the contact hole, as compared with the case where the pixel electrode and the semiconductor layer are directly connected by one contact hole. This has the effect of preventing breakthrough. Further, by forming this conductive layer with the same film as the light-shielding film, the number of manufacturing steps can be reduced. Further, when the conductive layer is formed so as to overlap with the semiconductor layer, light incident on the electro-optical device does not enter the semiconductor layer; therefore, the conductive layer can be used as a barrier layer. Alternatively, a storage capacitor can be provided by disposing another conductive layer with an insulating film interposed therebetween so as to overlap the conductive layer in a planar manner.

According to another aspect of the invention, there is provided an electronic apparatus comprising: a light source; a light valve having the electro-optical device according to any one of the above, wherein the light emitted from the light source is incident and performs modulation corresponding to image information; Projection means for projecting light modulated by the light valve. According to such a configuration, there is an effect that an electronic device with high display quality is obtained.

Further, in the method of manufacturing an electro-optical device according to the present invention, a step of forming a switching element on a substrate; a step of forming a light-shielding film on the switching element via an insulating layer; Forming a first interlayer insulating film made of a planarizing film, forming a concave portion in the first interlayer insulating film selectively, and forming a data line connected to the switching element in the concave portion. A step of forming a second interlayer insulating film on the data line, and a step of forming a pixel electrode so as to be connected to the switching element via a contact hole formed in the second interlayer insulating film. Wherein at least a part of the light shielding film is formed so as to face the concave portion.

According to the structure of the present invention, the data line can be formed so as to be embedded in the concave portion of the first interlayer insulating film. Therefore, even if the end of the pixel electrode is arranged on the data line so as to overlap, the data line is formed in the concave portion, so that the data line is prevented from protruding, and the end of the pixel electrode is located on the data line. Irregularities can be reduced. Therefore, when the present invention is applied to a liquid crystal device, poor alignment of liquid crystal at the edge of the pixel electrode can be suppressed. In addition, since the light-shielding film is formed so as to face the concave portion, poor alignment of the liquid crystal at the edge of the pixel electrode can be hidden by the light-shielding film, and the display quality can be improved.

In the method of manufacturing an electro-optical device according to the present invention, the first interlayer insulating film is formed by a CMP method (Chemical Mechanical Polishing method).

According to the structure of the present invention, an insulating film having high flatness can be formed as the first interlayer insulating film by the CMP method.

In the method of manufacturing an electro-optical device according to the present invention, the width of the light shielding film is wider than the width of the concave portion.

According to the configuration of the present invention, the edge of the pixel electrode formed on the concave portion can be covered with the light shielding film. Therefore, for example, when the present invention is applied to a liquid crystal device, it is possible to cover the alignment defect of the liquid crystal at the end with the light shielding film, and to improve the display quality.

In the method of manufacturing an electro-optical device according to the present invention, the second interlayer insulating film is made of a flattening film.

According to this structure of the present invention, since the second interlayer insulating film is also formed of the flattening film, the pixel electrode formed thereon can be formed more flat, and the pixel electrode is formed by the step of the pixel electrode. Poor alignment can be suppressed, and display quality can be improved.

The operation and other advantages of the present invention will become more apparent from the embodiments explained below.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment of Electro-Optical Device) The configuration of a liquid crystal device which is a first embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. FIG.
FIG. 2 shows an equivalent circuit of various elements, wiring, and the like in a plurality of pixels formed in a matrix forming an image display area of a liquid crystal device. FIG. 2 shows a data line, a scanning line, a pixel electrode, a light shielding film, and the like. FIG. 3 is a plan view of a plurality of pixel groups adjacent to each other on the TFT array substrate, FIG. 3 is a cross-sectional view along AA ′ of FIG. 2, and FIG. 4 is a cross-sectional view of BB ′ of FIG. Note that FIG.
In FIG. 4, the scale of each layer and each member is different for each layer and each member in order to make the size recognizable in the drawing.

In FIG. 1, a plurality of pixels formed in a matrix and constituting an image display area of the liquid crystal device according to the present embodiment are provided with a TFT 3 for controlling a pixel electrode 9a.
A plurality of 0s are formed in a matrix, and the data line 6a to which an image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. good. Also, T
The scanning line 3a is electrically connected to the gate of the FT 30, and is configured to apply the scanning signals G1, G2,..., Gm in a pulsed manner to the scanning line 3a in this order at a predetermined timing. ing. The pixel electrode 9a is a TFT 30
Of the TFT 30 which is a switching element and is closed by a switch for a predetermined period, so that the image signal S supplied from the data line 6a is provided.
1, S2,..., Sn are written at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal via the pixel electrodes 9a are supplied to a counter substrate (described later).
Is maintained for a certain period of time with a counter electrode (to be described later). The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gray scale display. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. For example, the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time during which the source voltage is applied. Thereby, the holding characteristics are further improved,
A liquid crystal device having a high contrast ratio can be realized.

In FIG. 2, a plurality of transparent pixel electrodes 9a are arranged in a matrix on a TFT array substrate of a liquid crystal device.
(The outline is indicated by a dotted line portion 9a ′), and the data line 6a, the scanning line 3a, and the capacitor line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a.
The data line 6a is electrically connected to a source region described later in the semiconductor layer 1a made of a polysilicon film or the like via the contact hole 5, and the pixel electrode 9a is connected to a region shown by oblique lines rising to the right in the figure. The conductive layer 80 (hereinafter, referred to as a barrier layer), which is formed and functions as a buffer, is connected to a drain region of the semiconductor layer 1a via a first contact hole 8a and a second contact hole 8b. Electrically connected. In addition, the scanning line 3a is arranged so as to face the channel region 1a '(the hatched region downward in the figure) of the semiconductor layer 1a.
a functions as a gate electrode. Thus, scanning line 3
The TFT 30 is provided at each intersection of the data line 6a with the scanning line 3a facing the channel region 1a 'as a gate electrode.

The capacitance line 3b has a main line portion extending substantially linearly along the scanning line 3a, and a protruding portion protruding forward (upward in the figure) along the data line 6a from a portion intersecting the data line 6a. And

A first light-shielding film 11a is provided in a region indicated by a thick line in the drawing so as to pass below the scanning line 3a, the capacitor line 3b and the TFT 30, respectively. More specifically, in FIG. 2, the first light-shielding films 11a
Are formed in a striped shape along with the data line 6a, and a portion intersecting with the data line 6a is formed wide downward in the figure, and the channel portion 1a 'of each TFT is formed by the wide portion.
It is provided at a position to cover each as viewed from the T array substrate side.

In this liquid crystal device, a third light-shielding film 24 is provided so as to cover the data line 6a between the adjacent pixel electrodes 9a. The third light shielding film 24 is formed from the same layer as the barrier layer 80. Part of the third light-shielding film 24 and the barrier layer functions as an electrode for a storage capacitor.

Next, as shown in the sectional view of FIG. 3, the liquid crystal device comprises a TFT array substrate 10 which constitutes an example of one transparent substrate, and an example of another transparent substrate which is disposed to face the TFT array substrate 10. And the opposing substrate 20. The TFT array substrate 10 is made of, for example, a quartz substrate, and has a counter substrate 20.
Is made of, for example, a glass substrate or a quartz substrate. The pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is provided above the pixel electrode 9a. The pixel electrode 9a is, for example,
It is composed of a transparent conductive thin film such as an ITO (Indium Tin Oxide) film. The alignment film 16 is made of, for example, an organic thin film such as a polyimide thin film.

On the other hand, a counter electrode (common electrode) 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode. Is provided. The counter electrode 21 is, for example, I
It is made of a transparent conductive thin film such as a TO film. Also, the alignment film 22
Consists of an organic thin film such as a polyimide thin film.

Each pixel electrode 9 is provided on the TFT array substrate 10.
A pixel switching TFT 30 that controls switching of each pixel electrode 9a is provided at a position adjacent to the pixel electrode 9a.

As shown in FIG. 3, a second light-shielding film 23 called a black mask or a black matrix may be provided in the non-opening area of each pixel in the counter substrate 20. For this reason, incident light from the side of the counter substrate 20 is applied to the channel region 1 of the semiconductor layer 1 a of the pixel switching TFT 30.
a 'and the source side LDD region 1b and the drain side LDD region 1c do not enter. Further, the second light shielding film 23
Has functions of improving contrast, preventing color mixture of color materials when a color filter is formed, and the like.

A sealing material 52 (to be described later) is provided between the TFT array substrate 10 and the opposing substrate 20, which are configured as described above and in which the pixel electrode 9a and the opposing electrode 21 face each other.
Liquid crystal, which is an example of an electro-optical material, is sealed in a space surrounded by (see FIGS. 13 and 14), and a liquid crystal layer 50 is formed. The liquid crystal layer 50 assumes a predetermined alignment state by the alignment films 16 and 22 when no electric field is applied from the pixel electrode 9a. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several kinds of nematic liquid crystals are mixed. The sealing material is an adhesive made of, for example, a photocurable resin or a thermosetting resin for bonding the TFT array substrate 10 and the opposing substrate 20 around the periphery thereof, in order to set the distance between the two substrates to a predetermined value. Gap material (spacer) such as glass fiber or glass beads.

Further, as shown in FIG. 3, a first light-shielding film 11a is provided between the TFT array substrate 10 and each pixel switching TFT 30 at a position facing each of the pixel switching TFTs 30. First light shielding film 1
1a is Ti, C, preferably an opaque refractory metal
It is composed of a single metal, an alloy, a metal silicide or the like containing at least one of r, W, Ta, Mo and Pb. With such a material, the first light-shielding film 11a is not broken or melted by high-temperature processing in the step of forming the pixel switching TFT 30 performed after the step of forming the first light-shielding film 11a on the TFT array substrate 10. I can do it. Since the first light shielding film 11a is formed, reflected light (return light) from the side of the TFT array substrate 10 is formed.
Pixel switching TFTs that are easily excited by light
30 channel regions 1a 'and source-side LDD regions 1b,
The incident on the drain LDD 1c can be prevented beforehand, and the characteristics of the pixel switching TFT 30 do not deteriorate due to the generation of the photocurrent due to this.

Further, a base insulating film 12 is provided between the first light-shielding film 11a and the plurality of pixel switching TFTs 30. The base insulating film 12 is formed by forming the semiconductor layer 1a constituting the pixel switching TFT 30 into a first light shielding film 11a.
It is provided for electrical insulation from Further, the base insulating film 12 is formed on the entire surface of the TFT array substrate 10 so that the pixel switching TFT 30 is formed.
It also has a function as a base film for the purpose. That is, TFT
It has a function of preventing deterioration of the characteristics of the pixel switching TFT 30 due to roughening of the surface of the array substrate 10 during polishing, dirt remaining after cleaning, and the like.

In this embodiment, the semiconductor layer 1a extends from the high-concentration drain region 1e to form a first storage capacitor electrode 1f, and a part of the capacitor line 3b opposed to the first storage capacitor electrode 1f serves as a second storage capacitor electrode. The first storage capacitor 70a is formed by extending the film 2 from a position facing the scanning line 3a to form a first dielectric film sandwiched between these electrodes. Further, the barrier layer 8 facing the second storage capacitor electrode
A part of 0 is a third storage capacitor electrode 80b, and a first interlayer insulating film 81 is provided between these electrodes. First interlayer insulating film 81
Functions also as a second dielectric film, and a second storage capacitor 70b is formed. The first and second storage capacitors 70a and 70b are connected in parallel via the first contact hole 8a to form the storage capacitor 70. The barrier layer 80 is formed substantially along the capacitance line 3b.

More specifically, the high-concentration drain region 1e of the semiconductor layer 1a extends below the data line 6a and the scanning line 3a to form a pixel switching TFT 30, and is also connected to the data line 6a and the scanning line 3a. Capacitance line 3 extending along
b, the first dielectric film 2
This is the storage capacitor electrode 1f. In particular, the first dielectric film 2 is a TFT 3 formed on a polysilicon film by high-temperature oxidation or the like.
Since it is nothing but the gate insulating film 2 of 0, it can be a thin and high withstand voltage insulating film, and the first storage capacitor 70a can be configured as a large-capacity storage capacitor with a relatively small area. Also,
Since the second dielectric film 81 can be formed as thin as the gate insulating film 2, the second storage capacitor 70b can be compared by using the region between adjacent data lines as shown in FIG. It can be configured as a large-capacity storage capacitor with a relatively small area. Therefore, the three-dimensional storage capacitor 70 composed of the first and second storage capacitors 70a and 70b has an area under the data line 6a and an area where liquid crystal disclination occurs along the scanning line 3a (that is, an area where the disclination occurs). (A region where the capacitance line 3b is formed)
Is effectively used in the space outside the pixel opening region to provide a large-capacity storage capacitor with a small area.

In FIG. 3, the pixel switching TFT
Reference numeral 30 denotes a scanning line 3a, a channel region 1a 'of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, a scanning line 3a and the semiconductor layer 1.
a, a low concentration source region (source-side LDD region) 1b of the semiconductor layer 1a.
And low concentration drain region (drain side LDD region) 1
c, a high-concentration source region 1d and a high-concentration drain region 1e of the semiconductor layer 1a. High concentration drain region 1
To e, a corresponding one of the plurality of pixel electrodes 9a is connected via the barrier layer 80. Source region 1b
And 1d and the drain regions 1c and 1e should be doped with a predetermined concentration of n-type or p-type dopant in the semiconductor layer 1a depending on whether an n-type or p-type channel is to be formed, as described later. Is formed. An n-type channel TFT has the advantage of a high operating speed, and is a pixel switching TFT which is a pixel switching element.
Often used as 30. In the present embodiment, in particular, the data line 6a is formed of a light-shielding and conductive thin film such as a low-resistance metal film such as Al or an alloy film such as metal silicide. On the barrier layer 80 and the second dielectric film (first interlayer insulating film) 81, a contact hole 5 leading to the high-concentration source region 1d and a contact hole 8b leading to the barrier layer 80 are formed respectively. Interlayer insulating film 4
Are formed. The data line 6a is electrically connected to the high-concentration source region 1d via the contact hole 5 to the high-concentration source region 1d. Further, the data line 6a
On the second interlayer insulating film 4, a third interlayer insulating film 7 in which a contact hole 8b to the barrier layer 80 is formed is formed. The pixel electrode 9a is electrically connected to the barrier layer 80 via the contact hole 8b, and is further electrically connected to the high-concentration drain region 1e via the contact hole 8a via the barrier layer 80. The above-described pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 configured as described above.

The pixel switching TFT 30 preferably has an LDD structure as described above, but may have an offset structure in which impurity ions are not implanted into the low-concentration source region 1b and the low-concentration drain region 1c. A self-aligned TFT in which impurity ions are implanted at a high concentration using 3a as a mask to form high-concentration source and drain regions in a self-aligned manner may be used.

As shown in FIGS. 3 and 4, in the liquid crystal device of this embodiment, the data line 6a is provided between the second interlayer insulating film 4 and the third interlayer insulating film 7. In this example, the second interlayer insulating film 4 is flattened by, for example, a CMP method (chemical mechanical polishing), and the data line 6a is formed on the flattened first interlayer insulating film.
The third interlayer insulating film 7 has unevenness due to the conductive layer such as the data line 6a, and the pixel electrode 9 disposed on the unevenness.
a, the alignment film 16 also has irregularities following the shape of the third interlayer insulating film 7. For example, the uneven region 16 of the alignment film 16
The rubbing defect tends to occur in the region b and in the vicinity of the region b, and the alignment defect of the liquid crystal layer 50 occurs.

In the liquid crystal device of the present invention, the third light shielding film 24
Are provided so as to face the uneven region 16b of the alignment film 16 and the vicinity thereof. Therefore, in the liquid crystal device of the present invention, even if the liquid crystal layer has an abnormal alignment due to the pixel electrode or the alignment film disposed in this region, the abnormal alignment portion can be shielded by the light shielding film. That is, since the area where the liquid crystal is poorly aligned is covered with the third light-shielding film 24,
It is possible to prevent a decrease in contrast due to light leakage or the like and improve display quality. In addition, the third light-shielding film 24
It is formed in an island shape along the data line, and is arranged in a region between the pixel electrodes 9a adjacent to each other with the data line 6a interposed therebetween. Then, the end of the third light-shielding film 24 and the end of the pixel electrode 9a are arranged so as to overlap in a plane. Further, the third light-shielding film 24 is electrically connected to the capacitor line 3b through the contact hole 8c, and the third light-shielding film 24 is formed in the same manner as a part of the barrier layer 80 functions as the third storage capacitor electrode 80b. ,
Functions as a third storage capacitor electrode.

For the third light-shielding film, for example, opaque refractory metals such as Ti, Cr, W, Ta, Mo and P
What is necessary is just to comprise from light-shielding substances, such as a metal simple substance, an alloy, and a metal silicide containing at least one of b.

As shown in FIGS. 2 and 3, in the liquid crystal device of the present embodiment, the data lines 6 a and the scanning lines 3 b are three-dimensionally formed on the TFT array substrate 10 via the second interlayer insulating film 4. Are provided so as to cross each other. The barrier layer 80 is interposed between the semiconductor layer 1a and the pixel electrode 9a, and electrically connects the high-concentration drain region 1e and the pixel electrode 9a via the first and second contact holes 8a and 8b. Connecting.

For this reason, the semiconductor layer 1a is separated from the pixel electrode 9a.
The diameter of each of the first and second contact holes 8a and 8b can be reduced as compared with the case where one contact hole is formed up to the drain region. That is, when one contact hole is opened, if the selectivity at the time of etching is low, the etching accuracy decreases as the contact hole is opened deeper, so that penetration through a very thin semiconductor layer 1a of, for example, about 50 nm is prevented. In order to achieve this, dry etching that can reduce the diameter of the contact hole is stopped halfway, and finally the semiconductor layer 1 is wet-etched.
The process must be designed so as to open the hole to a. Alternatively, it becomes necessary to separately provide a polysilicon film for preventing penetration through dry etching.

On the other hand, in the present embodiment, the pixel electrode 9
a and the high-concentration drain region 1e may be connected by two serial first and second contact holes 8a and 8b, and these first and second contact holes 8a and 8b are opened by dry etching, respectively. It becomes possible. Alternatively, it is possible to shorten at least the opening distance by wet etching. However, in order to slightly taper the first and second contact holes 8a and 8b, respectively, a relatively short time wet etching may be performed after the dry etching.

As described above, according to the present embodiment, the diameters of the first and second contact holes 8a and 8b can be reduced, and the barrier layer 80 in the first contact hole 8a can be reduced.
Since the dents and irregularities formed on the surface of the pixel electrode 9a can be made small, the flattening of the portion of the pixel electrode 9a located thereabove is promoted. Further, since the depressions and irregularities formed on the surface of the pixel electrode 9a in the second contact hole 8b can be small, flattening of the pixel electrode 9a is promoted. As a result, disclination (poor alignment) in the liquid crystal layer 50 due to depressions and irregularities on the surface of the pixel electrode 9a is reduced, and finally, a high-quality image can be displayed by the liquid crystal device. For example, the second interlayer insulating film 4 interposed between the barrier layer 80 and the pixel electrode 9a
If the total film thickness of the third interlayer insulating film 12 is suppressed to about several hundreds of nm, the diameter of the second contact hole 8b which directly affects the above-described depressions and irregularities on the surface of the pixel electrode 9a is extremely reduced. Can be made smaller.

In this embodiment, since the barrier layer 80 is composed of a high melting point metal film or an alloy film thereof, the selectivity in etching between the metal film and the interlayer insulating film is greatly different. There is almost no possibility of penetration of the barrier layer 80 by etching.

In the present embodiment, in particular, in the storage capacitor 70 three-dimensionally constructed with the barrier layer 80 at the center, the first
Each of the dielectric film 2 and the second dielectric film 81 is a dielectric film different from the second interlayer insulating film 4 interposed between the data line 6a and the scanning line 3b which are three-dimensionally intersecting with each other.

On the other hand, the thickness of the barrier layer 80 is, for example, 50
It is preferable that the thickness be approximately from 500 nm to 500 nm. 50
If the thickness is about nm, the possibility of penetration when the second contact hole 8b is opened in the manufacturing process is low. If the thickness is about 500 nm, the unevenness on the surface of the pixel electrode 9a does not matter or is relatively easy. This is because flattening is possible.

Further, in the present embodiment, by forming the first interlayer insulating film (second dielectric film) 81 thin in this way, the diameter of the first contact hole 8a can be further reduced. The depressions and irregularities of the barrier layer 80 in the holes 8a can be further reduced, and the planarization of the pixel electrodes 9a located above the barrier layers 80 is further promoted. Therefore, the discnation of the liquid crystal due to the depressions and irregularities in the pixel electrode 9a is reduced, and ultimately, a higher quality image display can be performed by the liquid crystal device.

In the configuration of the liquid crystal device according to the present embodiment, the second interlayer insulating film 4 interposed between the scanning line 3b and the data line 6a also suffers from the problem of the parasitic capacitance between the two wirings. Thickness (for example, 800
(thickness of about nm).

In the present embodiment configured as described above, in particular, the first light-shielding film 11a formed in a stripe shape extends under the scanning line 3a and is electrically connected to a constant potential source or a large capacity portion. It may be connected. According to this structure, the pixel switching TFT 3 disposed opposite to the first light-shielding film 11a is provided.
0 does not adversely affect the potential change of the first light-shielding film 11a. In this case, as the constant potential source, a constant potential source such as a negative power supply or a positive power supply supplied to a peripheral circuit (for example, a scanning line driving circuit, a data line driving circuit, or the like) for driving the liquid crystal device, a ground power supply And a constant potential source supplied to the counter electrode 21.

The capacitor line 3b and the scanning line 3a are made of the same polysilicon film, and the first dielectric film 2 of the first storage capacitor 70a and the gate insulating film 2 of the pixel switching TFT 30 are the same. Of the first storage capacitor electrode 1f and the channel forming region 1a 'of the pixel switching TFT 30, the low concentration source region 1b, the low concentration drain region 1c, the high concentration source region 1d, the high concentration drain region 1e, etc. Are composed of the same semiconductor layer 1a. For this reason, the laminated structure formed on the TFT array substrate 10 can be simplified, and further, in the method of manufacturing an electro-optical device described later, the capacitor line 3b and the scanning line 3a can be simultaneously formed in the same thin film forming step, and The first dielectric film of the capacitor 70a and the gate insulating film 2 can be formed simultaneously.

In this embodiment, in particular, the barrier layer 80 is made of a conductive light-shielding film. Therefore, the barrier layer 80
It is possible to at least partially define each pixel opening area. Further, by defining the pixel openings by the barrier layer 80 or in combination with the third light-shielding film 24, the second light-shielding film on the counter substrate 20 side can be omitted. Instead of the second light-shielding film 23 on the counter substrate 20,
Barrier layer 8 as a built-in light-shielding film on TFT array substrate 10
The configuration provided with 0 is extremely advantageous in that the pixel aperture ratio does not decrease due to the displacement between the TFT array substrate 10 and the counter substrate 20 in the manufacturing process.

The barrier layer 80 made of a light shielding film is, for example,
Opaque refractory metals Ti, Cr, W, Ta, Mo
And at least one of Pb and Pb. With such a configuration, the barrier layer 80 can be prevented from being broken or melted by the high-temperature treatment performed after the barrier layer 80 forming step.

Further, the refractory metal and the pixel electrode 9a
Since the high melting point metal does not corrode even when it comes into contact with the ITO film constituting the above, a good contact can be obtained between the barrier layer 80 and the pixel electrode 9a via the second contact hole 8b.

In this embodiment, in particular, as shown in FIG. 2, the barrier layer 80 made of a light-shielding film extends along the scanning line 3a between the data lines 6a whose plane shapes on the TFT array substrate 10 are adjacent to each other. , Are formed in an island shape for each pixel unit. As a result, the stress due to the light shielding film can be reduced. Further, part or all of the sides of the pixel opening region along the scanning line 3a can be defined by the barrier layer 80. Here, if the parasitic capacitance between the scanning line 3a and the barrier layer 80 poses a problem depending on the specific circuit design, the barrier layer 8 is provided on the scanning line 3a as in this embodiment.
It is preferable that the barrier layer 80 defines the side along the scanning line 3a of the pixel opening region on the side where the capacitor line 3b and the pixel electrode 9a are adjacent to each other without providing 0. Or,
According to the specific circuit design, the scanning line 3a and the barrier layer 80
If the parasitic capacitance between them does not matter, the barrier layer 8
0 may also be formed at a position facing the scanning line 3a via the second dielectric film 81. With this configuration, the light-shielding barrier layer 80 that at least partially covers both the scanning line 3a and the capacitor line 3b defines a larger portion of the side of the pixel opening region along the scanning line 3a. It becomes possible. In other words, in the case of such a configuration, it is preferable to configure the second dielectric film 81 to be thick enough that the parasitic capacitance of the scanning line 3a and the barrier layer 80 does not matter. Alternatively, to keep this parasitic capacitance small,
It is preferable that the barrier layer 80 covers the scanning line 3a only in an area necessary for defining the pixel opening area.

The scanning line 3a in the pixel opening region on the side (lower side in FIG. 2) where the scanning line 3a and the pixel electrode 9a are adjacent to each other.
May be defined by the first light-shielding film 11 a and the second light-shielding film 23. The side of the pixel opening region along the data line 6a may be defined by the data line 6a made of Al or the like or the first light shielding film 11a or the second light shielding film 23.

Further, as shown in FIG. 2, each end of the island-shaped third light-shielding film 24 formed along the data line 6a is slightly overlapped with the pixel electrode 9a in plan view. Is preferred. With this configuration, there is no need to form a gap between the two so as to transmit the incident light, and it is possible to prevent display defects such as white spots in this portion. Here, the pixel opening may be defined by a light-shielding film such as the data line 6a, the third light-shielding film 24, the barrier layer 80, and the first light-shielding film 11a, or the data line 6a and the barrier layer 80. It is possible. In such a case, it is not necessary to form the second light-shielding film 23 on the counter substrate 20, so that the step of forming the second light-shielding film 23 on the counter substrate 20 can be reduced. Further, it is possible to prevent the pixel aperture ratio from being lowered or varied due to misalignment between the counter substrate 20 and the TFT array substrate 10. When the second light-shielding film 23 is provided on the counter substrate 20, the second light-shielding film 23 is formed relatively large in consideration of the misalignment with the TFT array substrate 10. However, as described above, the data line 6a, the barrier layer 80, etc. Since the pixel opening is defined by the light-shielding film formed on the side, the pixel opening can be accurately defined, and the opposing substrate 20 can be defined.
Accordingly, the aperture ratio can be improved as compared with the case where the pixel opening is determined.

As described above, in this embodiment,
Since the barrier layer 80 is made of a conductive light-shielding film, various advantages can be obtained. However, the barrier layer 80 is not a high-melting-point metal film but a low-resistance doped polysilicon (for example, polysilicon doped with phosphorus or the like). Or a conductive polysilicon film. With this configuration, the barrier layer 80 does not function as a light-shielding film, but can sufficiently exhibit the function of increasing the storage capacitance 70 and the inherent relay function of the barrier layer. Further, stress due to heat or the like is less likely to be generated between the barrier layer 8 and the second interlayer insulating film 4.
It is useful for preventing cracks at and around zero. On the other hand,
Light shielding for defining the pixel opening region may be separately performed by the first light shielding film 11a and the second light shielding film 23.

In the present embodiment, in particular, as shown in FIGS. 2 and 3, the first contact hole 8a and the second contact hole 8b are opened at different plane positions on the TFT array substrate 10. ing. Therefore, it is possible to avoid a situation in which the irregularities generated at the planar positions where the first and second contact holes 8a and 8b are opened are superimposed and the irregularities are amplified. Therefore, good contact in these contact holes can be expected.

The planar shape of the contact holes 8a, 8b and 5 may be circular, square or other polygonal shapes, but the circular shape is particularly useful for preventing cracks in the interlayer insulating film around the contact holes. Then, in order to obtain a good contact, wet etching is performed after dry etching to form these contact holes 8.
Preferably, a, 8b and 5 each have a slight taper.

(Manufacturing Process in First Embodiment of Electro-Optical Device) Next, a manufacturing process of the liquid crystal device in the embodiment having the above-described configuration will be described with reference to FIGS.
This will be described with reference to FIG. FIGS. 5 to 8 show each layer on the TFT array substrate side in each step, as in FIG.
It is a process drawing shown corresponding to -A 'cross section.

First, as shown in step (1) of FIG. 5, a TFT array substrate 10 such as a quartz substrate, hard glass, or silicon substrate is prepared. Here, annealing is preferably performed in an inert gas atmosphere such as N ₂ (nitrogen) and at a high temperature of about 900 to 1300 ° C., and a pre-treatment is performed so that distortion generated in the TFT array substrate 10 in a high-temperature process performed later is reduced. Keep it. That is, the TFT array substrate 10 is preliminarily heat-treated at the same temperature or higher in accordance with the highest processing temperature at the highest temperature in the manufacturing process.
Then, a metal such as Ti, Cr, W, Ta, Mo and Pb or a metal alloy film such as metal silicide is formed on the entire surface of the TFT array substrate 10 thus processed by sputtering to a thickness of about 100 to 500 nm. , Preferably about 2
A light-shielding film 11 having a thickness of 00 nm is formed. The light shielding film 1
An anti-reflection film such as a polysilicon film may be formed on the substrate 1 to reduce surface reflection.

Next, as shown in step (2), a resist mask corresponding to the pattern of the first light-shielding film 11a (see FIG. 2) is formed on the formed light-shielding film 11 by photolithography. The first light-shielding film 11a is formed by etching the light-shielding film 11 through the step.

Next, as shown in step (3), a base insulating film 12 made of a silicon nitride film, a silicon oxide film or the like is formed on the first light shielding film 11a. The thickness of the base insulating film 12 is, for example, about 500 to 2000 nm. still,
When returning light from the back surface of the TFT array substrate 10 does not matter, it is not necessary to form the first light shielding film 11a.

Next, as shown in step (4), an amorphous silicon film is formed on the underlying insulating film 12. Then, in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 1
By performing an annealing process for 0 hour, preferably for 4 to 6 hours, the polysilicon film 1 is made to have a thickness of about 50 to 200 nm.
, Preferably to a thickness of about 100 nm.

Incidentally, without passing through the amorphous silicon film,
The polysilicon film 1 may be directly formed by a low pressure CVD method or the like. Alternatively, the polysilicon film 1 may be formed by implanting silicon ions into a polysilicon film deposited by a low-pressure CVD method or the like to make the polysilicon film once amorphous (amorphized), and then recrystallize by annealing or the like.

Next, as shown in a step (5), a semiconductor layer 1a having a predetermined pattern including the first storage capacitor electrode 1f as shown in FIG. 2 is formed by a photolithography step, an etching step and the like.

Next, as shown in the step (6), the first layer together with the semiconductor layer 1a constituting the pixel switching TFT 30 is formed.
By thermally oxidizing the storage capacitor electrode 1f at a temperature of about 900 to 1300 ° C., preferably at a temperature of about 1000 ° C., a relatively thin thermally oxidized silicon film 2 of about 30 nm is formed.
a, and then, as shown in step (7),
An insulating film 2b made of a high-temperature silicon oxide film (HTO film) or a silicon nitride film is deposited to a relatively thin thickness of about 50 nm by a method or the like, and a pixel switching having a multilayer structure including the thermal silicon oxide film 2a and the insulating film 2b The first dielectric film 2 for forming a storage capacitor is formed simultaneously with the gate insulating film 2 of the TFT 30 for use. As a result, the first storage capacitor electrode 1f has a thickness of about 30 to 150 nm, preferably about 35 to 5 nm.
The thickness becomes 0 nm, and the gate insulating film 2 (first dielectric film)
Has a thickness of about 20 to 150 nm, preferably about 3 nm.
The thickness is 0 to 100 nm. By shortening the high-temperature thermal oxidation time in this way, warpage due to heat can be prevented particularly when a large substrate of about 8 inches is used. However, the gate insulating film 2 having a single-layer structure may be formed only by thermally oxidizing the polysilicon film 1.

Next, as shown in a step (8), a resist layer 50 is formed by a photolithography step, an etching step and the like.
0 is the semiconductor layer 1 excluding the portion serving as the first storage capacitor electrode 1f
After forming on P.a, for example, P ions are dosed at about 3 × 1
The resistance of the first storage capacitor electrode 1f may be reduced by doping at 0 ¹² / cm ² .

Next, as shown in step (9), after removing the resist layer 500, a polysilicon film 3 is deposited by a low pressure CVD method or the like, and phosphorus (P) is thermally diffused to form the polysilicon film 3. It becomes conductive. Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film 3 may be used. The thickness of the polysilicon film 3 is about 100 to 50.
Deposit to a thickness of 0 nm, preferably about 300 nm.

Next, as shown in a step (10) of FIG. 6, by a photolithography step using a resist mask, an etching step, etc., the capacitor lines 3b are formed together with the scanning lines 3a having a predetermined pattern as shown in FIG. . The scanning line 3a and the capacitance line 3b may be formed of a metal alloy film such as a high melting point metal or a metal silicide, or may be a multilayer wiring combined with a polysilicon film or the like.

Next, as shown in step (11), when the pixel switching TFT 30 shown in FIG. 3 is an n-channel type TFT having an LDD structure, the semiconductor layer 1a first has a low concentration source region 1b and a low concentration source region 1b. In order to form the concentration drain region 1c, a dopant of a group V element such as P is used at a low concentration (for example, P ions are doped at a dose of 1 to 3 × 10 ¹³ / cm ² ) using the scanning line 3a (gate electrode) as a mask. Dope in amount). Thereby, the semiconductor layer 1 under the scanning line 3a
a becomes the channel region 1a '. The resistance of the capacitance line 3b and the scanning line 3a is also reduced by the doping of the impurity.

Next, as shown in step (12), the high-concentration source region 1d constituting the pixel switching TFT 30
After forming the resist layer 600 on the scanning line 3a with a mask wider than the scanning line 3a in order to form the high-concentration drain region 1e, a dopant of a group V element such as P is also added at a high concentration (for example, , P ions from 1 to 3 × 10 ¹⁵
/ Cm ² (dose amount). Note that, for example, a TFT having an offset structure may be used without doping at a low concentration, or a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, or the like using the scanning line 3a as a mask. The resistance of the capacitance line 3b and the scanning line 3a is further reduced by the doping of the impurity.

Incidentally, in parallel with the element forming process of these TFTs 30, an n-channel TFT and a p-channel TFT
Peripheral circuits such as a data line driving circuit and a scanning line driving circuit having a complementary structure composed of the TFT array substrate may be formed in the peripheral portion on the TFT array substrate 10. As described above, if the semiconductor layer 1a constituting the pixel switching TFT 30 in this embodiment is formed of polysilicon, the peripheral circuit can be formed in substantially the same process when the pixel switching TFT 30 is formed, which is advantageous in manufacturing. It is.

Next, as shown in step (13), after the resist layer 600 is removed, a low pressure CVD is performed on the capacitance line 3b, the scanning line 3a, and the gate insulating film 2 (first dielectric film).
High-temperature silicon oxide film (H
TO film) or a first interlayer insulating film 81 made of a silicon nitride film
Is deposited to a relatively thin thickness of 10 nm or more and 200 nm or less. However, as described above, the first interlayer insulating film 81 may be composed of a multilayer film, or may be formed by various known techniques generally used for forming a gate insulating film of a TFT. Can be formed. First interlayer insulating film 8
In the case of 1, if the thickness is too small as in the case of the second interlayer insulating film 4, the parasitic capacitance between the data line 6a and the scanning line 3a does not increase, and also, as in the case of the gate insulating film 2 in the TFT 30, If it is made too thin, no unique phenomenon such as a tunnel effect will occur. In addition, the first interlayer insulating film 81 functions as a second dielectric film between the second storage capacitor electrode 3b and the barrier layer 80. Then, as the second dielectric film 81 is made thinner, the second storage capacitor 70b becomes larger. As a result, a thickness of 50 nm or less, which is thinner than the gate insulating film 2, is set on condition that defects such as film breakage do not occur. When the second dielectric film 81 is formed so as to have an extremely thin insulating film, the effect of the present embodiment can be increased.

Next, as shown in a step (14), a contact hole 8a for electrically connecting the barrier layer 80 and the high-concentration drain region 1e, and a contact hole 8a for electrically connecting the light-shielding film 24 and the capacitor line 3b are formed. Is formed by dry etching such as reactive ion etching or reactive ion beam etching. Since such dry etching has high directivity, a contact hole 8a having a small diameter can be formed. Alternatively, wet etching which is advantageous for preventing the contact hole 8a from penetrating through the semiconductor layer 1a may be used together. This wet etching is also effective from the viewpoint of providing a taper for making better contact with the contact hole 8a.

Next, as shown in step (15), Ti, Cr, W, and Ti are formed on the entire surface of the high-concentration drain region 1e which is viewed through the first interlayer insulating film 81 and the contact holes 8a and 8c.
A metal such as Ta, Mo and Pb or a metal alloy film such as metal silicide is deposited by a sputtering process, and 50 to 500 n
A conductive film 80 'having a thickness of about m is formed. If the thickness is about 50 nm, there is almost no possibility that the second contact hole 8b will be penetrated when the second contact hole 8b is later formed. Note that an anti-reflection film such as a polysilicon film may be formed on the conductive film 80 'to reduce surface reflection. Also, the conductive film 8
For 0 ', a doped polysilicon film or the like may be used for stress relaxation.

Next, as shown in step (16) of FIG. 7, a resist mask corresponding to the pattern of the barrier layer 80 and the light shielding film 24 (see FIG. 2) is formed on the formed conductive film 80 'by photolithography. The barrier layer 80 including the third storage capacitor electrode 80b and the light-shielding film 24 which also functions as the third storage capacitor electrode are formed by forming and etching the conductive film 80 'through the resist mask.

Next, as shown in step (17), NS or NS gas is used to cover the first interlayer insulating film 81 and the barrier layer 80 by using, for example, normal pressure or reduced pressure CVD or TEOS gas.
A second interlayer insulating film 4 made of a silicate glass film such as G, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed, and the surface is flattened by, for example, a CMP method. The thickness of the second interlayer insulating film 4 is about 500
~ 1500 nm is preferred. If the thickness of the second interlayer insulating film 4 is 500 nm or more, the parasitic capacitance between the data line 6a and the scanning line 3a causes little or no problem.

Next, in the step (18), an annealing process at about 1000 ° C. is performed for about 20 minutes to activate the high-concentration source region 1d and the high-concentration drain region 1e.
A contact hole 5 for the data line 6a is opened.
Also, contact holes for connecting the scanning lines 3a and the capacitance lines 3b to wirings (not shown) in the peripheral region of the substrate are provided.
The second interlayer insulating film 4 can be opened by the same process as the contact hole 5.

Then, as shown in step (19), a low-resistance metal such as Al or a metal silicide having a light-shielding property is formed on the second interlayer insulating ~ 500 nm thickness, preferably about 300
nm.

Next, as shown in the step (20), the data lines 6 are formed by a photolithography step, an etching step and the like.
a is formed.

Next, as shown in step (21) of FIG. 8, for example, normal pressure or reduced pressure CV is applied so as to cover the data line 6a.
NSG, PSG, BS using D method or TEOS gas
A third interlayer insulating film 7 made of a silicate glass film such as G or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the third interlayer insulating film 7 is about 500 to 1500
nm is preferred.

Next, as shown in step (22), a contact hole 8b for electrically connecting the pixel electrode 9a and the barrier layer 80 is formed by dry etching such as reactive ion etching or reactive ion beam etching. I do. Further, wet etching may be used to form a tapered shape.

Next, as shown in step (23), a transparent conductive thin film 9 such as an ITO film is deposited on the third interlayer insulating film 7 by sputtering or the like to a thickness of about 50 to 200 nm. Then, as shown in the step (24), the pixel electrode 9a is formed by a photolithography step, an etching step and the like. When the liquid crystal device is used for a reflection type liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.

Subsequently, after applying a coating liquid for a polyimide-based alignment film on the pixel electrode 9a, a rubbing treatment is performed so as to have a predetermined pretilt angle and in a predetermined direction. 3) is formed.

On the other hand, for the counter substrate 20 shown in FIG. 3, a glass substrate or the like is first prepared, and the second light shielding film 23 and the fourth light shielding film 53 as a frame (see FIGS. 13 and 14).
Are formed through, for example, a photolithography step and an etching step after sputtering metal chromium. The second and fourth light-shielding films may be formed of a material such as resin black in which carbon or Ti is dispersed in a photoresist, in addition to a metal material such as Cr, Ni, and Al. still,
On the TFT array substrate 10, the data line 6a, the barrier layer 8
If the light-shielding region is defined by the first light-shielding film 11a and the like, the second light-shielding film 23 and the fourth light-shielding film on the counter substrate 20 can be omitted.

Thereafter, a transparent conductive thin film such as ITO is applied to the entire surface of the counter substrate 20 by sputtering or the like for about 50 to 2 hours.
The counter electrode 21 is formed by depositing to a thickness of 00 nm. Furthermore, after applying a coating liquid for a polyimide-based alignment film to the entire surface of the counter electrode 21, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction, so that the alignment film 22 (see FIG. 3) is formed. It is formed.

At this time, for example, the scanning line 3a, the capacitance line 3
b of the alignment film 16 formed corresponding to
In addition, the rubbing failure is likely to occur in the vicinity of this region, and the alignment failure of the liquid crystal layer 50 occurs. In the liquid crystal device of the present invention. The third light-shielding film 24 is patterned so as to face the second region of the alignment film 16 (the uneven region 16b and its vicinity). Therefore, in the liquid crystal device of the present invention, even if the liquid crystal layer is abnormally aligned due to the pixel electrode or the alignment film disposed in this region, the abnormal alignment portion can be shielded from light by the light shielding film, and light leakage or the like can be caused. The contrast can be prevented from lowering, and the display quality can be improved. In particular, since the third light-shielding film 24 is formed along the data line 6a and is arranged so as to overlap the edge of the pixel electrode, the step at the edge of the pixel electrode is covered with the third light-shielding film 24. This makes it possible to hide the alignment defect due to the step with the third light-shielding film 24.

Finally, the T on which each layer is formed as described above
The FT array substrate 10 and the opposing substrate 20 are sealed with a sealing material 52 (FIG. 13 and FIG. 1) such that the alignment films 16 and 22 face each other.
4), and a liquid crystal formed by mixing a plurality of types of nematic liquid crystals is sucked into a space between the two substrates by vacuum suction or the like, thereby forming a liquid crystal layer 50 having a predetermined thickness.

(Second Embodiment of Electro-Optical Device) The configuration of a liquid crystal device which is a second embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. Various elements in a plurality of pixels formed in a matrix constituting an image display area of the liquid crystal device, an equivalent circuit such as wiring,
T on which data lines, scanning lines, pixel electrodes, light shielding films, etc. are formed
A plan view of a plurality of pixel groups adjacent to each other on the FT array substrate is similar to that of the first embodiment (see FIGS. 1 and 2).

In the second embodiment, the scanning lines 3a and the capacitance lines 3
The first embodiment differs from the first embodiment in that b is formed not in the second interlayer insulating film 4 but in the second interlayer insulating film 4 made of a planarizing film formed by a CMP method or the like as a recess. Is different. Hereinafter, only the configuration different from the first embodiment will be described, and the description of the same configuration as the first embodiment will be omitted.

FIG. 9 is a sectional view taken along the line AA ′ of FIG. 2, and FIG. 10 is a sectional view taken along the line BB ′ of FIG. 9 and 10
In the above, in order to make each layer or each member a size recognizable in the drawings, the scale of each layer or each member is made different.

As shown in the sectional views of FIGS. 9 and 10, the data line 6a is provided between the second interlayer insulating film 4 and the third interlayer insulating film 7. In this example, a groove is formed on the surface of the second interlayer insulating film 4 along the data line 6a, and the data line 6a is arranged in the groove. Third interlayer insulating film 7
Has unevenness due to the end region of the groove, and the pixel electrode 9 a and the alignment film 16 disposed on the unevenness also have unevenness following the shape of the third interlayer insulating film 7. . For example, the concave region 16c of the alignment film 16 and the region in the vicinity thereof are liable to be rubbed, and the alignment of the liquid crystal layer 50 is poor.

In the liquid crystal device of the present invention, the third light shielding film 24
Is a concave region 16c of the alignment film 16 and a region in the vicinity thereof.
And further overlaps with respective ends of the pixel electrodes 9a adjacent to each other with the data line 6a as a boundary. Therefore, in the liquid crystal device of the present invention, even if the liquid crystal layer has an abnormal alignment due to the pixel electrode or the alignment film disposed in this region, the abnormal alignment portion can be shielded by the light shielding film. That is, since the region where the alignment of the liquid crystal is poor is covered with the third light-shielding film 24, a decrease in contrast due to light leakage or the like can be prevented, and the display quality can be improved. Further, in the present embodiment, since the data line 6a is formed in the groove, the ratio of unevenness on the surface of the third interlayer insulating film 7 is reduced, and the occurrence of alignment failure is compared with the first embodiment. Can be reduced.

(Manufacturing Process in Second Embodiment of Electro-Optical Device) Next, a manufacturing process of the liquid crystal device in the embodiment having the above-described configuration will be described with reference to FIGS.
This will be described with reference to FIG. Note that some drawings and descriptions of the same manufacturing process as in the first embodiment are partially omitted. FIG.
FIGS. 1 and 12 are process diagrams showing each layer on the TFT array substrate side in each process in a manner corresponding to the AA ′ section in FIG. 2 as in FIG.

Manufacturing Process of First Embodiment FIG. 5
Through the same steps as in (1) to FIG. 7 (16), the substrate shown in FIG. 11 (16) in which the third light shielding film 24 and the barrier layer 80 are formed is manufactured.

Next, as shown in step (17), the NSG, PSG, and the like are used to cover the third light-shielding film 24 and the barrier layer 80 by using, for example, normal pressure or reduced pressure CVD, TEOS gas, or the like.
A second interlayer insulating film 4 made of a silicate glass film such as SG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed, and the surface is planarized by, for example, a CMP method. The thickness of the second interlayer insulating film 4 is about 500 to 15
00 nm is preferred. The thickness of the second interlayer insulating film 4 is 500
If it is not less than nm, the parasitic capacitance between the data line 6a and the scanning line 3a does not cause much or little problem.

Next, in the step (18), an annealing process at about 1000 ° C. is performed for about 20 minutes to activate the high concentration source region 1d and the high concentration drain region 1e.
A contact hole 5 for the data line 6a is opened.
Also, contact holes for connecting the scanning lines 3a and the capacitance lines 3b to wirings (not shown) in the peripheral region of the substrate are provided.
The second interlayer insulating film 4 can be opened by the same process as the contact hole 5. Further, grooves for arranging the scanning lines 3a and the capacitance lines 3b are also formed by a photoetching process.

Next, as shown in step (19), a low-resistance metal such as Al or a metal silicide such as Al, which is light-shielding, is applied to the trench (trench) provided in the second interlayer insulating film 4 by sputtering or the like. About 100 to 500 n as the metal film 6
m, preferably about 300 nm.

Next, as shown in the step (20), the data lines 6 are formed by a photolithography step, an etching step and the like.
a is formed.

Next, as shown in step (21) of FIG.
For example, at normal pressure or reduced pressure C so as to cover the data line 6a.
NSG, PSG, B using VD method or TEOS gas
A third interlayer insulating film 7 made of a silicate glass film such as SG or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the third interlayer insulating film 7 is about 500 to 150
0 nm is preferred.

Next, as shown in step (22), a contact hole 8b for electrically connecting the pixel electrode 9a and the barrier layer 80 is formed by dry etching such as reactive ion etching or reactive ion beam etching. I do. Further, wet etching may be used to form a tapered shape.

Next, as shown in step (23), a transparent conductive thin film 9 such as an ITO film is deposited on the third interlayer insulating film 7 by sputtering or the like to a thickness of about 50 to 200 nm. Then, as shown in the step (24), the pixel electrode 9a is formed by a photolithography step, an etching step and the like. When the liquid crystal device is used for a reflection type liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.

Subsequently, after applying a coating liquid for a polyimide-based alignment film on the pixel electrode 9a, a rubbing treatment is performed so as to have a predetermined pre-tilt angle and in a predetermined direction, or the like, so that the alignment film 16 (FIG. 9) is formed.

(Overall Configuration of Electro-Optical Device) The overall configuration of the liquid crystal device in each embodiment configured as described above will be described with reference to FIGS. Note that FIG.
FIG. 14 is a plan view of the FT array substrate 10 together with the components formed thereon viewed from the counter substrate 20 side.
FIG. 14 is a sectional view taken along line HH ′ of FIG. 13.

In FIG. 13, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof, and is made of, for example, the same or different material as the second light shielding film 23 in parallel with the inside thereof. A fourth light-shielding film 53 is provided as a frame defining the periphery of the image display area. In a region outside the sealing material 52, a data line driving circuit 101 that drives the data line 6a by supplying an image signal to the data line 6a at a predetermined timing and a mounting terminal 102 are provided.
A scanning line driving circuit 104, which is provided along one side of the FT array substrate 10 and drives the scanning line 3a by supplying a scanning signal to the scanning line 3a at a predetermined timing, operates along two sides adjacent to this one side. It is provided. If the delay of the scanning signal supplied to the scanning line 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuits 101 may be arranged on both sides along the side of the image display area. For example, the odd-numbered data lines 6a supply image signals from a data line driving circuit arranged along one side of the image display area, and the even-numbered data lines extend along the opposite side of the image display area. The image signal may be supplied from a data line driving circuit disposed in the same manner. If the data lines 6a are driven in a comb-tooth shape in this manner, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be formed. Further, on the remaining side of the TFT array substrate 10,
Scanning line drive circuits 104 provided on both sides of the image display area
A plurality of wirings 105 for connecting between them are provided.
In at least one of the corners of the opposing substrate 20, a conductive material 106 for establishing electric conduction between the TFT array substrate 10 and the opposing substrate 20 is provided. Then, as shown in FIG. 14, the opposite substrate 20 having substantially the same contour as the sealing material 52 shown in FIG. 13 is fixed to the TFT array substrate 10 by the sealing material 52. Incidentally, in addition to the data line driving circuit 101, the scanning line driving circuit 104, etc., on the TFT array substrate 10,
A sampling circuit for applying an image signal to the plurality of data lines 6a at a predetermined timing; a precharge circuit for supplying a precharge signal of a predetermined voltage level to the plurality of data lines 6a prior to the image signal; An inspection circuit or the like for inspecting the quality, defect, etc. of the liquid crystal device may be formed. According to the present embodiment, the opposing substrate 2
The second light-shielding film 23 on 0 may be formed smaller than the light-shielding region of the TFT array substrate 10. Further, the second light shielding film 23 can be easily removed depending on the use of the liquid crystal device.

In each of the embodiments described above with reference to FIGS. 1 to 14, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, TAB (Tape Automated Bonding) The driving LSI mounted on the substrate may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. For example, TN (Twisted) is provided on each of the side of the opposite substrate 20 where the projection light is incident and the side where the emission light of the TFT array substrate 10 is emitted.
Nematic) mode, VA (Vertically Aligned) mode,
A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as a PDLC (Polymer Dispersed Liquid Crystal) mode or a normally white mode / a normally black mode.

Since the liquid crystal device in each of the embodiments described above is applied to a color liquid crystal projector, three liquid crystal devices are used as light valves for R (red), G (green), and B (blue), respectively. The light of each color separated via the dichroic mirror for RGB color separation is incident on each light valve as projection light. Therefore, in each embodiment, the opposing substrate 20 is not provided with a color filter. However, in a predetermined region facing the pixel electrode 9a where the second light shielding film 23 is not formed, the R
The counter substrate 2 is provided with a GB color filter together with its protective film.
It may be formed on zero. Alternatively, the TFT array substrate 1
It is also possible to form a color filter layer with a color resist or the like below the pixel electrode 9a facing RGB on 0.
In this way, the liquid crystal device in each embodiment can be applied to a color liquid crystal device such as a direct-view or reflection type color liquid crystal television other than the liquid crystal projector. Further, the counter substrate 2
A micro lens may be formed so as to correspond to one pixel on 0. In this case, a bright liquid crystal device can be realized by improving the efficiency of collecting incident light. Furthermore, a dichroic filter that produces RGB colors using light interference may be formed by depositing a number of interference layers having different refractive indexes on the counter substrate 20. According to the counter substrate with the dichroic filter, a brighter color liquid crystal device can be realized.

In the liquid crystal device according to each of the embodiments described above, incident light is incident from the side of the counter substrate 20 as in the related art. However, since the first light-shielding film 11a is provided, the TFT array substrate The incident light may be incident from the side and emitted from the counter substrate 20 side. That is,
Thus, even if the liquid crystal device is mounted on the liquid crystal projector, the channel region 1a 'of the semiconductor layer 1a and the source side L
Light can be prevented from entering the DD region 1b and the drain-side LDD region 1c, and a high-quality image can be displayed. Here, conventionally, the TFT array substrate 10
Anti-reflection AR to prevent reflection on the back side of the
(Anti Reflection) Although it was necessary to separately arrange a coated polarizing plate or attach an AR film, in each embodiment, the surface of the TFT array substrate 10 and the semiconductor layer 1a
Since the first light-shielding film 11a is formed between at least the channel region 1a ', the source-side LDD region 1b, and the drain-side LDD region 1c, such an AR-coated polarizing plate or AR film may be used. There is no need to use a substrate obtained by subjecting the TFT array substrate 10 to an AR process. Therefore, according to each of the embodiments, the material cost can be reduced, and the yield is not significantly reduced due to dust, scratches or the like when attaching the polarizing plate, which is very advantageous. In addition, since light resistance is excellent, even if a bright light source is used or polarization conversion is performed by a polarizing beam splitter to improve light use efficiency, image quality deterioration such as crosstalk due to light does not occur.

The switching element provided in each pixel has been described as a normal stagger type or coplanar type polysilicon TFT.
The embodiments are also effective for other types of TFTs such as TFTs and amorphous silicon TFTs.

(Electronic Apparatus) Next, an embodiment of an electronic apparatus including the liquid crystal device 100 described in detail above will be described with reference to FIGS.

First, as shown in FIG.
1 shows a schematic configuration of an electronic device provided with.

In FIG. 15, the electronic equipment includes a display information output source 1000, a display information processing circuit 1002, and a drive circuit 1.
004, a liquid crystal device 100, a clock generation circuit 1008, and a power supply circuit 1010. The display information output source 1000 includes a ROM (Read Only Memory),
It includes a memory such as an AM (Random Access Memory), an optical disk device, and a tuning circuit that tunes and outputs an image signal, and displays display information such as an image signal in a predetermined format based on a clock signal from a clock generation circuit 1008. Output to the information processing circuit 1002. The display information processing circuit 1002 includes various known processing circuits such as an amplification / polarity inversion circuit, a serial-parallel conversion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and is input based on a clock signal. Digital signals are sequentially generated from the display information and output to the drive circuit 1004 together with the clock signal CLK. The drive circuit 1004 drives the liquid crystal device 100. The power supply circuit 1010 supplies a predetermined power to each of the above-described circuits. Note that the drive circuit 1004 may be mounted on the TFT array substrate included in the liquid crystal device 100, and in addition, the display information processing circuit 1002 may be mounted.

Next, FIGS. 16 to 17 show specific examples of the electronic apparatus configured as described above.

In FIG. 16, a liquid crystal projector 1100, which is an example of electronic equipment, prepares three liquid crystal display modules each including the liquid crystal device 100 in which the above-described drive circuit 1004 is mounted on a TFT array substrate, and each of the light sources for RGB. The projector is used as the bulbs 100R, 100G, and 100B. In the liquid crystal projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, three mirrors 1106 and two dichroic mirrors 11 are provided.
08, light components R corresponding to the three primary colors of RGB,
Light valve 100 divided into G and B and corresponding to each color
R, 100G and 100B, respectively. At this time, in particular, the B light is used to prevent light loss due to a long optical path, so that the input lens 1122, the relay lens 1123, and the output lens 11
24, through a relay lens system 1121. Then, the light valves 100R, 100G and 10
The light components corresponding to the three primary colors, each modulated by 0B,
After being recombined by the dichroic prism 1112, it is projected as a color image on the screen 1120 via the projection lens 1114.

In FIG. 17, a laptop personal computer (PC) 1200 for multimedia, which is another example of electronic equipment, has the above-described liquid crystal device 100 provided in a top cover case, and further includes a CPU,
The keyboard 1202 accommodates a memory, a modem, and the like.
Is provided.

In addition to the electronic devices described above with reference to FIGS. 16 to 17, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic organizer, a calculator, a word processor, an engineering machine, etc. A workstation (EWS), a mobile phone, a video phone, a POS terminal, a device having a touch panel, and the like are examples of the electronic apparatus shown in FIG.

As described above, according to the present embodiment, it is possible to realize various electronic apparatuses having a liquid crystal device capable of displaying a high-quality image with high manufacturing efficiency.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements, wirings, and the like provided in a plurality of pixels in a matrix forming an image display area in a liquid crystal device according to a first embodiment of the electro-optical device.

FIG. 2 shows a data line in the liquid crystal device according to the first embodiment;
FIG. 3 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which a scanning line, a pixel electrode, a light shielding film, and the like are formed.

FIG. 3 is a sectional view taken along line A-A 'of FIG.

FIG. 4 is a sectional view taken along the line B-B 'of FIG.

FIG. 5 is a process diagram (part 1) for sequentially illustrating the manufacturing process of the liquid crystal device of the first embodiment.

FIG. 6 is a process diagram (part 2) for sequentially illustrating the manufacturing process of the liquid crystal device of the first embodiment.

FIG. 7 is a process diagram (part 3) for sequentially illustrating the manufacturing process of the liquid crystal device of the first embodiment.

FIG. 8 is a process view (part 4) for sequentially illustrating the manufacturing process of the liquid crystal device of the first embodiment.

FIG. 9 is a sectional view taken along line A-A ′ of FIG. 2;

FIG. 10 is a sectional view taken along line B-B 'of FIG.

FIG. 11 is a process diagram (part 1) for sequentially illustrating the manufacturing process of the liquid crystal device of the second embodiment.

FIG. 12 is a process diagram (part 2) for sequentially illustrating the manufacturing process of the liquid crystal device of the second embodiment.

FIG. 13 is a plan view of a TFT array substrate in the liquid crystal device according to each embodiment together with components formed thereon as viewed from a counter substrate.

FIG. 14 is a sectional view taken along line H-H ′ of FIG.

FIG. 15 is a block diagram showing a schematic configuration of an embodiment of an electronic device according to the present invention.

FIG. 16 is a cross-sectional view illustrating a liquid crystal projector as an example of an electronic apparatus.

FIG. 17 is a front view showing a personal computer as another example of the electronic apparatus.

[Explanation of symbols]

 1a Semiconductor layer 1a 'Channel region 1b Low-concentration source region (source-side LDD region) 1c Low-concentration drain region (drain-side LDD region) 1d High-concentration source region 1e High-concentration drain region 1f First accumulation Capacitance electrode 2 ... Gate insulating film (first dielectric film) 3a ... Scan line 3b ... Capacitance line (second storage capacitor electrode) 4 ... Second interlayer insulating film 5 ... Contact hole 6a ... Data line 7 ... Third interlayer insulating Film 8a: first contact hole 8b: second contact hole 9a: pixel electrode 10: TFT array substrate 11a, 11b: first light-shielding film 12: base insulating film 15: contact hole 16: alignment film 16b: alignment film (poor alignment) Region) 16c: alignment film (alignment defective region) 20: counter substrate 21: counter electrode 22: alignment film 23: second light shielding film 24: third light shielding film 30: pixel Etching TFT 50 ... Liquid crystal layer 52 ... Seal material 53 ... Fourth light shielding film 70 ... Storage capacitance 70a ... First storage capacitance 70b ... Second storage capacitance 80 ... Barrier layer 81 ... First interlayer insulating film (second dielectric film) 101: data line driving circuit 104: scanning line driving circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 GA48 GA50 GA51 GA59 HA25 JA25 JA33 JA35 JA46 JB24 JB51 JB52 JB58 JB69 KA04 KA10 KA12 KB02 KB23 KB25 MA05 MA07 MA08 MA13 MA17 MA19 MA25 MA27 MA29 MA37 MA41 NA01 NA04 NA07 PA02 PA09 PA10 PA11 QA07 QA15 RA05

Claims (9)

[Claims] A first thin film transistor disposed on the substrate, the thin film transistor having a semiconductor layer and a gate electrode disposed on the substrate with a gate insulating film interposed therebetween, and a flattening film disposed so as to cover the thin film transistor. An interlayer insulating film, a data line disposed on the first interlayer insulating film, and electrically connected to the semiconductor layer via a contact hole formed in the first interlayer insulating film; and A second interlayer insulating film disposed so as to cover the first interlayer insulating film; and a contact hole provided on the second interlayer insulating film and formed in the first interlayer insulating film and the second interlayer insulating film. A pixel electrode electrically connected to the semiconductor layer via a light-shielding film disposed along the data line and disposed so as to overlap an end of the pixel electrode. Optical device. 2. The electro-optical device according to claim 1, wherein the data line is disposed in a recess formed on a surface of the first interlayer insulating film. 3. The electro-optical device according to claim 2, wherein a width of the light shielding film is wider than a width of the concave portion. 4. A conductive layer interposed between the semiconductor layer and the pixel electrode, electrically connected to the semiconductor layer, and electrically connected to the pixel electrode, the conductive layer being made of the same film as the light shielding film. 4. The method according to claim 1, wherein
The electro-optical device according to any one of the above. 5. A light valve, comprising: a light source; and a light valve according to claim 1, wherein light emitted from the light source is incident and performs modulation corresponding to image information. An electronic device comprising: a projection unit configured to project light modulated by the light valve. . 6. A step of forming a switching element on a substrate, a step of forming a light-shielding film on the switching element via an insulating layer, and a first interlayer insulating film made of a flattening film on the light-shielding film. Forming a recess in the first interlayer insulating film; forming a data line connected to the switching element in the recess; and forming a second interlayer insulating film on the data line. Forming a pixel electrode such that the pixel electrode is connected to the switching element via a contact hole formed in the second interlayer insulating film; A method for manufacturing an electro-optical device, wherein the electro-optical device is formed so as to face each other. 7. The method according to claim 6, wherein the flattening film is formed by a CMP method (Chemical Mechanical Polishing method). 8. The method according to claim 6, wherein a width of the light shielding film is wider than a width of the concave portion. 9. The method of manufacturing an electro-optical device according to claim 6, wherein the second interlayer insulating film is formed of a flattening film.