JP7435087B2 - Electro-optical devices and electronic equipment - Google Patents

Description

The present invention relates to an electro-optical device and an electronic device.

2. Description of the Related Art As an electro-optical device, an active drive type liquid crystal device having a switching element in each pixel is known. Such a liquid crystal device is used, for example, as a light valve for a projector as an electronic device.

A liquid crystal device includes a transistor arranged on a substrate and a light shielding film arranged to prevent the transistor from malfunctioning due to light incident on the liquid crystal device. For example, Patent Document 1 discloses a liquid crystal device in which a semiconductor layer is arranged on a substrate, and scanning lines functioning as a light shielding film are arranged so as to overlap with a pixel electrode side LDD (Lightly Doped Drain) region of the semiconductor layer. Disclosed.

Japanese Patent Application Publication No. 2010-117399

However, in order to cope with the increase in luminous flux of projectors, further improvement in light shielding properties is desired.

The electro-optical device includes a substrate, a semiconductor layer including an LDD region disposed on the substrate, a gate insulating layer disposed on the semiconductor layer and the substrate, and a semiconductor layer disposed on the gate insulating layer. a first insulating layer disposed on the gate electrode and the gate insulating layer; and a light shielding layer disposed on the first insulating layer and electrically connected to the gate electrode. a gate wiring; a second insulating layer disposed on the gate wiring and the first insulating layer; a third insulating layer disposed on the second insulating layer; and a third insulating layer disposed on the third insulating layer. a wiring layer having a light-shielding property arranged therein; and a recessed part arranged in a position overlapping with the LDD region in a plan view and penetrating the second insulating layer, the recessed part being arranged in the first insulating layer. and a wall surface exposing end surfaces of the second insulating layer, the first insulating layer, and the gate wiring, and the third insulating layer has a bottom surface exposing the bottom surface and the wall surface of the recess. At a position where the end surface of the gate wiring is exposed on the wall surface of the recess, the end surface of the gate wiring and the wiring layer are arranged to face each other with the third insulating layer interposed therebetween.

The electronic device includes the electro-optical device described above.

FIG. 1 is a schematic plan view showing the configuration of a liquid crystal device as an electro-optical device. 2 is a schematic cross-sectional view taken along line H-H' of the liquid crystal device shown in FIG. 1. FIG. FIG. 2 is an equivalent circuit diagram showing the electrical configuration of a liquid crystal device. A cross-sectional view showing the structure of a pixel. FIG. 3 is a plan view showing the structure of a pixel. FIG. 6 is an enlarged plan view showing an enlarged portion A of the pixel shown in FIG. 5; 7 is a schematic cross-sectional view taken along line B-B' of the pixel shown in FIG. 6. FIG. 1 is a flowchart showing part of a method for manufacturing an element substrate. FIG. 3 is a cross-sectional view showing a part of a method for manufacturing an element substrate. FIG. 3 is a cross-sectional view showing a part of a method for manufacturing an element substrate. FIG. 3 is a cross-sectional view showing a part of a method for manufacturing an element substrate. FIG. 3 is a cross-sectional view showing a part of a method for manufacturing an element substrate. FIG. 3 is a cross-sectional view showing a part of a method for manufacturing an element substrate. FIG. 1 is a schematic diagram showing the configuration of a projector as an electronic device.

As shown in FIGS. 1 and 2, the liquid crystal device 100 of the present embodiment includes an element substrate 10 and a counter substrate 20 that are arranged to face each other, and a liquid crystal layer 15 as an electro-optic layer sandwiched between these pair of substrates. have The first base material 10a as a substrate constituting the element substrate 10 and the second base material 20a constituting the counter substrate 20 are made of, for example, glass or quartz.

The element substrate 10 is larger than the counter substrate 20, and both substrates are bonded via a sealing material 14 disposed along the outer periphery of the counter substrate 20. A liquid crystal having positive or negative dielectric anisotropy is sealed in the gap to constitute the liquid crystal layer 15.

As the sealing material 14, an adhesive such as a thermosetting or ultraviolet curable epoxy resin is used, for example. The sealing material 14 contains, for example, a spacer for keeping the distance between the pair of substrates constant.

A display area E is provided inside the sealing material 14 in which a plurality of pixels P contributing to display are arranged. A peripheral area E1 is arranged around the display area E, in which peripheral circuits and the like that do not contribute to display are provided.

A data line drive circuit 22 is provided between the sealing material 14 along one side of the element substrate 10 and that side. Further, a test circuit 25 is provided between the sealing material 14 and the display area E along the other side opposite to one side. Furthermore, a scanning line drive circuit 24 is provided between the display area E and the sealing material 14 along the other two sides that are perpendicular to one side and opposite to each other. A plurality of wires 29 connecting the two scanning line drive circuits 24 are provided between the sealing material 14 and the inspection circuit 25 along the other side opposite to one side.

Inside the sealing material 14 arranged in a frame shape on the side of the counter substrate 20, a light shielding film 18 is provided in a frame shape as well. The light-shielding film 18 is made of, for example, a light-reflecting metal or metal oxide, and the inside of the light-shielding film 18 is a display area E having a plurality of pixels P. As the light shielding film 18, for example, tungsten silicide (WSi) can be used.

Wiring connected to these data line drive circuits 22 and scanning line drive circuits 24 are connected to a plurality of external connection terminals 70 arranged along one side. Hereinafter, the direction along one side will be referred to as the X direction, and the direction along the other two sides perpendicular to the one side and facing each other will be referred to as the Y direction. Further, a view viewed from the Z direction is called a plan view, and a drawing viewed from the Z direction is called a plan view. Further, a cross-section of the liquid crystal device 100 or a portion thereof viewed from the X direction or the Y direction is referred to as a cross-sectional view, and a drawing of the cross-section of the liquid crystal device 100 or a portion thereof viewed from the X direction or the Y direction is referred to as a cross-sectional view.

As shown in FIG. 2, on the surface of the first base material 10a on the liquid crystal layer 15 side, a pixel electrode 27 having light reflectivity provided for each pixel P and a thin film transistor (hereinafter referred to as a "transistor") which is a switching element are provided. 30''), a data line (not shown), and a first alignment film 28 covering these are formed.

The pixel electrode 27 is formed of, for example, a transparent conductive film such as ITO (Indium Tin Oxide). The element substrate 10 in the present invention includes at least a pixel electrode 27, a transistor 30, and a first alignment film 28.

On the surface of the counter substrate 20 on the liquid crystal layer 15 side, there is a light shielding film 18 , an insulating layer 33 formed to cover this, a counter electrode 31 provided to cover the insulating layer 33 , and a counter electrode 31 provided to cover the insulating layer 33 . A second alignment film 32 is provided to cover the second alignment film 32 . The counter substrate 20 in the present invention includes at least a light shielding film 18, a counter electrode 31, and a second alignment film 32.

The light shielding film 18 surrounds the display area E as shown in FIG. 1, and is provided at a position that overlaps the scanning line drive circuit 24 and the inspection circuit 25 in a plan view. This serves to block light from entering the peripheral circuits including these drive circuits from the opposing substrate 20 side, thereby preventing the peripheral circuits from malfunctioning due to the light. Furthermore, unnecessary stray light is blocked from entering the display area E, thereby ensuring high contrast in the display of the display area E.

The insulating layer 33 is made of, for example, an inorganic material such as silicon oxide (SiO ₂ ), and is provided so as to have light transparency and cover the light shielding film 18 . An example of a method for forming such an insulating layer 33 is a method of forming a film using a CVD (Chemical Vapor Deposition) method.

The counter electrode 31 is made of, for example, a transparent conductive film such as ITO, covers the insulating layer 33, and connects to the wiring on the element substrate 10 side through the upper and lower conductive portions 26 provided at the four corners of the counter substrate 20, as shown in FIG. electrically connected.

The first alignment film 28 covering the pixel electrode 27 and the second alignment film 32 covering the counter electrode 31 are selected based on the optical design of the liquid crystal device 100. As the first alignment film 28 and the second alignment film 32, inorganic materials such as silicon oxide are formed using a vapor phase growth method, and are aligned substantially perpendicularly to liquid crystal molecules having negative dielectric anisotropy. Examples include inorganic alignment films.

Such a liquid crystal device 100 is of a transmissive type, and is normally white in which the transmittance of the pixel P when no voltage is applied is higher than the transmittance when the voltage is applied, and the transmittance of the pixel P when no voltage is applied. A normally black mode optical design is adopted in which the transmittance is smaller than the transmittance when voltage is applied. Polarizing elements are arranged and used on each of the light incident side and light exit side according to the optical design.

As shown in FIG. 3, the liquid crystal device 100 includes a plurality of scanning lines 3a, a plurality of data lines 6a, and a capacitor line 3b, which are insulated from each other and orthogonal to each other, at least in the display area E. For example, the direction in which the scanning line 3a extends is the X direction, and the direction in which the data line 6a extends is the Y direction.

A pixel electrode 27, a transistor 30, and a capacitive element 16 are provided in an area divided by the scanning line 3a, data line 6a, capacitive line 3b, and these signal lines, and these constitute the pixel circuit of the pixel P. It consists of

The scanning line 3a is electrically connected to the gate of the transistor 30, and the data line 6a is electrically connected to the source region of the transistor 30. The pixel electrode 27 is electrically connected to the drain region of the transistor 30.

The data line 6a is connected to a data line drive circuit 22 (see FIG. 1), and supplies image signals D1, D2, . . . , Dn supplied from the data line drive circuit 22 to the pixels P. The scanning line 3a is connected to a scanning line driving circuit 24 (see FIG. 1), and supplies scanning signals SC1, SC2, . . . , SCm supplied from the scanning line driving circuit 24 to each pixel P.

The image signals D1 to Dn supplied from the data line driving circuit 22 to the data lines 6a may be supplied line-sequentially in this order, or may be supplied in groups to a plurality of data lines 6a adjacent to each other. good. The scanning line drive circuit 24 supplies scan signals SC1 to SCm line-sequentially in pulses at predetermined timings to the scanning lines 3a.

In the liquid crystal device 100, the transistor 30, which is a switching element, is turned on for a certain period of time by inputting the scanning signals SC1 to SCm, so that the image signals D1 to Dn supplied from the data line 6a are applied to the pixel electrodes at a predetermined timing. 27. The image signals D1 to Dn at a predetermined level written to the liquid crystal layer 15 via the pixel electrode 27 are held for a certain period of time between the pixel electrode 27 and a counter electrode 31 disposed opposite to each other via the liquid crystal layer 15. Ru.

In order to prevent the held image signals D1 to Dn from leaking, a capacitive element 16 is connected in parallel with the liquid crystal capacitor formed between the pixel electrode 27 and the counter electrode 31. The capacitive element 16 has a dielectric layer as a capacitive film between two capacitive electrodes.

As shown in FIG. 4, the liquid crystal device 100 includes an element substrate 10 and a counter substrate 20 disposed opposite thereto. The first base material 10a that constitutes the element substrate 10 is, for example, quartz. The element substrate 10 includes a scanning line 3a, a transistor 30, a data line 6a, a capacitive element 16, a pixel electrode 27, and a first alignment film 28 on a first base material 10a.

Specifically, an insulating layer 11a made of silicon oxide or the like is arranged on the first base material 10a. On the insulating layer 11a, a scanning line 3a which also functions as a light shielding film made of tungsten silicide (WSi) or the like is arranged.

An insulating layer 11b made of silicon oxide or the like is arranged on the scanning line 3a and the insulating layer 11a. A transistor 30 is formed on the insulating layer 11b.

The transistor 30 has, for example, an LDD (Lightly Doped Drain) structure, and includes a semiconductor layer 30a made of polysilicon (high-purity polycrystalline silicon), and a gate insulating layer 30b formed on the semiconductor layer 30a. , and a gate electrode 30g made of aluminum or the like formed on the gate insulating layer 30b. Note that the gate electrode 30g also functions as the scanning line 3a.

The semiconductor layer 30a is formed as an N-type transistor 30 by, for example, implanting N-type impurity ions such as phosphorus (P) ions. Specifically, the semiconductor layer 30a includes a channel region 30c, a first LDD region 30s1, a source region 30s, a second LDD region 30d1 as an LDD region, and a drain region 30d.

The channel region 30c is doped with P-type impurity ions such as boron (B) ions. Other regions (30s1, 30s, 30d1, 30d) are doped with N-type impurity ions such as phosphorus (P) ions.

A first insulating layer 11c made of silicon oxide or the like is formed on the gate electrode 30g and the gate insulating layer 30b. A gate wiring 30g1 made of aluminum or the like is formed on the first insulating layer 11c and electrically connected to the gate electrode 30g via a contact hole CNT1. The gate wiring 30g1 is electrically connected to the scanning line 3a via a contact hole CNT2.

A second insulating layer 11d made of silicon oxide or the like is formed on the gate wiring 30g1 and the first insulating layer 11c. A third insulating layer 11e made of silicon oxide or the like is formed on the second insulating layer 11d. A wiring layer 30d2 electrically connected to the drain region 30d via a contact hole CNT3 is formed on the third insulating layer 11e. The wiring layer 30d2 is made of aluminum, for example. A portion of the wiring layer 30d2 extends through the second insulating layer 11d to the first insulating layer 11c. This portion is referred to as a wiring layer 30d3. Further, on the third insulating layer 11e, a relay electrode 30s2 is formed which is electrically connected to the source region 30s via a contact hole CNT4.

An insulating layer 11f made of silicon oxide or the like is formed on the wiring layer 30d2, the relay electrode 30s2, and the third insulating layer 11e. A data line 6a electrically connected to the relay electrode 30s2 via a contact hole CNT5 is formed on the insulating layer 11f. Further, on the insulating layer 11f, a relay electrode 30d4 is formed which is electrically connected to the wiring layer 30d2 via a contact hole CNT6.

An insulating layer 11g made of silicon oxide or the like is formed on the data line 6a, the relay electrode 30d4, and the insulating layer 11f. A capacitive element 16 is provided on the insulating layer 11g. Specifically, the capacitor 16 includes, for example, a first capacitor electrode 16a that is a capacitor electrode on the fixed potential side, and a second capacitor that is electrically connected to the drain region 30d of the transistor 30 via a contact hole CNT7. It includes an electrode 16b and a dielectric layer 16c disposed between the first capacitor electrode 16a and the second capacitor electrode 16b. The first capacitor electrode 16a and the second capacitor electrode 16b are made of, for example, aluminum. The dielectric layer 16c is, for example, silicon nitride.

An insulating layer 11h made of silicon oxide or the like is formed on the capacitive element 16. A pixel electrode 27 electrically connected to the second capacitor electrode 16b via a contact hole CNT8 is formed on the insulating layer 11h. The pixel electrode 27 is, for example, a transparent conductive film such as ITO.

A first alignment film 28 is formed on the pixel electrode 27 and the insulating layer 11h by obliquely depositing an inorganic material such as silicon oxide. A liquid crystal layer 15 is provided on the first alignment film 28 , in which a liquid crystal or the like is sealed in a space surrounded by a sealing material 14 .

On the other hand, the counter substrate 20 includes an insulating layer 33, a counter electrode 31, and a second alignment film 32 on the second base material 20a (on the liquid crystal layer 15 side). The second base material 20a is, for example, quartz. The insulating layer 33 is made of silicon oxide, for example. The counter electrode 31 is, for example, a transparent conductive film such as ITO. The second alignment film 32 is formed by obliquely depositing an inorganic material such as silicon oxide.

The liquid crystal layer 15 assumes a predetermined alignment state by the alignment films 28 and 32 in a state where no electric field is generated between the pixel electrode 27 and the counter electrode 31. Light L from a projector 1000, which will be described later, enters from the element substrate 10 side, for example. Next, a partial configuration of the pixel P will be described with reference to FIGS. 5 to 7.

FIG. 5 is a plan view showing a simplified structure of the pixel P of the element substrate 10. As shown in FIG. FIG. 6 is a plan view showing the structure around the transistor 30 from the first base material 10a to the second insulating layer 11d of the element substrate 10.

As shown in FIGS. 5 and 6, the transistor 30 is disposed so as to overlap the intersection of the data line 6a and the scanning line 3a in plan view. The gate electrode 30g of the transistor 30 is electrically connected to the gate wiring 30g1 via a contact hole CNT1 (see FIG. 4). The gate wiring 30g1 is electrically connected to the scanning line 3a via a wall-shaped contact hole CNT2.

Next, a cross-sectional structure around the transistor 30 will be described with reference to FIG. 7. As shown in FIG. 7, a transistor 30 is provided on the first base material 10a. A recessed portion 11d2 is provided in the first insulating layer 11c and the second insulating layer 11d, adjacent to the gate wiring 30g1 having a light-shielding property, penetrating the second insulating layer 11d and spanning the first insulating layer 11c.

Returning to the plan view of FIG. 6, the recess 11d2 is provided at a position overlapping the second LDD region 30d1 of the semiconductor layer 30a. Further, a gate wiring 30g1 is arranged adjacent to the recessed portion 11d2. Further, the recessed portion 11d2 is arranged so as to be sandwiched between contact holes CNT2 serving as wall-shaped relay electrodes. Furthermore, the scanning line 3a is arranged so as to overlap the second LDD region 30d1 in plan view.

As shown in FIG. 7, the third insulating layer 11e formed on the second insulating layer 11d is drawn into the recess 11d2. Further, a wiring layer 30d2 having a light-shielding property is drawn into the recessed portion 11d2, and is laminated on the third insulating layer 11e.

In this way, the third insulating layer 11e disposed in the recess 11d2 ensures insulation between the gate wiring 30g1 having a light-shielding property and the wiring layer 30d2 having a light-shielding property. It becomes possible to bring the position of the third insulating layer 11e closer to the thickness of the third insulating layer 11e. Therefore, the light-shielding property of the second LDD region 30d1 can be improved, and as a result, for example, malfunction of the transistor 30 including the semiconductor layer 30a can be suppressed.

Next, a method for manufacturing the peripheral portion of the transistor 30 will be described with reference to FIGS. 8 to 13. As shown in FIG. 8, first, in step S11, a transistor 30 is formed. Specifically, as shown in FIG. 9, an insulating layer 11a, a scanning line 3a, an insulating layer 11b, and a transistor 30 are formed on a first base material 10a using a known manufacturing method.

Subsequently, the first insulating layer 11c is formed in step S12, the gate wiring 30g1 is formed in step S13, and the second insulating layer 11d is formed in step S14 using a known manufacturing method.

In step S15, a recessed portion 11d1 is formed. Specifically, as shown in FIG. 10, it is formed using, for example, an etching method so as to penetrate through a portion of the second insulating layer 11d that overlaps the second LDD region 30d1 of the semiconductor layer 30a in plan view. As a result, a recessed portion 11d1 is formed extending from a portion of the second insulating layer 11d that overlaps with the second LDD region 30d1 to a portion of the first insulating layer 11c.

Subsequently, as shown in FIG. 11, a part of the gate wiring 30g1 and the first insulating layer 11c are etched to form a recess 11d2. As a result, the end surface ef of the gate wiring 30g1 is exposed on the wall surface wf of the recess 11d2, the first insulating layer 11c is exposed on the bottom surface bf of the recess 11d2, and the bottom surface bf of the recess 11d2 is exposed on the bottom surface bf of the gate insulating layer 30b. The recess 11d2 dug to the front is completed.

In step S16, a third insulating layer 11e is formed. Specifically, as shown in FIG. 12, for example, a CVD method is applied to cover the entire inner surface of the recess 11d2 from above the second insulating layer 11d, that is, the entire surface of the wall surface wf and bottom surface bf of the recess 11d2. The third insulating layer 11e is formed using a film forming method such as the following.

In step S17, a wiring layer 30d2 is formed. Specifically, as shown in FIG. 13, a wiring layer is formed using a film forming method such as a CVD method or a patterning method so as to cover the entire surface of the third insulating layer 11e including the inside of the recess 11d2. 30d2 and 30d3 are formed.

In this way, after forming the gate wiring 30g1, the recess 11d2 is formed, and the third insulating layer 11e and the wiring layer 30d2 are formed in the recess 11d2, so there is no need to take into account manufacturing variations beforehand. , insulation between the gate wiring 30g1 and the wiring layer 30d2 can be ensured. Furthermore, at the position where the end surface ef of the gate wiring 30g1 is exposed on the wall surface wf of the recess 11d2, the end surface ef of the gate wiring 30g1 and the wiring layer 30d2 are arranged to face each other with the third insulating layer 11e interposed therebetween. It is possible to make the interval between the end face ef of the gate wiring 30g1 having a light-shielding property and the wiring layer 30d2 having a light-shielding property close to the thickness of the third insulating layer 11e, thereby improving the light-shielding property of the second LDD region 30d1. can be improved. In addition, since it can be manufactured without considering manufacturing variations, productivity can be improved.

Thereafter, the element substrate 10 is completed by forming the data line 6a, the capacitive element 16, the pixel electrode 27, the first alignment film 28, etc.

As shown in FIG. 14, the projector 1000 of this embodiment includes a polarized illumination device 1100 arranged along the system optical axis L, two dichroic mirrors 1104 and 1105 as light separation elements, and three reflection mirrors 1106. , 1107, 1108, five relay lenses 1201, 1202, 1203, 1204, 1205, three transmission type liquid crystal light valves 1210, 1220, 1230 as light modulation means, and a cross dichroic prism 1206 as a light combining element. , and a projection lens 1207.

The polarized illumination device 1100 is generally composed of a lamp unit 1101 as a light source made of a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 1102, and a polarization conversion element 1103.

The dichroic mirror 1104 reflects the red light (R) out of the polarized light beam emitted from the polarized illumination device 1100, and transmits the green light (G) and the blue light (B). Another dichroic mirror 1105 reflects the green light (G) that has passed through the dichroic mirror 1104 and transmits the blue light (B).

The red light (R) reflected by the dichroic mirror 1104 is reflected by the reflective mirror 1106 and then enters the liquid crystal light valve 1210 via the relay lens 1205. The green light (G) reflected by the dichroic mirror 1105 enters the liquid crystal light valve 1220 via the relay lens 1204. The blue light (B) transmitted through the dichroic mirror 1105 enters the liquid crystal light valve 1230 via a light guide system consisting of three relay lenses 1201, 1202, 1203 and two reflection mirrors 1107, 1108.

The liquid crystal light valves 1210, 1220, and 1230 are arranged opposite to the incident surface of the cross dichroic prism 1206 for each color light. The colored light incident on the liquid crystal light valves 1210, 1220, and 1230 is modulated based on video information (video signal) and is emitted toward the cross dichroic prism 1206.

This prism consists of four rectangular prisms bonded together, and has a cross-shaped dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light formed on its inner surface. These dielectric multilayer films combine three colored lights to create a light representing a color image. The combined light is projected onto the screen 1300 by a projection lens 1207, which is a projection optical system, and the image is enlarged and displayed.

The liquid crystal light valve 1210 is one to which the liquid crystal device 100 described above is applied. The liquid crystal device 100 is arranged with a gap between a pair of polarizing elements arranged in crossed nicols on an incident side and an exit side of colored light. The same applies to the other liquid crystal light valves 1220 and 1230.

In addition to the projector 1000, electronic devices equipped with the liquid crystal device 100 include a head-up display (HUD), a head-mounted display (HMD), a smartphone, an EVF (Electrical View Finder), a mobile mini projector, an e-book, and a mobile phone. It can be used in various electronic devices such as telephones, mobile computers, digital cameras, digital video cameras, displays, in-vehicle equipment, audio equipment, exposure equipment, and lighting equipment.

As described above, the liquid crystal device 100 of the present embodiment includes the first base material 10a, the semiconductor layer 30a including the second LDD region 30d1 disposed on the first base material 10a, and the semiconductor layer 30a and the first base material 10a. A gate insulating layer 30b disposed on the base material 10a, a gate electrode 30g disposed on the gate insulating layer 30b, and a first insulating layer 11c disposed on the gate electrode 30g and the gate insulating layer 30b. , a gate wiring 30g1 having a light-shielding property disposed on the first insulating layer 11c and electrically connected to the gate electrode 30g, and a second insulating layer disposed on the gate wiring 30g1 and the first insulating layer 11c. 11d, a third insulating layer 11e disposed on the second insulating layer 11d, wiring layers 30d2 and 30d3 having light-shielding properties disposed on the third insulating layer 11e, and a second LDD region 30d1 in plan view. a recess 11d2 that is arranged in an overlapping position and that penetrates through the second insulating layer 11d; the recess 11d2 has a bottom surface bf that exposes the first insulating layer 11c; The third insulating layer 11e has a wall surface wf that exposes the end surface ef of the layer 11c and the gate wiring 30g1, and the third insulating layer 11e is disposed to cover the bottom surface bf and the wall surface wf of the recessed portion 11d2, and the gate wiring on the wall surface wf of the recessed portion 11d2. At a position where the end surface ef of the gate wiring 30g1 is exposed, the end surface ef of the gate wiring 30g1 and the wiring layer 30d3 are arranged to face each other with the third insulating layer 11e interposed therebetween.

According to this configuration, the third insulating layer 11e disposed on the inner wall of the recess 11d2 ensures insulation between the gate wiring 30g1 having a light-shielding property and the wiring layer 30d3 having a light-shielding property. It becomes possible to bring the position of the layer 30d3 closer to the thickness of the third insulating layer 11e. Therefore, the light-shielding property of the second LDD region 30d1 can be improved, and as a result, for example, malfunction of the transistor 30 including the semiconductor layer 30a can be suppressed.

Further, a scanning line 3a having a light blocking property is electrically connected to the gate wiring 30g1, and the scanning line 3a is arranged to overlap the second LDD region 30d1 in a plan view.

According to this configuration, the scanning line 3a having a light-shielding property is arranged to overlap with the second LDD region 30d1, so that the light-shielding property of the second LDD region 30d1 can be improved.

Further, the wiring layers 30d3 and 30d2 are electrically connected to the drain region 30d of the semiconductor layer 30a, and the recessed portion 11d2 is arranged above the second LDD region 30d1 on the side of the drain region 30d.

According to this configuration, since the recessed portion 11d2 is arranged above the second LDD region 30d1 on the side of the drain region 30d, it is possible to improve the light-shielding property of the second LDD region 30d1 where leakage current is particularly likely to occur.

Further, a contact hole CNT2 is provided as a wall-shaped relay electrode that connects the gate wiring 30g1 and the scanning line 3a, and both sides of the recess 11d2 are sandwiched between the contact holes CNT2.

According to this configuration, since the contact hole CNT2 is arranged to sandwich the recess 11d2 arranged above the second LDD region 30d1, the light-shielding property of the second LDD region 30d1 can be improved.

Furthermore, since the projector 1000 includes the liquid crystal device 100 described above, it is possible to provide a projector 1000 that is unlikely to malfunction.

Note that the recessed portion 11d2 is not limited to being provided so as to overlap with the second LDD region 30d1, but may be provided so as to overlap with the first LDD region 30s1, for example.

Furthermore, the present invention is not limited to applying the liquid crystal device 100 as described above as an electro-optical device, but may be applied to, for example, an organic EL device, a plasma display, an electronic paper (EPD), or the like.

3a...Scanning line, 3b...Capacitance line, 6a...Data line, 10...Element substrate, 10a...First base material as a substrate, 11a, 11b...Insulating layer, 11c...First insulating layer, 11d...Second insulating layer , 11d1, 11d2... recess, 11e... third insulating layer, 11f, 11g, 11h... insulating layer, 14... sealing material, 15... liquid crystal layer, 16... capacitor element, 16a... first capacitor electrode, 16b... second capacitor Electrode, 16c... Dielectric layer, 18... Light shielding film, 20... Counter substrate, 20a... Second base material, 22... Data line drive circuit, 24... Scanning line drive circuit, 25... Inspection circuit, 26... Vertical conduction section, 27... Pixel electrode, 28... First alignment film, 29... Wiring, 30... Transistor, 30a... Semiconductor layer, 30b... Gate insulating layer, 30c... Channel region, 30d... Drain region, 30d1... Second LDD region as LDD region , 30d2, 30d3... wiring layer, 30d4... relay electrode, 30g... gate electrode, 30g1... gate wiring, 30s... source region, 30s1... first LDD region, 30s2... relay electrode, 31... counter electrode, 32... second alignment film , 33... Insulating layer, 70... External connection terminal, 100... Liquid crystal device, 1000... Projector, 1100... Polarized illumination device, 1101... Lamp unit, 1102... Integrator lens, 1103... Polarization conversion element, 1104, 1105... Dichroic mirror , 1106, 1107, 1108... Reflection mirror, 1201, 1202, 1203, 1204, 1205... Relay lens, 1206... Cross dichroic prism, 1207... Projection lens, 1210, 1220, 1230... Liquid crystal light valve, 1300... Screen.

Claims (5)

A substrate and
a semiconductor layer including an LDD region disposed on the substrate;
a gate insulating layer disposed on the semiconductor layer and the substrate;
a gate electrode disposed on the gate insulating layer;
a first insulating layer disposed on the gate electrode and the gate insulating layer;
a gate wiring having a light-shielding property disposed on the first insulating layer and electrically connected to the gate electrode;
a second insulating layer disposed on the gate wiring and the first insulating layer;
a third insulating layer disposed on the second insulating layer;
a wiring layer having a light-shielding property disposed on the third insulating layer;
a concave portion located at a position overlapping the LDD region in plan view and penetrating the second insulating layer;
Equipped with
The recess is
a bottom surface exposing the first insulating layer;
a wall surface exposing an end surface of the second insulating layer, the first insulating layer, and the gate wiring;
The third insulating layer is disposed to cover the bottom surface and the wall surface of the recess,
The electro-optic device is characterized in that at a position on the wall surface of the recess where the end face of the gate wiring is exposed, the end face of the gate wiring and the wiring layer are arranged to face each other with the third insulating layer interposed therebetween. Device. The electro-optical device according to claim 1,
comprising a scanning line electrically connected to the gate wiring and having a light-shielding property;
The electro-optical device is characterized in that the scanning line is arranged to overlap the LDD region in a plan view. The electro-optical device according to claim 1 or 2,
The wiring layer is electrically connected to the drain region of the semiconductor layer,
The electro-optical device is characterized in that the recess is arranged above the LDD region on the side of the drain region. The electro-optical device according to claim 2 ,
comprising a wall-shaped relay electrode connecting the gate wiring and the scanning line,
An electro-optical device, wherein both sides of the recess are sandwiched between the relay electrodes. An electronic device comprising the electro-optical device according to claim 4.

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