JP2014142385A - Electro-optic device, method for manufacturing electro-optic device, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal device capable of improving electric reliability, a method for manufacturing a liquid crystal device, and electronic equipment.SOLUTION: The liquid crystal device comprises: a first wiring line 61 disposed on a first substrate 10a; a guard wiring line 60 and a first element-side wiring line 81 disposed on the first wiring line 61 via a first insulating layer 91; a second wiring line 62 and a second element-side wiring line 82 disposed on the guard wiring line 60 and the first element-side wiring line 81, in which the guard wiring line 60 and the first wiring line 61 are electrically connected via the second wiring line 62, and the first element-side wiring line 81 and the first wiring line 61 are electrically connected via the second element-side wiring line 82; a third insulating layer 93 disposed between an overlay wiring line 75 and each of the second wiring line 62 and the second element-side wiring line 82; a first contact hole CNT71 opened in the third insulating layer 93, for connecting the second element-side wiring line 82 and the overlay wiring line 75; and a second contact hole CNT72 opened in the third insulating layer 93 and overlapping the second wiring line 62 in a plan view.

Description

  The present invention relates to an electro-optical device, a method for manufacturing the electro-optical device, and an electronic apparatus.

  As one of the electro-optical devices, for example, an active drive type liquid crystal device including a transistor for each pixel as an element for switching control of a pixel electrode is known. Liquid crystal devices are used in, for example, direct-view displays and projector light valves.

  In a liquid crystal panel constituting such a liquid crystal device, for example, as described in Patent Document 1, wiring called a short ring (high resistance wiring) is arranged in order to eliminate a potential difference between wiring patterns in the manufacturing process. ing.

  For example, one of the short rings is connected to a gate line of a liquid crystal panel, and the other is electrically connected to a guard ring that is routed over the entire mother board on which a plurality of liquid crystal panels are attached. ing. The short ring is finally separated from the circuit and does not have a function as a wiring at the stage of the finished product.

JP 2007-122071

  However, when contact holes are formed to connect liquid crystal panel wirings (source lines, gate lines, power supply wirings, etc.), excessive static electricity accumulated in the guard ring flows to the short ring. Accordingly, there is a problem that the short ring causes electrostatic breakdown and affects the liquid crystal panel.

  An aspect of the present invention has been made to solve at least a part of the above problems, and can be realized as the following forms or application examples.

  [Application Example 1] An electro-optical device according to this application example includes a first base material, a first wiring disposed on the first base material, and a first insulation disposed on the first wiring. A layer, a guard wiring and a first element side wiring arranged on the first insulating layer, a second insulating layer arranged on the guard wiring and the first element side wiring, and the second insulation A second wiring and a second element side wiring disposed on the layer; a third insulating layer disposed on the second wiring and the second element side wiring; and disposed on the third insulating layer. The guard wiring and the first wiring are electrically connected via the second wiring, and the first element-side wiring and the first wiring are connected to the second wiring. It is electrically connected through an element side wiring, and penetrates the third insulating layer to connect the second element side wiring and the upper layer wiring. It is disposed urchin first contact hole, so as to overlap with the second wiring in plan view, wherein the second contact hole so as to penetrate the third insulating layer is arranged.

  According to this application example, the first contact hole connected to the second element side wiring on the element (transistor) side and the second contact hole connected to the second wiring on the guard wiring side are connected to the third insulating layer. Accordingly, static electricity accumulated on the electro-optical device side including the second element side wiring can be released from the first contact hole, and static electricity accumulated in the guard wiring can be released from the second contact hole. In other words, by providing the second contact hole separately from the first contact hole, excessive static electricity accumulated in the guard wiring having a large wiring area flows in the first wiring (short ring), It is possible to suppress the first wiring from being electrostatically broken. As a result, it is possible to prevent the electro-optical device from being affected.

  Application Example 2 An electro-optical device according to this application example includes a first substrate, a first wiring disposed on the first substrate, and a first insulation disposed on the first wiring. A layer, a guard wiring and a first element side wiring arranged on the first insulating layer, a second insulating layer arranged on the guard wiring and the first element side wiring, and the second insulation A second wiring, a third wiring, and a second element side wiring disposed on the layer; a third insulating layer disposed on the second wiring, the third wiring, and the second element side wiring; An upper layer wiring disposed on the third insulating layer, wherein the second wiring and the first wiring are electrically connected via the guard wiring and the third wiring, and The first element side wiring and the first wiring are electrically connected via the second element side wiring, and the second element side wiring and the upper layer wiring The first contact hole is disposed so as to penetrate the third insulating layer, and the second contact hole penetrates the third insulating layer so as to overlap the second wiring in a plan view. It is characterized by being arranged.

  According to this application example, the first contact hole connected to the second element side wiring on the element side and the second contact hole connected to the second wiring on the guard wiring side are opened in the third insulating layer. Therefore, static electricity accumulated on the electro-optical device side including the second element side wiring can be released from the first contact hole, and static electricity accumulated in the guard wiring can be released from the second contact hole. In other words, by providing the second contact hole separately from the first contact hole, for example, excessive static electricity accumulated in the guard wiring having a large wiring area flows to the first wiring and flows first. It is possible to suppress electrostatic breakdown of the wiring. As a result, it is possible to prevent the electro-optical device from being affected. In addition, by disposing the second contact hole at a position away from the first wiring via the third wiring, the second contact hole is provided in a narrow area around the first wiring as compared with the case where the second contact hole is provided. Wiring can be widely provided, and the second contact hole can be reliably provided.

  Application Example 3 In the electro-optical device according to the application example, the sheet resistance of the first wiring is the sheet resistance of the first element side wiring, the second element side wiring, the second wiring, and the upper layer wiring. It is preferable that it is larger than

  According to this application example, since the sheet resistance of the first wiring is larger than the sheet resistance of the other wiring, for example, static electricity can be prevented from flowing from the guard wiring side to the element side, and the first element on the element side can be suppressed. The side wiring, the second element side wiring, and the like can be prevented from electrostatic breakdown.

  Application Example 4 In the electro-optical device according to the application example, it is preferable that a second upper layer wiring is provided on the second contact hole.

  According to this application example, since the second upper layer wiring is provided on the second contact hole, the second upper layer wiring is also left when the upper layer wiring is formed, and the second wiring below the second upper layer wiring is left. Can be prevented from being damaged. Therefore, the guard wiring and the second upper layer wiring can be reliably connected, and excess static electricity can be released from the second contact hole in the subsequent manufacturing process.

  Application Example 5 In the electro-optical device according to the application example, it is preferable that the guard wiring is provided between adjacent electro-optical devices.

  According to this application example, even when the guard wiring is connected to a plurality of electro-optical devices and excessive static electricity is accumulated in the guard wiring (when there is a large parasitic capacitance), the guard wiring is routed through the first wiring. In addition, static electricity can be released from the second contact hole. Therefore, it is possible to prevent the first wiring and the electro-optical device from being destroyed.

  Application Example 6 An electro-optical device manufacturing method according to this application example includes a first wiring forming step of forming a first wiring on a first substrate, the first wiring, and the first substrate. A first insulating layer forming step of forming a first insulating layer; a guard wiring forming step of forming a guard wiring and a first element side wiring on the first insulating layer; the guard wiring and the first element side wiring; A second insulating layer forming step of forming a second insulating layer on the first insulating layer; a second wiring forming step of forming a second wiring and a second element side wiring on the second insulating layer; Contact holes are formed in a region overlapping the guard wiring and the first wiring and the second wiring in a plan view, and in a region overlapping the first wiring and the first element side wiring and the second element side wiring in a plan view. And electrically connecting the guard wiring, the second wiring, and the first wiring. A connecting step of electrically connecting the first wiring, the second element side wiring, and the first element side wiring; and a second step on the second wiring, the second element side wiring, and the second insulating layer. Forming a third insulating layer; forming a first contact hole in a region of the third insulating layer overlapping the second element side wiring in a plan view; and A contact hole forming step of forming a second contact hole in the overlapping region.

  According to this application example, since the first contact hole on the element side and the second contact hole on the guard wiring side are opened in the third insulating layer, the first contact hole on the element side is accumulated on the electro-optical device side including the second element side wiring and the like. The static electricity that has escaped from the first contact hole can be released from the second contact hole. In other words, by forming the second contact hole separately from the first contact hole, for example, excessive static electricity accumulated in the guard wiring having a large wiring area flows to the first wiring and flows. Can suppress electrostatic breakdown. As a result, it is possible to prevent the liquid crystal device from being affected.

  Application Example 7 A method for manufacturing an electro-optical device according to this application example includes a first wiring forming step of forming a first wiring on a first substrate, the first wiring, and the first substrate. A first insulating layer forming step of forming a first insulating layer; a guard wiring forming step of forming a guard wiring and a first element side wiring on the first insulating layer; the guard wiring and the first element side wiring; A second insulating layer forming step for forming a second insulating layer on the first insulating layer; and a second wiring for forming a second wiring, a third wiring, and a second element side wiring on the second insulating layer. Forming a contact hole in a region overlapping the second wiring and the third wiring and the guard wiring in a plan view, and forming a contact hole in a region overlapping the third wiring and the first wiring in a plan view; Forming the second element side wiring, the first wiring, and the first element side wiring. A contact hole is formed in a region overlapping in plan view, the second wiring, the guard wiring, the third wiring, and the first wiring are electrically connected, and the first wiring and the second element side A connection step of electrically connecting the wiring and the first element side wiring; and forming a third insulating layer on the second wiring, the third wiring, the second element side wiring, and the second insulating layer Forming a first contact hole in a region overlapping with the second element side wiring in a plan view, and forming a second contact in the region overlapping with the second wiring in a plan view. A contact hole forming step of forming a contact hole.

  According to this application example, since the first contact hole on the element side and the second contact hole on the guard wiring side are opened in the third insulating layer, the first contact hole on the element side is accumulated on the electro-optical device side including the second element side wiring. The static electricity that has escaped from the first contact hole can be released from the second contact hole. In other words, by forming the second contact hole separately from the first contact hole, for example, excessive static electricity accumulated in the guard wiring having a large wiring area flows to the first wiring and flows. Can suppress electrostatic breakdown. As a result, it is possible to prevent the electro-optical device from being affected. In addition, the second contact hole is formed at a position away from the first wiring via the third wiring, so that the second contact hole is formed in a narrow region around the first wiring compared to the case where the second contact hole is formed. Two wirings can be formed widely, and the second contact hole can be reliably formed.

  Application Example 8 In the method of manufacturing the electro-optical device according to the application example, after the contact hole forming step, an upper layer wiring is formed on the first contact hole, and a second wiring is formed on the second contact hole. It is preferable to have an upper layer wiring forming step of forming an upper layer wiring.

  According to this application example, since the second upper layer wiring is formed on the second contact hole, when the upper layer wiring is formed, the second upper layer wiring is also left, and the second wiring below the second upper layer wiring is left. Damage can be prevented. Therefore, the guard wiring and the second upper layer wiring can be reliably connected, and excess static electricity can be released from the second contact hole in the subsequent manufacturing process.

  Application Example 9 An electronic apparatus according to this application example includes the electro-optical device described above.

  According to this application example, the electro-optical device including the element-side wiring can be protected from excessive static electricity, and a highly reliable electronic device can be provided.

FIG. 3 is a schematic plan view showing a configuration of a part of a mother substrate on which a plurality of liquid crystal devices as electro-optical devices are attached. FIG. 2 is a schematic plan view illustrating a configuration of a liquid crystal device. FIG. 3 is a schematic cross-sectional view taken along the line H-H ′ of the liquid crystal device illustrated in FIG. 2. FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device. The enlarged plan view which expands and shows the A section of the mother board | substrate shown in FIG. FIG. 3 is a schematic cross-sectional view illustrating a partial structure of the liquid crystal device illustrated in FIG. 2. FIG. 6 is a schematic cross-sectional view illustrating a partial structure of the liquid crystal device illustrated in FIG. 5. FIG. 4 is a schematic cross-sectional view illustrating a manufacturing method around a guard wiring and a first wiring among manufacturing methods of a liquid crystal device. FIG. 4 is a schematic cross-sectional view illustrating a manufacturing method around a guard wiring and a first wiring among manufacturing methods of a liquid crystal device. Schematic which shows the structure of the projection type display apparatus provided with the liquid crystal device. FIG. 9 is a schematic cross-sectional view illustrating a structure of a liquid crystal device according to a modification. FIG. 9 is a schematic cross-sectional view illustrating a structure of a liquid crystal device according to a modification.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. Note that the drawings to be used are appropriately enlarged or reduced so that the part to be described can be recognized.

  In the following embodiments, for example, when “on the substrate” is described, the substrate is disposed so as to be in contact with the substrate, or is disposed on the substrate via another component, or the substrate. It is assumed that a part is arranged so as to be in contact with each other and a part is arranged via another component.

  In the present embodiment, an active matrix liquid crystal device including a thin film transistor (TFT) as a pixel switching element will be described as an example of an electro-optical device. This liquid crystal device can be suitably used, for example, as a light modulation element (liquid crystal light valve) of a projection display device (liquid crystal projector).

<Configuration of electro-optical device>
FIG. 1 is a schematic plan view showing a configuration of a part of a mother substrate on which a plurality of liquid crystal devices as electro-optical devices are attached. FIG. 2 is a schematic plan view showing the configuration of the liquid crystal device. FIG. 3 is a schematic cross-sectional view taken along the line HH ′ of the liquid crystal device shown in FIG. FIG. 4 is an equivalent circuit diagram showing an electrical configuration of the liquid crystal device. Hereinafter, the configuration of the liquid crystal device will be described with reference to FIGS.

  As shown in FIG. 1, for example, the mother substrate 500 has a plurality of substrates (for example, element substrates) out of a pair of substrates constituting the liquid crystal device 100, and is imposed in a matrix. The size of the mother substrate 500 is, for example, 8 inches. The thickness of the mother substrate 500 is, for example, 1.2 mm. The material of the mother substrate 500 is, for example, quartz. Hereinafter, the configuration of the liquid crystal device 100 will be described.

  As shown in FIGS. 2 and 3, the liquid crystal device 100 of the present embodiment includes an element substrate 10 and a counter substrate 20 that are arranged to face each other, and a liquid crystal layer 15 that is sandwiched between the pair of substrates. As the first base material 10a constituting the element substrate 10 and the second base material 20a constituting the counter substrate 20, for example, a transparent substrate such as a glass substrate or a quartz substrate is used.

  The element substrate 10 is larger than the counter substrate 20, and both the substrates are bonded via a sealing material 14 disposed along the outer periphery of the counter substrate 20. In the element substrate 10, liquid crystal having positive or negative dielectric anisotropy is sealed between the opposing substrates 20 inside the sealing material 14 provided in an annular shape in plan view, thereby forming a liquid crystal layer 15. For the sealing material 14, for example, an adhesive such as a thermosetting or ultraviolet curable epoxy resin is employed. Spacers (not shown) are mixed in the sealing material 14 to keep the distance between the pair of substrates constant.

  A display area E in which a plurality of pixels P are arranged is provided inside the sealing material 14. Although not shown in FIGS. 2 and 3, a light-shielding film (black matrix; BM) that divides a plurality of pixels P in the display area E in a plane is provided on the counter substrate 20.

  A data line driving circuit 22 is provided between the sealing material 14 along one side of the element substrate 10 and the one side. Further, an inspection circuit 25 is provided between the sealing material 14 and the display area E along the other one side facing the one side. Further, a scanning line driving circuit 24 is provided between the sealing material 14 and the display area E along the other two sides that are orthogonal to the one side and face each other. A plurality of wirings 29 connecting the two scanning line driving circuits 24 are provided between the sealing material 14 and the inspection circuit 25 along the other one side facing the one side.

  A light shielding film 18 (parting portion) is provided between the sealing material 14 arranged in an annular shape on the counter substrate 20 and the display region E. The light shielding film 18 is made of, for example, a light shielding metal or metal oxide, and the inside of the light shielding film 18 is a display area E having a plurality of pixels P. Although not shown in FIG. 2, the display region E is also provided with a light shielding film that divides a plurality of pixels P in a plane.

  Wirings connected to the data line driving circuit 22 and the scanning line driving circuit 24 are connected to a plurality of external connection terminals 65 arranged along the one side. Hereinafter, the direction along the one side will be referred to as the X direction, and the direction along the other two sides orthogonal to the one side and facing each other will be described as the Y direction.

  As shown in FIG. 3, on the surface of the first base material 10a on the liquid crystal layer 15 side, a transparent pixel electrode 27 provided for each pixel P and a thin film transistor (TFT: Thin Film Transistor, which is a switching element) are provided. Hereinafter, it is referred to as “TFT 30”), signal wirings, and an alignment film 28 covering them.

  In addition, a light shielding structure is employed that prevents light from entering the semiconductor layer in the TFT 30 to make the switching operation unstable. The element substrate 10 in the present invention includes at least the pixel electrode 27, the TFT 30, and the alignment film 28.

  On the surface of the counter substrate 20 on the liquid crystal layer 15 side, a light shielding film 18, a planarizing layer 33 formed so as to cover the light shielding film 18, a counter electrode 31 provided so as to cover the planarizing layer 33, An alignment film 32 that covers the electrode 31 is provided. The counter substrate 20 in the present invention includes at least the counter electrode 31 and the alignment film 32.

  As shown in FIG. 2, the light shielding film 18 surrounds the display region E and is provided at a position where the scanning line driving circuit 24 and the inspection circuit 25 overlap in a plan view (illustration is simplified). Thus, the light incident on the peripheral circuit including these drive circuits from the counter substrate 20 side is shielded, and the peripheral circuit is prevented from malfunctioning due to the light. Further, unnecessary stray light is shielded from entering the display area E, and high contrast in the display of the display area E is ensured.

  The planarizing layer 33 is made of an inorganic material such as silicon oxide, for example, and is provided so as to cover the light shielding film 18 with optical transparency. As a method for forming such a planarization layer 33, for example, a method of forming a film by using a plasma CVD (Chemical Vapor Deposition) method or the like can be cited.

  The counter electrode 31 is made of a transparent conductive film such as ITO (Indium Tin Oxide), for example, covers the planarization layer 33, and as shown in FIG. 2, vertical conductive parts as conductive parts provided at the four corners of the counter substrate 20 26 is electrically connected to the wiring on the element substrate 10 side.

  The alignment film 28 covering the pixel electrode 27 and the alignment film 32 covering the counter electrode 31 are selected based on the optical design of the liquid crystal device 100. For example, an inorganic alignment film formed by depositing an inorganic material such as SiOx (silicon oxide) using a vapor deposition method and substantially vertically aligning with liquid crystal molecules having negative dielectric anisotropy can be given.

  Such a liquid crystal device 100 is of a transmissive type, and the transmittance of the pixel P when no voltage is applied is larger than the transmittance when the voltage is applied, resulting in a normally white display, or when no voltage is applied. A normally black mode optical design is adopted in which the transmittance of the pixel P is smaller than the transmittance when a voltage is applied and dark display is achieved. Polarizing elements are arranged and used according to the optical design on the light incident side and the light exit side, respectively.

  As shown in FIG. 4, the liquid crystal device 100 includes a plurality of scanning lines 3 a and a plurality of data lines 6 a that are insulated from each other and orthogonal to each other in at least the display region E, and capacitance lines 3 b. The direction in which the scanning line 3a extends is the X direction, and the direction in which the data line 6a extends is the Y direction.

  A pixel electrode 27, a TFT 30, and a capacitive element 16 as a capacitor are provided in a region divided by the scanning line 3 a, the data line 6 a, the capacitive line 3 b, and these signal lines, and these are the pixels of the pixel P The circuit is configured.

  The scanning line 3 a is electrically connected to the gate of the TFT 30, and the data line 6 a is electrically connected to the data line side source / drain region (source region) of the TFT 30. The pixel electrode 27 is electrically connected to the pixel electrode side source / drain region (drain region) of the TFT 30.

  The data line 6a is connected to the data line driving circuit 22 (see FIG. 2), and supplies image signals D1, D2,..., Dn supplied from the data line driving circuit 22 to the pixels P. The scanning line 3a is connected to the scanning line driving circuit 24 (see FIG. 2), and supplies the scanning signals SC1, SC2,..., SCm supplied from the scanning line driving circuit 24 to each pixel P.

  The image signals D1 to Dn supplied from the data line driving circuit 22 to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each of a plurality of adjacent data lines 6a for each group. Good. The scanning line driving circuit 24 supplies the scanning signals SC1 to SCm to the scanning line 3a at a predetermined timing.

  In the liquid crystal device 100, the TFT 30 as a switching element is turned on for a certain period by the input of the scanning signals SC1 to SCm, so that the image signals D1 to Dn supplied from the data line 6a are supplied to the pixel electrode 27 at a predetermined timing. It is the structure written in. The predetermined level of the image signals D1 to Dn written to the liquid crystal layer 15 through the pixel electrode 27 is held for a certain period between the pixel electrode 27 and the counter electrode 31 disposed to face the liquid crystal layer 15. The

  In order to prevent the held image signals D1 to Dn from leaking, the capacitive element 16 is connected in parallel with the liquid crystal capacitance formed between the pixel electrode 27 and the counter electrode 31. The capacitive element 16 is provided between the pixel electrode side source / drain region of the TFT 30 and the capacitive line 3b. The capacitive element 16 has a dielectric layer between two capacitive electrodes.

  FIG. 5 is an enlarged plan view showing an A portion of the mother board shown in FIG. FIG. 6 is a schematic cross-sectional view showing a part of the structure of the liquid crystal device shown in FIG. FIG. 7 is a schematic cross-sectional view showing a partial structure of the liquid crystal device shown in FIG. Hereinafter, the configuration of the liquid crystal device will be described with reference to FIGS. 6 and 7 show cross-sectional positional relationships among the constituent elements, and are expressed on an expressible scale.

  As shown in FIG. 5, in the mother substrate 500, as described above, a plurality of liquid crystal devices 100 are arranged in a matrix. A guard wiring 60 that is electrically connected to the plurality of liquid crystal devices 100 provided on the mother substrate 500 is provided at the boundary between the adjacent liquid crystal devices 100. In other words, the guard wiring 60 is routed over the entire mother board 500. Therefore, the area of the guard wiring 60 is extremely wide compared to the areas of the other wirings. That is, in the manufacturing process, the guard wiring 60 may have a large parasitic capacitance.

  The guard wiring 60 is used to eliminate the potential difference between the wiring patterns in the manufacturing process. Specifically, the guard wiring 60 is electrically connected to the gate line of the liquid crystal device 100 via a first wiring 61 (also referred to as a short ring or a high resistance wiring), for example. The first wiring 61 is provided in the area of the scribe line 64 in the mother substrate 500. Therefore, it is finally disconnected from the circuit and does not have a function as wiring at the stage of the finished product.

  Further, the scribe line 64 is provided with a second contact hole CNT72 for releasing excess static electricity accumulated in the guard wiring 60. Details of the guard wiring 60 and the second contact hole CNT72 will be described later. Hereinafter, a cross-sectional structure of the liquid crystal device 100 will be described.

<Configuration of electro-optical device>
As shown in FIG. 6, a lower light-shielding film 3c made of titanium (Ti), chromium (Cr), or the like is formed on the first base material 10a. The lower light-shielding film 3c is planarly patterned in a lattice shape and defines an opening area of each pixel. The lower light shielding film 3c may function as a part of the scanning line 3a. A base insulating layer 11a made of a silicon oxide film or the like is formed on the first base material 10a and the lower light shielding film 3c.

  On the base insulating layer 11a, the TFT 30, the scanning line 3a, and the like are formed. The TFT 30 has, for example, an LDD (Lightly Doped Drain) structure, and is formed on the semiconductor layer 30a made of polysilicon, the gate insulating film 11g formed on the semiconductor layer 30a, and the gate insulating film 11g. And a gate electrode 30g made of a polysilicon film or the like. As described above, the scanning line 3a also functions as the gate electrode 30g.

  The semiconductor layer 30a is formed as an N-type TFT 30 by implanting N-type impurity ions such as phosphorus (P) ions. Specifically, the semiconductor layer 30a includes a channel region 30c, a data line side LDD region 30s1, a data line side source / drain region 30s, a pixel electrode side LDD region 30d1, and a pixel electrode side source / drain region 30d. ing.

  The channel region 30c is doped with P-type impurity ions such as boron (B) ions. The other regions (30s1, 30s, 30d1, 30d) are doped with N-type impurity ions such as phosphorus (P) ions. Thus, the TFT 30 is formed as an N-type TFT.

  A first interlayer insulating layer 11b made of a silicon oxide film or the like is formed on the gate electrode 30g, the base insulating layer 11a, and the scanning line 3a. In the first interlayer insulating layer 11b, two contact holes CNT41 and CNT42 are provided at positions overlapping the end of the semiconductor layer 30a in plan view.

  Specifically, the contact hole CNT41 and the contact hole CNT42 are filled, and a conductive film is formed using a light-shielding conductive part material such as Al (aluminum) so as to cover the first interlayer insulating layer 11b. By patterning, the contact hole CNT41, the contact hole CNT42, and the relay wiring 51 connected to the pixel electrode side source / drain region 30d through the contact hole CNT42 are formed.

  The relay wiring 51 shields the TFT 30 together with the data line 6a described later. Further, the relay wiring 51 electrically connects a part between the TFT 30 and the pixel electrode 27.

  A second interlayer insulating layer 11c is provided on the relay wiring 51 so as to cover the relay wiring 51 and the first interlayer insulating layer 11b. In the second interlayer insulating layer 11c, a contact hole CNT43 is provided so as to overlap a part of the contact hole CNT41 in a plan view, and further, a contact hole CNT44 is provided so as to overlap a part of the relay wiring 51.

  Specifically, a conductive film is formed using a light-shielding conductive part material such as Al (aluminum) so as to fill the contact holes CNT43 and CNT44 and to cover the second interlayer insulating layer 11c, and is patterned. As a result, the data line 6a, the contact holes CNT43 and CNT44, and the relay wiring 52 are formed.

  The data line 6a is electrically connected to the data line side source / drain region 30s (source region) of the semiconductor layer 30a through the contact holes CNT43 and 41 opened in the second interlayer insulating layer 11c and the first interlayer insulating layer 11b. It is connected to the.

  A third interlayer insulating layer 11d is provided on the data line 6a and the relay wiring 52 so as to cover the data line 6a, the relay wiring 52, and the second interlayer insulating layer 11c. The third interlayer insulating layer 11d is made of, for example, silicon oxide or nitride, and may be subjected to a flattening process for flattening surface irregularities caused by covering the TFT 30 and the like. Examples of the planarization method include chemical mechanical polishing (CMP) and spin coating.

  On the third interlayer insulating layer 11d, a first capacitor electrode 16a constituting the capacitor 16 is provided by patterning. On the first capacitor electrode 16a, a dielectric film 16b constituting the capacitor element 16 is patterned and laminated.

  As the dielectric film 16b, a silicon compound such as a silicon oxide film or a silicon nitride film can be used, and an aluminum oxide film, a titanium oxide film, a tantalum oxide film, a niobium oxide film, a hafnium oxide film, a lanthanum oxide film, zirconium A dielectric layer having a high dielectric constant such as an oxide film can be used.

  On the dielectric film 16b, a second capacitor electrode 16c constituting the capacitor 16 is patterned and laminated. The second capacitor electrode 16c is disposed so as to overlap the first capacitor electrode 16a through the dielectric film 16b, and constitutes the capacitor element 16 together with the first capacitor electrode 16a and the dielectric film 16b.

  Specifically, the pixel electrode side source / drain region 30d (drain region) of the TFT 30 and the first capacitor electrode 16a as a pixel potential side capacitor electrode electrically connected to the pixel electrode 27, and the fixed potential side capacitor electrode as A part of the second capacitor electrode 16c is disposed to face the dielectric film 16b, whereby the capacitor element 16 is formed.

  The first capacitor electrode 16a and the second capacitor electrode 16c are at least one of refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). It may be composed of a single metal, an alloy, a metal silicide, a polysilicide, a laminate of these, or the like, or an Al (aluminum) film.

  Further, the end of the first capacitor electrode 16a overlaps a part of the relay wiring 52 in a plan view, and extends from the extension of the relay wiring 52 via a contact hole CNT45 provided in the third interlayer insulating layer 11d. Electrically connected.

  A fourth interlayer insulating layer 11e as an insulating layer is provided on the second capacitor electrode 16c so as to cover the second capacitor electrode 16c and the third interlayer insulating layer 11d. The fourth interlayer insulating layer 11e is made of, for example, silicon oxide or nitride, and is often subjected to a flattening process for flattening surface irregularities caused by covering wirings, electrodes, and the like.

  A translucent pixel electrode 27 made of an ITO film or the like is provided on the fourth interlayer insulating layer 11e. The pixel electrode 27 is electrically connected to the extending portion of the first capacitor electrode 16a through a contact hole CNT70 provided in the fourth interlayer insulating layer 11e.

  In this manner, the pixel electrode 27 and the first capacitor electrode 16a are connected to the pixel electrode side source / drain region 30d (drain region) of the semiconductor layer 30a via the relay wiring 52, the contact hole CNT44, the relay wiring 51, and the contact hole CNT42. Is electrically connected.

On the pixel electrode 27 and the fourth interlayer insulating layer 11e, an alignment film 28 in which an inorganic material such as silicon oxide (SiO ₂ ) is obliquely deposited is provided (see FIG. 3). On the alignment film 28, a liquid crystal layer 15 in which liquid crystal or the like is sealed in a space surrounded by the sealing material 14 is provided (see FIG. 3).

<Configuration around the guard wiring and the first wiring>
Next, the structure around the guard wiring and the first wiring will be described with reference to FIG. For convenience of explanation, the first base material 10a to the lower layer of the first wiring 61 will be referred to as the first base material 10a.

  On the first base material 10 a of the liquid crystal device 100, the first wiring 61 is provided. The sheet resistance of the first wiring 61 is larger than the sheet resistance of the peripheral wiring (for example, wiring such as the first element side wiring 81 and the second element side wiring 82). The resistance value of the first wiring 61 is, for example, 1 MΩ.

  A first insulating layer 91 is provided on the first wiring 61 and the first base material 10a. On the first insulating layer 91, a guard wiring 60 made of a conductive material such as polysilicon and a first element side wiring 81 are provided. As described above, the guard wiring 60 is routed over the entire mother substrate 500 in order to be electrically connected to the plurality of liquid crystal devices 100 provided on the mother substrate 500. By using the guard wiring 60 in this way, the potential difference between the wiring patterns can be eliminated in the manufacturing process.

  The first element side wiring 81 is provided in the same layer as the scanning line 3a, for example. The scanning line 3a is not limited, and the scanning line 3a may be provided in the same layer as the light shielding film 3c. A second insulating layer 92 is provided on the guard wiring 60 and the first element side wiring 81.

  On the second insulating layer 92, two contact holes CNT73 and CNT74 are provided at positions overlapping the guard wiring 60 in plan view. The second insulating layer 92 is provided with a contact hole CNT77 at a position overlapping the first element side wiring 81 in plan view. Further, two contact holes CNTs 75 and 76 are provided at positions overlapping the first wiring 61 in plan view so as to penetrate the first insulating layer 91 and the second insulating layer 92.

  On the second insulating layer 92, the contact holes CNT 73, 74, 75, 76, 77 are filled using a conductive material such as aluminum, and the second wiring 62, the third wiring 63, and the second element side wiring 82 are formed. Pattern.

  A third insulating layer 93 is provided on the second wiring 62, the third wiring 63, the second element side wiring 82, and the second insulating layer 92. The third insulating layer 93 is provided with a first contact hole CNT71 at a position overlapping the second element side wiring 82 in plan view. The third insulating layer 93 is provided with a second contact hole CNT72 at a position overlapping the second wiring 62 in plan view.

  Thus, the first contact hole CNT71 is connected to the first wiring 61 via the second element side wiring 82 and the contact hole CNT76. The second contact hole CNT72 is connected to the first wiring 61 through the second wiring 62, the contact hole CNT73, the guard wiring 60, the contact hole CNT74, the third wiring 63, and the contact hole CNT75.

  That is, when excessive static electricity is accumulated in the guard wiring 60 having a large wiring area, the second contact hole CNT72 is opened in the same process as the first contact hole CNT71, so that the excessive static electricity is discharged to the second contact hole CNT72. Can escape from the side. Therefore, it is possible to prevent excessive static electricity from flowing to the first wiring 61 as in the case where the second contact hole CNT72 cannot be opened, and it is possible to prevent the first wiring 61 from being electrostatically broken.

  On the third insulating layer 93, a conductive material such as aluminum is used to fill the first contact hole CNT71 and the second contact hole CNT72, and an upper wiring 75 is formed on the first contact hole CNT71 by patterning.

<Method of manufacturing electro-optical device>
FIG. 8 and FIG. 9 are schematic cross-sectional views showing a manufacturing method around the guard wiring and the first wiring in the manufacturing method of the liquid crystal device as the electro-optical device. Hereinafter, a method of manufacturing the liquid crystal device will be described with reference to FIGS.

  First, in the steps shown in FIG. 8A (first wiring forming step, first insulating layer forming step, guard wiring forming step), a well-known film forming technique is formed on the first base material 10a made of a glass substrate or the like. The first wiring 61 is formed using a photolithography technique and an etching technique. The resistance value of the first wiring 61 is, for example, 1 MΩ. Next, a first insulating layer 91 made of a silicon oxide film or the like is formed on the first wiring 61 and the first base material 10a. As a manufacturing method of the first insulating layer 91, for example, a CVD method (Chemical Vapor Deposition) is used.

  Thereafter, the guard wiring 60 and the first element side wiring 81 are formed on the first insulating layer 91. Specifically, the guard wiring 60 and the first element side wiring 81 made of polysilicon or the like are formed using a well-known film forming technique, a photography technique, and an etching technique.

  In the step shown in FIG. 8B (second insulating layer forming step, second wiring forming step), the contact holes CNT73, 74, 75, 76, 77, the second wiring 62, the third wiring 63, and the second element Side wiring 82 is formed. Specifically, first, a second insulating layer 92 made of a silicon oxide film or the like is formed so as to cover the guard wiring 60, the first element side wiring 81, and the first insulating layer 91.

  Thereafter, contact holes CNT 73 to 77 are formed in the second insulating layer 92. Then, the second wiring 62 electrically connected to the contact hole CNT73, the third wiring 63 electrically connected to the contact holes CNT74 and 75, and further electrically connected to the contact holes CNT76 and 77. The second element side wiring 82 is formed on the second insulating layer 92.

  In the step shown in FIG. 9C (third insulating layer forming step, connecting step), the first contact hole CNT71 and the second contact hole CNT72 are formed. Specifically, first, a third insulating layer 93 made of a silicon oxide film or the like is formed so as to cover the second wiring 62, the third wiring 63, the second element side wiring 82, and the second insulating layer 92. . Next, the first contact hole CNT 71 connected to the second element side wiring 82 and the second contact hole CNT 72 connected to the second wiring 62 are formed in the third insulating layer 93.

  Thus, the first contact hole CNT71 is connected to the first wiring 61 via the second element side wiring 82 and the contact hole CNT76. The second contact hole CNT72 is connected to the first wiring 61 through the second wiring 62, the contact hole CNT73, the guard wiring 60, the contact hole CNT74, the third wiring 63, and the contact hole CNT75.

  That is, in the manufacturing process, when excessive static electricity is accumulated in the guard wiring 60 having a large wiring area, the second static contact hole CNT 72 is opened in the same process as the first contact hole CNT 71, thereby generating excessive second static electricity. It can escape from the contact hole CNT72 side. Therefore, it is possible to prevent excessive static electricity from flowing to the first wiring 61 as in the case where the second contact hole CNT72 cannot be opened, and it is possible to prevent the first wiring 61 from being electrostatically broken.

  In the step shown in FIG. 9D, the upper layer wiring 75 is formed on the third insulating layer 93. Specifically, first, a conductive material such as aluminum is formed on the third insulating layer 93 and embedded in the first contact hole CNT71 and the second contact hole CNT72, and the upper layer wiring 75 is formed on the first contact hole CNT71. It is formed by patterning. In the subsequent scribe / break process, the first wiring 61 is divided and the liquid crystal device 100 is separated from the guard wiring 60.

<Configuration of electronic equipment>
Next, a projection display device as an electronic apparatus according to the present embodiment will be described with reference to FIG. FIG. 10 is a schematic diagram showing a configuration of a projection display device including the above-described liquid crystal device.

  As shown in FIG. 10, the projection display apparatus 1000 of the present embodiment includes a polarization illumination apparatus 1100 arranged along the system optical axis L, two dichroic mirrors 1104 and 1105 as light separation elements, and three Reflective mirrors 1106, 1107, 1108, five relay lenses 1201, 1202, 1203, 1204, 1205, three transmissive liquid crystal light valves 1210, 1220, 1230 as light modulation means, and a cross dichroic as a light combiner A prism 1206 and a projection lens 1207 are provided.

  The polarized light illumination device 1100 is generally configured by a lamp unit 1101 as a light source composed of a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 1102, and a polarization conversion element 1103.

  The dichroic mirror 1104 reflects red light (R) and transmits green light (G) and blue light (B) among the polarized light beams emitted from the polarization illumination device 1100. Another dichroic mirror 1105 reflects the green light (G) transmitted through the dichroic mirror 1104 and transmits the blue light (B).

  The red light (R) reflected by the dichroic mirror 1104 is reflected by the reflection mirror 1106 and then enters the liquid crystal light valve 1210 via the relay lens 1205. Green light (G) reflected by the dichroic mirror 1105 enters the liquid crystal light valve 1220 via the relay lens 1204. The blue light (B) transmitted through the dichroic mirror 1105 enters the liquid crystal light valve 1230 via a light guide system including three relay lenses 1201, 1202, 1203 and two reflection mirrors 1107, 1108.

  The liquid crystal light valves 1210, 1220, and 1230 are disposed to face the incident surfaces of the cross dichroic prism 1206 for each color light. The color light incident on the liquid crystal light valves 1210, 1220, and 1230 is modulated based on video information (video signal) and emitted toward the cross dichroic prism 1206.

  In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. The three color lights are synthesized by these dielectric multilayer films, and the light representing the color image is synthesized. The synthesized light is projected on the screen 1300 by the projection lens 1207 which is a projection optical system, and the image is enlarged and displayed.

  The liquid crystal light valve 1210 is the one to which the liquid crystal device 100 described above is applied. The liquid crystal device 100 is arranged with a gap between a pair of polarizing elements arranged in crossed Nicols on the incident side and the emission side of colored light. The same applies to the other liquid crystal light valves 1220 and 1230.

  According to such a projection type display apparatus 1000, the liquid crystal light valve 1210, 1220, 1230 uses the liquid crystal apparatus 100 in which image sticking or the like is suppressed, so that high display quality can be realized.

  The electronic device on which the liquid crystal device 100 is mounted includes a projection display device 1000, a head-up display, a smartphone, an EVF (Electrical View Finder), a mobile mini projector, a mobile phone, a mobile computer, a digital camera, and a digital video. It can be used for various electronic devices such as cameras, displays, in-vehicle devices, audio devices, exposure devices, and lighting devices.

  As described above in detail, according to the liquid crystal device 100, the method for manufacturing the liquid crystal device 100, and the electronic apparatus of the present embodiment, the following effects can be obtained.

  (1) According to the liquid crystal device 100 of the present embodiment, the second contact connected to the first contact hole CNT71 connected to the second element side wiring 82 on the TFT 30 side and the second wiring 62 on the guard wiring 60 side. Since the holes CNT72 are opened in the third insulating layer 93, the static electricity accumulated in the liquid crystal device 100 including the second element side wiring 82 and the like is released from the first contact holes CNT71, and the static electricity accumulated in the guard wiring 60 is second. It is possible to escape from the contact hole CNT72. In other words, by separately providing the second contact hole CNT72 separately from the first contact hole CNT71, for example, excessive static electricity accumulated in the guard wiring 60 having a large wiring area is concentrated on the first wiring 61. Thus, the first wiring 61 can be prevented from electrostatic breakdown. This can prevent the liquid crystal device 100 from being affected. In addition, by disposing the second contact hole CNT72 at a position away from the first wiring 61 via the third wiring 63, the second wiring 62 can be widely provided, and the second contact hole CNT72 is surely provided. Can be provided.

  (2) According to the liquid crystal device 100 of the present embodiment, when a plurality of liquid crystal devices 100 are connected by the guard wiring 60 and excessive static electricity is accumulated in the guard wiring 60 (when having a large parasitic capacitance). However, static electricity can be released from the second contact hole CNT72 without passing through the first wiring 61. Further, since the sheet resistance of the first wiring 61 is larger than the sheet resistance of the other wiring, it is possible to suppress static electricity from flowing from the guard wiring 60 side to the TFT 30 side.

  (3) According to the method for manufacturing the liquid crystal device 100 of the present embodiment, the first contact hole CNT 71 on the TFT 30 side and the second contact hole CNT 72 on the guard wiring 60 side are formed in the third insulating layer 93 at the same time. Static electricity accumulated on the liquid crystal device 100 side including the second element side wiring 82 and the like can be released from the first contact hole CNT71, and static electricity accumulated in the guard wiring 60 can be released from the second contact hole CNT72. Therefore, it is possible to prevent the first wiring 61 from being electrostatically broken.

  (4) According to the electronic apparatus of this embodiment, the liquid crystal device 100 side including the second element side wiring 82 can be protected from excessive static electricity, and a highly reliable electronic apparatus can be provided.

  The aspect of the present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification. It is included in the range. Moreover, it can also implement with the following forms.

(Modification 1)
As described above, the structure in the vicinity of the first wiring 61 of the liquid crystal device 100 is not limited to the structure as illustrated in FIG. 7, and may be a structure as illustrated in FIGS. 11 and 12, for example. FIG. 11 and FIG. 12 are schematic cross-sectional views showing the structure of liquid crystal devices 101 and 102 according to modified examples.

  The liquid crystal device 101 shown in FIG. 11 is connected to the guard wiring 60 and the first wiring 61 not directly via the third wiring 63 but directly via the second wiring 62. Is different. The second wiring 62 is connected to a contact hole CNT 72 provided in the third insulating layer 93.

  According to this, although the second contact hole CNT72 for releasing static electricity is provided in the vicinity of the first wiring 61 in plan view, excessive static electricity accumulated in the guard wiring 60 can be released from the contact hole CNT72. . Therefore, it is possible to prevent the first wiring 61 from being electrostatically damaged.

  The liquid crystal device 102 shown in FIG. 12 is different from the liquid crystal device 101 of the above modification in that an island-shaped second upper layer wiring 76 is provided on the second contact hole CNT72. According to this, when the second upper layer wiring 76 connected to the second contact hole CNT72 is formed, the second wiring 62 can be prevented from being excessively etched (damaged). That is, the guard wiring 60 and the first wiring 61 can be prevented from being divided.

  Further, the layers where the pixel electrodes 27 are formed may be connected using contact holes and wirings so as to be electrically connected to the second upper layer wiring 76. According to this, in the wiring formation process after the contact hole CNT72 (second upper layer wiring 76), the risk of occurrence of electrostatic breakdown can be reduced as described above.

(Modification 2)
As described above, the present invention is not limited to the transmissive liquid crystal device 100. For example, the present invention may be applied to a reflective liquid crystal device.

(Modification 3)
As described above, the liquid crystal device 100 is not limited to the electro-optical device, and may be applied to, for example, an organic EL device, a plasma display, electronic paper, and the like.

  3a ... scanning line, 3b ... capacitance line, 3c ... lower light shielding film, 6a ... data line, 10 ... element substrate, 10a ... first substrate, 11a ... underlying insulating layer, 11b ... first interlayer insulating layer, 11c ... 2nd interlayer insulation layer, 11d ... 3rd interlayer insulation layer, 11e ... 4th interlayer insulation layer, 11g ... Gate insulation film, 14 ... Sealing material, 15 ... Liquid crystal layer, 16 ... Capacitance element, 16a ... 1st capacitance electrode, 16b: Dielectric film, 16c: Second capacitor electrode, 18: Light shielding film, 20: Counter substrate, 20a: Second substrate, 22: Data line driving circuit, 24 ... Scanning line driving circuit, 25 ... Inspection circuit, 26 ... vertical conduction part, 27 ... pixel electrode, 28, 32 ... alignment film, 29 ... wiring, 30 ... TFT, 30a ... semiconductor layer, 30c ... channel region, 30d ... pixel electrode side source / drain region (drain region), 30d1 ... Pixel electrode side LDD region, 30 g... 30 s... Data line side source / drain region (source region), 30 s 1... Data line side LDD region, 31... Counter electrode, 33 ... planarization layer, CNT 41, 42, 43, 44, 45. 52 ... Relay wiring, 60 ... Guard wiring, 61 ... First wiring, 62 ... Second wiring, 63 ... Third wiring, 64 ... Scribe line, 65 ... External connection terminal, CNT71 ... First contact hole, CNT72 ... Second contact hole, CNT 70, 73, 74, 75, 76, 77 ... contact hole, 75 ... upper layer wiring, 76 ... second upper layer wiring, 81 ... first element side wiring, 82 ... second element side wiring, 91 ... 1st insulating layer, 92 ... 2nd insulating layer, 93 ... 3rd insulating layer, 100, 101, 102 ... Liquid crystal device, 500 ... Mother board, 1000 ... Projection type display device, 1100 Polarized illumination device, 1101 ... lamp unit, 1102 ... integrator lens, 1103 ... polarization conversion element, 1104, 1105 ... dichroic mirror, 1106, 1107, 1108 ... reflection mirror, 1201, 1202, 1203, 1204, 1205 ... relay lens, 1206 ... cross dichroic prism, 1207 ... projection lens, 1210, 1220, 1230 ... liquid crystal light valve, 1300 ... screen.

Claims (9)

A first substrate;
A first wiring disposed on the first substrate;
A first insulating layer disposed on the first wiring;
A guard wiring and a first element side wiring disposed on the first insulating layer;
A second insulating layer disposed on the guard wiring and the first element side wiring;
A second wiring and a second element side wiring disposed on the second insulating layer;
A third insulating layer disposed on the second wiring and the second element side wiring;
An upper layer wiring disposed on the third insulating layer;
Including
The guard wiring and the first wiring are electrically connected via the second wiring,
The first element side wiring and the first wiring are electrically connected via the second element side wiring,
In order to connect the second element side wiring and the upper layer wiring, a first contact hole is disposed so as to penetrate the third insulating layer,
An electro-optical device, wherein a second contact hole is disposed so as to penetrate the third insulating layer so as to overlap the second wiring in a plan view. A first substrate;
A first wiring disposed on the first substrate;
A first insulating layer disposed on the first wiring;
A guard wiring and a first element side wiring disposed on the first insulating layer;
A second insulating layer disposed on the guard wiring and the first element side wiring;
A second wiring, a third wiring, and a second element side wiring disposed on the second insulating layer;
A third insulating layer disposed on the second wiring, the third wiring, and the second element side wiring;
An upper layer wiring disposed on the third insulating layer;
Including
The second wiring and the first wiring are electrically connected via the guard wiring and the third wiring,
The first element side wiring and the first wiring are electrically connected via the second element side wiring,
In order to connect the second element side wiring and the upper layer wiring, a first contact hole is disposed so as to penetrate the third insulating layer,
An electro-optical device, wherein a second contact hole is disposed so as to penetrate the third insulating layer so as to overlap the second wiring in a plan view. The electro-optical device according to claim 1 or 2,
2. The electro-optical device according to claim 1, wherein a sheet resistance of the first wiring is larger than a sheet resistance of the first element side wiring, the second element side wiring, the second wiring, and the upper layer wiring. An electro-optical device according to any one of claims 1 to 3,
An electro-optical device, wherein a second upper layer wiring is provided on the second contact hole. The electro-optical device according to any one of claims 1 to 4,
The electro-optical device, wherein the guard wiring is provided between adjacent electro-optical devices. A first wiring forming step of forming a first wiring on the first substrate;
A first insulating layer forming step of forming a first insulating layer on the first wiring and the first substrate;
A guard wiring forming step of forming a guard wiring and a first element side wiring on the first insulating layer;
A second insulating layer forming step of forming a second insulating layer on the guard wiring, the first element side wiring, and the first insulating layer;
A second wiring formation step of forming a second wiring and a second element side wiring on the second insulating layer;
Contact holes in the guard wiring, the first wiring, and the second wiring overlapping in a plan view, and in the region overlapping the first wiring, the first element side wiring, and the second element side wiring in a plan view. And electrically connecting the guard wiring, the second wiring, and the first wiring, and electrically connecting the first wiring, the second element side wiring, and the first element side wiring. Connection process;
A third insulating layer forming step of forming a third insulating layer on the second wiring, the second element side wiring, and the second insulating layer;
In the third insulating layer, a first contact hole is formed in a region overlapping with the second element side wiring in a plan view, and a second contact hole is formed in a region overlapping with the second wiring in a plan view. Process,
A method for manufacturing an electro-optical device. A first wiring forming step of forming a first wiring on the first substrate;
A first insulating layer forming step of forming a first insulating layer on the first wiring and the first substrate;
A guard wiring forming step of forming a guard wiring and a first element side wiring on the first insulating layer;
A second insulating layer forming step of forming a second insulating layer on the guard wiring, the first element side wiring, and the first insulating layer;
Forming a second wiring, a third wiring, and a second element side wiring on the second insulating layer;
Forming a contact hole in a region overlapping the second wiring and the third wiring and the guard wiring in a plan view;
Forming a contact hole in a region overlapping the third wiring and the first wiring in plan view;
Forming a contact hole in a region overlapping the second element side wiring, the first wiring, and the first element side wiring in a plan view;
The second wiring, the guard wiring, the third wiring, and the first wiring are electrically connected, and the first wiring, the second element side wiring, and the first element side wiring are electrically connected. A connecting step,
A third insulating layer forming step of forming a third insulating layer on the second wiring, the third wiring, the second element side wiring, and the second insulating layer;
In the third insulating layer, a first contact hole is formed in a region overlapping with the second element side wiring in a plan view, and a second contact hole is formed in a region overlapping with the second wiring in a plan view. Process,
A method for manufacturing an electro-optical device. A method of manufacturing the electro-optical device according to claim 6 or 7,
After the contact hole forming step, there is an upper layer wiring forming step of forming an upper layer wiring on the first contact hole and forming a second upper layer wiring on the second contact hole. Manufacturing method of optical device.   An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 5.

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