JP2003163194A - Polishing method and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide technology for reducing unevenness of polishing speed due to the density of a pattern causing protrusions and recesses when a film having multilayer structure is planarized by polishing the protrusions and recesses. <P>SOLUTION: Unevenness of polishing speed is reduced by providing openings positively in the surface of a film having a high pattern density being polished for planarization thus forming a planarized film having high in-plane uniformity regardless of the pattern density and the dimensions. A semiconductor device having a high degree of integration can be obtained using a uniform planarized film thus formed. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, for example, an electro-optical device represented by a liquid crystal display device or an EL display device, and a method for manufacturing an electronic device having such an electro-optical device mounted as a component. . In particular, it relates to a technique for flattening an insulating film on an element and wiring in a semiconductor device having a multilayer wiring structure. Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor integrated circuits, and electronic devices are also semiconductor devices.

[0002]

2. Description of the Related Art In semiconductor devices, miniaturization and multilayer wiring technology are indispensable for increasing the degree of integration, but considering the suppression of increase in wiring resistance, it is a case where the width of wiring is reduced. However, since it is not possible to reduce the thickness of the wiring, the level difference of the underlying layer that occurs in the insulating film formed on the wiring becomes larger as the miniaturization progresses. Such deterioration of the flatness of the insulating film makes it difficult to process the wiring after forming the through holes in the insulating film. Specifically, in the photolithography process, it becomes difficult to uniformly focus on the top and bottom of the step. Further, in the etching process, since the film thickness to be etched at the time of opening the through hole is locally different, it is difficult to surely open the hole, and an etching residue is likely to occur in a step during the wiring etching.

Therefore, in order to solve the above problems, in the prior art, the surface of the insulating film is chemically and mechanically polished with a polishing agent and a polishing pad to form a CMP (Chemical Mechanical).
calPolishing) technology is used. Other than the CMP technique, mechanical polishing, ELID, and the like are included, which are suitable for obtaining a film having excellent flatness.

For example, when the CMP technique is used for flattening an interlayer insulating film of a multi-layer wiring, after forming an element such as a transistor and a wiring, an insulating film covering the wiring is formed by a CVD method. At this time, the insulating film formed by the CVD method is
Since the film is formed so as to follow the shape of the wiring, irregularities reflecting the dimensions and density of the wiring pattern are formed on the surface thereof. Since such irregularities cause the above-mentioned processing problems, the surface of the insulating film is polished and flattened by a CMP apparatus.

However, in the conventional polishing method, the polishing rate changes depending on the uneven shape of the film to be polished, and the polishing rate locally varies depending on the size and density of the underlying wiring pattern. For this reason, the step cannot be completely eliminated, and there arises a problem that the remaining film thickness of the insulating film becomes nonuniform on the substrate surface.

Due to such a process having insufficient flattening ability, when forming through holes in the insulating film and forming wiring on the insulating film, the above-mentioned processing problems cannot be solved. Become.

In the conventional flattening method by polishing the surface of the insulating film, a portion having a high wiring density (for example, TF for a liquid crystal display device) is used.
In the driving circuit portion of the T panel, the polishing rate of the insulating film is slowed, and the wiring density is low (TF for liquid crystal display device).
In the pixel portion in the T panel), the polishing rate of the insulating film is increased, and thus the polishing rate becomes non-uniform in the substrate surface due to the influence of the density of the wiring.

Therefore, as a whole, a difference in film thickness of the insulating film occurs, and a dent is formed in a portion (pixel portion) where the wiring density is low. The graph of FIG. 6 is obtained by measuring the film thickness of the insulating film on the wiring pattern after polishing the insulating film formed on the substrate having the drive circuit portion and the pixel portion as shown in FIG. 17 by the CMP apparatus. Is.

It is apparent from FIG. 6 that the polishing states of the drive circuit section and the pixel section are different. Further, depending on the in-plane undulation of the substrate and the characteristics of the apparatus, even when patterns having the same underlying step are compared with each other, the polishing rate may become non-uniform within the substrate surface.

In order to improve this problem, as shown in FIG. 5, the dummy wiring 15 is formed in a portion of the semiconductor substrate having a low wiring density.
There is a method of arranging 0 to make the wiring density uniform and then polishing the insulating film.

However, such a method has a problem that not only the degree of freedom of wiring arrangement is lost due to the restriction on the area where the dummy wiring is arranged, but also the parasitic capacitance and the wiring capacitance due to the dummy wiring are increased. Further, in the case of a transmissive liquid crystal display device, as shown in FIG. 17, a portion having a high wiring density is a source side driving circuit 1701 and a gate side driving circuit 1702.
A driving circuit portion 1706 including a region in which a number of wirings 1705 electrically connecting to the pixel portion 1703 are provided,
Since the portion where the wiring density is low becomes the pixel portion 1703, the position where the dummy wiring is provided becomes the pixel portion, and there is a problem that the aperture ratio decreases.

[Problems to be Solved by the Invention]

The present invention is intended to solve the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device which does not depend on the density and size of a pattern which causes a step difference in an underlying layer during planarization by polishing. And

[0013]

SUMMARY OF THE INVENTION The present invention provides a method for suppressing a difference in film thickness of an insulating film depending on the size and density of a step difference in an underlying layer which causes unevenness in the insulating film when the insulating film is flattened. To do.

First, CM which is a typical device for polishing
The P device will be described. As shown in FIG. 16, a polishing cloth (also referred to as a pad) 16 is provided on a circular rotary platen 1621.
22 is attached. As a material used for the polishing cloth 1622, urethane foam or the like is used. Also, the rotating surface plate 1
621 rotates with its center as a rotation shaft 1625.

The object 1627 to be polished has a circular metal-made polishing head 162 with the surface to be polished facing the rotary platen 1621.
6 is vacuum-adsorbed. Workpiece 1627 and polishing head 1
A wafer suction pad 1628 is provided between the wafer 626 and 626. Wafer suction pad 1628 and polishing head 16
There is a hole in the glass substrate 26 and the glass substrate 16 through the hole.
27 is attracted to the polishing head 1626. Polishing head 16
The center of 26 is the center of the rotary platen 1621 and the center of the rotary platen 1621.
It is located between the circumference of 21.

During polishing, the slurry 1624 is supplied to the center of the rotary platen 1621 through the pipe 1623, and the slurry 1624 spreads over the entire surface of the polishing cloth 1622 on the rotary platen 1621 by the rotation and swing of the rotary platen 1621.
Slurry 1624 is a colloidal solution in which particles are mixed with liquids and chemicals. As the slurry 1624,
Silica-based slurry of pH 9 to 11 made of KOH,
pH = 3 to 4 of alumina (Al ₂ O ₃₎ based slurry or manganese oxide _{(MnO 2, Mn 2 O 3} ), based slurry can be used for. The alumina-based slurry can be used by mixing a chemical having an oxidizing power.
Besides, it is also possible to use a neutral slurry or the like. It should be noted that the neutral slurry referred to here includes a slurry formed of silica and water. Further, a surfactant can be added if necessary.

A pressure is applied to the polishing head 1626 to move an object to be polished 1627 to a polishing cloth 1622 on a rotating surface plate 1621.
Press on. When the pressure of the polishing head 1626 is changed,
The polishing rate of the film to be polished can be adjusted.

It should be noted that the slurry, the apparatus, etc. used in the CMP technique described here are only preferable examples, and other known ones can be used, and also known methods can be used for the processing conditions and the like. You can

According to the present invention, an opening is formed in an insulating film to be polished for the purpose of making the polishing rate of the insulating film, which becomes uneven depending on the size, shape, density, etc. of the underlying pattern which causes a step difference, uniform. It is characterized by forming. for that reason,
In addition to the CMP technique described as the method for polishing an insulating film, mechanical polishing, ELID, or other means may be employed to obtain an insulating film having uniform flatness by applying the present invention.

Further, in the present specification, an interlayer insulating film of a semiconductor device having a multi-layer wiring structure will be described. However, even if such an interlayer insulating film is used, it is affected by the size of the pattern and the density of arrangement which cause a step difference in the underlying layer. Needless to say, the effect of the present invention can be obtained even if it is not an insulating film as long as it is a film that is uniformly flattened.

Considering a case where one layer of a pattern made of a conductive film, a semiconductor film, an insulating film or the like causes a step in the interlayer film, the pattern causing the step is peculiar to an LSI formed on a Si wafer. The element isolation film (LO
COS), the ones peculiar to the TFT panel are the lower light-shielding film,
The active layer, which is common to both, is a gate wiring, a wiring for connecting elements, and a wiring for connecting wirings. Further, when an element formed of a plurality of layers causes a step in the interlayer film, considering the influence on the element performance, the capacitive element and the transistor cannot be flattened until the structure is completed. It causes a big step. The present invention is effective for flattening the film on the stepped underlayer.

The openings referred to in the present specification include grooves, recesses, holes, and holes, and the top surface of the openings has linear, lattice, or circular periodic structures as shown in FIG. A pattern that leaves only is conceivable. Size, arrangement, number of openings, etc. (eg width, pitch of openings in linear openings, etc.)
Is the material of the object to be polished, the purpose of polishing, the characteristics of the CMP apparatus,
It is appropriately set according to the polishing conditions and the like. The depth of the opening is preferably such that it does not penetrate the insulating film in which the opening is provided and does not reach the wiring that causes a step, but it may penetrate the insulating film in which the opening is provided. When setting the depth that penetrates the insulating film in which the opening is provided, the wiring that causes the step is made of a material that does not react with the polishing material, or the wiring that causes the step in the insulating film that provides the opening is formed. An interlayer insulating film that does not react with the polishing agent may be formed therebetween.

[0023]

(Embodiment 1) One embodiment of the present invention will be described with reference to FIGS. 1 to 3. The feature of the present embodiment is that an opening is formed in the interlayer insulating film covering the underlying step as a pretreatment for polishing. The opening can be formed by the commonly used patterning and etching. The shape is not particularly limited, and may be linear, lattice-shaped, circular, rectangular, or any other shape. In this embodiment mode, a linear opening is formed.

FIG. 1 shows a sectional view. In FIG. 1, 10
Reference numeral 1 is a substrate having an insulating surface. For example, a substrate formed of glass, quartz, stainless steel, metal, ceramics, or silicon and provided with a silicon oxide film on the surface thereof can be used. First, the silicon oxide film 1 is formed on the substrate 101.
A base film of No. 02 is formed to a thickness of 10 to 200 nm.
The base film may be formed by stacking a silicon nitride film or may be only a silicon nitride film. The film formation method is plasma CVD
Method, thermal CVD method, or sputtering method may be used.

Next, a thickness of 25 to 80 n is formed on the base film 102.
A semiconductor film of m is formed by a plasma CVD method, a thermal CVD method or a sputtering method. After that, a crystalline semiconductor film is formed using a crystallization technique using nickel as a metal element for promoting crystallization of silicon in the semiconductor film. Although the material of the crystalline semiconductor film is not limited, it is preferably formed of silicon, a silicon germanium (SiGe) alloy, or the like. Although a crystallization technique using nickel as a metal element that promotes crystallization of silicon is used here, other known crystallization techniques such as a solid phase growth method and a laser crystallization method may be used.

In the case of the above laser crystallization method, a continuous wave or pulsed gas laser or solid laser is used as the laser. Gas lasers include excimer lasers, Ar lasers, Kr lasers, etc., and solid-state lasers include YAG lasers, YVO ₄ lasers, YLF lasers, YAlO ₃ lasers, glass lasers, ruby lasers, Alexandride lasers,
Ti: sapphire laser etc. are mentioned.

As the solid-state laser, Cr, Nd, E
A laser using crystals of YAG, YVO ₄ , YLF, YAlO ₃ or the like doped with r, Ho, Ce, Co, Ti or Tm is applied. The fundamental wave of the laser differs depending on the material to be doped, and laser light having a fundamental wave of about 1 μm can be obtained. The harmonic wave with respect to the fundamental wave can be obtained by using a non-linear optical element.

In order to obtain crystals with a large grain size when crystallizing the amorphous semiconductor film, a solid-state laser capable of continuous oscillation is used, and the second to fourth harmonics of the fundamental wave are applied. Preferably. Typically, the second harmonic (532 nm) of the Nd: YVO ₄ laser (fundamental wave 1064 nm) or the third harmonic
Apply harmonics (355 nm).

Laser light emitted from a continuous oscillation YVO ₄ laser having an output of 10 W is converted into a harmonic by a non-linear optical element. There is also a method in which a YVO ₄ crystal and a non-linear optical element are put in a resonator to emit a higher harmonic wave. Then, it is preferably shaped into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and the object to be processed is irradiated.
The energy density at this time is 0.01 to 100 MW / c
m ² (preferably 0.1 to 10 MW / cm ² ) is required. Then, the semiconductor film may be moved relative to the laser light at a speed of about 10 to 2000 cm / s for irradiation.

After that, the crystalline semiconductor film is patterned to form island-shaped semiconductor layers (also referred to as active layers of thin film transistors) 104 and 105 of the thin film transistor. Note that RTA may be performed after the formation of the crystalline semiconductor film to enhance crystallinity. In addition, the island-shaped semiconductor layers 104 and 105
It may be performed after the formation of. A publicly known technique may be used for the RTA process, and thus description thereof will be omitted.

Next, a gate insulating film 106 that covers the island-shaped semiconductor layers 104 and 105 is formed. Gate insulating film 106
Is a plasma CVD method or a sputtering method, and the thickness is 4
It is formed of an insulating film containing silicon with a thickness of 0 to 150 nm. Of course, the gate insulating film is not limited to such an insulating film, and another insulating film containing silicon may be used as a single layer or a laminated layer. For example, when a silicon oxide film is used, TEOS (Tetraeth
yl Orthosilicate) and O ₂ are mixed, reaction pressure is 40 Pa,
Substrate temperature is 300-400 ℃, high frequency (13.56MH)
z), and can be formed by discharging at a power density of 0.5 to 0.8 W / cm ² . The silicon oxide film produced in this way can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Then, a conductive film for forming a gate electrode is formed on the gate insulating film 106 to have a thickness of 100 to 400 nm. In this embodiment mode, a conductive film of Ta is formed by a sputtering method and a target of Ta is formed by sputtering with Ar. In this case, appropriate amount of Xe or Kr for Ar
The addition of the element can alleviate the internal stress of the Ta film and prevent the film from peeling. The resistivity of the α-phase Ta film is 2
Although it is about 0 μΩcm and can be used as a gate electrode, the β-phase Ta film has a resistivity of about 180 μΩcm and is not suitable for a gate electrode. To form an α-phase Ta film, an α-phase Ta film can be easily obtained by forming tantalum nitride having a crystal structure similar to that of Ta to a thickness of 10 to 50 nm on a Ta underlayer. Can be done.

Although the conductive film is made of Ta in the present embodiment, it is not particularly limited, and Ta, W, Ti, Mo and A are used.
It may be formed of an element selected from l, Cu, or the like, or an alloy material or a compound material containing the above element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. The conductive film may have a laminated structure, or the lower conductive film may be tapered.

Next, a mask made of resist is formed, and an etching process for forming the gate electrodes is performed to form the gate electrodes 111 and 112.

Then, an impurity region is formed in the island-shaped semiconductor layer. In FIG. 1B, 107 and 108 are N-channel type Ts.
It becomes a source region or a drain region of FT, and an impurity imparting N-type is added. In addition, 109 in FIG.
Becomes a source region or a drain region of a P-channel TFT, and an impurity imparting P-type is added.

As a method of adding impurities, there are an ion doping method, an ion implantation method, and the like. In this embodiment, the ion doping method is used. As the impurity imparting N-type, an element belonging to Group 15 is used, typically phosphorus (P) or arsenic (As). In the present embodiment, P is 1 × 10 ²⁰ to 1 × 10 ^21.
Add in the concentration range of atoms / cm ⁻³ . In this embodiment, B is used as an impurity imparting P-type conductivity, and 2 × 1
It is added in a concentration range of 0 ^{20 to} 2 × 10 ²¹ atoms / cm ^-3 .

Further, in this embodiment, as a pretreatment for adding an impurity, a mask is formed which forms a resist pattern having an opening only in the region to which the impurity is added and prevents the impurity from being added to a region other than the designated region. And When adding impurities,
In addition to the resist mask, the gate electrodes 111 and 112 can be used as a mask to form the source region or the drain region in a self-aligned manner. The resist pattern used as a mask is peeled off after adding impurities. An LDD (Lightly Doped Drain) region can be provided between the channel formation region and the source region or the drain region as needed, but the LDD region is not provided in this embodiment.

After the impurities are added, a step of activating the impurity elements added to the respective island-shaped semiconductor layers is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. Besides, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. However, when the wiring material used for the conductive layer is weak to heat, it is preferable to perform activation after forming an interlayer insulating film (having silicon as a main component) in order to protect the wiring and the like.

Further, a step of hydrogenating the island-shaped semiconductor layer is performed by performing heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. This step is a step of terminating the dangling bond of the semiconductor layer by thermally excited hydrogen. As another means of hydrogenation,
Plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, as shown in FIG. 1C, a first interlayer insulating film 125 made of a silicon oxynitride film is formed by plasma CVD to a thickness of 200 to 500 nm.
SiH ₄ , N ₂ O, NH ₃ and H ₂ are used as source gases,
The substrate side (sample stage) also has 100 W RF (13.5
Power (6 MHz) and apply a substantially negative self-bias voltage. As a film forming method, a low pressure CVD method, a thermal CVD method or a sputtering method may be used.

After that, a mask for forming a contact hole for establishing electrical connection between the wiring and the active layer is formed on the first interlayer insulating film, and the first interlayer insulating film is etched. Then, a conductive film for forming wiring is formed. The conductive film at this time is a Ti film continuously formed by a sputtering method,
It has a laminated structure of a TiN film, an Al film and a W film.

The conductive film is a Ti film, a TiN film, an Al film and W.
Although it has a laminated structure with a film, it is not particularly limited, and Ta, W,
An element selected from Ti, Al, Mo, Cr, Cu, etc.,
Alternatively, an alloy material or a compound material containing the above element as a main component may be used, or a single layer structure may be used.

Next, a mask made of resist is formed and an etching process for forming wiring is performed. A wiring 119 made of a Ti film, a TiN film, an Al film and a W film is formed by etching.

Then, a second layer formed of a silicon oxynitride film
The interlayer insulating film of 400 to 100 by plasma CVD method.
It is formed with a thickness of 0 nm. The film forming method is a low pressure CVD method,
A thermal CVD method or a sputtering method may be used. SiH ₄ , N ₂ O, NH ₃ and H ₂ were used as source gases, and 100 W RF (13.56 MH) was applied to the substrate side (sample stage).
z) Apply power and apply a substantially negative self-bias voltage. An insulating material containing silicon such as silicon oxide, silicon oxynitride, or silicon nitride can be used for the interlayer insulating film.
Since the interlayer insulating film formed by the CVD method is formed along the shape of the wiring, the concave portion 120 and the convex portion 122 are formed like the surface of the second interlayer insulating film shown in FIG. Hereinafter, referred to as a concavo-convex shape), a step is generated.

In order to flatten this step, polishing is performed by a CMP apparatus. Then, in order to uniformly perform CMP polishing, a linear opening 121 is formed in the second interlayer insulating film as shown in FIG. 2B.

The opening is formed using a mask made of resist. The width and arrangement of the openings are such that the drive circuit section of the interlayer insulating film and the convex sections 130 and 13 of the pixel section after the openings are formed.
Design the 1s to be interspersed with approximately equal size, shape and density. However, when the difference in pattern density is extreme, it may be set by appropriately modifying it according to the material and purpose of the object to be polished and the conditions of the CMP apparatus. For example, a driver circuit portion having a high wiring density is formed with more openings than a pixel portion having a low wiring density. By providing the opening at the portion where the polishing rate is low, the polishing rate is increased and the in-plane uniformity of the polishing rate is improved.

After that, an etching process is performed to form the opening 12
1 is formed. The depth of this opening is approximately the same as the depth of the concave-convex recess 120 formed in the second interlayer insulating film due to the underlying step. As the etching, anisotropic etching or isotropic etching may be selected as necessary. Furthermore,
The second interlayer insulating film may have a laminated structure and the lower insulating film may serve as an etching stop film, but the present invention does not need the etching stop film.

The resist mask is removed, and the second interlayer insulating film is polished using the CMP technique. In a typical polishing process, first, an object to be polished is attracted to a rotating polishing head with the surface to be polished facing down. Polishing is performed by pressing the object to be polished against a rotating rotary platen (also referred to as a platen). A polishing cloth (pad) is attached to the surface of the rotary platen that contacts the substrate, and the polishing liquid (slurry) attached to the pad is used for polishing.

Further, the polishing conditions for the CMP process, such as polishing pressure, polishing time, Tb / Sp (ratio of rotation speed of rotary platen and rotation speed of polishing head), polishing liquid, etc. The number of rotations of the substrate, the number of rotations of the polishing pad, and the time may be appropriately set depending on the material of the object to be polished and the amount of polishing, since they differ depending on the material and size, the material of the pad and the roughness of the mesh.

In the present embodiment, the substrate and the polishing cloth are rotated in the CMP apparatus, and the polishing pressure is 50 g / c.
Polishing was performed by applying a pressure of about m ^{2 to} 500 g / cm ² , and the recessed surface (lower surface of the step) was also polished. The polishing at this time can be most efficiently performed in a short time if the polishing is completed on the surface of the recessed portion of the step (the lower surface of the step), but polishing may be further performed to flatten the surface. Examples of CMP abrasives (slurry) for the interlayer insulating film include those in which fumed silica particles obtained by thermally decomposing silicon chloride gas are dispersed in a KOH-added aqueous solution. In this way, the second interlayer insulating film is uniformly planarized by using the CMP technique. (Fig. 2
(C) After that, unnecessary abrasives are removed by using hydrofluoric acid.

Next, as shown in FIG. 3A, a light-shielding film 122 made of a metal film may be provided on the uniformly flattened interlayer insulating film of the pixel portion. Here, an Al film is formed. Since the light-shielding film is provided so that light does not enter the TFT, any material other than Al may be used as long as it does not transmit light. Further, it may be provided on the interlayer insulating film of the driving circuit portion.

When the parasitic capacitance between the wiring and the light shielding film poses a problem, a third interlayer insulating film may be further provided on the uniformly planarized second interlayer insulating film. Further, if flattening is required, the same flattening as described above may be performed on the third interlayer insulating film on the light shielding film.

After forming the light-shielding film, it is used as a protective film.
A silicon oxynitride film 123 having a thickness of nm is formed. After that, a contact for establishing electrical continuity between the pixel electrode 124 and the connection wiring 119 is opened to form the pixel electrode 124. In this embodiment, an ITO film is used as the pixel electrode. In addition, as a pixel electrode, indium oxide or indium oxide 2 to 20
%, A transparent conductive film in which zinc oxide (ZnO) is mixed may be used.

As the first and second insulating films, a silicon oxide film, a silicon nitride film, an organic resin material (polyimide, acrylic, polyamide, polyimide amide, BC) is used.
A B (benzocyclobutene) film can be used.

In the present embodiment, the present invention is used to uniformly polish the second interlayer insulating film, but the present invention may be used to evenly planarize the first interlayer insulating film. Needless to say. Further, although the liquid crystal display device is assumed and described, the applicable range of the present invention is not limited to this. For example, when a multilayer wiring of three layers or more such as an LSI is formed, a step caused by each wiring layer is not formed. The present invention can also be used for planarizing a covering film.

As a material for the first and second interlayer insulating films, a material having a small relative dielectric constant of 2.5 to 3.0 (hereinafter referred to as low-
An insulating film made of a k material) may be used. This is because by lowering the dielectric constant of the interlayer insulating film, it is possible to reduce the parasitic capacitance and prevent signal delay. l
The insulating film made of the ow-k material includes an inorganic type and an organic type.
As the inorganic material, a material in which C and H are added to the SiO ₂ film to reduce the dielectric constant can be used. As the organic material, polyaryl ether having fine pores inside, fluorinated polyimide, or the like can be used, and in particular, a fluorine resin film is expected as a material that realizes a low dielectric constant.

By using the method for manufacturing a semiconductor device of the present invention, a uniform planarized interlayer insulating film can be obtained without providing dummy wirings, so that a uniform flat surface can be obtained while maintaining a high aperture ratio. An interlayer insulating film can be realized.

Further, the present invention is based on SOG (Spin On Glass:
Even when compared with the method of forming a flattening film by forming a material such as a coated silicon oxide film) or BCB (benzocyclobutene) in the recesses and performing etching back, the excellent effect is achieved.
It is possible to form a laminated structure thinner, and there is no problem of refractive index and dielectric constant due to different materials of the interlayer insulating film and SOG, BCB, etc., and the step of heating and hardening SOG, BCB, etc. is not necessary. This is because it is not necessary to consider a problem such as corrosion of the wiring due to moisture adsorbed by BCB or the like.

Further, according to the present invention, an insulating film having in-plane uniformity can be obtained by etching the insulating film using a mask, and new capital investment and new investment as in the case of using SOG or the like. There is no need to purchase materials, and the advantage is that you can use conventional equipment.

(Embodiment 2) A step corresponding to the size of the wiring is formed in the interlayer insulating film formed on the wiring. The polishing rate of the interlayer insulating film is affected by the density of the wiring density, which causes steps, but is further affected by the size of the wiring, and if the wiring has a large area pattern, the polishing rate of the interlayer insulating film is low, The polishing rate increases with a small area pattern.

First, in the graph of FIG. 8, the convex pattern causing the step is (a) 500 μm × 1100 μm, (b)
7.5 μm × 12 μm, (c) 300 μm × 650 μ
m, (d) 62 μm × 125 μm, (e) two 100 μm wide lines (spacing 100 μm), (f) 200 μm × 50
The result of polishing the interlayer insulating film on the pattern is shown as 0 μm, (g) without pattern.

From the graph, the polishing rate varies depending on the size of the pattern causing the step (also referred to as the step pattern), and the step pattern has the smallest shape (the area viewed from the upper surface) (b) has the highest polishing rate. In the following (d), the polishing rates are almost the same (c), (e) and (f), then (a), and the stepless pattern (g) has the lowest polishing rate.

From this, it is understood that the polishing rate depends on the size of the underlying wiring pattern that causes a step, and the polishing rate decreases as the shape of the underlying pattern increases. This is because the peripheral portion (edge of the convex portion) of the convex portion of the interlayer insulating film by the underlying pattern is polished from the upper surface and the periphery, whereas the central portion of the convex portion is polished from only the upper surface. Therefore, since the peripheral portion occupies a large proportion of the area of the convex portion, the polishing rate of the small independent pattern is increased.
That is, judging only from the result of FIG. 8, the polishing speed becomes the highest when there is a small convex portion as in (b).

The cause of this convex step pattern is the wiring itself, and it is unavoidable that the size and density of the pattern occur as long as the degree of freedom in circuit design is prioritized. In order to correct the non-uniformity of the CMP polishing rate caused by this,
In this embodiment, an opening is formed in a portion of the interlayer insulating film where the polishing rate is desired to be increased so that the convex portions as in (b) above are uniformly present. On the other hand, in the portion where the polishing rate is desired to be slowed, the number of openings may be reduced or no openings may be provided.

Since a large number of wirings are present in the drive circuit section and thick wirings are frequently used to reduce wiring resistance, large ground step differences are concentrated. As a result, the polishing rate of the interlayer insulating film is lower in the drive circuit section than in the pixel section. In order to avoid the uneven thickness of the interlayer insulating film as shown in FIG. 6, in the present embodiment, as shown in FIG. And different.

As shown in FIG. 4, the second interlayer insulating film made of a silicon oxynitride film is formed in the same manner as in the first embodiment.
It is formed to a thickness of 1000 nm. After that, a resist mask for forming the linear opening 143 is formed in the interlayer insulating film. In this embodiment mode, the width of the opening formed in the interlayer insulating film of the driver circuit portion is set so that the area of the protrusion portion of the driver circuit portion is equal to the area of the protrusion portion of the pixel portion. The width is larger than the width of the opening formed in the film. With such a configuration, the polishing rate can be constant in the drive circuit section and the pixel section, and the interlayer insulating film can be uniformly polished.

Generally, the larger the shape of the opening, the larger the reaction area with the etching gas and the solution, so that the reaction is faster and deeper etching is possible. Therefore, by changing the width of the opening, the etching rate can be changed to change the depth of etching in the same time. This is particularly remarkable in dry etching.

After that, the interlayer insulating film is polished by using a CMP apparatus. At this time, by forming the opening, the polishing rate of the interlayer insulating film is improved, and the degree of improvement is large in the driving circuit part and small in the pixel part, so that it is uniform in the plane and the interlayer insulating film is flattened uniformly. You can By changing the shape of the opening and the depth of the opening, the finished film thickness can be made constant.

After that, a TFT panel for a display device is manufactured in the same manner as in the first embodiment. In addition, in the first embodiment,
The structure described in 2 is merely an example, and is not limited to the structure shown in FIGS. 1 to 4.

When a circular or rectangular opening is formed in the interlayer insulating film, the size of the opening may be smaller than the opening formed in the interlayer insulating film of the pixel portion in the driving circuit portion,
When forming an opening so as to leave a dot-shaped convex portion, the number of dot-shaped convex portions formed in the interlayer insulating film of the driving circuit portion is equal to the number of dot-shaped convex portions formed in the pixel portion interlayer insulating film. The shape of the opening may be appropriately set, for example, more than the number.
The important point in the present invention is to control the polishing rate by forming an opening in the interlayer insulating film to obtain a uniform flat surface,
The effect of the present invention can be obtained if there is no difference in that respect.

As in the present embodiment, by changing the shape of the opening of the interlayer insulating film in the driving circuit portion and the pixel portion, a more evenly planarized interlayer insulating film can be obtained.

EXAMPLE 1 FIG. 9 shows a top gate type TFT manufactured by using the present invention.

First, a base insulating film 901 is formed over a substrate 900, a first semiconductor film having a crystal structure is obtained, and then the semiconductor layers 902 to 906 separated into islands by etching into a desired shape. To form.

As the substrate 900, a glass substrate (# 17
37) and plasma C is used as the base insulating film 901.
Film formation temperature of 400 ° C. by VD method, source gas SiH_Four, NH₃,
N₂ Silicon oxynitride film 901a made of O (pair
Composition ratio Si = 32%, O = 27%, N = 24%, H = 17
%) Is formed to 50 nm (preferably 10 to 200 nm).
Next, after cleaning the surface with ozone water, remove the oxide film on the surface.
Remove with dilute hydrofluoric acid (1/100 dilution). Then Plas
Film formation temperature of 400 ° C. by the CVD method, source gas SiH_Four, N₂
Silicon oxynitride film 901b (composition ratio)
Si = 32%, O = 59%, N = 7%, H = 2%) 1
Stacked to a thickness of 00 nm (preferably 50 to 200 nm)
And the film-forming temperature by plasma CVD without exposing to the atmosphere.
300 ° C, film forming gas SiH_FourAmorphous silicon film (amorphous)
54).
It is formed with a thickness of nm (preferably 25 to 80 nm).

Although the base film 901 has a two-layer structure in this embodiment, it may have a single-layer structure of the insulating film or a structure in which two or more layers are laminated. Also, plasma CVD
The device may be a single-wafer type device or a batch type device. Alternatively, the base insulating film and the semiconductor film may be successively formed in the same film formation chamber without exposure to the air.

Next, after cleaning the surface of the amorphous silicon film, an extremely thin oxide film of about 2 nm is formed on the surface with ozone water. Next, a slight amount of impurity element (boron or phosphorus) is doped to control the threshold value of the TFT.
Here, an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation is used, the doping conditions are an acceleration voltage of 15 kV, a gas flow rate of 30 sccm of diborane diluted to 1% with hydrogen, and a dose amount of 2 × 10 ^12. Boron was added to the amorphous silicon film at a rate of / cm ² .

Then, a nickel acetate salt solution containing 10 ppm by weight of nickel is applied by a spinner. Since the amorphous silicon film repels the nickel-containing solution, the amorphous silicon film is oxidized by UV irradiation, thermal oxidation, hydrogen peroxide solution, or ozone water treatment to form a thin oxide film (silicon oxide film). ) To improve the wettability. Instead of coating, a method of spattering nickel element over the entire surface by a sputtering method may be used. Here, an example of applying it on the entire surface is shown, but
A mask may be formed to selectively form the nickel-containing layer.

Next, energy is applied to crystallize the amorphous silicon film into a crystalline silicon film (also referred to as a polysilicon film or a crystalline silicon film). For this energy, heat treatment of an electric furnace or irradiation of strong light may be used.
When it is performed by heat treatment in an electric furnace, it is 4 at 500 ° C to 650 ° C.
The treatment may be performed for up to 24 hours. Here, after heat treatment for dehydrogenation (500 ° C., 1 hour), heat treatment for crystallization (550 ° C., 4 hours) is performed to obtain a crystalline silicon film. Although crystallization is performed here by heat treatment using a furnace, crystallization may be performed by a lamp annealing apparatus that can perform crystallization in a short time. Although the crystallization technique using nickel as a metal element that promotes crystallization of silicon is used here, other known crystallization techniques such as the solid phase growth method and the laser crystallization method described above may also be used. Good.

Next, after removing the oxide film on the surface of the crystalline silicon film with dilute hydrofluoric acid or the like, the crystallization rate is further increased, and laser light (XeCl:
Irradiation with a wavelength of 308 nm) is performed in the air or an oxygen atmosphere. As the laser light, excimer laser light having a wavelength of 400 nm or less, and second and third harmonic waves of YVO ₄ laser are used. In any case, the repetition frequency is 10 to 1
Using a pulsed laser light of about 000 Hz, the laser light is condensed to 100 to 500 mJ / cm ² by an optical system,
Irradiation may be performed with an overlap rate of 90 to 95% to scan the surface of the silicon film. Here, laser light irradiation is performed in an air atmosphere with a repetition frequency of 30 Hz and an energy density of 393 mJ / cm ² . In the atmosphere,
Alternatively, since it is performed in an oxygen atmosphere, an oxide film is formed on the surface by irradiation with laser light.

After removing the oxide film formed by the laser light irradiation with dilute hydrofluoric acid, the second laser light irradiation may be performed in a nitrogen atmosphere or in a vacuum to flatten the surface of the semiconductor film. . In this case, as the laser light (second laser light), excimer laser light having a wavelength of 400 nm or less, second harmonic wave, or third harmonic wave of YAG laser is used. The energy density of the second laser light is higher than that of the first laser light, preferably 30
Increase by ~ 60 mJ / cm ² .

The metal element (nickel in this case) remains in the crystalline silicon film thus obtained. Even if it is not uniformly distributed in the film, it remains at a concentration exceeding 1 × 10 ¹⁹ / cm ³ as an average concentration. Of course, even in such a state, it is possible to form various semiconductor elements including the TFT, but the element is removed by the method described below.

Gettering is performed to remove the added nickel element. An amorphous silicon film containing an argon element, which serves as a gettering site, is formed with a thickness of 5 nm by a plasma CVD method. The film formation conditions by the plasma CVD method of the present embodiment are: substrate temperature of 300 ° C., chamber pressure of 26.66 Pa (0.2 Torr), and SiH ₄ gas flow rate of 100 sc from the gas introduction system.
cm, argon gas at a flow rate of 500 sccm, and nitrogen gas at 200 sccm, respectively, and a discharge frequency of 27.12 MHz from a high frequency power source, and an input RF power of 300.
Discharge with W (RF power density 0.5 W / cm ² ).
The atomic concentration of the argon element contained in the first amorphous silicon film under the above conditions is 1 × 10 ²⁰ / cm ³ to 1 ×.
10 ²¹ / cm ³ , the atomic concentration of nitrogen is 1 × 10 ²⁰ / cm ³ ~
It is 1 × 10 ²¹ / cm ³ . Further, the adhesion may be improved by performing an argon plasma treatment before forming the amorphous silicon film containing an argon element. After that, gettering is performed by heat treatment at 650 ° C. for 3 minutes using a lamp annealing device.

As described above, after a thin oxide film was formed on the surface of the obtained crystalline silicon film with ozone water, a mask made of a resist was formed, and a desired shape was etched to be separated into islands. A crystalline silicon film (hereinafter, simply referred to as a semiconductor layer) is formed. After forming the semiconductor layer, the resist mask is removed.

Next, after removing the oxide film with an etchant containing hydrofluoric acid and simultaneously cleaning the surface of the silicon film,
An insulating film containing silicon as its main component is formed to be the gate insulating film 907. In this embodiment, 11 is formed by the plasma CVD method.
A silicon oxynitride film with a thickness of 5 nm (composition ratio Si = 32
%, O = 59%, N = 7%, H = 2%).

Next, as shown in FIG. 9A, a first conductive film 908a having a film thickness of 20 to 100 nm and a second conductive film 9 having a film thickness of 100 to 400 nm are formed on the gate insulating film 907.
08b is formed by stacking. In this embodiment, a tantalum nitride film with a thickness of 50 nm and a thickness of 370 are formed on the gate insulating film 907.
nm tungsten films are sequentially stacked.

As the conductive material for forming the first conductive film and the second conductive film, Ta, W, Ti, Mo, Al, Cu
It is formed of an element selected from the above or an alloy material or a compound material containing the above element as a main component. Further, the structure is not limited to the two-layer structure, and for example, a tungsten film having a film thickness of 50 nm,
An alloy of aluminum and silicon with a thickness of 500 nm (Al
A -Si) film and a titanium nitride film having a film thickness of 30 nm may be sequentially laminated to form a three-layer structure. Also, in the case of a three-layer structure,
Tungsten nitride may be used instead of tungsten of the first conductive film, and an aluminum-titanium alloy film (Al-Ti) may be used instead of the aluminum-silicon alloy (Al-Si) film of the second conductive film. Or a titanium film may be used instead of the titanium nitride film of the third conductive film. Further, it may have a single layer structure.

Next, as shown in FIG. 9B, masks 910 to 915 made of resist are formed by an exposure process,
A first etching process for forming a gate electrode and wiring is performed. The first etching process is performed under the first and second etching conditions. ICP (Induct) for etching
It is advisable to use a collectively coupled plasma (inductively coupled plasma) etching method. A film having a desired taper shape is formed by appropriately adjusting the etching conditions (the amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) using the ICP etching method. Can be etched. As the etching gas, chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ or the like, or fluorine-based gas typified by CF ₄ , SF ₆ , NF ₃ or O ₂ is used as appropriate. Can be used.

In this embodiment, 150 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage),
A substantially negative self-bias voltage is applied. The electrode area size on the substrate side is 12.5 cm × 12.5 cm, and the coil type electrode area size (here, a quartz disk provided with a coil) is a disk having a diameter of 25 cm. The W film is etched under the first etching condition so that the end portion of the first conductive layer is tapered. The etching rate for W under the first etching condition is 200.39.
The etching rate for TaN is 80.nm / min.
It is 32 nm / min, and the selection ratio of W to TaN is about 2.5. Further, the taper angle of W is about 26 ° under the first etching condition. After that, the second mask is removed without removing the resist masks 910 to 915.
Of changing the etching condition, using CF ₄ and Cl ₂ as etching gas, setting the gas flow rate ratio 30/30
(Sccm), and a pressure of 1 Pa is applied to the coil-type electrode of 5
RF (13.56 MHz) power of 00 W was applied to generate plasma and etching was performed for about 30 seconds. 20W RF (13.56M) on the substrate side (sample stage)
Hz) power is applied and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching conditions is 58.97 nm / min, and the etching rate for TaN is 66.43 nm / min. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased at a rate of about 10 to 20%.

In the first etching process, the shape of the mask made of resist is adjusted to
The edges of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion may be 15 to 45 °.

Thus, the first shape conductive layers 917 to 921 (the first conductive layers 917a to 921a and the second conductive layer 917b) including the first conductive layer and the second conductive layer are formed by the first etching treatment. ~ 921b) are formed. The insulating film 907 serving as a gate insulating film is etched by about 10 to 20 nm, and becomes a gate insulating film 916 in which a region which is not covered with the first shape conductive layers 917 to 921 is thin.

Next, a second etching process is performed without removing the resist mask. Here, SF ₆ , Cl _2, and O ₂ are used as etching gases, and the gas flow rate ratios thereof are set to 24/12/24 (sccm).
A 700 W RF (13.
(56 MHz) Power was supplied to generate plasma and etching was performed for 25 seconds. 10 on the substrate side (sample stage)
RF (13.56 MHz) power of W is applied and a substantially negative self-bias voltage is applied. The etching rate for W in the second etching process is 227.3 nm / m.
The etching rate for in and TaN is 32.1 nm /
min, the selectivity of W with respect to TaN is 7.1, the etching rate with respect to SiON that is an insulating film is 33.7 nm / min, and the selectivity of W with respect to SiON is 6.83. As described above, when SF ₆ is used as the etching gas, the selection ratio to the insulating film 916 is high, so that film loss can be suppressed. In this embodiment, the insulating film 916 is reduced by only about 8 nm.

The taper angle of W was 70 ° by this second etching treatment. By this second etching process, second conductive layers 924b to 929b are formed. On the other hand, the first conductive layer is hardly etched,
Conductive layers 924a to 929a. Note that the first conductive layers 924a to 929a are the first conductive layers 917a to 92.
It is almost the same size as 2a. Actually, the width of the first conductive layer is about 0.3 μm as compared with that before the second etching process.
In some cases, the line width may recede by about 0.6 μm, but there is almost no change in size.

Further, instead of the two-layer structure, a three-layer structure in which a tungsten film having a film thickness of 50 nm, an alloy of aluminum and silicon (Al-Si) film having a film thickness of 500 nm, and a titanium nitride film having a film thickness of 30 nm are sequentially laminated is provided. In this case, as the first etching condition of the first etching process, BCl ₃ , Cl ₂ and O ₂ are used as source gases, and the gas flow rate ratio of each is set to 65/10/5 (sccm). The RF power (13.56 MHz) of 300 W is applied to the (sample stage), and the RF power (13.56 MHz) of 450 W is applied to the coil-shaped electrode at a pressure of 1.2 Pa to generate plasma for 117 seconds. Etching may be performed. As the second etching condition of the first etching process, CF ₄ , Cl _2, and O ₂ are used, and the gas flow rate ratio of each is 25/2.
5/10 (sccm), 20W of RF (13.56MHz) power was also applied to the substrate side (sample stage),
RF of 500 W (13.
56MHz) Power is generated and plasma is generated for about 30
It suffices to perform etching for about a second, BCl ₃ and Cl ₂ are used for the second etching treatment, the gas flow rate ratio of each is set to 20/60 (sccm), and 100 W of RF ( (13.56 MHz) electric power is applied, and 600 W RF (13.56 MHz) electric power is applied to the coil-shaped electrode at a pressure of 1.2 Pa to generate plasma to perform etching.

Next, after removing the resist mask, a first doping process is performed to obtain the state shown in FIG. 9D. The doping treatment may be performed by an ion doping method or an ion implantation method. The conditions of the ion doping method are that the dose amount is 1.5 × 10 ¹⁴ atoms / cm ² and the acceleration voltage is 60 to 100 keV. As an impurity element imparting n-type, typically phosphorus (P) or arsenic (A
s) is used. In this case, the first conductive layer and the second conductive layers 924 to 928 serve as masks for the impurity element imparting n-type, and the first impurity regions 930 to 930 are self-aligned.
934 is formed. First impurity regions 930 to 934
Is doped with an impurity element imparting n-type in a concentration range of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . Here, a region having the same concentration range as the first impurity region is also called an n ⁻ region.

In this embodiment, the first doping process is performed after removing the resist mask, but the first doping process may be performed without removing the resist mask.

Next, as shown in FIG. 10A, masks 935 to 937 made of resist are formed and a second doping process is performed. A mask 935 is a mask for protecting a channel formation region of a semiconductor layer which forms a p-channel TFT of a driver circuit and a peripheral region thereof, and a mask 936 is a semiconductor layer which forms one of n-channel TFTs of the driver circuit. The mask 937 is a mask that protects the channel formation region and its peripheral region, and the mask 937 is a mask that protects the channel formation region of the semiconductor layer forming the TFT of the pixel portion, the peripheral region thereof, and the region serving as the storage capacitor.

The condition of the ion doping method in the second doping process is that the dose amount is 1.5 × 10 ¹⁵ atoms / c.
m ² and an accelerating voltage of 60 to 100 keV, and phosphorus (P) is doped. Here, the second conductive layer 92
Impurity regions are formed in each semiconductor layer in a self-aligned manner using 4a to 929a as masks. Of course, the masks 935-93
It is not added to the area covered by 7. Thus, the second impurity regions 938 to 940 and the third impurity region 942 are formed.
Is formed. 1 in the second impurity regions 938 to 940
An impurity element imparting n-type is added within a concentration range of × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . Here, a region having the same concentration range as the second impurity region is also called an n ⁺ region.

Further, the third impurity region is formed at a lower concentration than the second impurity region by the first conductive layer, and has a concentration of 1 × 1.
An impurity element imparting n-type is added in the concentration range of 0 ¹⁸ to 1 × 10 ¹⁹ / cm ³ . Note that the third impurity region has a concentration gradient in which the impurity concentration increases toward the end portion of the tapered portion because doping is performed by passing through the portion of the first conductive layer having a tapered shape. . Here, a region having the same concentration range as the third impurity region is also called an n ⁻ region. Further, the regions covered with the masks 936 and 937 become first impurity regions 944 and 945 without being added with an impurity element by the second doping treatment.

Next, a mask 935 made of resist.
After removing 937, a mask 9 newly made of resist
46 to 948 to form a third layer as shown in FIG.
The doping process is performed.

In the drive circuit, by the third doping treatment, a fourth impurity element which imparts p-type conductivity is added to the semiconductor layer forming the p-channel TFT and the semiconductor layer forming the storage capacitor. Impurity region 949,
950 and fifth impurity regions 951 and 952 are formed.

The impurity element imparting p-type conductivity is added to the fourth impurity regions 949 and 950 in the concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . The fourth impurity regions 949 and 950 are regions (n ⁻ regions) to which phosphorus (P) has been added in the previous step, but the concentration of the impurity element imparting p-type is 1.5 to The conductivity type is p-type by adding 3 times. Here, a region having the same concentration range as the fourth impurity region is also called ap ⁺ region.

The fifth impurity regions 951 and 952 are formed in a region overlapping with the tapered portion of the second conductive layer 925a, and have a concentration range of 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ^3. An impurity element imparting p-type is added. Here, a region having the same concentration range as the fifth impurity region is also called ap ⁻ region.

By the steps up to this point, each semiconductor layer has n
An impurity region having a conductivity type of p-type or p-type is formed. The conductive layers 924 to 927 become the gate electrodes of the TFT. The conductive layer 928 serves as one electrode which forms a storage capacitor in the pixel portion. Further, the conductive layer 929 forms a source wiring in the pixel portion.

Next, an insulating film (not shown) is formed to cover almost the entire surface. In this embodiment, a silicon oxide film having a film thickness of 50 nm is formed by the plasma CVD method. Of course, this insulating film is not limited to the silicon oxide film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

Then, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating the back surface with a YAG laser or an excimer laser, a heat treatment using a furnace, or a combination of these methods. By the method. The laser may be any of the lasers described above.

In this embodiment, an example in which the insulating film is formed before the activation is shown, but after the activation is performed,
It may be a step of forming an insulating film.

Then, a first silicon oxynitride film is formed.
The interlayer insulating film 953 of
It is formed with a thickness of m. SiH ₄ , N ₂ O as raw material gas,
Using NH ₃ and H ₂ , 10 on the substrate side (sample stage)
A 0 W RF (13.56 MHz) power is applied and a substantially negative self-bias voltage is applied. After that, heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours) is performed,
A step of hydrogenating the semiconductor layer is performed. (FIG. 10C) This step is a step of terminating the dangling bond of the semiconductor layer by hydrogen contained in the first interlayer insulating film 953.
However, in this embodiment, since the material containing aluminum as the main component is used as the second conductive layer, it is important to set the heat treatment conditions that the second conductive layer can withstand in the hydrogenation step. Plasma hydrogenation (using hydrogen excited by plasma) may be performed as another means of hydrogenation. Further, acrylic, SOG (Spin on Glass; coated silicon oxide film), BCB are formed on the first interlayer insulating film 953.
Second made of organic insulating material such as (benzocyclobutene)
The interlayer insulating film 954 may be formed. In this embodiment, an SOG film having a thickness of 1.6 μm is formed.

Then, a contact hole reaching the source wiring 929, a contact hole reaching the conductive layers 927 and 928, and a contact hole reaching each impurity region are formed. In this embodiment, a plurality of etching processes are sequentially performed. In this embodiment, after etching the second interlayer insulating film using the first interlayer insulating film as an etching stopper, the first interlayer insulating film is etched using an insulating film (not shown) as an etching stopper, and then the insulating film (illustrated). do not do)
Was etched.

After that, wirings and pixel electrodes are formed by using Al, Ti, Mo, W and the like. As a material of these electrodes and pixel electrodes, it is desirable to use a film having Al or Ag as a main component or a material having excellent reflectivity such as a laminated film thereof. Thus, the source or drain electrode 9
55 to 960, a gate wiring 962, and a connection wiring 961 are formed.

Then, a third layer made of a silicon oxynitride film is formed.
The interlayer insulating film of 800 nm thick by plasma CVD
To form. SiH as source gas_Four, N₂O, NH₃Over
And H₂ Of 100W on the substrate side (sample stage)
Applying RF (13.56MHz) power, the
Apply self bias voltage. The third shown in FIG.
An uneven shape occurs like the surface of the interlayer insulating film.

CMP polishing is performed to flatten the uneven shape. Then, a linear opening is formed in the third interlayer insulating film so as to uniformly perform CMP polishing.

Therefore, a resist mask is formed on the second interlayer insulating film. The interval between the adjacent linear openings of the mask may be appropriately set according to the material and purpose of the object to be polished and the CMP apparatus conditions. However, in the drive circuit section with high wiring density, the pixel section with low wiring density is used. The mask may be formed so as to form more linear openings. After that, etching treatment is performed to form a linear opening.

The mask is removed, and the third interlayer insulating film is CM.
Polish by P technology. It is the polishing condition of the CMP device,
The polishing pressure, polishing time, Tb / Sp, etc. are different depending on the material and size of the device or the object to be polished and the CMP device, and may be appropriately set according to the purpose. The conditions of the CMP apparatus in this example are as follows: polishing pressure 600 gf / cm ² , polishing time 120 sec, Tb / Sp =
40/40. As the CMP slurry, for example, fumed silica particles obtained by thermally decomposing silicon chloride gas are dispersed in a KOH-added aqueous solution. In this way, the second interlayer insulating film can be planarized uniformly by polishing with the CMP apparatus.

As described above, the n-channel TFT 90
1, p-channel TFT 902, n-channel TFT 9
The pixel portion 907 including the driver circuit 906 including the TFT 03, the pixel TFT 904 including the n-channel TFT, and the storage capacitor 905 can be formed over the same substrate. (FIG. 11B) In this specification, such a substrate is referred to as an active matrix substrate for convenience.

A drive circuit 906 may be formed by appropriately combining these TFTs 901 to 903 to form a shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, and the like. For example, when forming a CMOS circuit, an n-channel TFT 901 and a p-channel TFT
It may be formed by connecting 902 complementarily.

In particular, for a buffer circuit having a high driving voltage,
The structure of the n-channel TFT 903 is suitable for the purpose of preventing deterioration due to the hot carrier effect.

Further, for a circuit in which reliability is given the highest priority,
The structure of the n-channel TFT 901 having the GOLD structure is suitable.

By using the method for manufacturing a semiconductor device of the present invention, an evenly planarized interlayer insulating film can be obtained without providing a dummy wiring. Therefore, a high aperture ratio can be maintained and a uniform and flat interlayer insulating film can be obtained. An interlayer insulating film can be realized.

[Embodiment 2] Even in the inverted stagger type TFT, since the wiring density is different between the driving circuit portion and the pixel portion, a flat interlayer insulating film can be formed by the present invention.
In this embodiment, a pixel structure using an inverted stagger type TFT will be described.

FIG. 12 shows a sectional view of the pixel of this embodiment.
Driving TFTs 1203 to 120 of the driving circuit unit 1201
6, pixel TFTs 1208 and 1209 of the pixel portion 1202.

FIG. 12A shows the first interlayer insulating film 122.
Source wiring, drain wiring, and connection wiring are formed on 0,
FIG. 11 is a diagram showing a state in which a second interlayer insulating film 1223 is formed on the first interlayer insulating film by a plasma CDV method so as to cover the source wiring, the drain wiring, and the connection wiring 1222.

After that, polishing is performed by a CMP apparatus to obtain a uniformly flat second interlayer insulating film. And FIG.
As shown in (b), on the second interlayer insulating film 1223,
The pixel electrode 1224 is formed. The pixel electrode 12
24 is connected through a contact hole formed in the second interlayer insulating film 1223.

By using the method for manufacturing a semiconductor device of the present invention as in this embodiment, it is possible to obtain a uniformly planarized interlayer insulating film without providing dummy wiring even in an inverted stagger type TFT. A uniform and flat interlayer insulating film can be realized while maintaining a high aperture ratio.

[Embodiment 3] In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described below. FIG. 13 is used for the description.

First, according to the first embodiment, after obtaining the active matrix substrate in the state of FIG. 11, an alignment film is formed on the active matrix substrate of FIG. 11 and rubbing treatment is performed. In this embodiment, before forming the alignment film, the organic resin film such as the acrylic resin film was patterned to form the columnar spacers for holding the substrate distance at desired positions. Further, spherical spacers may be dispersed over the entire surface of the substrate instead of the columnar spacers.

Next, a counter substrate is prepared. The counter substrate is provided with a color filter in which a colored layer and a light shielding layer are arranged corresponding to each pixel. Further, a light-shielding layer was also provided in the drive circuit portion. A flattening film was provided to cover the color filter and the light shielding layer. Next, a counter electrode made of a transparent conductive film was formed on the flattening film in the pixel portion, an alignment film was formed on the entire surface of the counter substrate, and a rubbing treatment was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are bonded together with a sealant. A filler is mixed in the sealing material, and the two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. After that, a liquid crystal material is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display device is completed. Then, if necessary, the active matrix substrate or the counter substrate is cut into a desired shape. Further, an optical film such as a polarizing plate or a retardation plate was appropriately provided by using a known technique. Then, using a known technique, the FP
I pasted C.

The structure of the liquid crystal module thus obtained will be described with reference to the top view of FIG.

A pixel portion 1304 is arranged in the center of the active matrix substrate 1301. Pixel unit 130
A source signal line drive circuit 1302 for driving the source signal line is arranged on the upper side of 4. Pixel unit 130
Gate signal line drive circuits 1303 for driving the gate signal lines are arranged on the left and right sides of 4. In the example shown in this embodiment, the gate signal line driving circuit 1303 is arranged symmetrically with respect to the pixel portion, but this may be arranged on only one side, and the designer may consider the substrate size of the liquid crystal module or the like. May be selected as appropriate. However, considering the operational reliability of the circuit, the driving efficiency, and the like, the left-right symmetrical arrangement shown in FIG. 13 is desirable.

Input of a signal to each drive circuit is performed by a flexible printed circuit (FPC) 1
It starts from 305. The FPC 1305 is the substrate 1301.
A contact hole is opened in the interlayer insulating film and the resin film so as to reach the wiring arranged up to a predetermined position, and a connection electrode 1309 is formed, and then pressure bonding is performed via an anisotropic conductive film or the like. In this embodiment, the connection electrode is made of ITO.

A sealant 1307 is applied to the periphery of the driving circuit portion and the pixel portion along the outer periphery of the substrate, and a constant gap (distance between the substrate 1301 and the counter substrate 1306 is formed by a spacer formed on the active matrix substrate in advance. ) Is maintained, the counter substrate 306 is attached. After that, a liquid crystal element is injected from a portion where the sealant 1307 is not applied and is sealed with a sealant 1308. The liquid crystal module is completed through the above steps.

Although an example in which all the driving circuits are formed on the substrate is shown here, several ICs may be used as a part of the driving circuits. This embodiment can be freely combined with Embodiments 1 and 2.

As in this embodiment, an active matrix type liquid crystal display device can be manufactured from an active matrix substrate having a film which is uniformly flattened.

[Embodiment 4] The present invention is intended to solve the unevenness of the planarization film due to the wiring density of the multilayer wiring, and to form an organic light emitting device (OLED).
It goes without saying that it can also be used for a light emitting display device provided with e). In this embodiment, an example of manufacturing a light emitting display device including an organic light emitting element is shown in FIG.

The OLED has a layer containing an organic compound (organic light emitting material) capable of obtaining luminescence (electroluminescence) generated by applying an electric field (hereinafter referred to as an organic light emitting layer), an anode and a cathode. There is. Luminescence in an organic compound includes light emission (fluorescence) when returning from a singlet excited state to a ground state and light emission when returning to a ground state from a triplet excited state (phosphorescence). One of the above-mentioned light emissions may be used, or both of the light emissions may be used.

In this specification, all the layers formed between the anode and the cathode of the OLED are defined as the organic light emitting layer.
The organic light emitting layer specifically includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, an OLED has a structure in which an anode, a light emitting layer, and a cathode are laminated in this order, and in addition to this structure, an anode / hole injection layer /
It may have a structure in which a light emitting layer / cathode or an anode / hole injection layer / light emitting layer / electron transport layer / cathode are laminated in this order.

FIG. 14 (A) is a top view of a module having an OLED, a so-called EL module, FIG. 14 (B).
FIG. 14 is a cross-sectional view taken along the line AA ′ in FIG. A pixel portion 1402, a source side driver circuit 1401, and a gate side driver circuit 1403 are formed over a substrate 1400 having an insulating surface (eg, a glass substrate, a crystallized glass substrate, a plastic substrate, or the like). These pixel portion and drive circuit can be obtained according to the above-described embodiment.

In addition, 1418 is a sealing material, and 1419 is a protective material.
It is a protective film and uses a DLC film. Pixel part and drive circuit
The road is covered with a seal material 1418, and the seal material is protected.
Covered with membrane 919. In addition, cover with an adhesive.
It is sealed with a material 1420. Cover material 1420
, Plastic, glass, metal, ceramics, etc.
A substrate having any composition may be used. Also, the cover material 1420
The shape and the shape of the support are not particularly limited, and may be flat.
Those that have a curved surface, those that have a bendability,
It may have a film shape. Change due to heat or external force
Cover material 1420 is the same as substrate 1400 to withstand shape
It is desirable to use a material such as a glass substrate.
In this embodiment, the sand blast method or the like is used.
Processed into the concave shape (depth 3 to 10 μm) shown in FIG. Furthermore
Recessed by processing into a desiccant 1421 (depth 50
˜200 μm) is desirable. Also, many sides
When manufacturing the EL module by taking the substrate, the substrate and cover material
After attaching and, CO₂ The end surface can be
You may divide so that it may correspond.

Although not shown here, in order to prevent the background from being reflected by the reflection of the metal layer used (here, the cathode or the like), a circular polarizing plate including a retardation plate (λ / 4 plate) and a polarizing plate is used. A so-called circular polarization means may be provided on the substrate 1400.

The reference numeral 1408 designates the source side driving circuit 140.
1 and an FPC which is a wiring for transmitting a signal input to the gate side driving circuit 1403 and serves as an external input terminal.
(Flexible Printed Circuit) Receives a video signal and a clock signal from 1409. Further, the light emitting device of this embodiment may be digitally driven or analogly driven, and the video signal may be a digital signal or an analog signal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to this FPC. The light emitting device in this specification includes not only the light emitting device main body but also a state in which the FPC or PWB is attached thereto. Further, it is possible to form a complicated integrated circuit (memory, CPU, controller, D / A converter, etc.) on the same substrate as these pixel portion and drive circuit, but it is difficult to manufacture with a small number of masks. is there. Therefore, it is preferable to mount an IC chip including a memory, a CPU, a controller, a D / A converter and the like by a COG (chip on glass) method, a TAB (tape automated bonding) method, or a wire bonding method.

Next, the sectional structure will be described with reference to FIG. An insulating film 1410 is provided over a substrate 1400, a pixel portion 902 and a gate side driver circuit 903 are formed above the insulating film 1410, and the pixel portion 1402 is electrically connected to a current control TFT 1411 and its drain. And a plurality of pixels including the pixel electrode 1412. Actually, a plurality of TFTs are built in one pixel, but here, for simplification, the current control TFT 1
Only 411 is shown. In addition, the gate side driving circuit 140
3 is an n-channel TFT 1413 and a p-channel TFT
It is formed using a CMOS circuit in combination with 1414.

These TFTs (1411, 1413, 1)
(Including 414) is the n-channel TF of the first embodiment.
T, it may be manufactured according to the p-channel TFT of the first embodiment. Although the example using the top gate type TFT is shown here, the structure is not limited to the TFT, and the example 2
It is also possible to use a bottom gate type TFT as described in (1).

An insulating film is provided on the connection wiring of these TFTs. In the present invention, as the insulating material used as the material of the insulating film, in addition to insulating materials containing silicon such as silicon oxide, silicon oxynitride, and silicon nitride, polyimide, polyamide,
An organic resin film such as acrylic (including photosensitive acrylic) or BCB (benzocyclobutene) can also be used. Further, as another material for the insulating film, a layer represented by AlNxOy may be used. A nitride oxide layer containing aluminum (a layer represented by AlNxOy) obtained by forming a film using a sputtering method, for example, using an aluminum nitride (AlN) target in an atmosphere in which argon gas, nitrogen gas, and oxygen gas are mixed. ) Is nitrogen at 2.5 atm
% To 47.5 atm%, and in addition to the effect of blocking moisture and oxygen, it has a high heat conductivity and a heat dissipation effect, and further has a very high translucency. There is. In addition, impurities such as alkali metal and alkaline earth metal can be prevented from entering the active layer of the TFT.

After that, an opening is formed in the insulating film and uniformly polished and flattened. Thereby, the film thickness of the organic compound layer can be made uniform, and an electric field can be uniformly applied to the organic compound layer. Note that when an electric field is applied non-uniformly, the current density in the organic compound layer also becomes non-uniform, which not only reduces the brightness of the light-emitting element but also shortens the element life due to accelerated deterioration of the element. Therefore, the treatment by the CMP method has an effect of improving the device characteristics in terms of applying a uniform electric field to the organic compound layer. The insulating film functions as a bank 1415 by etching.

Further, the pixel electrode may be used as a cathode, and the EL layer and the anode may be laminated to emit light in the direction opposite to that shown in FIG. FIG. 15 shows an example thereof. Since the top view is the same, it is omitted.

The sectional structure shown in FIG. 15 will be described below. As the substrate 1500, a semiconductor substrate or a metal substrate can be used as well as a glass substrate or a quartz substrate. An insulating film 1510 is provided on the substrate 1500,
A pixel portion 1502 and a gate side driver circuit 1503 are formed above the insulating film 1510. The pixel portion 1502 is formed by a plurality of pixels including a current control TFT 1511 and a pixel electrode 1512 electrically connected to its drain. To be done. The gate side driver circuit 1503 is formed using a CMOS circuit in which an n-channel TFT 1513 and a p-channel TFT 1514 are combined.

The pixel electrode 1512 functions as the cathode of the OLED. In addition, the bank 1 is provided on both ends of the pixel electrode 1512.
515 is formed, and the EL layer 15 is formed on the pixel electrode 1512.
16 and the anode 1517 of the OLED are formed.

The anode 1517 also functions as a wiring common to all the pixels, and is connected to the FPC 1509 via the connection wiring 1508.
Electrically connected to. Further, all the elements included in the pixel portion 1502 and the gate side driver circuit 1503 are covered with the anode 1517, the sealing material 1518, and the protective film 1519. Further, the cover material 1520 and the substrate 1500 were attached to each other with an adhesive. Further, a recess is provided in the cover material and a desiccant 1521 is placed therein.

As the sealing material 1518, it is preferable to use a material that is as transparent or translucent to visible light as possible. Further, it is desirable that the sealing material 1518 be a material that does not allow moisture and oxygen to permeate as much as possible.

Further, in FIG. 15, the pixel electrode is used as a cathode,
Since the EL layer and the anode are laminated, the light emitting direction is the direction of the arrow shown in FIG.

Although not shown here, a retardation plate (λ / 4 plate) is provided in order to prevent the background from being reflected by reflection of a metal layer used (here, a pixel electrode serving as a cathode, etc.).
A circularly polarizing means called a circularly polarizing plate composed of a polarizing plate or a polarizing plate may be provided on the cover material 1520.

The driving method of the light emitting display device having the organic light emitting element includes constant current driving and constant voltage driving, but this embodiment may use either method.

This embodiment can be freely combined with Embodiments 1 and 2. [Embodiment 5] The present invention can be used as a display portion of any electronic device including a display display as a component, including the above-mentioned EL display.

Examples of such electronic devices include EL displays, video cameras, digital cameras, head-mounted displays (head-mounted displays, etc.), car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones or electronic books). Etc.), an image reproducing device equipped with a recording medium (specifically, a compact disc (CD), a laser disc (registered trademark) (LD), a digital video disc (DVD), or other recording medium is reproduced, and the image is displayed. Device having a display) and the like. Examples of these electronic devices are shown in FIGS.

FIG. 18A shows a display device, which is a housing 20.
01, support base 2002, display unit 2003, speaker unit 2004, video input terminal 2005 and the like. The light emitting device manufactured according to the present invention can be used for the display portion 2003. Since a light emitting device having a light emitting element is a self-luminous type, it does not need a backlight and can have a thinner display portion than a liquid crystal display device. The display device includes all display devices for displaying information, such as those for personal computers, those for receiving TV broadcasting, and those for displaying advertisements.

FIG. 18B shows a digital still camera including a main body 2101, a display section 2102, an image receiving section 2103,
An operation key 2104, an external connection port 2105, a shutter 2106 and the like are included. The light emitting device manufactured according to the present invention can be used for the display portion 2102.

FIG. 18C shows a laptop personal computer, which has a main body 2201, a housing 2202, and a display section 2.
203, keyboard 2204, external connection port 220
5, including a pointing mouse 2206 and the like. The light emitting device manufactured according to the present invention can be used for the display portion 2203.

FIG. 18D shows a mobile computer, which has a main body 2301, a display portion 2302, and a switch 230.
3, an operation key 2304, an infrared port 2305 and the like. The light emitting device manufactured according to the present invention can be used for the display portion 2302.

FIG. 18E shows a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a casing 2402, a display portion A2403, a display portion B2404, and a recording medium ( DVD, etc.) reading unit 240
5, an operation key 2406, a speaker portion 2407, and the like. The display portion A2403 mainly displays image information and the display portion B2404 mainly displays textual information, but the light-emitting device manufactured according to the present invention has these display portions A and B240.
3, 2404 can be used. Note that the image reproducing device provided with the recording medium includes a home game machine and the like.

FIG. 18F shows a goggle type display (head mount display), which is a main body 250.
1, a display portion 2502 and an arm portion 2503 are included. The light emitting device manufactured according to the present invention can be used for the display portion 2502.

FIG. 18G shows a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, and an image receiving portion 260.
6, a battery 2607, a voice input unit 2608, operation keys 2609, and the like. The light emitting device manufactured according to the present invention can be used for the display portion 2602.

Here, FIG. 18H shows a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, a voice input portion 2704, a voice output portion 2705, operation keys 2706,
An external connection port 2707, an antenna 2708, and the like are included.
The light emitting device manufactured according to the present invention can be used for the display portion 2703. Note that the display portion 2703 can suppress power consumption of the mobile phone by displaying white characters on a black background.

If the emission brightness of the organic material becomes higher in the future, the light including the output image information can be enlarged and projected by a lens or the like and used in a front type or rear type projector.

The above-mentioned electric appliances are the Internet and C
Information distributed through electronic communication lines such as ATV (cable television) is often displayed, and in particular, opportunities for displaying moving image information are increasing. Since the response speed of organic materials is extremely high, the light emitting device is suitable for displaying moving images.

Since the light emitting device consumes power in the light emitting portion, it is preferable to display information so that the light emitting portion is as small as possible. Therefore, when a light emitting device is used for a display unit mainly for character information such as a mobile information terminal, especially a mobile phone or a sound reproducing device, driving is performed so that the character information is formed by the light emitting portion with the non-light emitting portion as the background. Preferably.

As described above, the applicable range of the light-emitting device manufactured by the manufacturing method of the present invention is so wide that it can be used for electric appliances in all fields. Further, in the electric appliance of this embodiment, the light emitting device manufactured by carrying out the present invention can be used for its display portion.

【The invention's effect】

By using the method for manufacturing a semiconductor device of the present invention, a uniformly planarized film surface can be obtained,
It is possible to provide a semiconductor device that does not depend on the density and size of the pattern that causes the underlying step.

[0167]

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 5 is a sectional view of a conventional semiconductor device.

FIG. 6 is a view showing a conventional polishing rate.

FIG. 7 is a diagram illustrating a configuration of the invention.

FIG. 8 is a diagram showing the measured polishing efficiency of the present invention.

9A to 9C are diagrams illustrating a manufacturing process of a semiconductor device of the present invention.

FIG. 10 is a diagram illustrating a manufacturing process of a semiconductor device of the present invention.

FIG. 11 is a diagram illustrating a manufacturing process of a semiconductor device of the present invention.

FIG. 12 is a diagram illustrating a structure of an inverted staggered TFT.

FIG. 13 is a top view of a semiconductor device of the present invention.

FIG. 14 is a cross-sectional view of a light emitting device of the present invention.

FIG. 15 is a cross-sectional view of a light emitting device of the present invention.

FIG. 16 is a diagram illustrating a configuration of the invention.

FIG. 17 is a diagram showing a configuration of the invention.

FIG. 18 is a diagram showing an example of an electric appliance.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/336 H01L 29/78 627A 23/12 501 601A 29/786 21/88 K F term (reference) 2H092 GA59 JA25 JB58 MA01 NA19 NA29 PA06 3C058 AA07 CA01 CB01 DA12 5F033 GG04 HH08 HH11 HH17 HH18 HH19 HH20 HH21 HH33 JJ08 JJ11 JJ17 JJ18 JJ19 JJ20 JJ21 JJ33 KK04 MM08 MM13 NN06 NN07 PP15 QQ09 QQ16 QQ18 QQ25 QQ46 QQ47 QQ48 RR04 RR08 RR21 RR22 RR26 SS08 SS11 SS15 XX01 5F110 AA26 BB02 BB04 CC02 CC08 DD01 DD02 DD03 DD05 DD13 DD14 DD15 DD17 EE01 EE02 EE03 EE04 EE05 EE06 EE09 EE14 EE15 EE23 FF02 FF04 HJJO GG HJJO GGJ GG01 GG01 GG01 GG01 GG01 GG04 GG01 GG01 GG04 GG01 GG01 GG04 HL04 HL06 HL23 HM15 NN03 NN22 NN23 NN24 NN27 NN28 NN34 NN35 NN40 NN47 NN72 PP01 PP02 PP03 PP04 PP05 PP10 PP13 PP29 PP34 QQ09 QQ11 QQ19 QQ24 QQ25 QQ28

Claims (19)

[Claims] 1. A method of polishing a step of a film having a laminated structure, wherein an opening is formed in the film, and the film in which the opening is formed is polished to a surface of the film having a low step. Polishing method. 2. A method of polishing a step of a film having a laminated structure, wherein an opening is formed only on a surface of the film having a high step, and the film having the opening is polished to a surface of the film having a low step. A polishing method comprising: 3. A polishing method, which comprises forming a film covering a step of an underlayer, forming an opening on the surface of the film, and polishing the film having the opening. 4. A method of forming a film covering a step of an underlayer, forming an opening in the surface of the film, and polishing the film having the opening, wherein the surface of the film has a convex portion and a concave portion. Have
A polishing method comprising forming openings so that the areas of the protrusions are equal. 5. A method of forming a film covering a step of an underlayer, forming an opening in the surface of the film, and polishing the film in which the opening is formed, wherein the surface of the film has a convex portion and a concave portion. Have
The polishing method is characterized in that the opening is formed only in a convex portion of the film. 6. A method of forming a film covering a step of an underlayer, forming an opening in the surface of the film, and polishing the film in which the opening is formed, wherein the surface of the film has a convex portion and a concave portion. Have
A polishing method, wherein the opening is formed in a convex portion of the film, and is not formed in a concave portion of the film, and the film in which the opening is formed is polished to the thickness of the concave portion. 7. The method according to claim 3, wherein
A polishing method, wherein the underlying step is a wiring. 8. The method according to claim 1, wherein
A polishing method comprising polishing the film by a CMP method, a mechanical polishing method or an ELID method. 9. The polishing method according to claim 1, wherein the film is formed by a plasma CVD method, a low pressure CVD method, a thermal CVD method or a sputtering method. 10. The polishing method according to claim 1, wherein the opening is formed by an etching method. 11. The polishing method according to claim 1, wherein the opening is formed so as not to penetrate the film. 12. The polishing method according to claim 1, wherein the plurality of openings have a linear shape, a circular shape, a lattice shape, or a rectangular shape. 13. The polishing method according to claim 1, wherein the openings are formed so that the areas of the openings are equal to each other. 14. The polishing method according to claim 1, wherein the film is made of silicon oxide, silicon oxynitride, or silicon nitride. 15. A thin film transistor in which a semiconductor film is formed on an insulating surface, an insulating film is formed on the semiconductor film, an opening is formed in the surface of the insulating film, and the insulating film having the opening is polished. The thin film transistor has a driving circuit portion and a pixel portion, and the number of openings on the driving circuit portion in the insulating film is larger than the number of openings on the pixel portion. A method for manufacturing a thin film transistor having characteristics. 16. A semiconductor film formed on an insulating surface,
The source region and the drain region are formed through a source region and a drain region formed in the semiconductor film, a first insulating film formed on the semiconductor film, and a contact formed in the first insulating film. In a method for manufacturing a semiconductor device having a wire connected to a wire and a second insulating film formed on the wire, an opening is formed on the surface of the first and second insulating films, and the opening is formed. A method for manufacturing a thin film transistor, which comprises polishing an insulating film in which a portion is formed. 17. The method of manufacturing a thin film transistor according to claim 11, wherein the plurality of openings have a linear shape, a circular shape, a lattice shape, or a rectangular shape. 18. The method for manufacturing a thin film transistor according to claim 11, wherein the insulating film is made of any one of silicon oxide, silicon oxynitride and silicon nitride. 19. The thin film transistor according to claim 11, wherein the diameter of the opening of the insulating film in the drive circuit portion is smaller than the diameter of the opening of the insulating film in the pixel portion. Manufacturing method.