JP2003163194A5 - - Google Patents

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JP2003163194A5
JP2003163194A5 JP2001363190A JP2001363190A JP2003163194A5 JP 2003163194 A5 JP2003163194 A5 JP 2003163194A5 JP 2001363190 A JP2001363190 A JP 2001363190A JP 2001363190 A JP2001363190 A JP 2001363190A JP 2003163194 A5 JP2003163194 A5 JP 2003163194A5
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Japan
Prior art keywords
film
semiconductor device
polishing
manufacturing
opening
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JP2001363190A
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Japanese (ja)
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JP2003163194A (en
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Priority to JP2001363190A priority Critical patent/JP2003163194A/en
Priority claimed from JP2001363190A external-priority patent/JP2003163194A/en
Publication of JP2003163194A publication Critical patent/JP2003163194A/en
Publication of JP2003163194A5 publication Critical patent/JP2003163194A5/ja
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Claims (19)

下地段差を覆う膜を形成し、
前記膜表面に開口部を形成して、前記膜の表面に複数の凸部が設けられた膜を研磨する方法であって、
前記複数の凸部の面積がそれぞれ等しくなるように、前記開口部を形成することを特徴とする研磨方法。Form a film that covers the base step,
A method for polishing a film in which an opening is formed on the film surface and a plurality of protrusions are provided on the surface of the film,
The polishing method , wherein the openings are formed so that the areas of the plurality of convex portions are equal to each other . 下地段差を覆う膜を形成して、前記膜の表面に凹部及び第１の凸部が設けられ、Forming a film that covers the base step, a concave portion and a first convex portion are provided on the surface of the film,
前記第１の凸部に、前記凹部と深さが等しい開口部を形成して、複数の第２の凸部が設けられた膜を研磨する方法であって、A method of forming an opening having the same depth as the concave portion in the first convex portion and polishing a film provided with a plurality of second convex portions,
前記複数の第２の凸部の面積がそれぞれ等しくなるように、前記開口部を形成することを特徴とする研磨方法。The polishing method, wherein the openings are formed so that the areas of the plurality of second convex portions are equal to each other. 請求項１又は２において、前記下地段差は配線であることを特徴とする研磨方法。 3. The polishing method according to claim 1 , wherein the base step is a wiring. 請求項１乃至３のいずれか一において、前記膜は酸化珪素、酸化窒化珪素または窒化珪素からなることを特徴とする研磨方法。In any one of claims 1 to 3, wherein the film is a silicon oxide, a polishing method characterized by comprising the silicon oxynitride or silicon nitride. 請求項１乃至４のいずれか一おいて、前記膜はプラズマＣＶＤ法、減圧ＣＶＤ法、熱ＣＶＤ法またはスパッタ法により形成されることを特徴とする研磨方法。Claim 1 to have any one up for 4, wherein the membrane is a plasma CVD method, reduced pressure CVD method, a polishing method characterized by being formed by a thermal CVD method or a sputtering method. 請求項１乃至５のいずれか一において、エッチング法により前記開口部を形成することを特徴とする研磨方法。In any one of claims 1 to 5, polishing method characterized by forming the opening by an etching method. 請求項１乃至６のいずれか一において、前記複数の開口部の形状は、線状、円状、格子状または矩形状であることを特徴とする研磨方法。In any one of claims 1 to 6, the shape of the plurality of openings, polishing and wherein the linear, circular, lattice or rectangular. 請求項１乃至７のいずれか一において、ＣＭＰ法、機械研磨法又はＥＬＩＤ法により前記膜を研磨することを特徴とする研磨方法。In any one of claims 1 to 7, the polishing method characterized by polishing the film by CMP, mechanical polishing or ELID method. 絶縁表面上に半導体膜を形成し、
前記半導体膜に接続される配線を形成し、
前記半導体膜上に、前記配線を覆って絶縁膜を形成して、前記絶縁膜の表面に凸部が設けられ、
前記凸部に開口部を形成し、
前記開口部が形成された絶縁膜を研磨する半導体装置の作製方法であって、
前記半導体装置は駆動回路部と画素部とを有し、
前記駆動回路部上の開口部の数は、前記画素部上の開口部の数より多いことを特徴とする半導体装置の作製方法。Forming a semiconductor film on the insulating surface;
Forming a wiring connected to the semiconductor film;
On the semiconductor film, an insulating film is formed so as to cover the wiring, and a convex portion is provided on the surface of the insulating film,
Forming an opening in the convex part ,
A method of manufacturing a semiconductor device for polishing an insulating film in which the opening is formed,
The semiconductor device has a drive circuit portion and a pixel portion ,
The number of openings on the front SL driver circuit portion, the method for manufacturing a semiconductor device, characterized in that more than the number of openings on the pixel portion. 絶縁表面上に半導体膜を形成し、Forming a semiconductor film on the insulating surface;
前記半導体膜に接続される配線を形成し、Forming a wiring connected to the semiconductor film;
前記半導体膜上に、前記配線を覆って絶縁膜を形成して、前記絶縁膜の表面に凹部及び凸部が設けられ、On the semiconductor film, an insulating film is formed so as to cover the wiring, and a concave portion and a convex portion are provided on the surface of the insulating film,
前記凸部に、前記凹部と深さが等しい開口部を形成し、An opening having the same depth as the recess is formed in the protrusion,
前記開口部が形成された絶縁膜を研磨する半導体装置の作製方法であって、A method of manufacturing a semiconductor device for polishing an insulating film in which the opening is formed,
前記半導体装置は駆動回路部と画素部とを有し、The semiconductor device has a drive circuit portion and a pixel portion,
前記駆動回路部上の開口部の数は、前記画素部上の開口部の数より多いことを特徴とする半導体装置の作製方法。The method for manufacturing a semiconductor device, wherein the number of openings on the driver circuit portion is larger than the number of openings on the pixel portion. 絶縁表面上に半導体膜を形成し、Forming a semiconductor film on the insulating surface;
前記半導体膜に接続される配線を形成し、Forming a wiring connected to the semiconductor film;
前記半導体膜上に、前記配線を覆って絶縁膜を形成して、前記絶縁膜の表面に第１の凹部及び第１の凸部が設けられ、An insulating film is formed on the semiconductor film so as to cover the wiring, and a first concave portion and a first convex portion are provided on the surface of the insulating film,
前記第１の凸部に、前記第１の凹部と深さが等しい開口部を形成して、前記絶縁膜の表面には第２の凸部が設けられ、An opening having the same depth as the first concave portion is formed in the first convex portion, and a second convex portion is provided on the surface of the insulating film,
前記開口部が形成された絶縁膜を研磨する半導体装置の作製方法であって、A method of manufacturing a semiconductor device for polishing an insulating film in which the opening is formed,
前記半導体装置は駆動回路部と画素部とを有し、The semiconductor device has a drive circuit portion and a pixel portion,
前記駆動回路部上の前記第２の凸部の面積と、前記画素部上の前記第２の凸部の面積とが等しくなるように、前記開口部を形成することを特徴とする半導体装置の作製方法。In the semiconductor device, the opening is formed so that the area of the second protrusion on the driver circuit portion is equal to the area of the second protrusion on the pixel portion. Manufacturing method. 請求項１１において、In claim 11,
前記駆動回路部上の前記第２の凸部の面積と、前記画素部上の前記第２の凸部の面積とが等しくなるように、前記駆動回路部上の開口部の数を前記画素部上の開口部の数より多くすることを特徴とする半導体装置の作製方法。The number of openings on the driving circuit unit is set to the pixel unit so that the area of the second protruding unit on the driving circuit unit is equal to the area of the second protruding unit on the pixel unit. A method for manufacturing a semiconductor device, wherein the number of openings is larger than the number of openings. 請求項１１において、In claim 11,
前記駆動回路部上の前記第２の凸部の面積と、前記画素部上の前記第２の凸部の面積とが等しくなるように、前記画素部上の開口部の幅を前記駆動回路部上の開口部の幅より広くすることを特徴とする半導体装置の作製方法。The width of the opening on the pixel portion is set to the drive circuit portion so that the area of the second convex portion on the drive circuit portion is equal to the area of the second convex portion on the pixel portion. A method for manufacturing a semiconductor device, wherein the width is wider than the width of the upper opening. 絶縁表面上に形成された半導体膜を形成し、
前記半導体膜にソース領域及びドレイン領域を形成し、
前記半導体膜上に第１の絶縁膜を形成し、
前記第１の絶縁膜に形成されたコンタクトを介して前記ソース領域及びドレイン領域のそれぞれに接続される配線を形成し、
前記配線を覆って第２の絶縁膜を形成して、前記第２の絶縁膜の表面には凸部が設けられ、
前記凸部に開口部を形成し、
前記開口部が形成された絶縁膜を研磨する半導体装置の作製方法において、
前記半導体装置は駆動回路部と画素部とを有し、
前記駆動回路部上の開口部の数は、前記画素部上の開口部の数より多いことを特徴とする半導体装置の作製方法。 Forming a semiconductor film formed on an insulating surface,
Forming a source region and a drain region in the semiconductor film,
A first insulating film formed on the semiconductor film,
Via a contact formed in the first insulating film to form a connected Ru wired to each of the source region and the drain region,
A second insulating film is formed to cover the wiring , and a convex portion is provided on the surface of the second insulating film,
Forming an opening in the convex part,
In a method for manufacturing a semiconductor device for polishing an insulating film in which the opening is formed ,
The semiconductor device has a drive circuit portion and a pixel portion ,
The number of openings on the front SL driver circuit portion, the method for manufacturing a semiconductor device, characterized in that more than the number of openings on the pixel portion. 請求項９乃至１４のいずれか一において、前記絶縁膜は酸化珪素、酸化窒化珪素及び窒化珪素のいずれかからなることを特徴とする半導体装置の作製方法。In any one of claims 9 to 14, a method for manufacturing a semiconductor device wherein an insulating film is characterized in that it consists either of silicon oxide, silicon oxynitride and silicon nitride. 請求項９乃至１５のいずれか一おいて、前記膜はプラズマＣＶＤ法、減圧ＣＶＤ法、熱ＣＶＤ法またはスパッタ法により形成されることを特徴とする半導体装置の作製方法。16. The method for manufacturing a semiconductor device according to claim 9, wherein the film is formed by a plasma CVD method, a low pressure CVD method, a thermal CVD method, or a sputtering method. 請求項９乃至１６のいずれか一において、エッチング法により前記開口部を形成することを特徴とする半導体装置の作製方法。The method for manufacturing a semiconductor device according to claim 9, wherein the opening is formed by an etching method. 請求項９乃至１７のいずれか一において、前記複数の開口部の形状は、線状、円状、格子状または矩形状であることを特徴とする半導体装置の作製方法。18. The method for manufacturing a semiconductor device according to claim 9, wherein the plurality of openings have a linear shape, a circular shape, a lattice shape, or a rectangular shape. 請求項９乃至１８のいずれか一において、ＣＭＰ法、機械研磨法又はＥＬＩＤ法により前記膜を研磨することを特徴とする半導体装置の作製方法。The method for manufacturing a semiconductor device according to claim 9, wherein the film is polished by a CMP method, a mechanical polishing method, or an ELID method.
JP2001363190A 2001-11-28 2001-11-28 Polishing method and method for manufacturing semiconductor device Withdrawn JP2003163194A (en)

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Application Number Priority Date Filing Date Title
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JP3646718B2 (en) 2002-10-04 2005-05-11 セイコーエプソン株式会社 Manufacturing method of semiconductor device
JP2008229755A (en) * 2007-03-19 2008-10-02 Ookouchi Kinzoku Kk Cutting tool having dlc coating and its manufacturing method
CN101842871B (en) * 2007-12-18 2013-01-09 夏普株式会社 Semiconductor device manufacturing method and semiconductor device
JP5556232B2 (en) * 2010-02-25 2014-07-23 日本電気株式会社 Estimation apparatus, estimation method, and computer program
JP6127500B2 (en) * 2012-12-21 2017-05-17 セイコーエプソン株式会社 Electro-optical device manufacturing method, electro-optical device, and electronic apparatus
JP6328502B2 (en) * 2013-07-04 2018-05-23 Hoya株式会社 Substrate manufacturing method, mask blank substrate manufacturing method, mask blank manufacturing method, transfer mask manufacturing method, and substrate manufacturing apparatus

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