JP4593256B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT) and a manufacturing method thereof. For example, the present invention relates to a device represented by a liquid crystal display device (mounted with a liquid crystal module) and an electronic device mounted with such a device as a component.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a light-emitting device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and development of switching devices for image display devices is urgently required.

  Conventionally, a liquid crystal display device is known as an image display device. Active matrix liquid crystal display devices are often used because high-definition images can be obtained compared to passive liquid crystal display devices. In an active matrix liquid crystal display device, a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix. Specifically, by applying a voltage between the selected pixel electrode and the counter electrode corresponding to the pixel electrode, optical modulation of the liquid crystal layer disposed between the pixel electrode and the counter electrode is performed. The optical modulation is recognized by the observer as a display pattern.

  Applications of such active matrix liquid crystal display devices are expanding, and demands for higher definition, higher aperture ratio, and higher reliability are increasing as the screen size increases. At the same time, demands for improved productivity and lower costs are increasing.

  Conventionally, when a TFT is manufactured using aluminum as the gate wiring material of the TFT, TFT malfunction and TFT characteristics are caused by the formation of protrusions such as hillocks and whiskers by heat treatment and diffusion of aluminum atoms into the channel formation region. Was causing a decline. Therefore, when using a metal material that can withstand heat treatment, typically a metal element having a high melting point, problems such as increased wiring resistance occur when the screen size is increased, resulting in increased power consumption. And so on.

  Accordingly, an object of the present invention is to provide a structure of a semiconductor device that realizes low power consumption even when the screen is enlarged and a manufacturing method thereof.

The present invention uses a gate electrode structure as a first layer, a material film containing TaN or W as a main component in order to prevent diffusion into a channel formation region, and mainly uses Al, Cu, Ag, or Au as a second layer. By using a low resistance material film as a component and a laminated structure using a material film mainly composed of Ti or TiN as the third layer, the resistance of the wiring is reduced.

The configuration of the invention disclosed in this specification is as follows.
A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film, wherein the gate electrode A pixel portion including a first n-channel TFT having a source wiring made of the same material;
A drive circuit comprising a circuit comprising a second n-channel TFT and a third n-channel TFT;
And a terminal portion made of the same material as the gate electrode.

  In the above structure, the gate electrode includes a material film (first layer) mainly composed of TaN, a material film mainly composed of Al (second layer), and a material film mainly composed of Ti (third layer). Layer).

  Alternatively, in the above structure, the gate electrode includes a material film (first layer) containing W as a main component, a material film (second layer) containing Al as a main component, and a material film containing Ti as a main component (first layer). It has a laminated structure with a third layer).

  Alternatively, in the above structure, the gate electrode includes a material film (first layer) containing W as a main component, a material film (second layer) containing Al as a main component, and a material film containing TiN as a main component ( It has a laminated structure with a third layer).

  With such a gate electrode structure, when an ICP (Inductively Coupled Plasma) etching method is used, the end of the gate electrode can be tapered.

  In the present specification, the taper angle refers to an angle formed by the horizontal plane and the side surface of the material layer. Further, in the present specification, for convenience, a side surface having a taper angle is referred to as a taper shape, and a portion having the taper shape is referred to as a taper portion.

  In the above structure, an EEMOS circuit or an EDMOS circuit is formed by the second n-channel TFT and the third n-channel TFT. In addition, the driving circuit of the present invention is all formed by an NMOS circuit made of an n-channel TFT, and the TFT of the pixel portion is also made of an n-channel TFT, thereby simplifying the process. A general driving circuit is designed on the basis of a CMOS circuit in which an n-channel type semiconductor element and a p-channel type semiconductor element are complementarily combined. In the present invention, however, only a n-channel TFT is combined to drive the driving circuit. Form.

The configuration of the invention for realizing the above structure is as follows.
A method for manufacturing a semiconductor device including a driver circuit, a pixel portion, and a terminal portion on an insulating surface,
Forming a semiconductor layer on the insulating surface;
Forming a first insulating film on the semiconductor layer;
Forming a gate electrode, a source wiring of a pixel portion, and an electrode of a terminal portion on the first insulating film;
Adding an impurity element imparting n-type to the semiconductor layer using the gate electrode as a mask to form an n-type impurity region;
Etching the gate electrode to form a tapered portion;
Forming a second insulating film covering the source wiring and the terminal portion of the pixel portion;
Forming a gate wiring and a source wiring of a driving circuit on the second insulating film;
A method for manufacturing a semiconductor device having

  In the above structure, the step of forming the gate electrode, the source wiring of the pixel portion, and the electrode of the terminal portion forms a material film mainly composed of TaN, forms a material film mainly composed of Al, A feature is that a material film containing Ti as a main component is formed and stacked, and then etched by a mask. In the above structure, the step of forming the gate electrode, the source wiring of the pixel portion, and the electrode of the terminal portion forms a material film mainly composed of W and forms a material film mainly composed of Al. In addition, after forming and laminating a material film containing Ti as a main component, it is formed by etching using a mask.

  Further, according to the present invention, a liquid crystal display device including the pixel portion and the driver circuit having the above structure or a light-emitting device including an OLED having the pixel portion and the driver circuit having the above structure can be manufactured.

  Further, according to the present invention, the manufacturing process of the p-channel TFT is reduced, so that the manufacturing process of the liquid crystal display device or the light emitting device is simplified, and the total manufacturing cost can be reduced.

  According to the present invention, in a semiconductor device typified by an active matrix liquid crystal display device or a light emitting device having an active matrix OLED, a favorable display can be realized even if the area of the pixel portion is increased and the screen size is increased. Since the resistance of the source wiring of the pixel portion is greatly reduced, the present invention can be applied to, for example, a large screen with a diagonal of 40 inches or a diagonal of 50 inches.

  Embodiments of the present invention will be described below.

  First, a base insulating film is formed over a substrate, and then a semiconductor layer having a desired shape is formed by a first photolithography process.

Next, an insulating film (including a gate insulating film) is formed to cover the semiconductor layer. A first conductive film, a second conductive film, and a third conductive film are stacked over the insulating film. These stacked films are subjected to a first etching process by a second photolithography process, and a gate electrode including the first conductive layer and the second conductive layer, a source wiring of the pixel portion, and an electrode of the terminal portion are formed. Form. In the present invention, after the gate electrode is formed first, the gate wiring is formed on the interlayer insulating film.

  Next, while leaving the resist mask formed in the second photolithography process as it is, an impurity element imparting n-type (phosphorus or the like) is added to the semiconductor to form an n-type impurity region (high concentration) in a self-aligning manner. ).

  Next, while the resist mask formed in the second photolithography step is left as it is, a second etching process is performed by changing etching conditions, and a first conductive layer (first width) having a tapered portion is formed. A second conductive layer (second width) and a third conductive layer (third width) are formed. The first width is larger than the second width, and the second width is larger than the third width. The electrode composed of the first conductive layer, the second conductive layer, and the third conductive layer here becomes a gate electrode (first gate electrode) of the n-channel TFT.

  As the first conductive layer in contact with the insulating film, a material film containing TaN or W as a main component may be used in order to prevent diffusion into the channel formation region. Further, as the second conductive layer, a low-resistance material film containing Al, Cu, Ag, or Au as a main component may be used. Further, as the third conductive layer, a material film mainly containing Ti with low contact resistance may be used.

  Note that W, which is a material having a relatively low electric resistance value, is used for the first conductive layer, and aluminum (Al—Si) containing 2 wt% Si having high heat resistance is used for the second conductive layer. It is preferable to use Ti as the third conductive layer to further increase the heat resistance of the second conductive layer. However, when Ti is used for the third conductive layer, if heat treatment at 350 ° C. or higher is performed in a subsequent process (such as thermal activation process), alloying occurs at the Ti / Al—Si interface, resulting in high resistance. Therefore, when heat treatment at 350 ° C. or higher is performed in a later step, it is preferable to use TiN as the third conductive layer. In addition, when laser light is irradiated in a later step (laser activation treatment or the like), nitride easily absorbs laser light and may damage the irradiated surface. Therefore, TiN is used as the third conductive layer. Further, by using Ti as the fourth conductive layer, damage due to laser light can be protected.

  Next, after removing the resist mask, an impurity element imparting n-type conductivity is added to the semiconductor layer through the insulating film using the first gate electrode as a mask.

  Thereafter, a resist mask is formed by a third photolithography method, and an impurity element imparting n-type conductivity is selectively added to reduce the off-state current of the TFT in the pixel portion.

Next, an interlayer insulating film is formed, and a transparent conductive film is formed. Next, the transparent conductive film is patterned by a fourth photolithography method to form a pixel electrode. Next, a contact hole is formed by a fifth photolithography process. Here, a contact hole reaching the impurity region, a contact hole reaching the gate electrode, and a contact hole reaching the source wiring are formed.

  Next, a conductive film made of a low-resistance metal material is formed, and an electrode that connects the gate wiring, the source wiring, and the impurity region, and an electrode that connects the pixel electrode and the impurity region are formed by a sixth photolithography process. . In the present invention, the gate wiring is electrically connected to the first gate electrode or the second gate electrode through a contact hole provided in the interlayer insulating film. The source wiring is electrically connected to the impurity region (source region) through a contact hole provided in the interlayer insulating film. An electrode connected to the pixel electrode is electrically connected to the impurity region (drain region) through a contact hole provided in the interlayer insulating film.

  Thus, a total of six photolithography steps, that is, a pixel portion having pixel TFTs (n-channel TFTs) with six masks, and an EEMOS circuit (n-channel TFT) as shown in FIG. An element substrate including the driving circuit can be formed. Note that although an example in which a transmissive display device is manufactured is shown here, a reflective display device can also be manufactured by using a highly reflective material for a pixel electrode. In the case of manufacturing a reflective display device, an element substrate can be formed with five masks because it can be formed at the same time as a gate wiring.

  An active matrix light-emitting device having an OLED (Organic Light Emitting Device) can also be manufactured. Also in the light-emitting device, the driver circuit is all formed by n-channel TFTs, and the pixel portion is also formed by a plurality of n-channel TFTs. In a light emitting device using an OLED, at least a TFT that functions as a switching element and a TFT that supplies current to the OLED are provided in each pixel. A TFT that is electrically connected to the OLED and supplies current to the OLED is an n-channel TFT regardless of the circuit configuration of the pixel and the driving method.

  The OLED has a layer (hereinafter, referred to as an organic light emitting layer) containing an organic compound (organic light emitting material) capable of obtaining luminescence generated by applying an electric field, an anode, and a cathode. Luminescence in organic compounds includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. Any one of the above-described light emission may be used, or both light emission may be used.

  In this specification, all layers formed between the anode and the cathode of the OLED are defined as organic light emitting layers. Specifically, the organic light emitting layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, the OLED has a structure in which an anode / light emitting layer / cathode is laminated in this order. In addition to this structure, the anode / hole injection layer / light emitting layer / cathode and the anode / hole injection layer / The light emitting layer / electron transport layer / cathode may be stacked in this order.

  In the case of forming an EDMOS circuit as shown in FIG. 7B by combining the enhancement type and the depletion type, a mask is formed in advance before forming the conductive film, and a periodic table is formed on the semiconductor to be a channel formation region. An element belonging to Group 15 (preferably phosphorus) or an element belonging to Group 13 of the periodic table (preferably boron) may be selectively added. In this case, the element substrate can be formed with seven masks.

  Although an n-channel TFT has been described here, it goes without saying that a p-channel TFT can be formed by using a p-type impurity element instead of an n-type impurity element. In that case, the driver circuits are all formed by p-channel TFTs, and the pixel portion is also formed by p-channel TFTs.

  The present invention having the above-described configuration will be described in more detail with the following examples.

  An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel portion and a driver circuit TFT (only an n-channel TFT) provided around the pixel portion on the same substrate will be described in detail.

  In FIG. 1A, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used as the substrate 100. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate with an insulating film formed thereon may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.

Then, as shown in FIG. 1A, a base insulating film 101 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO _x N _y ) is formed on the substrate 100. As a typical example, the base insulating film 101 has a two-layer structure, and a first silicon oxynitride film 101a formed using SiH ₄ , NH ₃ , and N ₂ O as a reaction gas is formed in a thickness of 50 to 100 nm, SiH ₄ , and A structure is employed in which the second silicon oxynitride film 101b formed using N ₂ O as a reactive gas is stacked to a thickness of 100 to 150 nm. Alternatively, a silicon nitride film with a thickness of 10 nm or less may be used as the base insulating film 101. In the case of using a silicon nitride film, in addition to the effect as a blocking layer, there is also an effect of improving gettering efficiency in a gettering step performed later. Since nickel tends to move to a region having a high oxygen concentration during gettering, it is extremely effective to use a silicon nitride film as the base insulating film in contact with the semiconductor film. Alternatively, a three-layer structure in which a first silicon oxynitride film, a second silicon oxynitride film, and a silicon nitride film are sequentially stacked may be used.

  The semiconductor film used as the active layer is obtained by crystallizing an amorphous semiconductor film formed over the base film 101. The amorphous semiconductor film is formed with a thickness of 30 to 60 nm, and then a catalytic metal element (nickel in this embodiment) that promotes crystallization is converted to weight on the surface of the amorphous semiconductor film. A catalyst-containing layer is formed by applying a nickel acetate salt solution containing 1 to 100 ppm of nickel with a spinner.

  Heat treatment for crystallization is performed while keeping the amorphous semiconductor film and the catalytic element-containing layer in contact with each other. In this embodiment, heat treatment is performed by the RTA method. The lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and this is repeated 1 to 10 times, preferably 2 to 6 times. The emission intensity of the lamp light source is arbitrary, but the semiconductor film is instantaneously heated to 600 to 1000 ° C., preferably about 650 to 750 ° C. Even at such a high temperature, the semiconductor film is only heated instantaneously, and the substrate 100 itself is not distorted and deformed. Thus, the amorphous semiconductor film can be crystallized to obtain a crystalline semiconductor film.

Further, in order to increase the crystallization rate (ratio of the crystal component in the total volume of the film) and repair defects remaining in the crystal grains, the crystalline semiconductor film is irradiated with laser light. As the laser, it is also possible to use excimer laser light having a wavelength of 400 nm or less, and second harmonic and third harmonic of a YAG laser. In any case, a pulsed laser beam having a repetition frequency of about 10 to 1000 Hz is used, and the laser beam is condensed to 100 to 400 mJ / cm ² by an optical system, and the crystalline semiconductor film has an overlap ratio of 90 to 95%. Laser processing for 104 may be performed.

Although an example using a pulsed laser is shown here, a continuous wave laser may be used, and in order to obtain a crystal with a large grain size when crystallizing an amorphous semiconductor film, continuous wave is possible. It is preferable to use a solid-state laser and apply the second to fourth harmonics of the fundamental wave. Typically, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) may be applied. In the case of using a continuous wave laser, laser light emitted from a continuous wave YVO ₄ laser having an output of 10 W is converted into a harmonic by a non-linear optical element. There is also a method of emitting harmonics by putting a YVO ₄ crystal and a nonlinear optical element in a resonator. Preferably, the laser beam is shaped into a rectangular or elliptical shape on the irradiation surface by an optical system, and the object to be processed is irradiated. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation may be performed by moving the semiconductor film relative to the laser light at a speed of about 10 to 2000 cm / s.

Note that here, a technique of irradiating laser light after performing thermal crystallization using nickel as a metal element for promoting crystallization of silicon is used. However, a pulsed excimer laser without adding nickel, or The amorphous silicon film may be crystallized with a continuous wave laser (second harmonic of YVO ₄ laser).

  Next, in order to remove the catalytic element contained in the crystalline semiconductor film, the following gettering treatment is performed. A barrier layer is formed on the crystalline semiconductor film. As the barrier layer, when heat treatment is performed, the catalytic element (nickel) can be moved to the gettering site, and a porous film that does not soak the etching solution used in the step of removing the gettering site is formed. For example, a chemical oxide film or silicon oxide film (SiOx) formed by treatment with ozone water may be used. In the present specification, a film having such properties is particularly referred to as a porous film.

Next, a semiconductor film containing a rare gas element is formed as a gettering site. In this embodiment, the rare gas element is added at 1 × 10 ¹⁹ to 1 × 10 ²² / cm at the stage where the film is formed by plasma CVD or sputtering, or is added by ion doping or ion implantation after film formation. ^3. Preferably, a semiconductor film containing a concentration of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ is formed.

  Thereafter, a heat treatment such as an RTA method using a lamp light source or a heat treatment using a furnace is performed to move the catalyst element to the gettering site in the vertical direction. This heat treatment also serves as annealing. As heating conditions, the lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and this is repeated 1 to 10 times, preferably 2 to 6 times. The emission intensity of the lamp light source is arbitrary, but the semiconductor film is instantaneously heated to 600 to 1000 ° C., preferably about 700 to 750 ° C.

After the gettering step is completed, the gettering site made of an amorphous semiconductor is selectively etched and removed. As an etching method, dry etching without using plasma with ClF ₃ or wet etching with an alkaline solution such as an aqueous solution containing hydrazine or tetraethylammonium hydroxide (chemical formula (CH ₃ ) ₄ NOH) can be performed. At this time, the barrier layer 106 functions as an etching stopper. The barrier layer 106 may be removed with hydrofluoric acid thereafter. In order to improve crystallization, laser light may be irradiated after the crystallization step.

  After that, the obtained crystalline semiconductor film is etched into a desired shape to form semiconductor layers 102 to 106 separated into island shapes.

  Further, after forming the semiconductor layers 102 to 106, an impurity element imparting p-type conductivity may be added in order to control the threshold value (Vth) of the n-channel TFT. As an impurity element imparting p-type to a semiconductor, periodic group 13 elements such as boron (B), aluminum (Al), and gallium (Ga) are known.

  Next, a gate insulating film 107 is formed to cover the semiconductor layers 102 to 106 separated in an island shape. The gate insulating film 107 is formed by a plasma CVD method or a sputtering method, and is formed of an insulating film containing silicon with a thickness of 40 to 150 nm. Needless to say, this gate insulating film can be formed using an insulating film containing silicon as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Ortho Silicate) and O ₂ are mixed by a plasma CVD method to a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.56 MHz) power density of 0.5 to It can be formed by discharging at 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. after formation.

  Over the gate insulating film 107, a film 108a containing tungsten (W) as a main component as a first conductive film with a thickness of 20 to 100 nm and aluminum (Al) as a second conductive film with a thickness of 100 to 500 nm are mainly used. A film 108b as a component and a film 108c containing titanium (Ti) as a main component as a third conductive film having a thickness of 20 to 100 nm are stacked. The total film thickness of the stack formed of these conductive films is preferably less than 600 nm in terms of the level difference when considering the subsequent steps. Here, a 50-nm-thick tungsten film, a 500-nm-thick aluminum-titanium alloy (Al—Ti) film, and a 30-nm-thick titanium film are sequentially stacked over the gate insulating film 107.

Note that the conductive material of the first conductive film, the second conductive film, or the third conductive film, which is to be a gate electrode by subsequent etching, is not limited to the above materials, and Ta, W, Ti, Mo, Al An element selected from Cu, or an alloy material or a compound material containing the element as a main component can be used as appropriate. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used as the first conductive film. For example, a combination in which the first conductive film is formed of a tungsten (W) film, the second conductive film is an alloy of aluminum and silicon (Al-Si) film, and the third conductive film is a titanium nitride (TiN) film. Alternatively, the first conductive film is formed of a tungsten (W) film, the second conductive film is a Cu film, and the third conductive film is a titanium (Ti) film, or the first conductive film is tantalum ( TaN) film, and the second conductive film is an aluminum (Al-Ti) film and the third conductive film is a titanium (Ti) film, or the first conductive film is a tantalum nitride (TaN) film. The second conductive film is an aluminum (Al-Ti) film, the third conductive film is a titanium nitride (TiN) film, or the first conductive film is a tantalum nitride (TaN) film. The second conductive film is a Cu film, and the third conductive film is Film may be used as the combination of titanium (Ti).

Next, as shown in FIG. 1B, masks 110 to 115 made of resist are formed by a light exposure process, and a first etching process for forming gate electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. For etching, an ICP (Inductively Coupled Plasma) etching method may be used. Using the ICP etching method, the film is formed into a desired taper shape by appropriately adjusting the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the electrode temperature on the substrate side, etc.) Can be etched. As an etching _{gas, Cl 2, BCl 3, SiCl} 4, CCl 4 chlorine gas or CF ₄ to the typified like, SF _6, fluorine-based gas NF ₃ and the like typified, or O ₂ as appropriate Can be used.

There is no limitation on the etching gas to be used, but here it is suitable to use BCl ₃ , Cl ₂ and O ₂ . Each gas flow rate ratio is 65/10/5 (sccm), 450 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa, plasma is generated, and etching is performed for 117 seconds. Do. 300 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The electrode area size on the substrate side is 12.5 cm × 12.5 cm, and the coil-type electrode area size (here, a quartz disk provided with a coil) is a disk having a diameter of 25 cm. The Al—Ti film and the titanium film are etched under the first etching conditions so that the ends of the second conductive film and the third conductive film are tapered. Note that the etching rates of the Al—Ti film and the titanium film under the first etching conditions are substantially the same.

Thereafter, the etching conditions are changed to the second etching condition, and CF ₄ , Cl ₂ and O ₂ are used as etching gases, the respective gas flow ratios are set to 25/25/10 (sccm), and the coil type pressure is set to 1 Pa. An RF (13.56 MHz) power of 500 W is applied to the electrode to generate plasma and perform etching for about 30 seconds. 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film, the Al—Ti film, and the titanium film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.

  In the first etching process, the first conductive layer, the second conductive layer, and the third conductive layer are formed by the effect of the bias voltage applied to the substrate side by making the shape of the resist mask suitable. The end of the layer is tapered. The angle of this taper portion is 15 to 45 °. In this manner, the first shape conductive layers 117 to 122 (the first conductive layers 1117a to 1122a and the second conductive layer formed of the first conductive layer, the second conductive layer, and the third conductive layer are formed by the first etching process. Conductive layers 117b to 122b and third conductive layers 117c to 122c) are formed. Reference numeral 116 denotes a gate insulating film, and a region that is not covered with the first shape conductive layers 117 to 122 is etched and thinned by about 20 to 50 nm.

  Here, a sample was prepared and an etching condition experiment was performed. As a sample, a tungsten film having a film thickness of 50 nm, an aluminum-titanium alloy (Al—Ti) film having a film thickness of 500 nm, and a titanium film having a film thickness of 30 nm are sequentially stacked on a quartz substrate as in this embodiment. FIG. 13 shows a photograph taken by SEM immediately after etching under the same conditions as in the first etching process. Therefore, the shape of the conductive layer shown in FIG. 13 can be regarded as the first shape of the conductive layer.

Next, a second etching process is performed as shown in FIG. 1C without removing the masks 110 to 115 made of resist. BCl ₃ and Cl ₂ are used as etching gases, the gas flow ratio is 20/60 (sccm), and 600 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa. Etching is performed by generating plasma. 100 W of RF (13.56 MHz) power is applied to the substrate side (sample stage). The second conductive layer and the third conductive layer are etched under the third etching condition for the second etching process. In this manner, the aluminum film containing a small amount of titanium and the titanium film are anisotropically etched under the third etching condition to conduct the second shape conductive layers 124 to 129 (the first conductive layers 124a to 129a and the second conductive layer). Layers 124b-129b and third conductive layers 124c-12
9c) is formed. 123 is a gate insulating film, and a region not covered with the second shape conductive layers 117 to 122 is slightly etched to form a thinned region. In FIGS. 1B and 1C, the length of the tapered portion of the first conductive layer is shown to be the same. However, since there is a dependency on the wiring width, the first conductive layer is actually dependent on the wiring width. The length of the taper portion of one conductive layer changes.

  Here again, a sample was prepared and an etching condition experiment was conducted. As a sample, a tungsten film having a film thickness of 50 nm, an aluminum-titanium alloy (Al—Ti) film having a film thickness of 500 nm, and a titanium film having a film thickness of 30 nm are sequentially stacked on a quartz substrate as in this embodiment. FIG. 14 is a photographic view observed by SEM immediately after performing the etching under the same conditions as the first etching process and further performing the second etching process. Therefore, the shape of the conductive layer shown in FIG. 14 can be regarded as the second shape of the conductive layer.

  In this embodiment, the first etching process (first etching condition and second etching condition) and the second etching process (third etching condition) were continuously performed without exposure to the atmosphere. Although an example has been shown, the present invention is not particularly limited, and after etching is taken out from the chamber, the reaction gas and the like are exhausted, and then placed in the chamber again, and etching may be sequentially performed under different conditions.

Then, a first doping process is performed without removing the resist mask, and an impurity element imparting n-type conductivity is added to the semiconductor layer. Note that the resist mask may be removed before the first doping process. The doping process may be performed by an ion doping method, a laser doping method, or an ion implantation method. The condition of the ion doping method is the dosage of ^{1.5 × 10 14 atoms / cm 2} , the accelerating voltage of 60～100KeV. As the impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As) is used. In this case, the second shape conductive layers 124 to 128 serve as a mask for the impurity element imparting n-type, and the first impurity regions 123 to 127 are formed in a self-aligning manner. An impurity element imparting n-type conductivity is added to the first impurity regions 130 to 134 in a concentration range of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ .

  Next, as shown in FIG. 2A, masks 135 and 136 made of resist are formed, and a second doping process is performed. The mask 135 is a mask that protects the channel formation region of the semiconductor layer that forms one of the n-channel TFTs of the driver circuit and its peripheral region, and the mask 136 is the channel formation region of the semiconductor layer that forms the TFT of the pixel portion. And a mask for protecting the surrounding area. In FIG. 2A, for the sake of convenience, the length of the tapered portion of the first conductive layer is illustrated as being the same, but actually, the length of the tapered portion of the first conductive layer varies depending on the wiring width. ing. Therefore, when a plurality of wirings having different wiring widths are provided on the same substrate, the widths of the doped regions are also different.

The condition of the ion doping method in the second doping process is that the dose is 1.5 × 10 ¹⁵ atoms / cm ² , the acceleration voltage is 60 to 100 keV, and phosphorus (P) is doped. Here, an impurity region is formed in each semiconductor layer by using a difference in film thickness between the second shape conductive layers 124 to 128 and the gate insulating film 123. Of course, phosphorus (P) is not added to the region covered with the masks 135 and 136. Thus, second impurity regions 180 to 182 and third impurity regions 137 to 141 are formed. An impurity element imparting n-type conductivity is added to the third impurity regions 137 to 141 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . The second impurity region is formed at a lower concentration than the third impurity region due to the difference in film thickness of the gate insulating film, and imparts n-type in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ^3. Impurity elements are added.

  Through the above steps, an impurity region having n-type conductivity is formed in each semiconductor layer. The second shape conductive layers 124 to 127 serve as gate electrodes. In addition, the second shape conductive layer 128 serves as one electrode forming a storage capacitor in the pixel portion. Further, the second shape conductive layer 129 forms a source wiring in the pixel portion.

  Next, a first interlayer insulating film 151 that covers substantially the entire surface is formed. The first interlayer insulating film 151 is formed of an insulating film containing silicon and hydrogen with a thickness of 100 to 200 nm by using a plasma CVD method or a sputtering method. A suitable example is a silicon oxynitride film with a thickness of 150 nm formed by a plasma CVD method. Needless to say, the first interlayer insulating film 151 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Thereafter, a step of activating the impurity element added to each semiconductor layer is performed. This activation is realized by performing heat treatment using a furnace annealing furnace or a clean oven. The temperature of the heat treatment is 400 to 700 ° C., typically 410 to 500 ° C. in a nitrogen atmosphere. In the case of performing such thermal activation, it is preferable to use titanium nitride instead of titanium which is a material of the third layer of the conductive layer in order to improve heat resistance. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can also be applied.

  Simultaneously with the activation treatment, nickel used as a catalyst in crystallization is gettered with the third impurity regions 137 to 141 containing high concentration of phosphorus, and the nickel concentration in the semiconductor layer mainly serving as a channel formation region is increased. Reduced. As a result, a TFT having a channel formation region has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.

  Next, as shown in FIG. 3, a second interlayer insulating film 152 made of an organic insulating material is formed on the first interlayer insulating film 151. Next, a contact hole reaching the source wiring 127 and a contact hole reaching each impurity region are formed.

  Thereafter, wirings and pixel electrodes are formed using Al, Ti, Mo, W, or the like. For example, a laminated film of a Ti film having a thickness of 50 to 250 nm and an alloy film (alloy film of Al and Ti) having a thickness of 300 to 500 nm is used. In this way, source or drain wirings 153 to 158, a gate wiring 160, a connection wiring 159, a pixel electrode 161, and a capacitor wiring 162 are formed.

  As described above, the driver circuit 406 including the n-channel TFT 401, the n-channel TFT 402, and the n-channel TFT 403, and the pixel portion 407 including the n-channel TFT 404 and the storage capacitor 405 can be formed over the same substrate. it can. In this specification, such a substrate is referred to as an active matrix substrate for convenience. Note that the n-channel TFT 401 and the n-channel TFT 403 have the same structure.

  Further, in the conventional method, depending on the doping conditions, the impurity element may wrap around below the gate electrode, resulting in an impurity region overlapping the gate electrode and having a concentration gradient of about 0.1 μm. The embodiment is 0.5 μm or more, preferably 1 μm or more, which is different from the conventional TFT structure.

The n-channel TFT 402 includes a channel formation region 165, a second impurity region 166 that does not partially overlap with the second shape conductive layer 125 that forms a gate electrode, and a third impurity region 167 that functions as a source region or a drain region. have.

  The n-channel TFT 403 includes a channel formation region 168, a second impurity region 169 partially overlapping with the second shape conductive layer 126 forming a gate electrode, and a third impurity region 170 functioning as a source region or a drain region. have.

  These n-channel TFTs form a shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, and the like. In particular, the structure of the n-channel TFT 401 or 403 is suitable for a buffer circuit having a high driving voltage in order to prevent deterioration due to the hot carrier effect.

  A pixel TFT 404 in the pixel portion 407 includes a channel formation region 171, a first impurity region 172 formed outside the second shape conductive layer 128 forming a gate electrode, and a third region functioning as a source region or a drain region. An impurity region 173 is provided. A third impurity region 176 and a second impurity region 177 are formed in the semiconductor layer functioning as one electrode of the storage capacitor 405. The storage capacitor 405 is formed of a capacitor wiring 162 and a semiconductor layer 106 using an insulating film (the same film as the gate insulating film) as a dielectric.

  A top view of such a pixel portion 407 is shown in FIG. FIG. 4 shows a top view of almost one pixel, and the reference numerals given are the same as those in FIG. Further, the cross-sectional structures taken along the lines AA ′ and BB ′ correspond to FIG. In the pixel structure of FIG. 4, by forming the gate wiring and the gate electrode on different layers, the gate wiring and the semiconductor layer can be overlapped, and a function as a light shielding film is added to the gate wiring. In addition, the end of the pixel electrode is arranged so as to overlap with the source wiring so that the gap between the pixel electrodes is shielded from light, and the formation of the light shielding film (black matrix) can be omitted. As a result, the aperture ratio can be improved as compared with the conventional case.

  In this embodiment, a process for manufacturing a liquid crystal module from the active matrix substrate obtained in Embodiment 1 will be described below.

  An alignment film is formed on the active matrix substrate of FIG. 3 and a rubbing process is performed. In this embodiment, before the alignment film is formed, columnar spacers for maintaining the distance between the substrates are formed at desired positions by patterning an organic resin film such as an acrylic resin film. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.

  Next, a counter substrate is prepared. The counter substrate is provided with a color filter in which a colored layer and a light shielding layer are arranged corresponding to each pixel. Further, a light shielding layer was also provided in the drive circuit portion. A flattening film covering the color filter and the light shielding layer was provided. Next, a counter electrode made of a transparent conductive film was formed on the planarizing film in the pixel portion, an alignment film was formed on the entire surface of the counter substrate, and a rubbing process was performed.

  Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are bonded together with a sealant. A filler is mixed in the sealing material, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material is injected between both substrates and completely sealed with a sealant. A known liquid crystal material may be used as the liquid crystal material. In this way, the liquid crystal module is completed. If necessary, the active matrix substrate or the counter substrate is divided into a desired shape. Furthermore, a polarizing plate or the like was appropriately provided using a known technique. And FPC was affixed using the well-known technique.

  The structure of the liquid crystal module thus obtained will be described with reference to the top view of FIG.

The top view shown in FIG. 5 is a pixel portion, a drive circuit, an external input terminal 209 for attaching an FPC (Flexible Printed Circuit Board: Flexible Printed Circuit) 211, a wiring 210 for connecting the external input terminal to the input portion of each circuit, and the like. The active matrix substrate on which the substrate is formed and the counter substrate 200 provided with a color filter or the like are attached to each other with a sealant 207 interposed therebetween.

  A light shielding layer 203a is provided on the counter substrate side so as to overlap with the gate wiring side driving circuit 201a, and a light shielding layer 803b is formed on the counter substrate side so as to overlap with the source wiring side driving circuit 201b. In addition, the color filter 202 provided on the counter substrate side over the pixel portion 205 includes a light-shielding layer and a colored layer of each color of red (R), green (G), and blue (B) corresponding to each pixel. It has been. When actually displaying, a color display is formed with three colors of a red (R) colored layer, a green (G) colored layer, and a blue (B) colored layer. It shall be arbitrary.

  Here, the color filter 202 is provided on the counter substrate for colorization; however, the present invention is not particularly limited. When an active matrix substrate is manufactured, a color filter may be formed on the active matrix substrate.

  In addition, a light-shielding layer is provided between adjacent pixels in the color filter to shield light other than the display area. Here, the light shielding layers 203a and 203b are also provided in the region covering the driver circuit. However, the region covering the driver circuit is covered with a cover when the liquid crystal display device is incorporated later as a display portion of an electronic device. It is good also as a structure which does not provide a light shielding layer. Further, when the active matrix substrate is manufactured, a light shielding layer may be formed on the active matrix substrate.

  Further, without providing the light-shielding layer, the light-shielding layer is appropriately disposed between the counter substrate and the counter electrode so as to be shielded from light by stacking a plurality of colored layers constituting the color filter. Or the drive circuit may be shielded from light.

  Further, an FPC 211 made of a base film and wiring is bonded to the external input terminal with an anisotropic conductive resin. Furthermore, the mechanical strength is increased by the reinforcing plate.

  The liquid crystal module manufactured as described above can be used as a display portion of various electronic devices.

  In Example 1, an example of a reflective display device in which a pixel electrode is formed of a reflective metal material is shown. However, in this embodiment, a transmissive display in which a pixel electrode is formed of a light-transmitting conductive film. An example of the apparatus is shown in FIG. When the pixel electrode is formed using a transparent conductive film, a transmissive display device can be formed although the number of photomasks is increased by one.

After an interlayer insulating film is formed according to Embodiment 1, a pixel electrode made of a light-transmitting conductive film is formed. As the light-transmitting conductive film, ITO (indium tin oxide alloy), indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like may be used.

Thereafter, contact holes are formed in the interlayer insulating film. Next, a connection electrode overlapping with the pixel electrode is formed. This connection electrode is connected to the drain region through a contact hole. In addition, the source electrode or drain electrode of another TFT is formed simultaneously with this connection electrode.

  Although an example in which all the drive circuits are formed on the substrate is shown here, several ICs may be used as part of the drive circuit.

  An active matrix substrate is formed as described above. Using this active matrix substrate, a liquid crystal module is manufactured according to Example 2, and a backlight 310 and a light guide plate 311 are provided and covered with a cover 312. Thus, the active matrix liquid crystal display device shown in FIG. Note that the cover 312 and the liquid crystal module are bonded together using an adhesive or an organic resin. In addition, when the substrate and the counter substrate are bonded to each other, the organic resin may be filled between the frame and the substrate by being surrounded by a frame and bonded. Further, since it is a transmissive type, the polarizing plate 309 is attached to both the active matrix substrate and the counter substrate.

The n-channel TFT shown in Example 1 is obtained by adding an element belonging to Group 15 of the periodic table (preferably phosphorus) or an element belonging to Group 13 of the periodic table (preferably boron) to the semiconductor serving as a channel formation region. The enhancement type and the depression type can be created separately.

  When an NMOS circuit is formed by combining n-channel TFTs, an enhancement type TFT is formed (hereinafter referred to as an EEMOS circuit), and an enhancement type and a depression type are combined (hereinafter referred to as an EDMOS circuit). Called).

Here, FIG. 7A shows an example of an EEMOS circuit, and FIG. 7B shows an example of an EDMOS circuit. In FIG. 7A, reference numerals 31 and 32 denote enhancement-type n-channel TFTs (hereinafter referred to as E-type NTFTs). In FIG. 7B, 33 is an E-type NTFT, and 34 is a depletion type n-channel TFT (hereinafter referred to as a D-type NTFT).

  7A and 7B, VDH is a power supply line to which a positive voltage is applied (positive power supply line), and VDL is a power supply line to which a negative voltage is applied (negative power supply line). . The negative power source line may be a ground potential power source line (ground power source line).

  Further, FIG. 8 shows an example in which a shift register is manufactured using the EEMOS circuit shown in FIG. 7A or the EDMOS circuit shown in FIG. In FIG. 8, 40 and 41 are flip-flop circuits. Reference numerals 42 and 43 denote E-type NTFTs. A clock signal (CL) is input to the gate of the E-type NTFT 42, and a clock signal (CL bar) having an inverted polarity is input to the gate of the E-type NTFT 43. Reference numeral 44 denotes an inverter circuit. As shown in FIG. 8B, the EEMOS circuit shown in FIG. 7A or the EDMOS circuit shown in FIG. 7B is used. Therefore, it is also possible to configure all the drive circuits of the display device with n-channel TFTs.

  Note that this embodiment can be freely combined with any one of Embodiments 1 to 3.

In this embodiment, a pixel structure (IPS method) different from that in Embodiment 1 is shown in FIG. 9, and a cross-sectional structure is shown in FIG. A-A 'sectional view and H-H' sectional view are shown, respectively.

  This embodiment shows an example of an active matrix liquid crystal display device of an IPS (In-Plane Switching) method (also referred to as a horizontal electric field method). The IPS method is characterized in that both a pixel electrode and a common wiring (hereinafter referred to as a common wiring) are formed on one substrate and an electric field is applied in the lateral direction, and the major axis of liquid crystal molecules is almost on the substrate surface. The orientation is controlled in a parallel direction. By using this IPS system, the viewing angle can be widened.

  9, 1101 is a first semiconductor layer, 1102 and 1103 are second semiconductor layers, 1104 is a first electrode, 1105 is a second electrode, 1106 is a source wiring, 1107 is a gate wiring, 1108 and 1109 are Common wiring, 1110 is a connection electrode, and 1111 is a pixel electrode. Note that the pixel electrode and the common wiring are arranged so that an electric field parallel to the substrate surface is generated. Further, the common wiring is disposed so as to overlap with the source wiring, and the aperture ratio of the pixel portion is improved.

  As shown in FIG. 10, the first electrode 1104, the second electrode 1105, and the source wiring 1106 are simultaneously formed on the insulating film covering the first semiconductor layer and the second semiconductor layer. Further, the pixel electrode 1111, the connection electrode 1110, the gate wiring 1107, and the common wiring 1109 are simultaneously formed on an interlayer insulating film that covers the source wiring.

  Further, the first electrode is electrically connected to the gate wiring, and the first electrode overlapping with the first semiconductor layer functions as a gate electrode.

  In this embodiment, a rectangular pixel electrode is shown. However, the pixel electrode and the common electrode may be formed into a U-shaped electrode structure to further widen the viewing angle.

  The storage capacitor is formed by the second semiconductor layer, the insulating film covering the second semiconductor layer, and the second electrode. This second electrode is electrically connected to the gate wiring of the adjacent pixel. In addition, an impurity element imparting n-type conductivity is added to the second semiconductor layer.

The present embodiment has a pixel configuration that can be obtained in the same process as the first embodiment if the mask pattern of the first embodiment is changed.

  After obtaining the state shown in FIG. 9 and FIG. 10 using Example 1, a liquid crystal display device is obtained by the method shown in Example 2. The gap between the pixels is shielded by using a color filter provided on the counter substrate as in the second embodiment. However, in order to use the IPS system, it is necessary to change the alignment process.

  In this embodiment, in the TFT (channel length: L / channel width: W = 10 μm / 8 μm) of the drive circuit obtained in Embodiment 1, the length in the channel length direction of the impurity region (also referred to as Lov region) overlapping with the gate electrode The relationship between reliability and reliability.

  Here, it is assumed that the time until the maximum mobility (μFE (max)) of the TFT when the length of the Lov region is a certain length fluctuates by 10% is the lifetime of the TFT, and the reciprocal of the drain voltage. Are plotted on a semi-logarithmic graph, and the value of the drain voltage with a lifetime of 10 years is derived as a 10-year guaranteed voltage from the obtained linear relationship.

  In this embodiment, the on-current value of the TFT when the length of the Lov region in the channel length direction (also referred to as Lov length) is 0.5 μm, 0.78 μ, 1 μm, 1.5 μm, and 1.7 μm. Is assumed to be the lifetime of the TFT, and the reciprocal of the drain voltage is plotted on a semilogarithmic graph, and the value of the drain voltage at which the lifetime is 10 years is obtained from the linear relationship obtained is 10 years. The result obtained by deriving as the guaranteed voltage is shown in FIG.

  FIG. 15 also shows the result of obtaining the drain voltage value that takes 20 hours until the on-current value of the TFT fluctuates by 10% in the transient stress test as the 20-hour guaranteed voltage.

  As shown in FIG. 15, the length of the Lov region of an n-channel TFT that is 19.2 V (16 × 1.2) or more when a 20% margin is considered assuming that it is used in a 16 V system device. The 20-hour guaranteed voltage is preferably 1 μm or more, and the 10-year guaranteed voltage is preferably 1.5 μm or more.

In this embodiment, an example in which a light-emitting display device including an organic light-emitting element (OLED: Organic Light Emitting Device) is manufactured is shown in FIG.

  16A is a top view of a module having an OLED, a so-called EL module, and FIG. 16B is a cross-sectional view of FIG. 16A cut along A-A ′. A pixel portion 902, a source side driver circuit 901, and a gate side driver circuit 903 are formed over a substrate 900 (eg, a glass substrate, a crystallized glass substrate, or a plastic substrate) having an insulating surface. These pixel portions and driving circuits can be obtained according to the first embodiment.

Reference numeral 918 denotes a sealing material, 919 denotes a protective film made of aluminum nitride oxide, aluminum nitride, or a DLC film. The pixel portion and the drive circuit portion are covered with the sealing material 918, and the sealing material is covered with the protective film 919. Yes. Further, it is sealed with a cover material 920 using an adhesive. The cover material 920 may be a base material having any composition, such as plastic, glass, metal, or ceramic. Further, the shape of the cover material 920 and the shape of the support are not particularly limited, and the cover material 920 may have a flat surface, a curved surface, a bendable shape, or a film shape. In order to withstand deformation due to heat or external force, the cover material 920 is preferably made of the same material as that of the substrate 900, for example, a glass substrate. In this embodiment, the concave shape (depth 3 to 3) shown in FIG. 10 μm). Further, it is desirable to form a recess (depth 50 to 200 μm) where the desiccant 921 can be installed by processing. In addition, when an EL module is manufactured by multi-chamfering, the substrate and the cover material may be bonded together, and then divided using a CO ₂ laser or the like so that the end faces coincide.

  Although not shown here, in order to prevent the background from being reflected due to the reflection of the metal layer used (here, the cathode or the like), circularly polarized light called a circularly polarizing plate made of a phase difference plate (λ / 4 plate) or a polarizing plate is used. Means may be provided on the substrate 900.

  Reference numeral 908 denotes a wiring for transmitting signals input to the source side driver circuit 901 and the gate side driver circuit 903, and receives a video signal and a clock signal from an FPC (flexible printed circuit) 909 serving as an external input terminal. The light emitting device of this embodiment may be digitally driven or analogly driven, and the video signal may be a digital signal or an analog signal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The light-emitting device in this specification includes not only a light-emitting device body but also a state in which an FPC or a PWB is attached thereto. In addition, it is possible to form a complicated integrated circuit (memory, CPU, controller, D / A converter, etc.) on the same substrate as these pixel portions and drive circuits, but it is difficult to manufacture with a small number of masks. is there. Therefore, it is preferable to mount an IC chip including a memory, a CPU, a controller, a D / A converter, and the like by a COG (chip on glass) method, a TAB (tape automated bonding) method, or a wire bonding method.

  Next, a cross-sectional structure is described with reference to FIG. An insulating film 910 is provided over the substrate 900, and a pixel portion 902 and a gate side driver circuit 903 are formed above the insulating film 910. The pixel portion 902 is electrically connected to the current control TFT 911 and its drain. The pixel electrode 912 is formed by a plurality of pixels. Actually, a plurality of TFTs are formed in one pixel, but only the current control TFT 911 is shown here for the sake of simplicity. Further, the gate side driver circuit 903 is formed with n-channel TFTs 913 and 914.

  These TFTs (including 911, 913, and 914) may be manufactured according to the n-channel TFT of the first embodiment.

In a display device having an OLED, a driving method in which a circuit is designed to supply a current by applying a constant voltage to the OLED, or a voltage applied to the OLED so that a constant current is supplied to the OLED. There is a driving method in which the circuit is designed so as to adjust the current, and a driving method in which the circuit is designed so that a constant current is supplied to the OLED, but it is electrically connected to the OLED regardless of the driving method. In addition, the luminance of the pixel by the on-current (I _on ) of a TFT that supplies current to the OLED (this TFT is referred to as a current control TFT in this specification and corresponds to the current control TFT 911 in FIG. 16). Is determined.

  In this embodiment, an n-channel TFT is used as the switching TFT 802 and an n-channel TFT is used as the current control TFT 911. However, the present invention is not limited to this configuration, and three TFTs are provided in one pixel. There may be 4, 5, 6, or more. The switching TFT and the current control TFT may be formed of a p-channel TFT. However, when the OLED cathode is used as a pixel electrode, the current control TFT is preferably an n-channel TFT, and when the OLED anode is used as a pixel electrode, the current control TFT is a p-channel TFT. desirable.

  The insulating film 808 provided between the active layer of the TFT and the OLED is preferably an insulating film with high flatness and high light transmission. Specifically, an organic resin film by a coating method and a silicon nitride film by a sputtering method may be stacked. Alternatively, planarization is preferably performed after the insulating film is formed. As the planarization treatment, a known technique for improving planarity, for example, a polishing process called chemical-mechanical polishing (hereinafter referred to as CMP) may be used. In the case of using CMP, as the CMP abrasive (slurry) for the insulating film, for example, fumed silica particles obtained by thermally decomposing silicon chloride gas in a KOH-added aqueous solution may be used. The insulating film is removed by about 0.1 to 0.5 μm by CMP to flatten the surface. In the OLED, if the organic compound layer has a non-uniform film thickness, light emission varies.

Note that the insulating films 807 and 808 provided between the active layer of the TFT and the OLED not only block diffusion of impurity ions such as alkali metal ions and alkaline earth metal ions but also positively detect alkali metal ions and alkalis. A material that adsorbs impurity ions such as earth metal ions is preferable, and a material that can withstand a subsequent process temperature is suitable. An example of a material that meets these conditions is a silicon nitride film containing a large amount of fluorine. The concentration of fluorine contained in the silicon nitride film is 1 × 10 ¹⁹ / cm ³ or more, preferably the fluorine composition ratio in the silicon nitride film is 1 to 5%. Fluorine in the silicon nitride film is combined with alkali metal ions, alkaline earth metal ions, etc., and is adsorbed in the film. As another example, an organic resin film containing fine particles made of an antimony (Sb) compound, a tin (Sn) compound, or an indium (In) compound that adsorbs alkali metal ions, alkaline earth metal ions, etc., for example, antimony pentoxide An organic resin film containing fine particles (Sb ₂ O ₅ .nH ₂ O) is also included. This organic resin film contains fine particles having an average particle diameter of 10 to 20 nm and has a very high light transmittance. The antimony compound represented by the antimony pentoxide fine particles easily adsorbs impurity ions such as alkali metal ions and alkaline earth metal ions.

Further, as another material of the insulating films 807 and 808 provided between the active layer of the TFT and the OLED, a layer represented by AlN _X O _Y may be used. A sputtering method is used, for example, an aluminum nitride (AlN) target, and an aluminum-containing nitride oxide layer (AlN _X O _Y ) obtained by forming a film in an atmosphere in which argon gas, nitrogen gas, and oxygen gas are mixed. The layer shown) is a film containing 2.5 atm% to 47.5 atm% of nitrogen. In addition to the effect of blocking moisture and oxygen, it has a high thermal conductivity and a heat dissipation effect, and further translucency. It has the characteristic that the property is very high. In addition, impurities such as alkali metals and alkaline earth metals can be prevented from entering the active layer of the TFT.

  The pixel electrode 912 that is electrically connected to the electrode 809 that is electrically connected to one impurity region 806 of the current control TFT 911 functions as an anode of the OLED. As the anode, a conductive film having a large work function, typically an oxide conductive film is used. As the oxide conductive film, indium oxide, tin oxide, zinc oxide, or a compound thereof may be used. A bank 915 made of an inorganic insulator or an organic insulator is formed at both ends of the pixel electrode 912, and an EL layer 916 and an OLED cathode 917 are formed on the pixel electrode 912.

  As the EL layer 916, an EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer. For example, a low molecular organic EL material or a high molecular organic EL material may be used. As the EL layer, a thin film made of a light emitting material (singlet compound) that emits light (fluorescence) by singlet excitation, or a thin film made of a light emitting material (phosphorescence) that emits light (phosphorescence) by triplet excitation can be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. As these organic EL materials and inorganic materials, known materials can be used.

  The cathode 917 also functions as a wiring common to all pixels, and is electrically connected to the FPC 909 via the connection wiring 908. As a material used for the cathode 917, it is preferable to use a metal having a small work function (typically, a metal element belonging to Group 1 or 2 of the periodic table) or an alloy containing these metals. The smaller the work function is, the better the light emission efficiency is. Therefore, among them, the material used for the cathode is preferably an alloy material containing Li (lithium), which is one of alkali metals. Further, all elements included in the pixel portion 902 and the gate side driver circuit 903 are covered with a cathode 917, a sealant 918, and a protective film 919.

Note that as the sealant 918, a material that is as transparent or translucent as possible to visible light is preferably used. Further, the sealant 918 is desirably a material that does not transmit moisture and oxygen as much as possible.

In addition, after completely covering the OLED with the sealing material 918, as shown in FIG. 16, at least a protective film made of a single layer or a laminate selected from an AlON film, an AlN film, an Al ₂ O ₃ film, or a DLC film It is preferable to provide 919 on the surface (exposed surface) of the sealant 918. Further, a protective film may be provided on the entire surface including the back surface of the substrate. Here, it is necessary to pay attention so that a protective film is not formed on the portion where the external input terminal (FPC) is provided. The protective film may be prevented from being formed using a mask, or the protective film may be prevented from being formed by covering the external input terminal portion with a tape such as a masking tape used in a CVD apparatus.

  By encapsulating the OLED with the sealing material 918 and the protective film with the structure as described above, the OLED can be completely shut off from the outside, and substances that promote deterioration due to oxidation of the EL layer such as moisture and oxygen enter from the outside. Can be prevented. In addition, if a film having thermal conductivity (such as an AlON film or an AlN film) is used as the protective film, heat generated when driven can be dissipated. Therefore, a highly reliable light-emitting device can be obtained.

  Alternatively, the pixel electrode may be a cathode, and an EL layer and an anode may be stacked to emit light in the direction opposite to that in FIG. An example is shown in FIG. Since the top view is the same, it is omitted.

  The cross-sectional structure shown in FIG. 17 will be described below. As the substrate 1000, a semiconductor substrate or a metal substrate can be used in addition to a glass substrate or a quartz substrate. An insulating film 1010 is provided over the substrate 1000, and a pixel portion 1002 and a gate side driver circuit 1003 are formed above the insulating film 1010. The pixel portion 1002 is electrically connected to the current control TFT 1011 and its drain. The pixel electrode 1012 is formed by a plurality of pixels. The gate side driver circuit 1003 is formed by combining an n-channel TFT 1013 and an n-channel TFT 1014.

  The pixel electrode 1012 functions as a cathode of the OLED. Further, banks 1015 are formed at both ends of the pixel electrode 1012, and an EL layer 1016 and an OLED anode 1017 are formed on the pixel electrode 1012.

  The anode 1017 also functions as a wiring common to all pixels, and is electrically connected to the FPC 1009 through the connection wiring 1008. Further, all elements included in the pixel portion 1002 and the gate side driver circuit 1003 are covered with an anode 1017, a sealant 1018, and a protective film 1019. Further, the cover material 1021 and the substrate 1000 were bonded together with an adhesive. Further, the cover material is provided with a recess, and a desiccant 1021 is provided.

Note that as the sealant 1018, it is preferable to use a material that is as transparent or translucent as possible to visible light. The sealing material 1018 is desirably a material that does not transmit moisture and oxygen as much as possible.

  In FIG. 17, since the pixel electrode is a cathode and the EL layer and the anode are stacked, the light emission direction is the direction of the arrow shown in FIG.

  Although not shown here, a circularly polarizing plate made of a retardation plate (λ / 4 plate) or a polarizing plate is used in order to prevent the background from being reflected by the reflection of the metal layer used (here, the pixel electrode serving as the cathode). May be provided on the cover material 1020.

  In addition, this embodiment can be freely combined with any of Embodiment 1, Embodiment 4, and Embodiment 6.

  Although it is possible to configure a driver circuit using the shift register described in Embodiment 4, a decoder using only n-channel TFTs is used instead of the shift register, and all of the source driver circuit and the gate driver circuit are E A case of forming with a type TFT will be described below with reference to FIGS.

  FIG. 18 shows an example of a gate side driving circuit. In FIG. 18, reference numeral 400 denotes a decoder of the gate side driving circuit, and 401 denotes a buffer part of the gate side driving circuit. The buffer unit refers to a part where a plurality of buffers (buffer amplifiers) are integrated. In addition, the buffer refers to a circuit that performs driving without affecting the preceding stage.

  First, the gate side decoder 400 will be described. First, reference numeral 402 denotes an input signal line (hereinafter referred to as a selection line) of the decoder 400. Here, A1, A1 bar (a signal in which the polarity of A1 is inverted), A2, A2 bar (a signal in which the polarity of A2 is inverted),. An and An bars (signals in which the polarity of An is inverted) are shown. That is, it can be considered that 2n selection lines are arranged.

The number of selection lines is determined by the number of gate lines output from the gate side driving circuit. For example, in the case of having a pixel portion for VGA display, there are 480 gate wirings, so a total of 18 selection lines are required for 9 bits (corresponding to n = 9). The selection line 402 transmits a signal shown in the timing chart of FIG. As shown in FIG. 19, when the frequency of A1 is 1, the frequency of A2 is 2 ⁻¹ times, the frequency of A3 is 2 ⁻² times, and the frequency of An is 2 ^{− (n−1)} times.

  Reference numeral 403a denotes a first-stage NAND circuit (also referred to as a NAND cell), reference numeral 403b denotes a second-stage NAND circuit, and reference numeral 403c denotes an n-th stage NAND circuit. The NAND circuit requires the number of gate wirings, and n pieces are required here. That is, in this embodiment, the decoder 400 is composed of a plurality of NAND circuits.

  The NAND circuits 403a to 403c are combined with n-channel TFTs 404 to 409 to form a NAND circuit. Actually, 2n TFTs are used in the NAND circuit 403. The gates of the n-channel TFTs 404 to 409 are connected to any of the selection lines 402 (A1, A1 bar, A2, A2 bar... An, An bar).

At this time, in the NAND circuit 403a, the n-channel TFTs 404 to 406 having gates connected to any one of A1, A2,... An (referred to as positive selection lines) are connected in parallel to each other and are common. Is connected to the negative power supply line (V _DL ) 410 as a source of the output, and connected to the output line 411 as a common drain. In addition, n-channel TFTs 407 to 409 having gates connected to any of A1 bar, A2 bar... An bar (which are referred to as negative selection lines) are connected in series with each other and are positioned at the circuit end. The source of the n-channel TFT 409 is connected to the positive power supply line (V _DH ) 412, and the drain of the n-channel TFT 407 located at the other circuit end is connected to the output line 411.

  As described above, in this embodiment, the NAND circuit includes n n-channel TFTs connected in series and n n-channel TFTs connected in parallel. However, in the n NAND circuits 403a to 403c, all combinations of n-channel TFTs and selection lines are different. That is, only one output line 411 is always selected, and a signal for selecting the output line 411 in order from the end is input to the selection line 402.

  Next, the buffer unit 401 is formed by a plurality of buffers 413a to 413c corresponding to each of the NAND circuits 403a to 403c. However, the buffers 413a to 413c may all have the same structure.

The buffers 413a to 413c are formed using n-channel TFTs 414 to 416. An output line 411 from the decoder is input as a gate of an n-channel TFT 414 (first n-channel TFT). The n-channel TFT 414 has a positive power supply line (V _DH ) 417 as a source and a gate wiring 418 following the pixel portion as a drain. The n-channel TFT 415 (second n-channel TFT) is always on with the positive power supply line (V _DH ) 417 as the gate, the negative power supply line (V _DL ) 419 as the source, and the gate wiring 418 as the drain. It has become.

  That is, in this embodiment, the buffers 413a to 413c are connected in series to the first n-channel TFT (n-channel TFT 414) and the first n-channel TFT, and the drain of the first n-channel TFT. A second n-channel TFT (n-channel TFT 415) having a gate as a gate is included.

The n-channel TFT 416 (third n-channel TFT) has a reset signal line (Reset) as a gate, a negative power supply line (V _DL ) 419 as a source, and a gate wiring 418 as a drain. Note that the negative power supply line (V _DL ) 419 may be a ground power supply line (GND).

  At this time, there is a relationship of W1 <W2 between the channel width (W1) of the n-channel TFT 415 and the channel width (W2) of the n-channel TFT 414. Note that the channel width is the length of a channel formation region in a direction perpendicular to the channel length.

  The operation of the buffer 413a is as follows. First, when a negative voltage is applied to the output line 411, the n-channel TFT 414 is turned off (a state in which no channel is formed). On the other hand, since the n-channel TFT 415 is always on (a channel is formed), the voltage of the negative power supply line 419 is applied to the gate wiring 418.

  However, when a positive voltage is applied to the output line 411, the n-channel TFT 414 is turned on. At this time, since the channel width of the n-channel TFT 414 is larger than the channel width of the n-channel TFT 415, the potential of the gate wiring 418 is pulled to the output on the n-channel TFT 414 side, and as a result, the voltage of the positive power supply line 417 is increased. Added to the gate wiring 418.

  Therefore, when a positive voltage is applied to the output line 411, the gate wiring 418 outputs a positive voltage (a voltage at which an n-channel TFT used as a pixel switching element is turned on), and a negative voltage to the output line 411. When a voltage is applied, a negative voltage (a voltage at which an n-channel TFT used as a pixel switching element is turned off) is output.

  Note that the n-channel TFT 416 is used as a reset switch for forcibly pulling down the gate wiring 418 to which a positive voltage is applied to a negative voltage. That is, when the selection period of the gate wiring 418 ends. A reset signal is input and a negative voltage is applied to the gate wiring 418. However, the n-channel TFT 416 can be omitted.

  The gate lines are sequentially selected by the gate side driving circuit operating as described above. Next, FIG. 20 shows a configuration of the source side driver circuit. The source side driver circuit illustrated in FIG. 20 includes a decoder 421, a latch 422, and a buffer unit 423. Note that the configurations of the decoder 421 and the buffer unit 423 are the same as those of the gate-side driver circuit, and thus description thereof is omitted here.

  In the case of the source side driver circuit shown in FIG. 20, the latch 422 includes a first-stage latch 424 and a second-stage latch 425. In addition, the first-stage latch 424 and the second-stage latch 425 each include a plurality of unit units 427 formed by m n-channel TFTs 426a to 426c. An output line 428 from the decoder 421 is input to the gates of m n-channel TFTs 426a to 426c forming the unit unit 427. Note that m is an arbitrary integer.

  For example, in the case of VGA display, the number of source lines is 640. When m = 1, 640 NAND circuits are required, and 20 selection lines (corresponding to 10 bits) are required. However, if m = 8, the number of necessary NAND circuits is 80, and the number of necessary selection lines is 14 (corresponding to 7 bits). That is, if the number of source wirings is M, the necessary NAND circuits are (M / m).

  The sources of the n-channel TFTs 426a to 426c are connected to video signal lines (V1, V2,... Vk) 429, respectively. That is, when a positive voltage is applied to the output line 428, the n-channel TFTs 426a to 426c are turned on at the same time, and video signals corresponding to the n-channel TFTs 426a to 426c are captured. The video signal thus captured is held in capacitors 430a to 430c connected to the n-channel TFTs 426a to 426c.

  The second-stage latch 425 also includes a plurality of unit units 427b, and the unit unit 427b is formed of m n-channel TFTs 431a to 431c. The gates of the n-channel TFTs 431a to 431c are all connected to the latch signal line 432. When a negative voltage is applied to the latch signal line 432, the n-channel TFTs 431a to 431c are turned on all at once.

  As a result, the signals held in the capacitors 430a to 430c are held in the capacitors 433a to 433c connected to the n-channel TFTs 431a to 431c and simultaneously output to the buffer 423. Then, as described in FIG. 19, the data is output to the source wiring 434 through the buffer. The source lines are selected in order by the source side driving circuit operating as described above.

  As described above, by forming the gate side driver circuit and the source side driver circuit with only the n-channel TFT, the pixel portion and the driver circuit can all be formed with the n-channel TFT. This embodiment can also be applied to the case where either one of the source side driver circuit or the gate side driver circuit is an external IC chip.

In addition, this embodiment can be freely combined with any one of Embodiments 1 to 6.

  In Example 1, an example in which thermal activation is performed is shown, but here, an example in which the conductive layer is not a three-layer structure but a four-layer structure when activated using laser light is shown.

  First, the steps up to forming a gate insulating film are similarly performed according to the first embodiment. Next, a W film is formed by sputtering as the first conductive film. The film formation conditions are as follows: a W target is used, a pressure is 0.2 Pa, a sputtering power is 1 kW, a substrate temperature is 200 ° C., an Ar flow rate is 20 sccm, and a distance between the substrate and the target is 60 mm.

  Next, an Al—Si film is formed as a second conductive film by a sputtering method. The film forming conditions were 300 nm to 500 nm using an Al target (Si: 2 wt% contained), pressure of 0.4 Pa, sputtering power of 4 kW, substrate temperature of room temperature, Ar flow rate of 50 sccm, and distance between the substrate and the target of 60 mm. Do the membrane.

Next, a TiN film is formed as a third conductive film by a sputtering method. Film formation conditions are ₂₀ to 100 nm using a Ti target, a pressure of 0.2 Pa, a sputtering power of 12 kW, a substrate temperature of room temperature, an N ₂ flow rate of 50 sccm, and a distance between the substrate and the target of 400 mm.

  Next, a Ti film is formed as a fourth conductive film by a sputtering method. Film formation conditions are 20 to 100 nm using a Ti target, a pressure of 0.1 Pa, a sputtering power of 12 kW, a substrate temperature of room temperature, an Ar flow rate of 20 sccm, and a distance between the substrate and the target of 400 mm. The fourth conductive film is provided to reflect the laser beam and protect the gate electrode when activated by the laser beam performed later.

  Next, etching may be performed in the same manner as in Example 1 to form a conductive layer to be a gate electrode. Although the fourth conductive film is formed in this embodiment, the etching rate is almost the same as that of the third conductive film.

  The subsequent steps may be performed according to the first embodiment. However, in this embodiment, instead of the thermal activation shown in the first embodiment, activation using the second harmonic and the third harmonic of a pulsed or continuous wave YAG laser is performed.

  When activation is performed by irradiating laser light, if the uppermost layer material is TiN, the TiN film absorbs laser energy and is easily damaged.

  The inventors conducted the following experiment.

A 50 nm tungsten film is formed as a first conductive film on the substrate, a 500 nm Al—Si film is formed as a second conductive film, and a 50 nm titanium nitride film is formed as a third conductive film. After forming under the above sputtering conditions, YAG laser light was irradiated. The laser light conditions were such that the laser energy density was 120.6 mJ / cm ² and 95.8 mJ / cm ² , respectively.

After irradiating with the laser light, photographs taken with a microscope are shown in FIGS. 21 (A) and 21 (B). FIG. 21A shows the case where laser light with a laser energy density of 120.6 mJ / cm ² is irradiated, and FIG. 21B shows 95.8 mJ / cm ² . In both cases, stripes or cracks that were probably caused by laser irradiation were observed. From this result, it can be read that the TiN film is easily damaged by the laser beam.

On the other hand, a 50-nm tungsten film is formed as the first conductive film, a 500-nm Al-Si film is formed as the second conductive film, and a 20-nm titanium nitride film is formed as the third conductive film. Further, after forming a 30 nm titanium film as a fourth conductive film, YAG laser light was irradiated. The laser light conditions were such that the laser energy density was 120.6 mJ / cm ² . FIG. 21C shows a photographic image observed with a microscope after the laser light irradiation. Even if the laser beam is irradiated, no particular change is observed, and it can be read that the film is protected by the fourth conductive film.

  With the four-layer structure shown in this embodiment, activation by laser light can be made possible. In particular, in the case where the substrate is a material having low heat resistance such as a plastic substrate, it is useful to have a four-layer structure because activation is performed by laser light.

  Further, although an example in which a four-layer structure is used is shown in this embodiment, even when the three-layer structure is used, both the third conductive film is a 50 nm tungsten film or a 50 nm titanium film. No change was observed on the irradiated surface.

  In addition, this embodiment can be freely combined with any one of Embodiments 1 to 7.

Various modules (active matrix type liquid crystal module, active matrix type EL module, active matrix type EC module) can be completed in the driver circuit and the pixel portion formed by implementing the present invention. That is, by implementing the present invention, all electronic devices incorporating them are completed.

  Such electronic devices include video cameras, digital cameras, head mounted displays (goggles type displays), car navigation systems, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Can be mentioned. Examples of these are shown in FIGS.

FIG. 11A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like.

FIG. 11B shows a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, a display unit 2205, and the like.

FIG. 11C shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet.

  FIG. 12A illustrates a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, an antenna 3006, and the like.

  FIG. 12B illustrates a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like. The present invention can complete a 10 to 50 inch diagonal display.

  As described above, the applicable range of the present invention is so wide that the present invention can be applied to methods for manufacturing electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-8.

10A and 10B illustrate a manufacturing process of an AM-LCD. 10A and 10B illustrate a manufacturing process of an AM-LCD. 10A and 10B illustrate a manufacturing process of an AM-LCD. FIG. 6 is a top view of a pixel. The figure which shows the external appearance of a liquid crystal module. The figure which shows the cross section of a transmissive liquid crystal display device. The figure which shows the structure of an NMOS circuit. FIG. 6 illustrates a structure of a shift register. The figure which shows the pixel part top view of this invention. The figure which shows pixel part sectional drawing of this invention. FIG. 11 illustrates an example of an electronic device. FIG. 11 illustrates an example of an electronic device. The observation SEM photograph figure after an etching. The observation SEM photograph figure after an etching. It is a figure which shows the relationship between the reliability (20 hours guarantee voltage, 10 years guarantee voltage) and Lov length in TFT of a drive circuit. The figure which shows the upper surface and cross section of EL module. The figure which shows the cross section of EL module. The figure which shows the structure of a gate side drive circuit. The figure which shows the timing chart of a decoder input signal. The figure which shows the structure of a source side drive circuit. The figure which shows the observation photograph of the metal film surface after laser irradiation.

Claims (3)

Forming a silicon nitride film having a thickness of 10 nm or less on the substrate;
Forming an amorphous silicon film in contact with the silicon nitride film;
Adding a metal element for promoting crystallization of silicon to the amorphous silicon film;
Crystallizing the amorphous silicon film added with the metal element to form a crystalline silicon film,
Forming a gettering site on the crystalline silicon film;
The metal element contained in the crystalline silicon film is moved to the gettering site by heat treatment, and the gettering site is removed to remove the metal element contained in the crystalline silicon film,
Forming a gate insulating film on the crystalline silicon film;
A multilayer film in which a tungsten film, an aluminum film containing Si, a titanium nitride film, and a titanium film are stacked on the gate insulating film is formed.
An end portion of the multilayer film is tapered by a first etching process, and an aluminum film containing Si, the titanium nitride film, and the titanium film are etched on the gate insulating film by a second etching process. Forming a gate electrode composed of the multilayer film ;
A method for manufacturing a semiconductor device, wherein heat treatment at 350 ° C. or higher or laser light irradiation is performed after the gate electrode is formed . A first silicon oxynitride film and a second silicon oxynitride film are sequentially stacked on the substrate,
Forming a silicon nitride film on the second silicon oxynitride film;
Forming an amorphous silicon film in contact with the silicon nitride film;
Adding a metal element for promoting crystallization of silicon to the amorphous silicon film;
Heating the amorphous silicon film to which the metal element is added to form a crystalline silicon film;
Forming a gettering site on the crystalline silicon film;
The metal element contained in the crystalline silicon film is moved to the gettering site by heat treatment, and the gettering site is removed to remove the metal element contained in the crystalline silicon film,
Forming a gate insulating film covering the crystalline silicon film;
A multilayer film in which a tungsten film, an aluminum film containing Si, a titanium nitride film, and a titanium film are stacked on the gate insulating film is formed.
An end portion of the multilayer film is tapered by a first etching process, and an aluminum film containing Si, the titanium nitride film, and the titanium film are etched on the gate insulating film by a second etching process. Forming a gate electrode composed of the multilayer film;
After forming the gate electrode, heat treatment at 350 ° C. or higher or laser light irradiation is performed,
The first silicon oxynitride film is formed using SiH ₄ , NH ₃ , and N ₂ O as a reactive gas, and the second silicon oxynitride film is formed using SiH ₄ and N ₂ O as a reactive gas. A method for manufacturing a semiconductor device, characterized in that a film is formed. In claim 1 or 2,
A chlorine-based gas is used as an etching gas for the first etching process,
The method for manufacturing a semiconductor device, wherein the first etching process and the second etching process are continuously performed without being exposed to the air.

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