JP3765194B2 - Liquid crystal display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electrode wiring of a liquid crystal display device.
[0002]
[Prior art]
As a wiring material for a liquid crystal display device, Japanese Patent Laid-Open No. 3-182723 discloses that a poly-Si film having a high concentration of impurities and an Al (aluminum) film are stacked as a gate wiring.
[0003]
Further, as a wiring material for a liquid crystal display device, Japanese Patent Laid-Open No. 5-55575 uses a metal material mainly composed of an alloy of Ta (tantalum) and Nb having a low resistance value and chemical resistance, Nb or Nb. The effect is described.
[0004]
Japanese Patent Laid-Open No. 2-106723 uses a wiring material for a gate line in which Nb and Ta are laminated in this order from the substrate side, and the surface is oxidized by anodization. ₂ A TFT in which a gate insulating film made of (silicon oxide) or SiN (silicon nitride) is stacked is proposed. According to this, it is described that the resistance value can be reduced as compared with the case where a Ta single layer film is used, and that it is effective in preventing a short circuit between the gate line and the drain line.
[0005]
Japanese Patent Application No. 7-147852 proposes the use of Nb for all or at least one of the gate / drain electrodes. According to this, a two-layer film made of an alloy or a different metal material is not used. Therefore, it is described that an electrode structure with improved throughput, low resistance, low stress, and easy dry etching can be realized.
[0006]
[Problems to be solved by the invention]
However, since the melting point (660.4 ° C.) of the Al film is low in the wiring of the conventional liquid crystal display device, particularly the gate electrode using Al, hillocks and whiskers are generated by the heat treatment when forming the interlayer insulating film, and the heat resistance of Al Due to the low oxidization property, the drive waveform was distorted and the wiring was short-circuited due to an increase in wiring resistance.
[0007]
In addition, since the Al film is usually patterned by wet etching, it is difficult to control the shape of the end, and it is easy to cause poor contact with the interlayer insulating film 110 and the drain electrode wiring 203. It causes drain disconnection failure.
[0008]
An object of the present invention is to provide a liquid crystal display device to which a wiring structure excellent in heat-resistant oxidation resistance is applied.
[0009]
[Means for Solving the Problems]
In a liquid crystal display device having a metal wiring, the metal wiring is formed of a first layer made of Nb or an alloy containing Nb as a main component and a nitride of Nb or an alloy containing Nb as a main component. With this configuration, it is possible to improve the heat oxidation resistance of the metal wiring. Further, when the resistance of the metal wiring does not matter, the metal wiring is omitted from the first layer made of Nb or an alloy containing Nb as a main component and nitrided from Nb nitride or an alloy containing Nb as a main component. Even if it is composed of a single material layer, the heat oxidation resistance can be improved in the same manner.
[0010]
In addition, when a third layer made of Nb nitride or Nb-based alloy nitride is formed under the first layer, direct contact between the first layer and another member is achieved. Can be avoided. Nb nitrides or nitrides of alloys containing Nb as a main component are particularly compatible with the insulating film, so that disconnection of the first layer, increase in resistance, and the like can be prevented. Even if a silicon oxide film is formed on these wirings, the wirings are not thermally oxidized, so that a higher effect can be obtained.
[0011]
Further, the number of process steps can be reduced by collectively etching the first layer and the second layer, preferably the third layer, with the same pattern. The end of the wiring can also be formed in a forward tapered shape.
[0012]
Another structure includes a pair of substrates and a liquid crystal layer sandwiched between the pair of substrates. The pair of substrates includes a plurality of gate electrode wirings and a plurality of gate electrode wirings intersecting with each other. In a liquid crystal display device having a plurality of drain electrode wirings formed, a plurality of thin film transistors formed corresponding to intersections of these wirings, and a plurality of source electrodes formed corresponding to the plurality of thin film transistors, In the case of having a plurality of gate electrode wirings, drain electrode wirings, source electrodes, common electrodes, and common electrode wirings, at least one of the common electrodes and the common electrode wirings is made of Nb or an alloy mainly composed of Nb. Even if it is constituted by a laminated film having a layer and a second layer made of Nb or a nitride of an alloy containing Nb as a main component, the thermal oxidation resistance is improved. Is particularly effective when used for the gate electrode wiring. If wiring resistance is not a problem, the first layer made of Nb or an alloy containing Nb as a main component is omitted, and the electrodes or electrode wires are nitrided with Nb nitride or an alloy containing Nb as a main component. Even if it comprises only the 2nd layer which consists of a thing, heat oxidation resistance can be improved similarly.
[0013]
Also for these structures, it is desirable to form a third layer made of Nb nitride or a nitride of an alloy containing Nb as a main component under the first layer.
[0014]
When an insulating film made of a silicon oxide film is formed on a wiring made of a laminated film having a first layer and a second layer, the effect is further clarified.
[0015]
Further, when the electrode structure of the present invention is used for the gate electrode wiring, it is preferable to form the silicon oxide film so as to be at least a part of the gate insulating film of the thin film transistor.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 14 is a plan view of a unit pixel of a liquid crystal display device of a comparative example configured using coplanar TFTs. 15, FIG. 16, and FIG. 17 are sectional views taken along lines xx ′, yy ′, and zz ′ in FIG. 14, respectively.
[0017]
The liquid crystal display device includes a gate electrode wiring 202 formed on a glass substrate 103 with a base film 104, a drain electrode wiring 203 formed so as to intersect with the gate electrode wiring 202, and an intersection corresponding to the intersection of these electrode wirings. It is composed of a TFT 101 formed in the vicinity and a pixel display region 102.
[0018]
As shown in FIG. 15, the TFT 101 includes a channel region 105 made of an intrinsic polycrystalline Si film, a gate insulating film 106 formed on the channel region 105, and a multi-doped impurity formed on the gate insulating film 106. A first gate electrode 1401 made of a crystalline Si film, a second gate electrode 201 made of Al (aluminum), and an active layer doped with impurities in the drain / source regions of the channel region 105 made of the intrinsic polycrystalline Si film 109 includes a drain electrode 111 and a source electrode 112 connected to each other through a through hole. A pixel electrode 113 is connected to the source electrode 112 of the TFT. Reference numerals 1501 and 110 denote interlayer insulating films, and reference numeral 114 denotes a protective insulating film.
[0019]
Focusing on the gate electrode of the TFT 101, as shown in FIG. 16, the first gate electrode 1401 made of polycrystalline Si and the second gate electrode 201 made of Al are through holes TH opened in the interlayer insulating film 1501. It can be seen that the structure is a two-layer gate electrode structure connected through the.
[0020]
In this two-layer electrode structure, the extended portion of the second gate electrode 201 made of Al becomes the gate electrode wiring 202 as it is. As shown in FIG. 17, the gate electrode wiring 202 and the drain electrode wiring 203 made of Al have a structure in which an intersection is formed with the interlayer insulating film 110 interposed therebetween.
[0021]
FIG. 18 is a cross-sectional view showing a gate electrode wiring formation step for each step in the comparative example shown in FIGS. The subject of this invention is demonstrated in detail using this sectional drawing.
[0022]
First, as shown in FIG. 18A, an island pattern 401 made of an intrinsic polycrystalline Si film is formed on a glass substrate 103 with a base film 104. Usually, an amorphous Si film formed by a CVD method or the like is polycrystallized by a technique such as thermal annealing or laser annealing.
[0023]
Next, as shown in FIG. 18B, a gate insulating film 106 and an amorphous Si film 1801 to be the first gate electrode 1401 after polycrystallization are formed on the entire surface of the substrate in a process described later. The gate insulating film 106 is usually made of SiO formed by the CVD method. ₂ A film, SiN film, or the like is used.
[0024]
Next, as shown in FIG. 18C, the gate insulating film 106 and the amorphous Si film 1801 are collectively etched with the same pattern. When such a process is employed, the first gate electrode needs to be made of an electrode wiring material that can be easily subjected to batch dry etching with the gate insulating film 106.
[0025]
Next, as shown in FIG. 18D, phosphorus ions as an n-type dopant are doped on the entire surface of the substrate. At this time, the layer pattern of the gate insulating film 106 and the amorphous Si film 1801 is used as a mask, and the channel region 105 made of the intrinsic polycrystalline Si film is formed in a self-aligned manner.
[0026]
Further, the P-type TFT portion of the peripheral circuit portion is selectively doped with boron ions, which are P-type dopants, using a photoresist or the like as a mask. An ion implantation method or an ion doping method is used for doping phosphorus and boron.
[0027]
Next, as shown in FIG. 18E, the doped impurity ions are activated by activation annealing to form a first gate electrode 1401 made of a polycrystalline Si film and an active layer 109 to be a drain / source region. Form. For this activation annealing, techniques such as thermal annealing and laser annealing are used. The temperature of thermal annealing is usually 600 ° C. or higher, and in the case of laser annealing, the surface temperature of the Si film reaches about 1000 ° C. Therefore, the first gate electrode is required to have heat resistance against these activation annealing steps. For example, Al, which is usually used as an electrode wiring material, cannot be used because it is a low melting point metal as described above. Further, since a thermal strain is applied, a low stress film is also required. Cr (chromium) is a refractory metal (melting point: 1860 ° C.), but since the film stress is high, the electrode is cracked after activation annealing and cannot be used.
[0028]
Here, although the first gate electrode 1401 made of polycrystalline Si has a higher resistance than metal even though it is doped, it cannot be used as the gate electrode wiring 202 routed around the display device. Therefore, a second gate electrode wiring made of a low resistance metal connected to the first gate electrode 1401 made of polycrystalline Si is required.
[0029]
However, if the gate electrode 201 made of an Al film is formed as the second gate electrode wiring at this stage where the TFT is exposed (FIG. 18E), the TFT is contaminated, the threshold voltage shifts and the off current. This causes a TFT characteristic defect such as an increase in the thickness.
[0030]
Therefore, next, as shown in FIG. 18F, an interlayer insulating film 1501 is formed on the entire surface of the substrate. The interlayer insulating film 1501 is a protective film for preventing contact between the TFT and the gate electrode 201 made of the Al film serving as the second gate electrode wiring. ₂ A film, a SiN film, or the like is used. Although not shown in FIG. 18, another interlayer insulating film 110 is formed on the second gate wiring 202 in the same manner as the interlayer insulating film 1501. These insulating films are formed by a plasma CVD method at a high temperature of 200 to 400 ° C. Therefore, there arises a problem that the surface of the Al film is easily oxidized.
[0031]
Instead of Al, the first and second gate electrode wirings are refractory metal Nb (described in Japanese Patent Application Laid-Open No. 7-147852), which is an electrode wiring material having low resistance, low stress, and easy dry etching. Application of melting point: 2470 ° C. was attempted. Although the resistance value immediately after the formation of the Nb film is low, when the insulating film is formed after this film is formed and then the wiring resistance is actually measured, the resistance value increases. This is because SiO 2 is formed on the wiring made of the Nb film by plasma CVD at a high temperature of 200 to 400 ° C. ₂ This is because an insulating film made of a film or SiN film is formed, so that the surface of the Nb film is oxidized and niobium oxide having a high resistance is formed. Especially SiO ₂ When the film was used, the resistance increased because the surface of the Nb film was exposed to a strong oxidizing plasma atmosphere.
[0032]
As an example of an increase in resistance due to thermal oxidation, FIG. 19 shows a change in resistance of the Nb film when the heat treatment temperature is changed (horizontal axis in the figure). The ratio of increase in resistance of the Nb film (vertical axis in the figure) when heat treatment is performed in the atmosphere at each temperature for 1 h using an oven is shown by the ratio of the resistance after heat treatment to the resistance before heat treatment. It can be seen that the resistance of the Nb film starts to increase from around 180 ° C. and rapidly increases when the temperature exceeds 250 ° C. It can be seen that the rate of resistance increase at 300 ° C is approximately 2.5 times, and that at 350 ° C is 4.5 times. This rate of increase in resistance coincides with the tendency of increase in resistance of the Nb electrode wiring observed when the TFT element was actually formed. Increasing the resistance of the wiring of the liquid crystal display device is a big problem. Particularly in the active matrix type liquid crystal display device, increasing the resistance of the electrode wiring is fatal. Unless some measure for improving the heat oxidation resistance of the Nb film is taken, it is difficult to realize wiring using Nb and a metal material mainly containing Nb. As a method for forming an insulating film for TFT, in addition to the plasma CVD method, for example, an inorganic polymer such as perhydropolysilazane soluble in an organic solvent is applied to a substrate by spin coating, SiO 2 ₂ There is a method of forming a film. Also in the coating method, the baking process of the coating film is indispensable for improving the film characteristics, and similarly, the improvement of the heat resistance and oxidation resistance of the electrode wiring is required.
[0033]
20 to 27, a laminated film structure of a first layer made of Nb or a compound containing Nb as a main component and a second layer made of a nitride of an alloy containing Nb or Nb as a main component is used. The structure and the effect will be described in principle.
[0034]
Hereinafter, “Nb or Nb-based alloy” is referred to as “Nb-based” and “Nb or Nb-based alloy nitride” is referred to as “NbN-based”. Are separated by “/”. In the case where the first layer (lower layer) has an Nb-based stacked film structure and the second layer (upper layer) has an NbN-based stacked film structure, it is described as an Nb-based / NbN-based stacked film in this document.
[0035]
FIG. 20 shows a case in which a SiO 2 nitride film and a Nb film formed on the surface of the Nb film are subjected to plasma nitriding. ₂ The resistance change at the time of forming a film is shown.
[0036]
The Nb film was formed by DC magnetron sputtering using a substrate temperature of 130 ° C., an Ar gas flow rate of 60 sccm, a power of 2100 W, a pressure of 0.2 Pa, and a film thickness of 200 nm. It was confirmed that the stress of the Nb film formed under these conditions was almost zero. The surface of the Nb film is N ₂ Plasma nitriding was performed with a gas of 200 sccm, a power of 500 W, and a pressure of 27 Pa. Evaluation was performed by changing the plasma nitriding time. SiO ₂ The film is formed by RF plasma CVD, the substrate temperature is 330 ° C., and TEOS (tetraethoxysilane): O ₂ Gas flow ratio = 15: 3000 sccm, power is 1000 W, pressure is 133 Pa, and film thickness is 300 nm. This is because SiO normally used in the TFT process. ₂ This corresponds to the film forming conditions.
[0037]
The horizontal axis in FIG. 20 represents the plasma nitriding time, and the longer the processing time, the thicker the NbN film formed on the surface. The value at the processing time 0 indicates the rate of increase in resistance of the Nb single layer film. The vertical axis in FIG. 20 shows the resistance increase rate as depo. (Deposited) resistance and SiO ₂ This is indicated by the ratio to the resistance after film formation. Nb film surface is SiO ₂ It can be seen that when the film is exposed to a strong oxidizing plasma atmosphere at 330 ° C., a resistance increase of about 2.5 times is recognized, whereas a film with a treatment time of 30 minutes hardly shows an increase in resistance. Thus, it is understood that the heat-resistant oxidation resistance is greatly improved by adopting the Nb-based / NbN-based laminated film structure as compared with the Nb-based single layer film. As a result, SiO, which is an interlayer insulating film, in a strong oxidation plasma atmosphere without causing an increase in resistance. ₂ A film can be formed. The obtained Nb-based / NbN-based laminated film had a high melting point and low stress like the Nb-based single layer film. Therefore, there is no fear of generating hillocks and whiskers as seen in the Al electrode wiring. In addition, SiO ₂ Even in the case of forming a film, the effect of improving the heat oxidation resistance was similarly recognized. Specifically, as an example, perhydropolysilazane diluted with cyclohexane is applied and formed by spin coating, and no increase in the resistance of the Nb-based / NbN-based laminated film is observed even after baking in the atmosphere at 400 ° C. for 1 hour. Was confirmed.
[0038]
The upper layer NbN-based film thickness will be described later with reference to FIG. 23, but the effect of improving the heat-resistant oxidation resistance was observed at 5 nm or more, but the effect tends to increase as the film thickness increases. However, since the specific resistance of the NbN-based film is larger than that of the Nb-based film, it is not desirable to make the NbN-based film too thick because it increases the resistance of the Nb-based / NbN-based laminated wiring. The thickness of the NbN film is preferably in the range of 5 nm to 100 nm. On the other hand, if the wiring resistance does not matter at the specific resistance level of the NbN-based film, the lower Nb-based film can be omitted and the wiring can be configured with an NbN-based single layer film.
[0039]
The specific resistance value of the lower Nb-based film is suitably 20 μΩcm or less. Since the Nb film having a resistance higher than this value already contains a large amount of oxygen at the stage of film formation, the effect of the Nb / NbN stacked film is difficult to obtain.
[0040]
Further, as an application of the above-described Nb-based / NbN-based laminated film, as shown in FIGS. 28 and 29, the wiring formed on the insulating film is made of Nb nitride or Nb-based alloy nitride. The third layer 150, the first layer 107 made of Nb or an alloy containing Nb as a main component, and the second layer 108 made of a nitride of Nb or an alloy containing Nb as a main component are stacked in this order. There is a structure constituted by the laminated film. In this way, the Nb-based film is not directly contacted on the insulating film, but the NbN-based film is interposed, so that the quality of the Nb film is not deteriorated by oxygen diffusion from the insulating film. In addition, the adhesion between the Nb-based / NbN-based laminated film and the insulating film can be improved by adding the NbN-based film to the lower layer.
[0041]
Similar to the film thickness of the upper NbN film, the thickness of the lower NbN film is suitably in the range of 5 to 100 nm.
[0042]
As a method for forming the Nb-based / NbN-based laminated film, in addition to the above-described means for nitriding the surface of the Nb-based film, a method of devising the sputtering apparatus, such as using a multi-chamber single wafer type sputtering apparatus, can be applied. According to this method, the Nb-based / NbN-based laminated film can be continuously formed, and the increase in the process due to the NbN-based film formation can be suppressed. As another method for forming the Nb-based / NbN-based laminated film, in addition to the above, for example, sputtering is performed using a target made of Nb-based nitride on an Nb-based film formed by sputtering using an Nb-based target. NbN-based films formed by the method may be stacked, or Nb-based targets may be used for sputtering gas. ₂ An NbN-based film formed by a reactive sputtering method to which (nitrogen) is added may be stacked. Alternatively, the Nb-based film may be formed by surface-nitriding the Nb-based film by laser annealing in a nitrogen atmosphere. In either case, the Nb-based / NbN-based laminated film can be continuously formed in the same manner, and an increase in the process can be suppressed. Further, not only the Nb film but also a material containing Nb as a main component can form nitrides by the same means, and the same heat-resistant oxidation property can be obtained. FIG. 23 shows the resistance change when the Nb-based / Nb-based laminated film formed by the reactive sputtering method shown in FIGS. 21 and 22 is heat-treated at different heat-treatment temperatures (horizontal axis in FIG. 23: unit ° C.). 23 vertical axis: the ratio of the resistance value after heat treatment divided by the resistance value before heat treatment as the rate of resistance increase. The parameter is the film thickness of the upper NbN. That is, the line ◇ indicates the case where the upper NbN film thickness is 0 nm, that is, there is no upper NbN film. The circles indicate the case where the upper NbN film thickness is 5 nm. The Δ line indicates the case where the upper NbN film thickness is 20 nm. The line □ is the case where the upper NbN film thickness is 40 nm. From FIG. 23, it can be seen that by stacking an NbN film having a thickness of 5 nm or more on the Nb film, sufficient heat-resistant oxidation resistance can be ensured even for heat treatment at 400 ° C. The greater the NbN film thickness, the better the thermal oxidation resistance, but the degree of the effect is moderate. Considering the resistance of the NbN-based film itself, as described above, the NbN-based film thickness applied to the Nb-based / NbN-based laminated wiring is preferably 5 nm or more and 100 nm or less.
[0043]
FIG. 21 shows a method of forming an NbN-based film by using N as a sputtering gas. ₂ An example of an NbN-based film obtained by using the reactive sputtering method to which is added is shown. The horizontal axis in FIG. 21 represents N as sputtering gas. ₂ N when adding gas ₂ / (Ar + N ₂ ) Flow rate ratio. The vertical axis in FIG. 21 represents the specific resistance (Ωcm) of the formed film. The substrate temperature is 130 ° C., the total gas flow rate is 60 sccm, the power is 2100 W, and the pressure is 0.5 Pa. Nb-based / NbN-based laminated films that contribute to improved thermal oxidation resistance can be obtained by using N ₂ Addition amount is N ₂ / (Ar + N ₂ ) An NbN film having a flow rate ratio of 0.05 to 0.25 and a specific resistance of the NbN film of 100 to 200 μΩcm (the range indicated by (b) in FIG. 21) was suitable. At this time, N ₂ The specific resistance of the Nb film obtained without addition (flow rate ratio = 0) was 18 μΩcm.
[0044]
Next, the structure of the film at each point shown in FIG. 21 was examined by X-ray diffraction. As a result, it was found that the structures were different in the three regions indicated by (a), (b), and (c).
FIG. 22 shows an X-ray diffraction spectrum (representative example) of a nitrided Nb film (NbN film) selected from the three regions (a), (b), and (c) shown in FIG. The vertical axis represents the X-ray diffraction intensity, and the unit is arbitrary units (a.u.). In FIG. 22, the black circles indicate cubic Nb, the open circles indicate crystal peaks from cubic NbN, and the black triangular marks indicate amorphous peaks from the underlying glass substrate. The range (N) shown in FIG. ₂ / (Ar + N ₂ ) The film obtained with a flow rate ratio of <0.05 and a specific resistance of the NbN film of <100 μΩcm) is N ₂ It was found that the Nb single phase or the mixed crystal state of NbN and Nb was caused by insufficient addition of.
[0045]
On the other hand, the optimum range for forming the Nb-based / NbN-based laminated film shown in FIG. ₂ / (Ar + N ₂ It can be seen that the film obtained at a flow rate ratio of 0.05 to 0.25 and a specific resistance of the NbN film of 100 to 200 μΩcm is composed of only NbN having high crystallinity. The range shown in FIG. 21C, that is, (N ₂ / (Ar + N ₂ The film obtained with a flow rate ratio of> 0.25 and the specific resistance of the NbN film is> 200 μΩcm) is composed only of NbN. ₂ It was found that the film was a film having a small crystal peak and low crystallinity due to excessive addition of. It can be inferred that the difference in the film quality is the cause of the difference in the effect of improving the heat resistance and oxidation resistance when forming the Nb-based / NbN-based laminated film.
[0046]
When a laminated film is used for the gate electrode wiring, it is desirable that the laminated wiring can be etched at a time without increasing the number of processes. Therefore, it is desirable that the Nb-based / NbN-based laminated film can be dry-etched at once even when the Nb-based / NbN-based laminated film is used. Further, as will be described later with reference to FIGS. 6 to 9, in the TFT portion forming the CMOS inverter and the terminal portion of the active matrix, a through hole for forming a contact is formed in the interlayer insulating film 110 on the gate electrode 201. There is a need to. Therefore, the condition is that the interlayer insulating film 110 can be selectively etched on the Nb-based / NbN-based laminated film. As described above, the interlayer insulating film 110 includes SiO. ₂ A film or a SiN film is used.
[0047]
FIG. 24 shows a typical SF as an F-based etching gas. ₆ Nb, NbN film, SiO when etching using gas ₂ The evaluation result of the etching rate of a film | membrane, a SiN film | membrane, and a resist film is shown. The horizontal axis in FIG. 24 indicates the etching time (seconds), and the vertical axis in FIG. 24 indicates the etched film thickness (nm). Nb film, NbN film, SiO ₂ The film was formed by the method shown in FIGS. The SiN film is RF plasma CVD, the substrate temperature is 230 ° C., SiH _Four (Monosilane): NH _Three (Ammonia): N ₂ The gas flow rate ratio was 20: 60: 200 sccm, the power was 175 W, and the pressure was 80 Pa. A commercially available positive resist was used as the resist. Etching conditions are
Using an RF parallel plate type reactive ion etching apparatus, power is 500 W, pressure is 27 Pa, SF ₆ The gas flow rate was 88 sccm. The etching rate can be obtained from the slope of the etching film thickness with respect to the etching time shown in FIG. Etching rate is SiO ₂ (0.2 nm / s) << resist (1.2 nm / s) <Nb system (1.7 nm / s) <NbN system (3.0 nm / s) <SiN (4.2 nm / s) I understand. Thus, it can be seen that the Nb / NbN stacked film can be collectively etched by using the F-based etching gas.
[0048]
However, SiO ₂ When the film is used as an interlayer insulating film, SiO ₂ Since the etching rate of the film is lower than the etching rate of the NbN-based film and the Nb-based film, it can be understood that the Nb-based / NbN-based stacked film that is the gate electrode wiring is damaged when the through hole is formed. In this regard, SF ₆ Instead of CHF _Three Is used as an etching gas, so that SiO ₂ The film can be selectively etched. On the other hand, the etching rate of the SiN film is larger than the etching rates of the NbN-based film and the Nb-based film, but the selectivity, which is the ratio of the etching speed, is 1.4 at most with respect to the NbN-based film. It can be seen that it is actually difficult to selectively etch the SiN film without damaging the Nb / NbN stacked film.
[0049]
This proves that it is difficult to use a SiN film as an interlayer insulating film. As mentioned above, SF is a typical F-based etching gas. ₆ CF instead of gas _Four Or CF _Four To O ₂ Similar results were obtained when using a gas to which was added.
[0050]
Next, FIG. 25 shows Nb, NbN, and SiO. ₂ Membrane CHF _Three The result obtained by etching with gas is shown. The horizontal axis in FIG. 25 indicates the etching time (minutes), and the vertical axis in FIG. 25 indicates the etched film thickness (nm). Using RF parallel plate type reactive ion etching system, power is 550W, pressure is 6.7Pa, CHF _Three The gas flow rate was 55 sccm. From this figure, SiO ₂ It can be seen that the Nb-based and NbN-based films are hardly etched with respect to the film etching rate of 23 nm / min. This is CHF _Three This is due to the fact that the gas is a highly depositable gas. That is, CHF _Three In etching using a gas, a C—F compound is formed together with the generation of F radicals that contribute to etching in plasma, and this is deposited on the surface of the Nb-based or NbN-based film. Therefore, etching is performed on the Nb-based or NbN-based film. Progress stops. On the other hand, SiO ₂ On the film, SiO ₂ Since oxygen is supplied from the film, deposition of C—F compound does not occur due to oxidative decomposition of C—F compound, and SiO ₂ The etching of the film proceeds constantly. Therefore, CHF _Three By using gas, SiO on Nb / NbN laminated film ₂ The film can be selectively etched. Due to the above-mentioned limitations on dry etching, the interlayer insulating film 110 on the gate electrode wiring 201 is made of SiO. ₂ It can be seen that the membrane is suitable.
[0051]
FIG. 26 is a schematic cross-sectional view of the end portion of the etching pattern when the Nb / NbN stacked film is etched using the gas shown in FIG. In FIG. 26, reference numeral 103 denotes a glass substrate, Nb, or a first layer 107 made of an alloy containing Nb as a main component, and a second layer made of an Nb-based film, an Nb nitride and an alloy nitride containing Nb as the main component. An NbN-based film is used as the layer 108, and reference numeral 2401 denotes a resist pattern. As shown in FIG. 26A, it is considered that the NbN-based film 108 is etched isotropically in the film thickness direction and in the lateral direction of the film. Here, as described with reference to FIG. 24, the etching rate a of the upper NbN-based film 108 in the Nb-based / NbN-based laminated film is approximately twice the etching rate b of the Nb-based film 107 (a> b). . Therefore, as shown in FIGS. 26B and 26C, the etching rate in the film thickness direction decreases as soon as the etching progresses to the Nb-based film side past the Nb-based / NbN-based interface. On the other hand, the lateral etching rate of the film is still governed by the etching rate a of the NbN-based film. Finally, as shown in FIG. 26 (d), the etching end portion is processed into a tapered shape having different angles across the Nb-based / NbN-based interface. At this time, the relationship between the angle α formed by the upper NbN-based film and the angle β formed by the lower Nb-based film satisfies α> β. In the actual etching of the Nb-based / NbN-based laminated film, the etching rate in the lateral direction of the film tends to be slightly higher than in the film thickness direction, not the isotropic etching. It was also confirmed by cross-sectional SEM observation that the film was etched into a shape substantially similar to the tapered shape shown in FIG. Such a taper shape can secure good contact characteristics of the drain electrode wiring 203 through the interlayer insulating film 110 and the inter-film insulating film when actually applied to the gate electrode wiring, and can prevent a short circuit between the wirings and a drain disconnection. Defects can be prevented. That is, the wiring end shape shown in FIG. 26 is an indispensable characteristic for the gate electrode wiring.
[0052]
As will be described later with reference to FIGS. 6 to 9, in the TFT portion forming the complementary (CMOS) inverter, it is necessary to form a through-hole contact between the Nb-based / NbN-based laminated film serving as the gate electrode wiring and the drain wiring material. There is.
[0053]
FIG. 27 shows a through-hole of an Nb-based / NbN-based laminated film, a general Cr as a drain wiring electrode material, and an alloy film of Cr and Mo (hereinafter abbreviated as CrMo) as an example of a Cr alloy film. The result of measuring the contact resistance is shown. The horizontal axis of FIG. 27 shows the contact area (μm ² The vertical axis of FIG. 27 shows the contact resistance (Ω · μm) ² ). The Cr film was formed using a DC magnetron sputtering method at a substrate temperature of 200 ° C., an Ar gas flow rate of 60 sccm, a power of 4000 W, and a pressure of 0.2 Pa. The CrMo film was formed under the same conditions as the Cr film except that an alloy target having a weight ratio of Cr and Mo of 50:50 was used. In FIG. 27, the ◯ marks indicate the measurement results when the Nb-based / NbN-based stacked film and Cr are used, and the □ marks indicate the measurement results when the Nb-based / NbN-based stacked film and CrMo are displayed. As a guideline for contact resistance specifications, 10 ⁶ Ωμm ² There is a need to keep it below. From FIG. 27, the contact resistance obtained for any combination of Nb-based / NbN-based laminated film and Cr, Nb-based / NbN-based laminated film and CrMo is a contact area of 25 to 400 μm. ² In the range of 10 ² Ωμm ² It can be seen that it is. This is a value 4 digits lower than the target, and it can be seen that the specification is sufficiently satisfied. Therefore, it is concluded that good contact characteristics can be ensured by using a gate electrode wiring as the Nb-based / NbN-based laminated film and a drain electrode wiring material as a Cr and / or Cr alloy film. Further, the contact characteristics are such that at least a portion of the drain electrode wiring or the source electrode wiring that is in contact with the gate electrode wiring made of the Nb-based / NbN-based laminated film is formed of chromium or an alloy film of chromium and molybdenum. If you can get it. Accordingly, if this condition is satisfied, as an application example of the drain electrode wiring or the source electrode wiring, chromium or a laminated film of an alloy film of chromium and molybdenum and another metal film, for example, an aluminum which is a low resistance metal film A laminated film with a niobium alloy film can also be used.
[0054]
Since the wiring structure according to the present invention is excellent in thermal oxidation resistance, if the wiring is a process that is exposed to a high-temperature oxidizing atmosphere, the drain electrode wiring, the source electrode wiring, the common electrode, and the common electrode wiring are used. The present invention is also effective when used for a common electrode, a common electrode wiring, etc. In particular, an example in which the present invention is applied to a gate electrode wiring of a TFT substrate will be described below.
[0055]
FIG. 2 is a plan view of a unit pixel of a liquid crystal display device constituted by using a coplanar type TFT according to the present invention. FIGS. 1 and 3 are lines indicated by xx ′ and yy ′ in FIG. It is sectional drawing which follows.
[0056]
As in the comparative example shown in FIG. 14, the basic configuration of the unit pixel of the liquid crystal display device is the gate electrode wiring 202 formed on the glass substrate 103 with the base film 104 and the drain electrode formed so as to intersect this. The wiring 203, the TFT 101 formed near the intersection of these electrode wirings, and the pixel display region 102 are configured. The difference from the comparative example is that, instead of the two-layer gate electrode structure of the first gate electrode 1401 made of polycrystalline Si and the second gate electrode 201 made of Al, in the present invention, Nb or Nb is the main component. A laminated electrode structure composed of a laminated film (Nb-based / NbN-based) of a first layer 107 made of an alloy and a second layer 108 made of a nitride film of the first layer is employed. is there.
[0057]
Therefore, as shown in FIG. 1, the TFT 101 is made of a channel region 105 made of an intrinsic polycrystalline Si film, a gate insulating film 106 formed on the channel region 105, and Nb or an alloy containing Nb as a main component. A stacked gate electrode 201 composed of a stacked film of a first layer 107 and a second layer 108 made of a nitride film of the first layer; and a drain / source region of the intrinsic polycrystalline Si film 105 A drain electrode 111 and a source electrode 112 are connected to an active layer 109 doped with impurities through a through hole. A pixel electrode 113 is connected to the source electrode 112 of the TFT 101. An interlayer insulating film 110 is formed between the gate electrode wiring and the source / drain electrodes of the TFT 101, and a protective insulating film 114 is formed on the TFT 101 and each wiring. Reference numeral 102 denotes a pixel display area.
[0058]
As in the comparative example, the extended portion of the gate electrode 201 becomes the gate electrode wiring 202 as it is.
[0059]
FIG. 3 shows an intersection of the gate electrode wiring 202 and the drain electrode wiring 203. As described above with reference to FIG. 26, the pattern end portion of the gate electrode wiring 202 made of a laminated film of the first layer 107 containing Nb or Nb as a main component and the second layer 108 made of the nitride film of the first layer. Is processed into a forward tapered shape. By processing into a taper shape in this way, it is possible to secure good contact characteristics of the interlayer insulating film 110 and the drain electrode wiring 203 on the gate electrode wiring 202, and it is possible to prevent a short circuit between the wirings and a disconnection of the drain electrode wiring 203. Can be prevented. Further, since hillocks and whiskers are not generated as seen in the Al electrode wiring, a short circuit failure due to a short circuit between the wirings can be further reduced.
[0060]
FIG. 4 shows a gate electrode wiring formation process of the embodiment shown in FIGS. The cross-sectional structure for each process is shown. First, as shown in FIG. 4A, an island pattern 401 made of an intrinsic polycrystalline Si film is formed on a glass substrate 103 with a base film 104.
Next, as shown in FIG. 2B, the gate insulating film 106, the first layer 107 made of Nb or an alloy mainly containing Nb, and the second layer 108 made of the first nitride film are formed on the entire surface of the substrate. And a laminated film is formed. The laminated film of the first layer 107 made of Nb or an alloy containing Nb as a main component and the second layer 108 made of the nitride film of the first layer is formed by forming a nitride film with Ar and N ₂ The first layer can be continuously formed by using a reactive sputtering method using a mixed gas. Next, as shown in FIG. 3C, the gate insulating film 106 and the first layer 107 made of Nb or an alloy mainly containing Nb, and the second layer 108 made of the nitride film of the first layer. The stacked gate electrode 201 and the gate insulating film 106 having substantially the same planar shape are obtained by collectively etching the stacked film with the same pattern.
[0061]
As described above with reference to FIG. 24, the laminated film of the first layer 107 made of Nb or an alloy containing Nb as a main component and the second layer 108 made of the nitride film of the first layer is formed of an F-based etching gas. By using this, batch etching can be easily performed.
[0062]
Next, as shown in FIG. 4D, the entire surface of the substrate is doped with phosphorus ions which are N-type dopants. At this time, a channel pattern 105 made of an intrinsic polycrystalline Si film is formed in a self-aligned manner using the stacked pattern of the gate insulating film 106 and the stacked gate electrode 201 as a mask.
[0063]
Finally, as shown in FIG. 5E, the impurity ions doped by activation annealing are activated to form an active layer 109 serving as a drain / source region. At this time, thermal annealing, laser annealing, or the like is used for the activation annealing. The Nb / NbN laminated film constituting the laminated gate electrode 201 has a high melting point and low stress. Defects such as peeling and cracking of the gate electrode pattern due to the annealing are not caused. In addition, since the gate electrode wiring has a Nb-based / NbN-based laminated film structure, the heat-resistant oxidation resistance against the activation annealing atmosphere is improved. In the subsequent process of forming the interlayer insulating film 110, the resistance of the gate electrode wiring does not increase.
[0064]
Further, the Nb-based / NbN-based laminated film has a remarkably low resistance as compared to 1401 which is a gate electrode made of polycrystalline Si of the comparative example described in FIGS. Only the gate electrode 201 can serve as a signal wiring in the liquid crystal display device. Therefore, the second gate electrode wiring made of the low resistance metal in the comparative example becomes unnecessary. Accordingly, the interlayer insulating film 1501 for preventing contact between the TFT and the second gate electrode wiring film 201 is not necessary, and the gate electrode wiring structure and the total process are greatly simplified. In other words, by applying the laminated gate electrode wiring structure of the present invention, the heat resistance oxidation and workability are excellent, the low resistance and the low stress, while taking advantage of the features of Nb and a metal material mainly composed of Nb. In addition, a simple gate electrode wiring structure excellent in process consistency can be realized. As a result, the cost of the liquid crystal display device can be reduced by greatly simplifying the TFT structure and process.
[0065]
In addition, since a short circuit due to a short circuit between wirings and a disconnection of the drain electrode wiring can be prevented at the intersection of the wirings, the yield of the liquid crystal display device can be improved.
[0066]
FIG. 5 shows an equivalent circuit of the entire active matrix liquid crystal display device in which a drive circuit configured using a CMOS inverter is integrated on the same substrate 501 together with an active matrix liquid crystal display portion.
[0067]
This liquid crystal display device divides a video signal for one scanning line into a plurality of blocks and supplies them in a time-sharing manner, with an active matrix 50 comprising TFTs as a display unit, a vertical scanning circuit 51 for driving the active matrix 50. And a switch matrix circuit 52 for supplying the video signal to the active matrix side for each divided block. The horizontal scanning circuit 53 for supplying the video signal and the data signal lines Vdr1, Vdg1, Vdb1,. Here, the vertical scanning circuit 51 and the horizontal scanning circuit 53 are configured by shift registers and buffers, and are driven by clock signals CL1, Cl2, and CKV.
[0068]
FIG. 6 is a circuit diagram of a CMOS inverter circuit formed on the substrate. The PMOS and NMOS are configured as shown in the figure, have an input terminal Vin and an output terminal Vout, and are supplied with a reference voltage Vss and a power supply voltage Vdd.
[0069]
FIG. 7 shows a pattern layout of the inverter circuit shown in FIG. 8 is a cross-sectional view taken along the line xx ′ in FIG. 7, and FIG. 9 is a cross-sectional view taken along the line yy ′ in FIG. The CMOS inverter in the present embodiment is composed of a PMOS 701 that is a P-type TFT and an NMOS 702 that is an N-type TFT.
[0070]
As shown in FIG. 8, the gate electrodes 703 and 704 of the two TFTs 701 and 702 are connected to the first wiring electrode 705 integrated with the input terminal Vin via the through hole TH.
[0071]
Further, as shown in FIG. 9, an electrode for supplying the reference voltage Vss and the power supply voltage Vdd to the circuit and an output terminal Vout connected to the drain electrodes of the two TFTs are formed by the second wiring electrode 706. The output terminal Vout becomes the input voltage of the shift register corresponding to the next-stage scanning line.
[0072]
At this time, both of the wiring electrodes 705 and 706 are made of the same layer and the same material as the drain electrode wiring of the TFT. Therefore, on the input terminal Vin side, good through-hole contact characteristics between the wiring electrode 705 and the TFT gate electrodes 703 and 704, that is, the drain electrode wiring material and the gate electrode wiring material must be ensured. By using the laminated gate electrode wiring structure for the TFT constituting the P-type transistor PMOS701 and the N-type transistor NMOS702, specifically, the gate electrodes 703 and 704 are made of Nb or a first alloy made of Nb as a main component. The layer 107 and the second layer 108 made of the first layer nitride film are formed, and the wiring electrodes 705 and 706 are formed of the drain electrode wiring material Cr or an alloy film of Cr and Mo. Will be. The interlayer insulating film 110 on the gate electrodes 703 and 704 is made of SiO. ₂ It will consist of a membrane.
[0073]
Also in this case, the gate electrodes 703 and 704 are constituted by an Nb-based / NbN-based laminated film structure, and sufficient heat-resistant oxidation resistance is guaranteed. Therefore, SiO ₂ After the interlayer insulating film 110 made of a film is formed, the gate electrode wiring resistance does not increase.
[0074]
Further, as shown in FIG. 27, the through-hole contact resistance between the laminated film of Nb and Nb nitride and Cr or CrMo is sufficiently low. Therefore, in the connection between the wiring electrode 705 and the TFT gate electrodes 703 and 704, good through-hole contact characteristics can be ensured.
[0075]
Further, as described above with reference to FIG. 25, since the interlayer insulating film 110 can be selectively etched on the gate electrodes 703 and 704, the underlying gate electrodes 703 and 704 are not damaged in the through-hole forming step. As a result, a CMOS inverter having a simple structure and good characteristics can be obtained, so that peripheral circuits can be easily built in, and the liquid crystal display device can be greatly improved in performance and cost. In the above embodiment, as the drain electrode and the drain electrode wiring material, Cr or an alloy film of Cr and Mo is used, but the portion in contact with the gate electrode and the gate electrode wiring is Cr, or Cr and Mo. The drain electrode and drain electrode wiring structure in which a second layer made of an aluminum alloy film, which is a low-resistance metal film, is laminated on the first layer made of an alloy film of A drain electrode and a drain electrode wiring with low wiring resistance can be obtained.
[0076]
In the above embodiment, the entire structure is formed using a coplanar type TFT, but the TFT may be an inverted stagger type or a normal stagger type. In the above embodiment, the entire structure is configured using a vertical electric field type TFT. However, a lateral electric field type TFT in which an electric field is applied in the horizontal direction between the common electrode formed on the same substrate as the source electrode of the TFT. You may comprise using. The present invention can be similarly applied to the case where amorphous Si is used in place of intrinsic polycrystalline Si for the channel semiconductor layer of the TFT. In the following embodiment, the present invention is applied to an inverted staggered amorphous Si-TFT.
[0077]
FIG. 10 is a plan view of a unit pixel of an active matrix liquid crystal display device according to the present invention configured using inverted staggered TFTs.
[0078]
11 and 12 are cross-sectional views taken along lines xx ′ and yy ′ in FIG. 10, respectively.
[0079]
The basic configuration of the present liquid crystal display device is that a gate electrode wiring 202 formed on a glass substrate 103 with a base film 104, a drain electrode wiring 203 formed so as to intersect with the gate electrode wiring 202, and the vicinity of the intersection of these electrode wirings , The pixel display region 102, and the additional capacitor 1001.
[0080]
1 to 4 are different from the coplanar TFT embodiment described above in that the TFT 101 is formed of an inverted staggered TFT, and the channel region 105 and the active layer 109 in which the drain and source regions are doped with impurities. It is composed of amorphous Si, and the gate insulating film is SiO. ₂ That is, the first gate insulating film 1101 made of a film and the second gate insulating film 1102 made of a SiN film are used.
[0081]
In an amorphous Si TFT, a SiN film is usually used as a gate insulating film in order to ensure the stability of the interface between amorphous Si as a channel layer and the gate insulating film.
[0082]
However, if the gate insulating film is composed of a single layer of SiN, as described above, the first layer 107 made of Nb located under the gate insulating film or an alloy containing Nb as a main component and the nitride film of the first layer A gate insulating film made of a SiN film may be selectively etched on the laminated gate electrode and gate electrode wiring 201 and 202 formed of a laminated film (Nb / NbN series) with the second layer 108 made of It becomes difficult.
[0083]
Therefore, in the embodiment, as described above, SiO ₂ A laminated gate insulating film structure of a first gate insulating film 1101 made of a film and a second gate insulating film 1102 made of a SiN film is employed, and the selective etching characteristics of the gate electrode and the gate electrode wiring 201 and 202 are SiO ₂ The first gate insulating film 1101 made of a film ensures the stability of the interface with the channel layer 105 by the second gate insulating film 1102 made of a SiN film.
[0084]
Also at this time, the gate electrode and gate electrode wiring 201 and 202 have a sufficient heat-resistant oxidation property by being configured with an Nb / NbN-based laminated film structure. Therefore, SiO ₂ The gate electrode wiring resistance does not increase after the first gate insulating film 110 made of a film is formed.
[0085]
FIG. 12 shows an intersection of the gate electrode wiring 202 and the drain electrode wiring 203. By applying the present invention, the pattern end portion of the gate electrode wiring 202 made of Nb or a laminated film of the first layer 107 mainly composed of Nb and the second layer 108 made of the nitride film of the first layer. Is processed into a forward tapered shape, so that SiO on the gate electrode wiring 202 is ₂ The first gate insulating film 1101 made of a film, the second gate insulating film 1102 made of a SiN film, and the drain electrode wiring 203 can be secured with good contact characteristics. Can be prevented. Needless to say, the occurrence of hillocks and whiskers as seen in the Al electrode wirings can be prevented, so that a short circuit failure due to a short circuit between the wirings can be prevented. FIG. 13 is a schematic sectional view of an active matrix type liquid crystal display device according to the present invention. A gate electrode wiring (scanning signal wiring) 202 and a drain electrode wiring (video signal wiring) 203 are formed in a matrix on the glass substrate 103 below the liquid crystal layer 1302, and ITO is formed by TFTs formed in the vicinity of the intersection. The pixel electrode 113 is driven. A counter electrode 1306 made of ITO, a color filter 1304, a color filter protective film 1307, and a light shielding film 1308 for forming a light shielding black matrix pattern are formed on a counter glass substrate 1305 facing each other across the liquid crystal layer 1302.
[0086]
The central part of FIG. 13 is a cross section of one pixel portion, the left side is a cross section of the left edge portion of the pair of glass substrates 103 and 1305 and the portion where the external lead terminal is present, and the right side is a right edge of the pair of glass substrates 103 and 1305. The cross section of the part which does not have an external extraction terminal in the part is shown.
[0087]
The sealing material SL shown on each of the left and right sides in FIG. 13 is configured to seal the liquid crystal layer 1302 and extends along the entire edges of the glass substrates 103 and 1305 excluding the liquid crystal sealing port (not shown). Is formed. The sealing agent is made of, for example, an epoxy resin. At least one counter electrode 1306 on the counter glass substrate 1305 side is connected to an external lead wiring formed on the glass substrate 103 by a silver paste material SIL. The external lead wiring is formed in the same manufacturing process as each of the gate electrode wiring 202, the source electrode 112, and the drain electrode wiring 203. Therefore, for example, the external lead wiring of the gate electrode wiring 202 can be specifically configured by the Nb / NbN stacked film structure of the present invention. Each external lead wiring is connected to an external drive circuit of a TCP (Tape Carrier Package) or COG (Chip On Glass) connection system via an anisotropic conductive film (ACF). Alignment film ORI1, ORI2, pixel electrode 113, protective film 114, interlayer insulating film 110, SiO ₂ Each layer of the gate insulating film 106 made of is formed inside the sealing material SL. The polarizing plates 1301 are formed on the outer surfaces of the pair of glass substrates 103 and 1305, respectively.
[0088]
The liquid crystal layer 1302 is sealed between a lower alignment film ORI1 that sets the orientation of liquid crystal molecules and an upper alignment film ORI2, and is sealed with a seal material SL. The lower alignment film ORI1 is formed on the protective insulating film 114 on the glass substrate 103 side. On the inner surface of the counter glass substrate 1305, a light shielding film 1308, a color filter 1304, a color filter protective film 1307, a counter electrode 1306, and an upper alignment film ORI2 are sequentially stacked. This liquid crystal display device is assembled by separately forming layers on the glass substrate 103 side and the counter glass substrate 1305 side, and then overlaying the upper and lower glass substrates 103 and 1305 and enclosing the liquid crystal 1302 therebetween. A TFT drive type color liquid crystal display device is configured by adjusting the transmission of light from the backlight BL at the pixel electrode 113 portion.
[0089]
Thus, as the gate electrode (scanning signal wiring) 201 and the gate electrode wiring 202, a laminated gate electrode wiring structure of Nb or an alloy mainly containing Nb and a nitride of an alloy mainly containing Nb or Nb is used. Active matrix type liquid crystal display device with excellent throughput and yield because it can easily realize a simple gate wiring structure with excellent thermal oxidation resistance and workability, low resistance, low stress and excellent process consistency. Can be realized easily.
[0090]
In addition, since it is easy to incorporate peripheral circuits, the liquid crystal display device can be greatly improved in performance and cost. Further, in the above embodiment, the entire structure is configured using the vertical electric field type TFT, but the same applies to the case where the horizontal electric field type TFT having the common electrode and the common electrode wiring is used.
[0091]
The TFT may be a coplanar type, an inverted staggered type, or a normal staggered type, but in particular, in a coplanar type element, the parasitic capacitance between the gate and the source or drain can be reduced, so that higher speed operation is possible. This is advantageous for a peripheral circuit built-in type liquid crystal display device.
[0092]
The present invention is also applicable to a non-peripheral circuit built-in type liquid crystal display device using amorphous Si instead of intrinsic polycrystalline Si for the TFT channel semiconductor layer.
[0093]
In the above-described embodiments, only the case where the stacked structure of Nb / NbN or NbN / Nb / NbN is applied to the gate electrode and the gate electrode wiring is shown. However, the drain electrode wiring, the source electrode, the common electrode, and the common electrode wiring are provided. Even when applied to the common electrode and the common electrode wiring, effects such as heat oxidation resistance, good matching with the insulating film, and good through-hole contact characteristics through the insulating film can be obtained.
[0094]
Examples of alloys containing Nb as a main component and nitrides of alloys containing Nb as a main component include, for example, Nb alloys containing W, Mo, Ti, V, Si, etc. in a range of several percent or less, and these There are nitrides of Nb alloys.
[0095]
【The invention's effect】
According to the present invention, it is possible to easily obtain a wiring excellent in heat and oxidation resistance, and to realize a high-performance and low-cost liquid crystal display device.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a liquid crystal display device according to an embodiment of the present invention configured using a coplanar type TFT, and is a cross-sectional view taken along the line xx ′ shown in FIG.
FIG. 2 is a plan view of a unit pixel of a liquid crystal display device according to an embodiment of the present invention configured using a coplanar TFT.
3 is a cross-sectional view of a liquid crystal display device according to an embodiment of the present invention configured using a coplanar TFT, and is a cross-sectional view taken along the line yy ′ shown in FIG.
4 is a cross-sectional view for each step of the gate electrode wiring shown in FIG. 2;
FIG. 5 is an equivalent circuit diagram of an entire active matrix liquid crystal display device according to an embodiment of the present invention in which a drive circuit configured using a CMOS inverter is integrated on the same substrate together with a display unit.
FIG. 6 is a configuration diagram of a CMOS inverter circuit according to an embodiment of the present invention.
7 is a pattern layout diagram of the inverter circuit shown in FIG. 6;
8 is a cross-sectional view taken along the line xx ′ shown in FIG.
9 is a cross-sectional view taken along the line yy ′ shown in FIG.
FIG. 10 is a plan view of a unit pixel of an active matrix liquid crystal display device according to an embodiment of the present invention configured by using an inverted staggered TFT.
11 is a sectional view taken along the line xx ′ shown in FIG. 10;
12 is a sectional view taken along the line yy ′ shown in FIG.
FIG. 13 is a schematic cross-sectional view of an active matrix liquid crystal display device according to an embodiment of the present invention.
FIG. 14 is a plan view of a unit pixel of an active matrix liquid crystal display device of a comparative example of the present invention configured using a coplanar TFT.
15 is a sectional view taken along the line xx ′ shown in FIG. 14;
16 is a cross-sectional view taken along the line yy ′ shown in FIG.
17 is a cross-sectional view taken along the line zz ′ shown in FIG. 14;
18 is a cross-sectional view for each step of forming a gate electrode wiring of the comparative example of the present invention shown in FIG.
FIG. 19 is a diagram showing a change in resistance of an Nb film when heat treatment is performed at different heat treatment temperatures.
FIG. 20 is a diagram showing a change in resistance when an Nb film subjected to surface plasma nitriding is heat-treated.
FIG. 21 N ₂ The figure which shows the resistance characteristic of the nitride Nb film | membrane (NbN type | system | group) formed by changing addition amount.
FIG. 22 shows N shown in FIG. ₂ The X-ray-diffraction spectrum of the Nb nitride film (NbN type) formed by changing the addition amount.
FIG. 23 is a diagram showing a change in resistance of an Nb-based / NbN-based laminated film when heat treatment is performed at different heat treatment temperatures.
FIG. 24 SF ₆ Nb, NbN, SiO when etched using ₂ The figure which plotted the relationship between the etching time of SiN and a resist film, and an etching film thickness.
FIG. 25: CHF _Three Nb, NbN, and SiO when etched using ₂ The figure which plotted the relationship between the etching time of a film | membrane, and an etching film thickness.
FIG. 26 is a schematic cross-sectional view of an end portion of a wiring pattern of an Nb-based / NbN-based laminated film.
FIG. 27 is a diagram showing through-hole contact resistance between an Nb-based / NbN-based laminated film and Cr or CrMo.
FIG. 28 is a wiring cross-sectional view of an NbN-based / Nb-based / NbN-based laminated film.
FIG. 29 is a wiring cross-sectional view of an NbN-based / Nb-based / NbN-based laminated film.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 50 ... Active matrix, 51 ... Vertical scanning circuit, 52 ... Switch matrix circuit, 53 ... Horizontal scanning circuit, 101 ... TFT, 102 ... Pixel display area, 103 ... Glass substrate, 104 ... Base film, 105 ... Channel area of TFT, 106... Gate insulating film, 107... Nb, or first layer made of Nb-based alloy, 108... Nb nitride and second layer made of Nb-based alloy nitride, 109 ... active layers doped with impurities in drain / source regions, 110, 1501 ... interlayer insulating film, 111 ... drain electrode, 112 ... source electrode, 113 ... pixel electrode, 114 ... protective insulating film, 201 ... gate electrode, 202 ... gate Electrode wiring, 203... Drain electrode wiring, 401... Island pattern made of intrinsic polycrystalline Si film, 701... PMOS, 70 ... NMOS, the gate electrode of the 703 and 704 ... TFT, 705 ... first wiring electrode, 706 ... second wiring electrodes, 1001 ... additional capacitor, 1101 ... SiO ₂ First gate insulating film made of film, 1102... Second gate insulating film made of SiN film, 1302... Liquid crystal layer, 1304... Color filter, 1305. , 1308... Shading film, 1401... First gate electrode made of a polycrystalline Si film doped with impurities, 1801... Amorphous Si film, TH... Through-hole TH, SL. ... Alignment film, BL ... Backlight BL.

Claims (14)

A pair of substrates;
A liquid crystal layer sandwiched between the pair of substrates;
Wiring disposed on one of the pair of substrates;
An insulating film disposed on the wiring,
The wiring includes a first layer made of Nb or an alloy mainly containing Nb,
A liquid crystal display device comprising a nitride of Nb or a nitride of an alloy containing Nb as a main component, and comprising a second layer disposed between the first layer and the insulating film. A pair of substrates;
A liquid crystal layer sandwiched between the pair of substrates;
Wiring disposed on one of the pair of substrates;
An insulating film disposed on the wiring,
The wiring includes a first layer made of Nb or an alloy mainly containing Nb,
A second layer composed of a nitride of Nb or a nitride of an alloy containing Nb as a main component, and disposed between the first layer and the insulating film;
A liquid crystal display device comprising a third layer disposed between the one substrate and the first layer, which is composed of a nitride of Nb or a nitride of an alloy containing Nb as a main component. 3. The liquid crystal display device according to claim 1, wherein the insulating film is made of a silicon oxide film.   2. The liquid crystal display device according to claim 1, wherein the first layer and the second layer are collectively etched with the same pattern. 3. The liquid crystal display device according to claim 2 , wherein the first layer, the second layer, and the third layer are collectively etched with the same pattern.   The liquid crystal display device according to claim 1, wherein an end portion of the wiring has a forward tapered shape.   2. The liquid crystal display device according to claim 1, wherein the specific resistance of the first layer is 20 [mu] [Omega] cm or less, and the specific resistance of the second layer is in the range of 100 to 200 [mu] [Omega] cm.   2. The liquid crystal display device according to claim 1, wherein the thickness of the second layer is 5 to 100 nm. A pair of substrates;
A liquid crystal layer sandwiched between the pair of substrates;
A plurality of gate electrode wirings disposed on one of the pair of substrates;
A plurality of drain electrode wirings formed to intersect the plurality of gate electrode wirings;
A plurality of thin film transistors formed corresponding to intersections of the gate electrode wiring and the drain electrode wiring;
A plurality of source electrodes formed corresponding to the plurality of thin film transistors,
An insulating film is disposed on at least one of the plurality of gate electrode wirings, drain electrode wirings or source electrodes;
The wiring on which the insulating film is arranged is made of Nb or a first layer made of an alloy containing Nb as a main component, and a nitride of an alloy containing Nb or Nb as a main component, and the first layer and the insulating film And a second layer disposed between the liquid crystal display device and the liquid crystal display device. A pair of substrates;
A liquid crystal layer sandwiched between the pair of substrates;
A plurality of gate electrode wirings disposed on one of the pair of substrates;
A plurality of drain electrode wirings formed to intersect the plurality of gate electrode wirings;
A plurality of thin film transistors formed corresponding to intersections of the gate electrode wiring and the drain electrode wiring;
A plurality of source electrodes formed corresponding to the plurality of thin film transistors,
An insulating film is disposed on at least one of the plurality of gate electrode wirings, drain electrode wirings or source electrodes;
The wiring on which the insulating film is arranged is made of Nb or a first layer made of an alloy containing Nb as a main component, and a nitride of an alloy containing Nb or Nb as a main component, and the first layer and the insulating film A second layer disposed between and
A liquid crystal display device comprising a third layer disposed between the one substrate and the first layer, which is composed of a nitride of Nb or a nitride of an alloy containing Nb as a main component. 11. The liquid crystal display device according to claim 9, wherein the insulating film is made of a silicon oxide film. 12. The liquid crystal display device according to claim 11 , wherein the silicon oxide film is at least a part of a gate insulating film of the thin film transistor. A pair of substrates;
A liquid crystal layer sandwiched between the pair of substrates;
A common electrode disposed on one of the pair of substrates;
An insulating film disposed on the common electrode;
The common electrode includes Nb or a first layer made of Nb as a main component, and
A liquid crystal display device comprising Nb or a nitride of an alloy containing Nb as a main component and including a second layer disposed between the first layer and the insulating film. A pair of substrates;
A liquid crystal layer sandwiched between the pair of substrates;
A common electrode disposed on one of the pair of substrates;
An insulating film disposed on the common electrode;
The common electrode includes Nb or a first layer made of Nb as a main component, and
A second layer made of Nb or a nitride of an Nb-based alloy and disposed between the first layer and the insulating film;
A liquid crystal display device comprising a third layer disposed between the one substrate and the first layer, which is composed of a nitride of Nb or a nitride of an alloy containing Nb as a main component.

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