JP6217161B2 - LIGHT EMITTING DEVICE AND ELECTRONIC DEVICE - Google Patents

Description

  The present invention relates to a light emitting device using a light emitting material such as an organic EL material.

  For example, a light-emitting device in which light-emitting elements using an organic EL material are arranged in a plane on a substrate has been conventionally proposed as a display device for various electronic devices. Patent Document 1 discloses a light emitting device in which pixels are arranged in a display area where an image is displayed, and dummy pixels that do not actually contribute to image display are arranged in adjacent areas around the display area. Pixels in the display area include a light emitting element in which a light emitting layer is interposed between an anode and a cathode. On the other hand, no anode is formed on the dummy pixel in the adjacent region.

JP 2006-18085 A

  However, in the configuration in which the electrode (anode) constituting the light emitting element of the pixel in the display area is omitted for the dummy pixel in the adjacent area as in Patent Document 1, the step corresponding to the film thickness of the electrode is different from the display area and the adjacent area. Occurs between. Therefore, for example, there is a problem that it is difficult to form a sealing body (sealing layer) for preventing intrusion of outside air or moisture into the light emitting element. In view of the above circumstances, an object of the present invention is to suppress a step between the inside and outside of a display area.

  In order to solve the above problems, a light-emitting device according to a preferred aspect of the present invention includes a first power supply conductor to which a first potential is supplied, a first electrode corresponding to each pixel in the display region, A light emitting functional layer overlapping one electrode, and a transistor (for example, a drive transistor TDR or a light emission control transistor TEL) that is electrically connected between the first electrode and the first power supply conductor and controls the supply of current to the light emitting layer. The second power supply conductor is formed in the peripheral layer around the display area from the same layer as the first power supply conductor and is supplied from the same layer as the first electrode. The second power supply conductor is supplied with a second potential different from the first potential. The conductive electrode that is conducted to the second power supply conductor and the display region and the peripheral region are formed, and the light emitting functional layer is sandwiched between the first electrode in the display region and the conductive electrode is interposed in the peripheral region. Second conducting to the second power conductor 2 electrodes. In the above configuration, the conductive electrode formed from the same layer as the first electrode in the display region and the second power supply conductor formed from the same layer as the first power supply conductor in the display region are in the peripheral region. The second electrode formed and extending over both the display region and the peripheral region is electrically connected to the second power supply conductor through the conductive electrode in the peripheral region. That is, similarly to the layer structure in which the first power supply conductor 41 and the first electrode overlap in the display area, the second power supply conductor and the conductive electrode overlap in the peripheral area. Accordingly, a step between the display area and the peripheral area can be suppressed.

  A light-emitting device according to a preferred aspect of the present invention includes a pixel definition layer that covers a formation surface of the first electrode and the conductive electrode, and the pixel definition layer includes a first opening corresponding to the first electrode, A second opening corresponding to the conducting electrode is formed, the light emitting functional layer is in contact with the first electrode through the first opening, and the second electrode is connected to the conducting electrode through the second opening. Contact. In the above configuration, in addition to the first opening corresponding to the first electrode in the display area, the second opening corresponding to the conductive electrode in the peripheral area is provided in the pixel definition layer extending over both the display area and the peripheral area. Is formed. That is, the pixel definition layer also has a structure similar to the display area in the peripheral area. Therefore, the effect of suppressing the step between the display area and the peripheral area is particularly remarkable.

  In a preferred aspect of the present invention, the first electrode and the conducting electrode have a common planar shape and size. In a configuration in which a plurality of first electrodes are arranged in the display area and a plurality of conductive electrodes are arranged in the peripheral area, the pitch of the arrangement of the plurality of first electrodes in the display area and the plurality of conductive electrodes in the peripheral area are arranged. A configuration in which the common electrode array pitch is shared is particularly suitable. According to each of the above aspects, the effect that the step between the display area and the peripheral area can be suppressed is particularly remarkable.

  A light emitting device according to a preferred embodiment of the present invention includes a signal line for supplying a gradation potential corresponding to a designated gradation to a gate of a transistor, and the first power supply conductor is from a layer different from the signal line. It is formed. In the above aspect, since the first power supply conductor is formed from a layer different from the signal line, for example, the first power supply conductor is compared with a configuration in which the first power supply conductor and the signal line are formed from the same layer. It is possible to secure a sufficient area (reducing resistance). For example, the first power supply conductor can be a solid pattern over substantially the entire display area. Therefore, there is an advantage that display spots due to a voltage drop in the plane of the first power supply conductor are suppressed. In a more preferred aspect, the first power supply conductor is formed between the wiring layer in which the signal line is formed and the wiring layer in which the first electrode is formed.

  In a preferred aspect of the present invention, the first power supply conductor and the second power supply conductor are formed on the surface of the insulating layer (for example, the insulating layer LD) on which the planarization process has been performed. In the above configuration, since the first power supply conductor and the second power supply conductor are formed from the same layer on the surface of the insulating layer on which the planarization process has been performed, for example, the first power supply caused by irregularities on the surface of the insulating layer. There is an advantage that an electrical short circuit between the power supply conductor and the second power supply conductor can be prevented. For example, in the configuration in which the above-described insulating layer (for example, the insulating layer LD) is formed so as to cover each element such as active elements (transistors) and various wirings, the surface of the insulating layer caused by the elements such as active elements and wirings After the unevenness is reduced by the planarization process, the first power supply conductor and the second power supply conductor are formed.

  The light emitting device according to a preferred aspect of the present invention includes a sealing body that is formed over both the display region and the peripheral region and covers the second electrode. In the above aspect, there exists an advantage that intrusion of external air or moisture can be prevented by the sealing body.

  The light emitting device according to each aspect described above is used in various electronic devices as a display device, for example. Specifically, a head-mounted display device, an electronic viewfinder of an imaging device, and the like can be exemplified as preferred examples of the electronic apparatus of the present invention, but the scope of application of the present invention is not limited to the above examples.

It is a top view of the light-emitting device of 1st Embodiment of this invention. It is a circuit diagram of a pixel. It is sectional drawing of a light-emitting device. It is sectional drawing of a light-emitting device. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is a schematic diagram of a 1st power supply conductor and a 2nd power supply conductor. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is sectional drawing of each display pixel which paid its attention to the optical path adjustment layer. It is explanatory drawing of the 2nd sealing layer of a sealing body. It is a top view of the light-emitting device of a 2nd embodiment. It is a schematic diagram of a head-mounted display device as an example of an electronic device.

<First Embodiment>
FIG. 1 is a plan view of a light emitting device 100 according to the first embodiment of the present invention. The light emitting device 100 of the first embodiment is an organic EL device in which a light emitting element using an organic EL material is formed on the surface of the substrate 10. The substrate 10 is a plate-like member (semiconductor substrate) formed of a semiconductor material such as silicon (silicon), and is used as a base (base) on which a plurality of light emitting elements are formed. As illustrated in FIG. 1, the surface of the substrate 10 is divided into a first region 12 and a second region 14. The first area 12 is a rectangular area, and the second area 14 is a rectangular frame area surrounding the first area 12.

  The first region 12 includes a plurality of scanning lines 22 extending in the X direction, a plurality of control lines 24 extending in the X direction corresponding to the scanning lines 22, and a Y direction that intersects the X direction. A plurality of existing signal lines 26 are formed. A pixel P (PD, PE) is formed corresponding to each intersection of the plurality of scanning lines 22 and the plurality of signal lines 26. Accordingly, the plurality of pixels P are arranged in a matrix over the X direction and the Y direction.

  In the second region 14, a drive circuit 30, a plurality of mounting terminals 36, and a guard ring 38 are installed. The drive circuit 30 is a circuit that drives each pixel P, and extends in the X direction among the two scanning line drive circuits 32 installed at each position sandwiching the first region 12 in the X direction and the second region 14. And a signal line driving circuit 34 installed in the existing area. The plurality of mounting terminals 36 are formed in a region opposite to the first region 12 with the signal line driving circuit 34 interposed therebetween, and are controlled via a flexible wiring substrate (not shown) joined to the substrate 10. It is electrically connected to an external circuit (for example, an electronic circuit mounted on a wiring board) such as a circuit or a power supply circuit.

  In the light emitting device 100 according to the first embodiment, a plurality of light emitting devices 100 are collectively formed by cutting (scribing) an original substrate having a size corresponding to a plurality of substrates 10. The guard ring 38 in FIG. 1 prevents the influence of the impact and static electricity at the time of cutting the original substrate from spreading on the drive circuit 30 or each pixel P and the intrusion of moisture from the end face (cut surface of the original substrate) of each substrate 10. To prevent. As illustrated in FIG. 1, the guard ring 38 is formed in an annular shape (rectangular frame shape) surrounding the drive circuit 30, the plurality of mounting terminals 36, and the first region 12.

  The first region 12 in FIG. 1 is divided into a display region 16 and a peripheral region 18. The display area 16 is an area where an image is actually displayed by driving each pixel P. The peripheral area 18 is a rectangular frame-like area surrounding the display area 16, and has a similar structure to each pixel P in the display area 16 but does not actually contribute to image display (hereinafter referred to as “dummy pixel PD”). ") Is arranged. From the viewpoint of clarifying the notation distinction from the dummy pixel PD in the peripheral area 18, in the following description, the pixel P in the display area 16 may be referred to as “display pixel PE” for convenience. The display pixel PE is an element that is a minimum unit of light emission.

  FIG. 2 is a circuit diagram of each display pixel PE located in the display area 16. As illustrated in FIG. 2, the display pixel PE includes a light emitting element 45, a drive transistor TDR, a light emission control transistor TEL, a selection transistor TSL, and a capacitive element C. In the first embodiment, each transistor T (TDR, TEL, TSL) of the display pixel PE is a P-channel type, but an N-channel type transistor can also be used.

  The light emitting element 45 is an electro-optical element in which a light emitting functional layer 46 including a light emitting layer of an organic EL material is interposed between a first electrode (anode) E1 and a second electrode (cathode) E2. The first electrode E1 is individually formed for each display pixel PE, and the second electrode E2 is continuous over a plurality of pixels P. As understood from FIG. 2, the light emitting element 45 is disposed on a path connecting the first power supply conductor 41 and the second power supply conductor 42. The first power supply conductor 41 is a power supply wiring to which a higher power supply potential VEL is supplied, and the second power supply conductor 42 is a power supply wiring to which a lower power supply potential (for example, ground potential) VCT is supplied. .

  The drive transistor TDR and the light emission control transistor TEL are arranged in series with respect to the light emitting element 45 on a path connecting the first power supply conductor 41 and the second power supply conductor 42. Specifically, one (source) of the pair of current ends of the driving transistor TDR is connected to the first power supply conductor 41. The light emission control transistor TEL functions as a switch for controlling the conduction state (conduction / non-conduction) between the other (drain) of the pair of current ends of the drive transistor TDR and the first electrode E1 of the light emitting element 45. The drive transistor TDR generates a drive current having a current amount corresponding to the voltage between its gate and source. In a state where the light emission control transistor TEL is controlled to be in the on state, the drive current is supplied from the drive transistor TDR to the light emitting element 45 via the light emission control transistor TEL, so that the light emission element 45 corresponds to the amount of current of the drive current. In a state where light is emitted with luminance and the light emission control transistor TEL is controlled to be in an off state, the light emitting element 45 is turned off by interrupting the supply of the driving current to the light emitting element 45. The gate of the light emission control transistor TEL is connected to the control line 24.

  The selection transistor TSL in FIG. 2 functions as a switch for controlling the conduction state (conduction / non-conduction) between the signal line 26 and the gate of the drive transistor TDR. The gate of the selection transistor TSL is connected to the scanning line 22. The capacitive element C is a capacitance in which a dielectric is interposed between the first electrode C1 and the second electrode C2. The first electrode C1 is connected to the gate of the driving transistor TDR, and the second electrode C2 is connected to the first power supply conductor 41 (the source of the driving transistor TDR). Therefore, the capacitive element C holds the voltage between the gate and the source of the driving transistor TDR.

  The signal line driving circuit 34 outputs a plurality of signal lines for each writing period (horizontal scanning period) with respect to a gradation potential (data signal) corresponding to a gradation specified by an image signal supplied from an external circuit for each display pixel PE. 26 in parallel. On the other hand, each scanning line drive circuit 32 supplies a scanning signal to each scanning line 22 to sequentially select each of the plurality of scanning lines 22 for each writing period. The selection transistor TSL of each display pixel PE corresponding to the scanning line 22 selected by the scanning line driving circuit 32 is turned on. Therefore, the gradation potential is supplied to the gate of the drive transistor TDR of each display pixel PE via the signal line 26 and the selection transistor TSL, and the capacitor C holds a voltage corresponding to the gradation potential. On the other hand, when the selection of the scanning line 22 in the writing period is completed, each scanning line driving circuit 32 supplies a control signal to each control line 24 to thereby control light emission of each display pixel PE corresponding to the control line 24. The transistor TEL is controlled to be on. Accordingly, a drive current corresponding to the voltage held in the capacitor C in the immediately preceding writing period is supplied from the drive transistor TDR to the light emitting element 45 via the light emission control transistor TEL. As described above, each light emitting element 45 emits light at a luminance corresponding to the gradation potential, whereby an arbitrary image designated by the image signal is displayed in the display area 16.

  A specific structure of the light emitting device 100 of the first embodiment will be described in detail below. In each drawing referred to in the following description, the dimensions and scales of each element are different from those of the actual light emitting device 100 for convenience of description. 3 and 4 are cross-sectional views of the light emitting device 100, and FIGS. 5 to 9 show the appearance of the surface of the substrate 10 at each stage of forming each element of the light emitting device 100 for one display pixel PE. It is the top view illustrated paying attention to. A cross-sectional view corresponding to the cross section including the line III-III in FIGS. 5 to 9 corresponds to FIG. 3, and a cross-sectional view corresponding to the cross section along the line IV-IV in FIGS. 5 to 9 corresponds to FIG. 5 to 9 are plan views. From the viewpoint of facilitating visual grasp of each element, each element common to FIG. 3 or FIG. 4 is hatched in the same manner as FIG. 3 or FIG. It is added for convenience.

  As understood from FIGS. 3, 4 and 5, the active region 10A (source) of each transistor T (TDR, TEL, TSL) of the display pixel PE is formed on the surface of the substrate 10 formed of a semiconductor material such as silicon. / Drain region) is formed. Ions are implanted into the active region 10A. The active layer of each transistor T (TDR, TEL, TSL) of the display pixel PE exists between the source region and the drain region, and ions of a different type from the active region 10A are implanted. It is omitted. 3 and 4, the surface of the substrate 10 on which the active region 10A is formed is covered with an insulating film L0 (gate insulating film), and the gate G (GDR, GEL, GSL) of each transistor T is insulated. It is formed on the surface of the film L0. The gate G of each transistor T faces the active layer across the insulating film L0. FIG. 4 shows the gate GSL of the selection transistor TSL, the gate GDR of the drive transistor TDR, and the gate GEL of the light emission control transistor TEL.

  As understood from FIGS. 3 and 4, on the surface of the insulating film L0 on which the gate G of each transistor T is formed, a plurality of insulating layers L (LA to LD), a plurality of conductive layers (wiring layers), and A multilayer wiring layer is formed by alternately stacking layers. Each insulating layer L is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). In the following description, a relationship in which a plurality of elements are collectively formed in the same process by selective removal of a conductive layer (single layer or a plurality of layers) is referred to as “formed from the same layer”.

  The insulating layer LA is formed on the surface of the insulating film L0 on which the gate G of each transistor T is formed. As understood from FIGS. 3, 4 and 6, the scanning line 22, the control line 24, and a plurality of relay electrodes QA (QA1, QA2, QA3, QA4) are formed on the surface of the insulating layer LA from the same layer. It is formed. The scanning line 22 and the control line 24 extend linearly in the X direction across the plurality of pixels P with a space therebetween. Specifically, as illustrated in FIG. 6, the scanning line 22 is formed so as to pass above the gate GSL of the selection transistor TSL and above the gate GDR of the driving transistor TDR, and conducts through the insulating layer LA. It conducts to the gate GSL of the selection transistor TSL through a hole (contact hole) HA1. The conduction hole HA1 is formed so as to overlap the gate GSL and the active layer of the selection transistor TSL in plan view. On the other hand, the control line 24 is formed so as to pass over the gate GEL of the light emission control transistor TEL, and is electrically connected to the gate GEL of the light emission control transistor TEL through the conduction hole HA2 penetrating the insulating layer LA. The conduction hole HA2 is formed so as to overlap the gate GEL and the active layer of the light emission control transistor TEL in plan view.

  The relay electrode QA1 is a wiring that connects the active region 10A of the selection transistor TSL and the gate GDR of the driving transistor TDR, and is located between the scanning line 22 and the control line 24 in plan view as illustrated in FIG. To do. Specifically, as understood from FIGS. 4 and 6, the relay electrode QA1 is electrically connected to the active region 10A of the selection transistor TSL through a conduction hole HA3 penetrating the insulating layer LA and the insulating film L0. It is electrically connected to the gate GDR of the drive transistor TDR through the conduction hole HA4 of the insulating layer LA. Further, as understood from FIG. 6, the relay electrode QA2 is electrically connected to the active region 10A of the selection transistor TSL through a conduction hole HA5 penetrating the insulating layer LA and the insulating film L0. The relay electrode QA3 is electrically connected to the active region 10A (source) of the drive transistor TDR through a conduction hole HA6 that penetrates the insulating layer LA and the insulating film L0. The relay electrode QA4 is electrically connected to the active region 10A (drain) of the light emission control transistor TEL via a conduction hole HA7 penetrating the insulating layer LA and the insulating film L0. As understood from FIG. 6, each of the selection transistor TSL, the drive transistor TDR, and the light emission control transistor TEL is formed so that the channel length is along the Y direction. The drive transistor TDR and the light emission control transistor TEL are arranged along the Y direction, and the selection transistor TSL is shifted in the X direction (the negative side in the X direction in FIG. 6) with respect to the drive transistor TDR and the light emission control transistor TEL. Placed in a different position.

  The insulating layer LB is formed on the surface of the insulating layer LA on which the scanning lines 22, the control lines 24, and the plurality of relay electrodes QA are formed. As understood from FIGS. 3, 4, and 7, the signal line 26, the first electrode C1, and the plurality of relay electrodes QB (QB1, QB2) are formed from the same layer on the surface of the insulating layer LB. . The signal line 26 extends linearly in the Y direction over the plurality of pixels P, and is electrically insulated from the scanning line 22 and the control line 24 by the insulating layer LA. Specifically, the signal line 26 is formed so as to pass through the active region 10A (source, drain) and the active layer of the selection transistor TSL and the relay electrode QA1 that is conductive to the gate GDR of the driving transistor TDR. , And extends along the channel length direction (Y direction) of the selection transistor TSL and overlaps the selection transistor TSL in plan view. The signal line 26 is formed in an upper layer than the active region 10A (source, drain) of each transistor T (TDR, TEL, TSL) and the gate G of each transistor T. As understood from FIG. 7, the signal line 26 is electrically connected to the relay electrode QA2 through the conduction hole HB1 penetrating the insulating layer LB. That is, the signal line 26 and the active region 10A (source) of the selection transistor TSL are connected via the relay electrode QA2. The first electrode C1 in FIG. 7 is electrically connected to the relay electrode QA1 through a conduction hole HB2 that penetrates the insulating layer LB. That is, the first electrode C1 of the capacitive element C and the gate GDR of the drive transistor TDR are connected via the relay electrode QA1. The relay electrode QB1 in FIG. 7 is electrically connected to the relay electrode QA3 via the conduction hole HB3 of the insulating layer LB, and the relay electrode QB2 is electrically connected to the relay electrode QA4 via the conduction hole HB4 of the insulating layer LB.

  The insulating layer LC is formed on the surface of the insulating layer LB on which the signal line 26, the first electrode C1, and the plurality of relay electrodes QB (QB1, QB2) are formed. As understood from FIGS. 3, 4 and 8, the second electrode C2 and the plurality of relay electrodes QC (QC1, QC2) are formed from the same layer on the surface of the insulating layer LC. The second electrode C2 is formed in a shape and a position overlapping the first electrode C1 in a plan view (that is, as viewed from a direction perpendicular to the surface of the substrate 10). As understood from FIG. 3, the capacitive element C is constituted by the first electrode C1 and the second electrode C2 and the insulating layer LC therebetween. As illustrated in FIG. 8, the capacitive element C (first electrode C1, second electrode C2) is disposed so as to overlap the drive transistor TDR and the light emission control transistor TEL in plan view. The relay electrode QC1 in FIG. 8 is electrically connected to the relay electrode QB1 via the conduction hole HC1 of the insulating layer LC, and the relay electrode QC2 is electrically connected to the relay electrode QB2 via the conduction hole HC2 of the insulating layer LC.

  As illustrated in FIGS. 3 and 4, the insulating layer LD is formed on the surface of the insulating layer LC on which the second electrode C2 and the plurality of relay electrodes QC (QC1, QC2) are formed. In the above description, attention is paid to the display pixel PE, but the structure of each element from the surface of the substrate 10 to the insulating layer LD is common to the dummy pixels PD in the peripheral region 18.

  A planarization process is performed on the surface of the insulating layer LD. For the planarization treatment, a known surface treatment technique such as chemical mechanical polishing (CMP) is arbitrarily employed. As illustrated in FIG. 3, the first power supply conductor 41 and the second power supply conductor 42 are formed from the same layer on the surface of the insulating layer LD that is highly planarized by the planarization process. FIG. 10 is a plan view of the first power supply conductor 41 and the second power supply conductor 42, and FIGS. 11 to 14 are enlarged views of the region α in FIG. As understood from FIGS. 10 and 11, the first power supply conductor 41 is formed in the display area 16 of the first area 12, and the second power supply conductor 42 is formed in the peripheral area 18 of the first area 12. The The first power supply conductor 41 and the second power supply conductor 42 are formed to be separated from each other and electrically insulated. The first power supply conductor 41 is electrically connected to the mounting terminal 36 to which the higher power supply potential VEL is supplied via a wiring (not shown) in the multilayer wiring layer. Similarly, the second power supply conductor 42 is electrically connected to the mounting terminal 36 to which the lower power supply potential VCT is supplied via wiring (not shown) in the multilayer wiring layer. The first power supply conductor 41 and the second power supply conductor 42 of the first embodiment are made of a light-reflective conductive material containing, for example, silver or aluminum and have a thickness of, for example, about 100 nm.

  The first power supply conductor 41 is a power supply line to which the higher power supply potential VEL is supplied as described above, and is formed in a planar shape over substantially the entire display region 16 as understood from FIGS. 10 and 11. It is a substantially rectangular solid pattern. The solid pattern is not a linear or belt-like pattern or a combination thereof (for example, a lattice pattern), but a planar shape (that is, a solid pattern) that is substantially continuous with no gap so as to fill almost the entire surface of the display area 16. Pattern).

  As understood from FIGS. 4, 9 and 11, the first power supply conductor 41 formed in the display region 16 is connected to the relay electrode via the conduction hole HD1 formed in the insulating layer LD for each display pixel PE. Conducts to QC1. That is, as understood from FIG. 4, the active region 10A functioning as the source of the driving transistor TDR is connected to the first power supply conductor 41 via the relay electrode QA3, the relay electrode QB1, and the relay electrode QC1. It is also possible to conduct the first power supply conductor 41 to the relay electrode QB2 through the conduction hole passing through the insulating layer LC and the insulating layer LD (therefore, the relay electrode QC1 is omitted). Further, as illustrated in FIGS. 9 and 11, the first power supply conductor 41 is connected to the second electrode C2 of the capacitive element C through the conduction hole HD2 of the insulating layer LD. That is, the capacitive element C is interposed between the gate GDR and the source (first power supply conductor 41) of the driving transistor TDR.

  As illustrated in FIG. 9, the first power supply conductor 41 has an opening 41A for each display pixel PE. A relay electrode QD1 is formed in the same layer as the first power supply conductor 41 and the second power supply conductor 42 inside each opening 41A. The relay electrode QD1 and the first power supply conductor 41 are formed away from each other and electrically insulated. As understood from FIGS. 4 and 9, the relay electrode QD1 is electrically connected to the relay electrode QC2 through a conduction hole HD3 formed in the insulating layer LD. Note that the relay electrode QD1 can be electrically connected to the relay electrode QB2 through a conduction hole that penetrates the insulating layer LC and the insulating layer LD (therefore, the relay electrode QC2 is omitted).

  On the other hand, the second power supply conductor 42 formed in the peripheral region 18 in which the dummy pixels PD are arranged in the first region 12 is a power supply wiring to which the lower power supply potential VCT is supplied as described above. 10 is formed in a rectangular frame shape (closed figure) surrounding the first power supply conductor 41 (display area 16) in plan view. As illustrated in FIG. 11, in the insulating layer LD, a conduction hole HD4 and a conduction hole HD5 are formed for each dummy pixel PD. The second power supply conductor 42 is conducted to the relay electrode QC1 of the dummy pixel PD through the conduction hole HD4, and is conducted to the relay electrode QC2 of the dummy pixel PD through the conduction hole HD5. On the other hand, the opening 41A and the relay electrode QD1 described above for the first power supply conductor 41 are not formed in the second power supply conductor.

  As illustrated in FIGS. 3 and 4, the optical path adjustment layer 60 is formed on the surface of the insulating layer LD on which the first power supply conductor 41, the second power supply conductor 42, and the relay electrode QD1 are formed. The optical path adjustment layer 60 is a light-transmitting film body that defines the resonance wavelength (that is, display color) of the resonance structure of each display pixel PE. Details of the resonance structure of each display pixel PE and the optical path adjustment layer 60 will be described later.

  As illustrated in FIG. 12, on the surface of the optical path adjustment layer 60, the relay electrode QE1 for each display pixel PE in the display region 16 and the relay electrode QE2 for each dummy pixel PD in the peripheral region 18 are formed from the same layer. Is done. The relay electrode QE1 and the relay electrode QE2 are made of, for example, a light-shielding conductive material (for example, titanium nitride).

  The relay electrode QE1 in the display region 16 is electrically connected to the relay electrode QD1 through a conduction hole HE1 penetrating the optical path adjustment layer 60. As understood from FIGS. 4 and 12, the relay electrode QE1 is formed so as to overlap the opening 41A of the first power supply conductor 41 in plan view. That is, the outer peripheral edge of the relay electrode QE1 is located outside the inner peripheral edge of the opening 41A in plan view. Since the relay electrode QE1 is formed of a light-shielding conductive material, the relay electrode QE1 prevents external light from entering the multilayer wiring layer from the opening 41A. Therefore, there is an advantage that current leakage of each transistor T due to light irradiation can be prevented. On the other hand, the relay electrode QE2 in the peripheral region 18 is electrically connected to the second power supply conductor 42 through the conduction hole HE2 penetrating the optical path adjusting layer 60 as understood from FIG.

  On the surface of the optical path adjustment layer 60 on which the relay electrode QE1 and the relay electrode QE2 are formed, the first electrode E1 for each display pixel PE in the display area 16 and The conductive electrode QF for each dummy pixel PD in the peripheral region 18 is formed from the same layer. The first electrode E1 and the conduction electrode QF are formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide). As described above with reference to FIG. 2, the first electrode E1 is a substantially rectangular electrode (pixel electrode) that functions as the anode of the light emitting element 45, and as illustrated in FIG. 4, the surface of the optical path adjustment layer 60. It contacts the upper relay electrode QE1. That is, the first electrode E1 is electrically connected to the active region 10A (drain) of the light emission control transistor TEL via the relay electrode QE1, the relay electrode QD1, the relay electrode QC2, the relay electrode QB2, and the relay electrode QA4.

  On the other hand, the conduction electrode QF in the peripheral region 18 is a substantially rectangular electrode formed in the same planar shape and size as the first electrode E1. The first electrodes E1 in the display area 16 and the conduction electrodes QF in the peripheral area 18 are arranged at a common pitch (period) over the X direction and the Y direction. That is, the first electrodes E1 and the conduction electrodes QF are arranged at a common pitch DX in the X direction and at a common pitch DY in the Y direction. The pitch between the first electrode E1 and the conduction electrode QF adjacent to each other across the boundary between the display region 16 and the peripheral region 18 is also set to the pitch DX in the X direction and the pitch DY in the Y direction. The pitch DX in the X direction is set to, for example, 1.3 μm or more and 3.5 μm or less. As understood from FIG. 13, the conduction electrode QF is in contact with the relay electrode QE2 on the surface of the optical path adjustment layer 60. That is, the conduction electrode QF is conducted to the second power supply conductor 42 via the relay electrode QE2. Although FIG. 13 illustrates the configuration in which the conduction electrodes QF are arranged in the peripheral region 18 over one row in the X direction and two columns in the Y direction, the number of arrangement of the conduction electrodes QF is arbitrary. . For example, the number of conductive electrodes QF is appropriately determined according to the connection resistance required between the second electrode E2 and the second power supply conductor 42, the formation range of the light emitting functional layer 46 or the second electrode E2, and the like. Selected. As understood from FIGS. 3 and 4, the first power supply conductor 41 is formed between the wiring layer in which the signal line 26 is formed and the wiring layer in which the first electrode E1 and the conduction electrode QF are formed. The

  As shown in FIG. 3, the guard ring 38 in FIG. 1 is formed by stacking a plurality of conductive layers QG (QG1 to QG6) formed from the same layer as each of the elements exemplified above. The conductive layer QG1 is formed from the same layer as the gate G of each transistor T, the conductive layer QG2 is formed from the same layer as the signal line 26, and the conductive layer QG3 is formed from the same layer as the second electrode C2 of the capacitive element C. . The conductive layer QG4 is formed from the same layer as the first power supply conductor 41 and the second power supply conductor 42, the conductive layer QG5 is formed from the same layer as the relay electrode QE2, and the conductive layer QG6 is formed from the first electrode E1 and the conductive layer. It is formed from the same layer as the common electrode QF. The conductive layers QG constituting the guard ring 38 can be omitted as appropriate. For example, the conductive layer QG3 can be omitted and the conductive layer QG2 and the conductive layer QG4 can be directly conducted.

  On the surface of the optical path adjustment layer 60 on which the relay electrode QE1, the relay electrode QE2, the first electrode E1, and the conduction electrode QF are formed, the entire region of the substrate 10 is illustrated as illustrated in FIGS. A pixel definition layer 65 is formed over the entire area. The pixel definition layer 65 is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). As understood from FIG. 14, the pixel definition layer 65 corresponds to the opening (first opening) 65 </ b> A corresponding to each first electrode E <b> 1 in the display region 16 and each conduction electrode QF in the peripheral region 18. An opening (second opening) 65B is formed. A region in the pixel definition layer 65 in the vicinity of the inner periphery of the opening 65A overlaps the periphery of the first electrode E1. That is, the inner peripheral edge of the opening 65A is located inside the peripheral edge of the first electrode E1 in plan view. Similarly, a region in the pixel definition layer 65 near the inner periphery of the opening 65B overlaps the periphery of the conduction electrode QF. As understood from FIGS. 12 and 14, the relay electrode QE1 and the relay electrode QE2 are covered with a pixel definition layer 65. Each opening 65A and each opening 65B have a common planar shape (rectangular shape) and size, and are arranged in a matrix at a common pitch in each of the X direction and the Y direction. As understood from the above description, the pixel definition layer 65 is formed in a lattice shape in plan view.

  As illustrated in FIGS. 3 and 4, the light emitting functional layer 46 is formed on the surface of the optical path adjustment layer 60 on which the first electrode E1, the conduction electrode QF, and the pixel definition layer 65 are formed. The light emitting functional layer 46 is formed in the display region 16 of the first region 12 and is continuous over a plurality of display pixels PE. On the other hand, as understood from FIG. 3, the light emitting functional layer 46 is not formed in the peripheral region 18 or the second region 14. The light emitting functional layer 46 includes a light emitting layer formed of an organic EL material, and emits white light by supplying current. Note that the light emitting functional layer 46 may include an electron or hole transport layer or an injection layer supplied to the light emitting layer.

On the surface of the optical path adjustment layer 60 on which the light emitting functional layer 46 is formed, the second electrode E2 is formed over the entire first region 12 (the display region 16 and the peripheral region 18). The second electrode E2 functions as the cathode of the light emitting element 45 as described above with reference to FIG. As illustrated in FIG. 4, a region (light emitting region) sandwiched between the first electrode E1 and the second electrode E2 inside the opening 65A of the pixel defining layer 65 in the light emitting functional layer 46 emits light. That is, a portion where the first electrode E1, the light emitting functional layer 46, and the second electrode E2 are stacked inside the opening 65A functions as the light emitting element 45. As understood from the above description, the pixel definition layer 65 defines the planar shape and size (area where light is actually emitted) of the light emitting element 45 of each display pixel PE. The light emitting device 100 of the first embodiment is a micro display in which the light emitting elements 45 are arranged with very high definition. For example, the area of one light emitting element 45 (the area of one opening 65A) is set to 40 μm ² or less, and the interval between the light emitting elements 45 adjacent to each other in the X direction is 1.2 μm or more and 1.5 μm or less. Set to

  Since the light emitting functional layer 46 is not formed in the peripheral region 18 as described above, the portion located in the peripheral region 18 of the second electrode E2 over the entire first region 12 is the opening 65B of the pixel defining layer 65 in FIG. In contact with the conduction electrode QF. As can be understood from the above description, the second electrode E2 extending over both the display region 16 and the peripheral region 18 is connected to the second power source conductor 42 via the conductive electrodes QF and the relay electrodes QE2 in the peripheral region 18. Conducted to. That is, the lower power supply potential VCT is supplied from the second power supply conductor 42 to the second electrode E2 through the relay electrode QE2 and the conduction electrode QF.

  The second electrode E2 functions as a semi-transmissive reflective layer having a property of transmitting part of the light reaching the surface and reflecting the rest (semi-transmissive reflective). For example, the transflective second electrode E2 is formed by forming a light-reflective conductive material such as an alloy containing silver or magnesium in a sufficiently thin film thickness. The radiated light from the light emitting functional layer 46 reciprocates between the first power supply conductor 41 and the second electrode E2, and a specific resonance wavelength component is selectively amplified and then transmitted through the second electrode E2. To the observation side (the side opposite to the substrate 10). That is, a resonance structure is formed that resonates the light emitted from the light emitting functional layer 46 between the first power supply conductor 41 functioning as a reflective layer and the second electrode E2 functioning as a semi-transmissive reflective layer. The optical path adjustment layer 60 is an element for individually setting the resonance wavelength (display color) of the resonance structure for each display color of the display pixel PE. Specifically, each optical path length (optical distance) between the first power supply conductor 41 and the second electrode E2 constituting the resonance structure is adjusted appropriately according to the film thickness of the optical path adjustment layer 60. The resonance wavelength of the light emitted from the display pixel PE is set for each display color.

  FIG. 15 is a cross-sectional view illustrating the configuration of three display pixels PE (red, green, and blue) having different display colors, focusing on the specific configuration of the optical path adjustment layer 60. In FIG. 15, a display pixel PE corresponding to red (R), a display pixel PE corresponding to green (G), and a display pixel PE corresponding to blue (B) are illustrated for convenience. As understood from FIG. 15, the optical path adjustment layer 60 is composed of a plurality of layers (first adjustment layer 61, second adjustment layer 61 made of a light transmissive insulating material such as a silicon compound (typically silicon nitride or silicon oxide)). The adjustment layer 62 and the third adjustment layer 63) are stacked. The first adjustment layer 61 is formed of, for example, silicon nitride with a thickness of 40 nm or more and 100 nm or less, and the second adjustment layer 62 is formed of, for example, silicon oxide with a thickness of 40 nm or more and 50 nm or less. 63 is formed of, for example, silicon oxide with a film thickness of 40 nm or more and 70 nm or less.

  The second adjustment layer 62 and the third adjustment layer 63 are selectively removed according to the display color of each display pixel PE. Specifically, in the blue display pixel PE, the second adjustment layer 62 and the third adjustment layer 63 are removed, so that the optical path adjustment layer 60 includes only the first adjustment layer 61. In the green display pixel PE, By removing the third adjustment layer 63, the optical path adjustment layer 60 is constituted by the first adjustment layer 61 and the second adjustment layer 62. On the other hand, in the red display pixel PE, the optical path adjustment layer 60 is configured by stacking the first adjustment layer 61, the second adjustment layer 62, and the third adjustment layer 63. For example, when the first adjustment layer 61 is formed with a film thickness of 50 nm, the second adjustment layer 62 is formed with a film thickness of 65 nm, and the third adjustment layer 63 is formed with a film thickness of 55 nm, the red display pixel PE The 170 nm optical path adjustment layer 60 (first adjustment layer 61 + second adjustment layer 62 + third adjustment layer 63) is configured, and the 115 nm optical path adjustment layer 60 (first adjustment layer 61 + second adjustment layer 62) in the green display pixel PE. ), And a 50 nm optical path adjustment layer 60 (first adjustment layer 61) is formed in the blue display pixel PE. In the above example, the difference in film thickness of the optical path adjustment layer 60 between the red display pixel PE and the blue display pixel PE is 120 nm. In the above description, the display area 16 is focused. However, the optical path adjustment layer 60 having the same configuration as that in the display area 16 is formed for each dummy pixel PD in the peripheral area 18.

  Since the light emitting functional layer 46 is not formed in the peripheral region 18 as described above, the portion located in the peripheral region 18 of the second electrode E2 over the entire first region 12 is the opening 65B of the pixel defining layer 65 in FIG. In contact with the conduction electrode QF. As can be understood from the above description, the second electrode E2 extending over both the display region 16 and the peripheral region 18 is connected to the second power source conductor 42 via the conductive electrodes QF and the relay electrodes QE2 in the peripheral region 18. Conducted to. That is, the lower power supply potential VCT is supplied from the second power supply conductor 42 to the second electrode E2 through the relay electrode QE2 and the conduction electrode QF.

  As illustrated in FIG. 3, a sealing body 70 is formed on the entire surface of the substrate 10 on the surface of the second electrode E2. In FIG. 4, the sealing body 70 is not shown for convenience. The sealing body 70 is a light-transmitting film body that seals each element formed on the substrate 10 to prevent intrusion of outside air and moisture, and includes a first sealing layer 71 and a second sealing layer. 72 and a third sealing layer 73. A second sealing layer 72 is formed on the surface of the first sealing layer 71, and a third sealing layer 73 is formed on the surfaces of the first sealing layer 71 and the second sealing layer 72. As understood from FIG. 3, the first sealing layer 71 and the third sealing layer 73 are formed over the entire region of the substrate 10 including the first region 12 and the second region 14. On the other hand, the second sealing layer 72 is formed in the first region 12 of the substrate 10 and is not formed in the second region 14. Specifically, as illustrated in FIG. 16, the second sealing layer 72 is formed over the display region 16 and a partial region on the inner peripheral side of the peripheral region 18. As understood from the above description, the sealing body 70 of FIG. 3 has a total of three layers of the first sealing layer 71, the second sealing layer 72, and the third sealing layer 73 in the display region 16. In the second region 14, the first sealing layer 71 and the second sealing layer 72 are laminated in total. Each mounting terminal 36 in FIG. 1 is exposed to the outside through an opening formed in a region connected to a flexible wiring board in the sealing body 70. Each mounting terminal 36 includes, for example, a conductive layer formed from the same layer as the first power supply conductor 41 and the second power supply conductor 42, a conductive layer formed from the same layer as the relay electrode QE2, and a first electrode E1. The conductive electrode QF and a conductive layer formed from the same layer are used.

  The first sealing layer 71 of the sealing body 70 is formed on the surface of the second electrode E2, and is in direct contact with the surface of the second electrode E2. The first sealing layer 71 is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide), for example, with a thickness of about 200 nm to 400 nm. The first sealing layer 71 is suitably formed with a film thickness that is greater than or equal to the film thickness difference (for example, 120 nm) of the optical path adjustment layer 60. For the formation of the first sealing layer 71, a high-density plasma film forming technique such as a plasma CVD (Chemical Vapor Deposition) method, an ECR (Electron Cyclotron Resonance) plasma sputtering method, or an ion plating method is preferably used. It is also possible to form the first sealing layer 71 of silicon oxynitride by depositing silicon oxide in a nitrogen atmosphere. In addition, an inorganic oxide typified by a metal oxide such as titanium oxide can also be adopted as the material of the first sealing layer 71.

  The second sealing layer 72 of the sealing body 70 functions as a planarizing film that fills the unevenness on the surfaces of the second electrode E2 and the first sealing layer 71. That is, the surface of the second electrode E2 and the first sealing layer 71 is formed with unevenness reflecting the shape of each element on the lower side (substrate 10 side), but the surface of the second sealing layer 72 is uneven. It is a substantially flat surface that is sufficiently reduced. In other words, the upper surface of the second sealing layer 72 is flat compared to the lower surface (that is, the contact surface with the first sealing layer 71). The second sealing layer 72 has a sufficiently thick film thickness (for example, 1 μm to 5 μm, for example) compared to the first sealing layer 71 and the third sealing layer 73 so that the planarization function described above is realized. And particularly preferably 3 μm). For example, the second sealing layer 72 is formed by applying a solution of a light transmissive organic material such as an epoxy resin to the surface of the first sealing layer 71 by a known coating technique (for example, a printing method or a spin coating method) and drying the solution. Is formed. Note that the material of the second sealing layer 72 is not limited to an organic material. For example, the second sealing layer 72 having a film thickness sufficient for planarization can be formed by applying an inorganic material such as silicon oxide by a coating technique such as a printing method and drying it. The second sealing layer 72 is formed so as to be continuous over a wide area as compared with the area where the light emitting functional layer 46 is formed and to cover at least the light emitting functional layer 46. A configuration in which the second sealing layer 72 covers the second electrode E2 may also be employed.

  The third sealing layer 73 is an inorganic material having excellent water resistance and heat resistance, for example, and is formed to a film thickness of, for example, about 300 nm to 700 nm (particularly preferably about 400 nm). For example, a nitrogen compound (silicon nitride, silicon oxide, silicon oxynitride) is suitable as the material of the third sealing layer 73. For the formation of the third sealing layer 73, a known film forming technique exemplified for the first sealing layer 71 is arbitrarily employed.

  A sealing substrate (not shown) is bonded to the surface of the substrate 10 on which the above elements are formed, for example, with an adhesive. The sealing substrate is a light-transmitting plate member (for example, a glass substrate) for protecting each element on the substrate 10. It is also possible to form a color filter for each display pixel PE on the surface of the sealing substrate or the surface of the sealing body 70 (third sealing layer 73).

  As described above, in the first embodiment, the conduction electrode QF formed from the same layer as the first electrode E1 in the display region 16 and the first power supply conductor 41 in the display region 16 are formed from the same layer. The second power source conductor 42 is formed in the peripheral region 18, and the second electrode E 2 extending over both the display region 16 and the peripheral region 18 is connected to the second power source conductor via the conduction electrode QF in the peripheral region 18. 42 conducts. That is, similarly to the layer structure in which the first power supply conductor 41 and the first electrode E1 overlap in the display region 16, the second power supply conductor 42 and the conduction electrode QF also overlap in the peripheral region 18. Therefore, a step between the display region 16 and the peripheral region 18 can be suppressed as compared with the configuration of Patent Document 1 in which the anode of the light emitting element is not formed in the dummy pixel in the adjacent region. In addition, since the step between the display region 16 and the peripheral region 18 is suppressed, there is an advantage that the sealing body 70 can be easily formed as compared with a configuration in which the step between the display region 16 and the peripheral region 18 is large. In the first embodiment, in particular, the first electrode E1 in the display region 16 and the conduction electrode QF in the peripheral region 18 have the same planar shape and size, the pitch DX in the X direction, and the pitch DY in the Y direction. Therefore, the effect of suppressing the level difference between the display area 16 and the peripheral area 18 is particularly remarkable.

  In addition, the pixel definition layer 65 extending over both the display region 16 and the peripheral region 18 corresponds to the conduction electrode QF in the peripheral region 18 in addition to the opening 65A corresponding to the first electrode E1 in the display region 16. An opening 65B is formed. In other words, the pixel definition layer 65 also has a structure similar to that of the display area 16 in the peripheral area 18. Therefore, the step difference between the display region 16 and the peripheral region 18 is suppressed as compared with the configuration in which the pixel definition layer 65 is not formed in the peripheral region 18 and the configuration in which the opening 65B is not formed in the pixel definition layer 65 in the peripheral region 18. Is possible. In the first embodiment, in particular, the opening 65A and the opening 65B have the same planar shape and size, and the pitch of the arrangement in the X direction and the Y direction, so that the step between the display area 16 and the peripheral area 18 is suppressed. The effect is particularly remarkable.

  In the first embodiment, since the first power supply conductor 41 is formed from a different layer from the scanning line 22, the control line 24, and the signal line 26, the first power supply conductor 41 is formed from the same layer as each wiring. It is possible to sufficiently secure the area of the first power supply conductor 41 (reducing the resistance of the first power supply conductor 41). Specifically, as described with reference to FIG. 10, the first power supply conductor 41 can be formed as a solid pattern over the entire display region 16. Therefore, the voltage drop of the power supply potential VEL in the plane of the first power supply conductor 41 is suppressed, and as a result, display spots of the display image (difference in display gradation in the plane of the display area 16) can be reduced. It is. In the above description, the first power supply conductor 41 is focused. However, the same applies to the second power supply conductor 42 formed from a layer different from each wiring (scanning line 22, control line 24, signal line 26). The effect is realized.

  In the configuration in which the first power supply conductor 41 and the second power supply conductor 42 are formed from the same layer, the first power supply conductor 41 and the second power supply conductor 42 are caused by, for example, irregularities on the surface of the insulating layer LD. May short-circuit each other. In the first embodiment, since the first power supply conductor 41 and the second power supply conductor 42 are formed after the planarization process is performed on the surface of the insulating layer LD, the unevenness on the surface of the insulating layer LD is formed. There is also an advantage that a short circuit between the first power supply conductor 41 and the second power supply conductor 42 can be effectively prevented.

Second Embodiment
A second embodiment of the present invention will be described. In addition, about the element which an effect | action and function are the same as that of 1st Embodiment in each form illustrated below, the reference | standard referred by description of 1st Embodiment is diverted, and each detailed description is abbreviate | omitted suitably.

  FIG. 17 is a plan view focusing on the sealing body 70 in the light emitting device 100 of the second embodiment. As illustrated in FIG. 17, in the light emitting device 100 of the second embodiment, a region (hereinafter referred to as “terminal region”) 15 in which a plurality of mounting terminals 36 are arranged in the second region 14 of the substrate 10 is sealed. The body 70 is not formed. Specifically, the first sealing layer 71 and the third sealing of the sealing body 70 span the first region 12 including the display region 16 and the peripheral region 18 and the region other than the terminal region 15 in the second region 14. Layer 73 is formed. The configuration in which the second sealing layer 72 of the sealing body 70 is formed in the display region 16 is the same as in the first embodiment. According to the above configuration, in addition to the same effect as that of the first embodiment, there is an advantage that it is not necessary to form a conduction hole in the sealing body 70 for conducting each mounting terminal 36 to the wiring in the multilayer wiring layer. There is. A plurality of mounting terminals 36 may be arranged along two or three sides of the substrate 10.

<Modification>
The above forms can be variously modified. Specific modifications are exemplified below. Two or more aspects arbitrarily selected from the following examples can be appropriately combined within a range that does not contradict each other.

(1) In each of the above-described embodiments, the sealing body 70 having a structure in which the first sealing layer 71, the second sealing layer 72, and the third sealing layer 73 are stacked is illustrated. The number (single layer / multiple layers) is arbitrary. For example, the sealing body 70 can be configured by a single layer of an inorganic material or an organic material. Further, in each of the above-described embodiments, the guard ring 38 is illustrated as being configured to overlap with the whole (first embodiment) or part (second embodiment) of the sealing body 70 in plan view. The presence or absence of overlap with the ring 38 is not questioned.

(2) In each of the above-described embodiments, the second electrode E2 is electrically connected to the second power supply conductor 42 through the opening 65B formed in the pixel definition layer 65 in the same manner as the opening 65A in the display region 16. However, the structure for conducting the second electrode E2 and the second power supply conductor 42 is appropriately changed. For example, as disclosed in Japanese Patent Application Laid-Open No. 2005-352498, the pixel definition layer 65 is formed through an opening formed in a straight line shape (that is, an aspect different from the opening 65A in the display region 16) in plan view. It is also possible to make the two electrodes E2 and the second power supply conductor 42 conductive.

(3) In each of the above-described embodiments, the light emitting device 100 using the semiconductor substrate as the substrate 10 is illustrated, but the material of the substrate 10 is arbitrary. For example, a plate-like member such as glass or quartz can be used as the substrate 10. In each of the above-described embodiments, the drive circuit 30 is disposed in the second region 14 outside the first region 12 of the substrate 10. However, the drive circuit 30 may be disposed in the peripheral region 18, for example. For example, the drive circuit 30 is disposed between the second power supply conductor 42 and the substrate 10.

(4) The configuration of the pixel P (pixel circuit) is not limited to the configuration illustrated in FIG. For example, a configuration in which the light emission control transistor TEL in each form described above is omitted, or a configuration in which an error in the threshold voltage of the driving transistor TDR is compensated by diode-connecting the driving transistor TDR before the gradation potential is supplied can be employed.

(5) The structure of the light emitting element 45 is not limited to the above illustration. For example, in each of the above-described embodiments, the configuration in which the light emitting functional layer 46 that generates white light is continuously formed over the plurality of display pixels PE is exemplified. However, monochromatic light having a wavelength corresponding to the display color of each display pixel PE is emitted. It is also possible to individually form the light emitting functional layer 46 for each display pixel PE. In each of the above-described embodiments, a resonant structure is formed between the first power supply conductor 41 (reflective layer) and the second electrode E2 (semi-transmissive reflective layer). For example, the first electrode E1 is formed as a reflective conductive material. It is also possible to form a resonance structure between the first electrode E1 (reflective layer) and the second electrode E2 (semi-transmissive reflective layer) by using a material. In the configuration using the first electrode E1 as the reflective layer, the optical path adjustment layer 60 is formed between the first electrode E1 and the second electrode E2. It is also possible to form a reflective layer (a reflective layer for each display pixel PE or a reflective layer continuous over a plurality of display pixels PE) separately from the first power supply conductor 41 and the first electrode E1.

  In each of the above-described embodiments, the resonance wavelength of each display pixel PE is adjusted by the optical path adjustment layer 60. However, the resonance wavelength of each display pixel PE may be adjusted according to the film thickness of the first electrode E1 and the light emitting functional layer 46. Is possible. Regardless of the specific configuration for adjusting the resonance wavelength, a configuration in which the first sealing layer 71 is formed with a film thickness that exceeds the step due to the difference in the resonance wavelength is preferable.

  In each of the above-described embodiments, the light emitting element 45 using the organic EL material is exemplified. However, the present invention is similarly applied to a configuration using a light emitting element in which a light emitting layer is formed with an inorganic EL material or a light emitting element such as an LED. . Further, in each of the above-described embodiments, the top emission type light emitting device 100 that emits light to the side opposite to the substrate 10 is illustrated, but the present invention also applies to a bottom emission type light emitting device that emits light to the substrate 10 side. The same applies.

(6) In each of the above-described embodiments, the configuration in which the dummy pixel PD having a structure similar to the display pixel PE (structure such as a wiring, a transistor, and a capacitor element) is disposed in the peripheral region 18 is illustrated. The configuration is not limited to the above examples. For example, a circuit other than the driving circuit 30 (the scanning line driving circuit 32 or the signal line driving circuit 34) or the driving circuit 30 and wirings can be arranged below the second power supply conductor 42 in the peripheral region 18. .

(7) In each of the above-described embodiments, attention is paid to the film thickness of the optical path adjustment layer 60 in order to simplify the description of the resonance wavelength. However, in reality, the reflection layer (for example, the first power supply conductor 41) having the resonance structure is used. The resonant wavelength of the resonant structure is set according to the refractive index of each layer positioned between the semi-transmissive reflective layer (for example, the second electrode E2) and the phase shift on the surfaces of the reflective layer and the semi-transmissive reflective layer.

<Electronic equipment>
The light emitting device 100 exemplified in each of the above embodiments is suitably used as a display device for various electronic devices. In FIG. 18, a head-mounted display device 90 (HMD: Head Mounted Display) using the light emitting device 100 exemplified in each of the above embodiments is illustrated as an electronic device.

  The display device 90 is an electronic device that can be worn on the user's head, and includes a transmissive portion (lens) 92L that overlaps the user's left eye, a transmissive portion 92R that overlaps the user's right eye, and a left-eye device. The light-emitting device 100L and the half mirror 94L, and the right-eye light-emitting device 100R and the half mirror 94R are provided. The light emitting device 100L and the light emitting device 100R are arranged so that the emitted light travels in opposite directions. The half mirror 94L for the left eye transmits the transmitted light of the transmission part 92L to the left eye side of the user and reflects the emitted light from the light emitting device 100L to the left eye side of the user. Similarly, the right-eye half mirror 94R transmits the light transmitted through the transmission portion 92R to the right eye side of the user and reflects the light emitted from the light emitting device 100R to the right eye side of the user. Therefore, the user perceives an image obtained by superimposing an image observed through the transmission unit 92L and the transmission unit 92R and a display image by each light emitting device 100. In addition, the stereoscopic image (the image for the left eye and the image for the right eye) with parallax added to each other is displayed on the light emitting device 100L and the light emitting device 100R, thereby allowing the user to perceive the stereoscopic effect of the display image. Is possible.

  Note that an electronic apparatus to which the light-emitting device 100 of each embodiment described above is applied is not limited to the display device 90 in FIG. For example, the light emitting device 100 of the present invention is also preferably used in an electronic view finder (EVF) used in an imaging device such as a video camera or a still camera. In addition, the light emitting device of the present invention can be used in various electronic devices such as mobile phones, personal digital assistants (smartphones), monitors such as televisions and personal computers, and car navigation devices.

DESCRIPTION OF SYMBOLS 100 ... Light-emitting device, 10 ... Board | substrate, 10A ... Active area | region, 12 ... 1st area | region, 14 ... 2nd area | region, 16 ... Display area, 18 ... Peripheral area | region, 22 ... Scanning line, 24 ... Control line 26... Signal line 30... Drive circuit 32... Scan line drive circuit 34 34 Signal line drive circuit 36... Mounting terminal 41. ... second power source conductor 45 ... light emitting element, E1 ... first electrode, E2 ... second electrode, 46 ... light emitting functional layer, TDR ... driving transistor, TEL ... light emission control transistor, TSL ... Selection transistor, C: Capacitance element, 60: Optical path adjustment layer, 65: Pixel definition layer, 65A, 65B ... Opening, 70: Sealing body, 71: First sealing layer, 72: Second sealing layer, 73... Third sealing layer, Q (QA1, QA2, QA3, QA4, QB1, QB2, QC1, QC2, QD 1, QE1, QE2) ... Relay electrode, QF ... Conduction electrode.

Claims (6)

A first power supply conductor to which a first potential is supplied;
A first electrode corresponding to each pixel in the display area;
A light emitting functional layer overlapping the first electrode;
A transistor that is electrically connected between the first electrode and the first power supply conductor and controls supply of current to the light emitting functional layer;
A second power supply conductor formed in the same area as the first power supply conductor in a peripheral region around the display area, and supplied with a second potential different from the first potential;
A conducting electrode formed from the same layer as the first electrode and conducting to the second power source conductor;
The light emitting functional layer is formed between the display region and the peripheral region, and the light emitting functional layer is sandwiched between the display region and the first electrode, while the peripheral region is electrically connected to the second power supply conductor via the conductive electrode. and a second electrode which,
Comprising a pixel definition layer covering a formation surface of the first electrode and the conductive electrode;
In the pixel definition layer, a first opening corresponding to the first electrode and a second opening corresponding to the conduction electrode are formed,
The light emitting functional layer is in contact with the first electrode through the first opening,
The second electrode is in contact with the conducting electrode through the second opening,
The light emitting device in which the first electrode and the conductive electrode have a common planar shape and size . A plurality of first electrodes are arranged in the display area,
A plurality of conductive electrodes are arranged in the peripheral region,
The light emitting device according to claim 1, wherein the pitch of the arrangement of the plurality of first electrodes in the display area is common to the pitch of the arrangement of the plurality of conductive electrodes in the peripheral area. Gradation potential corresponding to the specified gradation comprises a signal line for supplying a gate of said transistor, said first power supply conductor is according to claim 1 or 2, wherein the signal line is formed from another layer Light emitting device. The light emitting device according to any one of claims 1 to 3 , wherein the first power supply conductor and the second power supply conductor are formed on a surface of an insulating layer on which a planarization process has been performed. Any of the light-emitting device of claims 1 to 4 having a sealing body covering the second electrode is formed over both the display region and the peripheral region. An electronic device including any of the light-emitting device of claims 1 to 5.

Images