JP6658794B2 - Light emitting device and electronic equipment - Google Patents

Description

  The present invention relates to a light emitting device using a light emitting material such as an organic EL material.

  A light emitting device in which light emitting elements using an organic EL material are arranged in a display region of a substrate has been conventionally proposed. The light-emitting element includes a first electrode (anode), a second electrode (cathode), and a light-emitting functional layer that emits light in response to a current between the two electrodes, and a potential corresponding to luminance of light emission is supplied to the first electrode. , The second electrode is supplied with a lower power supply potential. Patent Literature 1 discloses a light-emitting device in which a power supply conductor (peripheral wiring) connected to a second electrode of a light-emitting element and supplying a power supply potential is formed around a display area in plan view. In the technique disclosed in Patent Document 1, the second electrode is formed on the surface of the light emitting function layer in the display area, and is electrically connected to the peripheral wiring through a through hole formed in the insulating layer around the display area.

JP 2013-54863 A

  In the technique of Patent Document 1, the periphery of the light emitting functional layer overlaps with the conductive hole used for conduction between the second electrode and the peripheral wiring (that is, a part of the conductive hole is covered with the light emitting functional layer). The second electrode and the peripheral wiring cannot be brought into contact with each other in the entire area inside the conduction hole. Therefore, as compared with the configuration in which the second electrode and the peripheral wiring contact all over the conduction hole, the area where the second electrode and the peripheral wiring contact in the conduction hole becomes smaller, and the second electrode and the peripheral wiring are connected to each other. Connection becomes insufficient. In view of the above circumstances, it is an object of the present invention to provide sufficient conduction between an electrode of a light emitting element and a peripheral wiring.

  In order to solve the above problems, a light emitting device of the present invention includes a peripheral wiring, an insulating layer covering the peripheral wiring, a first electrode and a second electrode disposed in a display region of a base, and a surface of the insulating layer. A light-emitting element including a light-emitting functional layer formed thereon and emitting light in response to a current between the first electrode and the second electrode, wherein the second electrode covers the light-emitting functional layer in the display region; In a first region located around the display region in a plan view, the first region is connected to the peripheral wiring through a conduction hole in the insulating layer, and a periphery of the light emitting functional layer is located between the display region and the first region in a plan view. And the peripheral wiring is formed over the first region and the second region. In the above configuration, the periphery of the light emitting function layer is located in the second region located on the display region side with respect to the first region in which the conduction hole for conducting the second electrode and the peripheral wiring is formed. That is, the light emitting functional layer does not intervene between the second electrode and the peripheral wiring inside the conduction hole of the insulating layer. Therefore, as compared with the configuration in which the light emitting functional layer is located inside the conduction hole in plan view (the configuration in which the light emitting functional layer is interposed between the second electrode and the peripheral wiring inside the conduction hole), It is possible to sufficiently conduct with the peripheral wiring. If only the conduction between the second electrode and the peripheral wiring is considered, it is sufficient that the peripheral wiring exists only in the first region where the conduction hole is formed. In the present invention, the peripheral wiring is formed so as to extend to the second region in addition to the first region. That is, the area of the peripheral wiring is sufficiently secured as compared with the configuration in which the peripheral wiring is formed only in the first region. Therefore, there is an advantage that the resistance of the peripheral wiring is reduced.

  In a preferred aspect of the present invention, the light emitting functional layer overlaps the peripheral wiring in a plan view. According to the above configuration, the peripheral wiring is formed wider in the second region than in a configuration in which the peripheral wiring does not overlap the light emitting function layer in plan view. Therefore, the resistance of the peripheral wiring is further reduced.

  In a preferred aspect of the present invention, the peripheral wiring and the conductive hole are formed in a continuous frame shape surrounding the display area in a plan view, and the second electrode is connected to the peripheral wiring over the entire periphery of the first area via the conductive hole. To conduct. In the above configuration, the second electrode and the peripheral wiring are electrically connected to each other over the entire periphery of the first region via the frame-shaped conductive hole surrounding the display region. Therefore, the effect that the second electrode and the peripheral wiring are sufficiently connected is particularly remarkable.

  In a preferred aspect of the present invention, a light-shielding layer formed of a first wiring layer of a light-shielding conductive material and shielding light toward the base is provided, and the peripheral wiring is formed of a first wiring layer formed of the first wiring layer. Including wiring. According to the above configuration, since external light traveling toward the base is shielded by the light-shielding layer, there is an advantage that a current leak due to light irradiation can be prevented, for example, in an active element formed on the surface of the base. Further, since both the first wiring and the light shielding layer are formed by the first wiring layer, they can be formed collectively in a common process. Therefore, there is an advantage that the manufacturing process is simplified as compared with the case where the light shielding layer is formed in a step separate from the formation of the first wiring.

  In a preferred aspect of the present invention, the semiconductor device further includes a reflecting layer formed of a second wiring layer of a light-reflective conductive material and reflecting light toward the base, and the peripheral wiring is formed of a second wiring layer formed of the second wiring layer. Including wiring. According to the above configuration, external light traveling toward the base can be reflected by the reflective layer. Further, since both the second wiring and the reflection layer are formed in the second wiring layer, they can be formed collectively in a common process. Therefore, there is an advantage that the manufacturing process is simplified as compared with the case where the reflective layer is formed in a step separate from the formation of the second wiring.

  In a preferred aspect of the present invention, the width of the second region is larger than the width of the first region in plan view. According to the above configuration, as compared with a configuration in which the width of the second region is smaller than the width of the first region in plan view, the area where the peripheral wiring is formed is widened, and the resistance of the peripheral wiring is reduced. Is particularly remarkable.

  In a preferred aspect of the present invention, a sealing layer formed on a surface of the second electrode to seal the light emitting element is provided, and a periphery of the sealing layer is opposite to the display area of the first area in plan view. The peripheral wiring is located in the third region located on the side, and is formed over the first region and the third region. In the above structure, the sealing layer for sealing the light emitting element is provided, so that the sealing performance of the light emitting element is improved. Further, in the present invention, the peripheral wiring is formed so as to extend to the third region in addition to the first region. That is, the area of the peripheral wiring is sufficiently secured as compared with the configuration in which the peripheral wiring is formed only in the first region. Therefore, the effect of reducing the resistance of the peripheral wiring is particularly remarkable.

  In a preferred aspect of the present invention, the width of the third region in plan view is larger than the width of the first region. According to the above configuration, as compared with a configuration in which the width of the third region is smaller than the width of the first region in a plan view, the area where the peripheral wiring can be formed is widened, and the effect of reducing the resistance of the peripheral wiring is It is particularly remarkable.

  The light emitting device according to each of the above aspects is used for various electronic devices as a display device, for example. Specifically, a head-mounted display device, an electronic viewfinder of an imaging device, and the like can be exemplified as preferred examples of the electronic apparatus of the present invention, but the scope of the present invention is not limited to the above examples.

FIG. 2 is a plan view of the light emitting device according to the first embodiment of the present invention. It is a circuit diagram of a pixel. It is sectional drawing of a light emitting device. It is sectional drawing of a light emitting device. FIG. 3 is an illustrative diagram of each element that is formed on the substrate. FIG. 3 is an illustrative diagram of each element that is formed on the substrate. FIG. 3 is an illustrative diagram of each element that is formed on the substrate. FIG. 3 is an illustrative diagram of each element that is formed on the substrate. FIG. 3 is an illustrative diagram of each element that is formed on the substrate. It is a schematic diagram of a 1st power supply conductor and a 2nd power supply conductor. FIG. 3 is an explanatory diagram of a positional relationship between elements formed on a substrate. It is an explanatory view of the effect of the 2nd conductor. It is a top view of each conduction hole formed in the peripheral region. It is sectional drawing of the vicinity of the conduction hole formed in the peripheral area in the comparative example. FIG. 2 is a cross-sectional view of the vicinity of a periphery of a light emitting functional layer according to the first embodiment of the present invention and a comparative example. It is sectional drawing of a sealing body and a filter layer. It is a top view of a sealing body and a filter layer. It is sectional drawing of a sealing body and a filter layer in a comparative example. It is sectional drawing of the sealing body in 2nd Embodiment, and a filter layer. It is sectional drawing of the sealing body in a modification, and a filter layer. It is a top view of the light emitting functional layer in a modification. It is a schematic diagram of a head-mounted display device as an example of an electronic apparatus.

<First embodiment>
FIG. 1 is a plan view of a light emitting device 100 according to the first embodiment of the present invention. The light emitting device 100 of the first embodiment is an organic EL device in which a light emitting element using an organic EL material is formed on a surface of a substrate 10. The substrate 10 is a plate-shaped member (semiconductor substrate) formed of a semiconductor material such as silicon (silicon), and is used as a base (base) on which a plurality of light emitting elements are formed.

  As illustrated in FIG. 1, a display area 12, a peripheral area 14, and a mounting area 16 are defined on the surface of the substrate 10. The display area 12 is a rectangular area in which a plurality of pixels P are arranged. The display area 12 includes a plurality of scanning lines 22 extending in the X direction, a plurality of control lines 24 extending in the X direction corresponding to each scanning line 22, and a plurality of control lines 24 extending in the Y direction crossing the X direction. And a plurality of signal lines 26 are formed. A pixel P is formed corresponding to each intersection of the plurality of scanning lines 22 and the plurality of signal lines 26. Therefore, the plurality of pixels P are arranged in a matrix in the X direction and the Y direction.

  The peripheral area 14 is a rectangular frame-shaped area surrounding the display area 12. The drive circuit 30 is provided in the peripheral area 14. The drive circuit 30 is a circuit that drives each pixel P in the display area 12, and includes two scan line drive circuits 32 and a signal line drive circuit. The light-emitting device 100 according to the first embodiment is a display device with a built-in circuit in which a drive circuit 30 is configured by active elements such as transistors formed directly on the surface of a substrate 10. Note that a dummy pixel that does not directly contribute to image display can be formed in the peripheral region 14.

  The mounting area 16 is an area on the opposite side of the display area 12 with respect to the peripheral area 14 (ie, outside the peripheral area 14), and a plurality of mounting terminals 36 are arranged. A control signal and a power supply potential are supplied to each mounting terminal 36 from various external circuits (not shown) such as a control circuit and a power supply circuit. The external circuit is mounted on, for example, a flexible wiring board (not shown) bonded to the mounting area 16.

  FIG. 2 is a circuit diagram of each pixel (pixel circuit) P in the display area 12. As illustrated in FIG. 2, the pixel P includes a light emitting element 45, a driving transistor TDR, a light emission control transistor TEL, a selection transistor TSL, and a capacitor C. In the first embodiment, each transistor T (TDR, TEL, TSL) of the pixel P is a P-channel type. However, an N-channel type transistor can be used.

  The light emitting element 45 is an electro-optical element in which a light emitting functional layer 46 including a light emitting layer of an organic EL material is interposed between a first electrode (anode) E1 and a second electrode (cathode) E2. The first electrode E1 is individually formed for each pixel P, and the second electrode E2 is continuous over a plurality of pixels P. As understood from FIG. 2, the light emitting element 45 is disposed on a current path connecting the first power supply conductor 41 and the second power supply conductor 42. The first power supply conductor 41 is a power supply wiring to which a higher power supply potential (first potential) VEL is supplied, and the second power supply conductor 42 is supplied with a lower power supply potential (second potential) VCT. Power wiring.

  The driving transistor TDR and the light emission control transistor TEL are arranged in series with the light emitting element 45 on a current path connecting the first power supply conductor 41 and the second power supply conductor 42. Specifically, one (source) of a pair of current terminals of the driving transistor TDR is connected to the first power supply conductor 41. The light emission control transistor TEL functions as a switch for controlling the conduction state (conduction / non-conduction) between the other (drain) of the pair of current terminals of the driving transistor TDR and the first electrode E1 of the light emitting element 45. The drive transistor TDR generates a drive current of a current amount according to the voltage between its own gate and source. In a state where the light-emitting control transistor TEL is controlled to the ON state, the driving current is supplied from the driving transistor TDR to the light-emitting element 45 via the light-emitting control transistor TEL, so that the light-emitting element 45 responds to the amount of the driving current. Emit light with brightness. In a state where the light emission control transistor TEL is controlled to be in the off state, the supply of the driving current to the light emitting element 45 is cut off, so that the light emitting element 45 is turned off. The gate of the light emission control transistor TEL is connected to the control line 24.

  The selection transistor TSL in FIG. 2 functions as a switch that controls the conduction state (conduction / non-conduction) between the signal line 26 and the gate of the driving transistor TDR. The gate of the selection transistor TSL is connected to the scanning line 22. Further, the capacitance element C is a capacitance in which a dielectric is interposed between the first electrode C1 and the second electrode C2. The first electrode C1 is connected to the gate of the driving transistor TDR, and the second electrode C2 is connected to the first power supply conductor 41 (the source of the driving transistor TDR). Therefore, the capacitive element C holds the voltage between the gate and the source of the driving transistor TDR.

  The signal line drive circuit 34 applies a gradation potential (data signal) corresponding to a gradation designated for each pixel P by an image signal supplied from an external circuit to a plurality of signal lines 26 in each writing period (horizontal scanning period). Are supplied in parallel. On the other hand, each scanning line drive circuit 32 sequentially selects each of the plurality of scanning lines 22 for each writing period by supplying a scanning signal to each scanning line 22. The selection transistor TSL of each pixel P corresponding to the scanning line 22 selected by the scanning line driving circuit 32 transits to the ON state. Accordingly, the gate of the driving transistor TDR of each pixel P is supplied with the gradation potential via the signal line 26 and the selection transistor TSL, and the capacitor C holds a voltage corresponding to the gradation potential. On the other hand, when the selection of the scanning line 22 in the writing period is completed, each scanning line driving circuit 32 supplies a control signal to each control line 24 to thereby control the light emission control transistor of each pixel P corresponding to the control line 24. Control TEL to ON state. Therefore, a driving current corresponding to the voltage held in the capacitor C in the immediately preceding writing period is supplied from the driving transistor TDR to the light emitting element 45 via the light emitting control transistor TEL. As described above, since each light emitting element 45 emits light at a luminance corresponding to the gradation potential, an arbitrary image specified by the image signal is displayed on the display area 12.

  The specific structure of the light emitting device 100 according to the first embodiment will be described in detail below. In each of the drawings referred to in the following description, the dimensions and scale of each element are different from those of the actual light emitting device 100 for the sake of convenience. 3 and 4 are cross-sectional views of the light emitting device 100. FIGS. 5 to 9 show the state of the surface of the substrate 10 at each stage of forming each element of the light emitting device 100 for one pixel P. It is the top view illustrated paying attention. A sectional view corresponding to a section including the line III-III in FIGS. 5 to 9 corresponds to FIG. 3, and a sectional view corresponding to a section along the line IV-IV in FIGS. 5 to 9 corresponds to FIG. Although FIGS. 5 to 9 are plan views, from the viewpoint of facilitating the visual grasp of each element, each element common to FIG. 3 or FIG. 4 is hatched in the same manner as FIG. 3 or FIG. It is added for convenience.

  As understood from FIGS. 3, 4 and 5, a substrate 10 formed of a semiconductor material such as silicon has an active region 10A (source / drain region) of each transistor T (TDR, TEL, TSL) of the pixel P. ) Is formed. Ions are implanted into the active region 10A. The active layer of each of the transistors T (TDR, TEL, TSL) of the pixel P exists between the source region and the drain region, and ions of a different type from the active region 10A are implanted. Have been. As illustrated in FIGS. 3 and 4, the surface of the substrate 10 on which the active region 10A is formed is covered with an insulating film L0 (gate insulating film), and the gate G (GDR, GEL, GSL) of each transistor T is insulated. It is formed on the surface of the film L0. The gate G of each transistor T faces the active layer with the insulating film L0 interposed therebetween. FIG. 4 shows the gate GSL of the selection transistor TSL, the gate GDR of the drive transistor TDR, and the gate GEL of the light emission control transistor TEL.

  As understood from FIGS. 3 and 4, on the surface of the insulating film L0 on which the gate G of each transistor T is formed, a plurality of insulating layers L (LA to LE) and a plurality of wiring layers W (WA to WE) are provided. ) Are alternately stacked to form a multilayer wiring layer. Each wiring layer W is formed of a low-resistance conductive material containing aluminum, silver, or the like. Each insulating layer L is formed of an insulating inorganic material such as a silicon compound (typically, silicon nitride or silicon oxide). In the following description, a relationship in which a plurality of elements are collectively formed in the same step by selective removal of a conductive layer (single layer or plural layers) is referred to as “formed from the same layer”.

  The insulating layer LA is formed on the surface of the insulating film L0 on which the gate G of each transistor T is formed. As understood from FIGS. 3, 4 and 6, the conductor pattern including the scanning line 22, the control line 24, and the plurality of relay electrodes QA (QA1, QA2, QA3, QA4) is formed on the surface of the insulating layer LA. Are formed from the same layer (wiring layer WA). The scanning line 22 and the control line 24 extend linearly in the X direction over a plurality of pixels P with an interval therebetween. Specifically, as illustrated in FIG. 6, the scanning line 22 is formed so as to pass above the gate GSL of the selection transistor TSL and above the gate GDR of the driving transistor TDR, and to conduct through the insulating layer LA. It conducts to the gate GSL of the selection transistor TSL via the hole (contact hole) HA1. The conduction hole HA1 is formed so as to overlap the gate GSL and the active layer of the selection transistor TSL in plan view. On the other hand, the control line 24 is formed so as to pass above the gate GEL of the light emission control transistor TEL, and is electrically connected to the gate GEL of the light emission control transistor TEL via the conduction hole HA2 penetrating the insulating layer LA. The conduction hole HA2 is formed so as to overlap the gate GEL and the active layer of the light emission control transistor TEL in plan view.

  The relay electrode QA1 is a wiring connecting the active region 10A of the selection transistor TSL and the gate GDR of the driving transistor TDR, and is located between the scanning line 22 and the control line 24 in a plan view as illustrated in FIG. I do. Specifically, as understood from FIGS. 4 and 6, the relay electrode QA1 conducts to the active region 10A of the selection transistor TSL through the conduction hole HA3 penetrating the insulating layer LA and the insulating film L0. Conduction is made to the gate GDR of the driving transistor TDR via the conduction hole HA4 of the insulating layer LA. Further, as understood from FIG. 6, the relay electrode QA2 conducts to the active region 10A of the selection transistor TSL via the conduction hole HA5 penetrating the insulating layer LA and the insulating film L0. The relay electrode QA3 conducts to the active region 10A (source) of the drive transistor TDR via a conduction hole HA6 penetrating the insulating layer LA and the insulating film L0. The relay electrode QA4 is electrically connected to the active region 10A (drain) of the light emission control transistor TEL through a through hole HA7 penetrating the insulating layer LA and the insulating film L0. As can be understood from FIG. 6, each of the selection transistor TSL, the driving transistor TDR and the light emission control transistor TEL is formed such that the channel length is along the Y direction. The drive transistor TDR and the light emission control transistor TEL are arranged along the Y direction, and the selection transistor TSL is shifted in the X direction (the negative side in the X direction in FIG. 6) with respect to the drive transistor TDR and the light emission control transistor TEL. Placed at the right position.

  The insulating layer LB is formed on the surface of the insulating layer LA on which the wiring layer WA is formed. As understood from FIGS. 3, 4 and 7, on the surface of the insulating layer LB, a conductor pattern including the signal line 26, the first electrode C1, and the plurality of relay electrodes QB (QB1, QB2) is in the same layer. (Wiring layer WB). The signal line 26 extends linearly in the Y direction over the plurality of pixels P, and is electrically insulated from the scanning line 22 and the control line 24 by the insulating layer LA. Specifically, the signal line 26 is formed so as to pass above the active region 10A (source and drain) and the active layer of the selection transistor TSL and above the relay electrode QA1 which is electrically connected to the gate GDR of the driving transistor TDR. Extend along the channel length direction (Y direction) of the select transistor TSL and overlap the select transistor TSL in plan view. The signal line 26 is formed above the active region 10A (source, drain) of each transistor T (TDR, TEL, TSL) and the gate G of each transistor T. As can be understood from FIG. 7, the signal line 26 of the wiring layer WB conducts to the relay electrode QA2 of the wiring layer WA via the conduction hole HB1 penetrating the insulating layer LB. That is, the signal line 26 and the active region 10A (source) of the selection transistor TSL are connected via the relay electrode QA2. The first electrode C1 of the wiring layer WB of FIG. 7 is electrically connected to the relay electrode QA1 of the wiring layer WA via a conductive hole HB2 penetrating the insulating layer LB. That is, the first electrode C1 of the capacitive element C and the gate GDR of the drive transistor TDR are connected via the relay electrode QA1. The relay electrode QB1 of the wiring layer WB of FIG. 7 is electrically connected to the relay electrode QA3 of the wiring layer WA via the conductive hole HB3 of the insulating layer LB, and the relay electrode QB2 of the wiring layer WB is connected to the conductive hole HB4 of the insulating layer LB. The wiring is electrically connected to the relay electrode QA4 of the wiring layer WA.

  The insulating layer LC is formed on the surface of the insulating layer LB on which the wiring layer WB is formed. As understood from FIGS. 3, 4 and 8, on the surface of the insulating layer LC, a conductor pattern including the second electrode C2 is formed from the same layer (wiring layer WC). The second electrode C2 is formed in a shape and position overlapping with the first electrode C1 in a plan view (that is, in a state viewed from a direction perpendicular to the surface of the substrate 10). As understood from FIG. 3, the capacitance element C is constituted by the first electrode C1 and the second electrode C2 and the insulating layer LC between them. As illustrated in FIG. 8, the capacitance element C (the first electrode C1 and the second electrode C2) is provided so as to overlap the driving transistor TDR and the light emission control transistor TEL in plan view.

  As illustrated in FIGS. 3 and 4, the insulating layer LD is formed on the surface of the insulating layer LC on which the wiring layer WC is formed. A flattening process is performed on the surface of the insulating layer LD. A known surface treatment technique such as chemical mechanical polishing (CMP) is arbitrarily adopted for the planarization treatment. A conductive pattern including a first power supply conductor 41, a second power supply conductor 42, and a relay electrode QD1, as illustrated in FIGS. 3 and 4, on the surface of the insulating layer LD highly planarized by the planarization process. Are formed from the same layer (wiring layer WD). As shown in FIG. 3, the first power supply conductor 41 and the second power supply conductor 42 are formed apart from each other and are electrically insulated. The first power supply conductor 41 is electrically connected to the mounting terminal 36 to which the higher power supply potential VEL is supplied via a wiring (not shown) in the multilayer wiring layer. Similarly, the second power supply conductor 42 (second wiring) conducts to the mounting terminal 36 to which the lower power supply potential VCT is supplied via a wiring (not shown) in the multilayer wiring layer. The wiring layer (second wiring layer) WD of the first embodiment is made of a light-reflective conductive material containing, for example, silver or aluminum and has a thickness of, for example, about 100 nm.

  FIG. 10 is a plan view of the first power supply conductor 41 and the second power supply conductor 42. The first power supply conductor 41 is a power supply line to which the higher power supply potential VEL is supplied as described above, and has a substantially rectangular shape formed in a planar shape over substantially the entire display region 12 as illustrated in FIG. This is a solid pattern. The solid pattern is not a linear or band-shaped pattern or a combination thereof (for example, a lattice shape), but a substantially continuous and substantially continuous space-like pattern (that is, a solid pattern) so as to substantially fill the entire display area 12. Shape). Note that the first power supply conductor 41 may be individually formed for each pixel P.

  As understood from FIGS. 4 and 9, the first power supply conductor 41 formed in the display area 12 is connected to the relay electrode via the conduction hole HD1 penetrating the insulating layer LD and the insulating layer LC for each pixel P. Conduction with QA3. That is, as understood from FIG. 4, the active region 10A functioning as the source of the driving transistor TDR is connected to the first power supply conductor 41 via the relay electrode QA3 and the relay electrode QB1. Further, as illustrated in FIG. 9, the first power supply conductor 41 is connected to the second electrode C2 of the capacitor C via the conduction hole HD2 of the insulating layer LD. That is, the capacitive element C is interposed between the gate GDR and the source (the first power supply conductor 41) of the drive transistor TDR. Note that it is also possible to form a plurality of conduction holes HD2 in the insulating layer LD and connect the first power supply conductor 41 and the second electrode C2 of the capacitor C at a plurality of locations.

  As illustrated in FIG. 9, an opening 41A is formed in the first power supply conductor 41 for each pixel P. Inside each opening 41A, a relay electrode QD1 is formed in the same layer as the first power supply conductor 41 and the second power supply conductor 42. The relay electrode QD1 and the first power supply conductor 41 are formed apart from each other and are electrically insulated. As understood from FIGS. 4 and 9, the relay electrode QD1 is electrically connected to the relay electrode QB2 via the conductive hole HD3 penetrating the insulating layer LD and the insulating layer LC. When the area obtained by dividing the area of the display area 12 by the total number of pixels P in the display area 12 is defined as the area of one pixel P, the area of each opening 41A is formed to be 20% or less of the area of each pixel P. Is done. For example, in a configuration in which the pixel P is formed in a rectangular shape of 2.5 μm in width × 7.5 μm in height, the opening 41A has a size of 0.9 μm in width × 0.9 μm in height (an area of about 4% of the pixel P). It is formed.

  The second power supply conductor 42 is a power supply wiring formed in the peripheral region 14 and supplied with the lower power supply potential VCT as described above. As illustrated in FIG. 10, the second power supply conductor 42 of the present embodiment is formed in a rectangular frame shape (closed figure) surrounding the first power supply conductor 41 (display area 12) in plan view. The width (the distance from the inner peripheral edge to the outer peripheral edge) of the second power supply conductor 42 is, for example, 1.5 mm. FIG. 11 is an explanatory diagram of the positional relationship of each element formed on the surface of the insulating layer LD. The enlarged view of the region α in FIG. 10 corresponds to each part ((A) to (D)) in FIG. As understood from the portion (A) of FIG. 10 and FIG. 11, the display region 12 and the peripheral region are surrounded by the periphery of the first power supply conductor 41 and the inner periphery of the second power supply conductor 42 in plan view. The boundary with the area 14 is located.

  As illustrated in FIGS. 3 and 4, the insulating layer LE is formed on the surface of the insulating layer LD on which the wiring layer WD is formed. On the surface of the insulating layer LE, a conductor pattern including the second conductor 58 shown in FIG. 3 and the relay electrode QE1 shown in FIG. 4 is formed from the same layer (wiring layer WE). The wiring layer (first wiring layer) WE is formed of, for example, a light-shielding conductive material (for example, titanium nitride).

  The relay electrode QE1 conducts to the relay electrode QD1 via a conduction hole penetrating the insulating layer LE. As understood from FIG. 4, the relay electrode QE1 is formed so as to overlap the opening 41A of the first power supply conductor 41 in plan view. That is, the outer peripheral edge of the relay electrode QE1 is located outside the inner peripheral edge of the opening 41A in plan view. Since the relay electrode QE1 is formed of a light-shielding conductive material, penetration of external light from the opening 41A into the multilayer wiring layer is prevented by the relay electrode QE1. Therefore, there is an advantage that the relay electrode QE1 functions as a light-shielding layer, and current leakage of each transistor T due to light irradiation can be prevented.

  The second conductor 58 (first wiring) is formed on the surfaces of the first power supply conductor 41 and the second power supply conductor 42, as shown in part (B) of FIGS. In FIG. 10, a part of the second conductor 58 is shown by a solid line, and another part of the outer shape is shown by a chain line. As understood from FIG. 10, the second conductor 58 is formed in an annular shape (rectangular frame shape) similar to the second power conductor 42, and the first power conductor 41 and the second power conductor 42 in plan view. Are formed in a band shape overlapping both sides. Specifically, the inner periphery of the second conductor 58 is located inside the periphery of the first power supply conductor 41 in plan view. That is, the second conductor 58 overlaps with a region near the periphery of the first power supply conductor 41. The outer peripheral edge of the second conductor 58 is located outside the outer peripheral edge of the second power supply conductor 42 in plan view. That is, the second conductor 58 overlaps the entire area of the second power supply conductor 42 in plan view. As understood from the above description, the second conductor 58 is formed in the area of the gap between the first power supply conductor 41 and the second power supply conductor 42 in plan view (that is, the boundary area between the display area 12 and the peripheral area 14). (Nearby area).

  A configuration in which the second conductor 58 is not formed is assumed as a comparative example (hereinafter, referred to as “comparative example 1”). FIG. 12 is a cross-sectional view (a cross-sectional view near the boundary between the display region 12 and the peripheral region 14) of the first power supply conductor 41 and the second power supply conductor 42 in Comparative Example 1. As illustrated in FIG. 12, in Comparative Example 1, after the formation of the insulating layer LE covering the first power supply conductor 41 and the second power supply conductor 42, the first power supply conductor 41 and the second power supply conductor 42 are formed. The edge (corner) e is exposed from the insulating layer LE, and the first power supply conductor 41 and the second power supply conductor 42 may be damaged or corroded. On the other hand, in the first embodiment, it overlaps with the gap between the first power supply conductor 41 and the second power supply conductor 42 (covers the edge e of the first power supply conductor 41 and the second power supply conductor 42). Since the second conductor 58 is formed, there is an advantage that damage and corrosion of the first power supply conductor 41 and the second power supply conductor 42 due to exposure from the insulating layer LE can be prevented.

  The second conductor 58 is electrically connected to the second power supply conductor 42 through the conduction hole HE1 penetrating the insulating layer LE as shown in FIG. 3 and FIG. 11B. FIG. 13 is a plan view of each conduction hole (HE1, HF1, HG1) formed in the peripheral region 14. FIG. As shown in FIG. 13, the conduction hole HE1 is a through hole obtained by removing a rectangular frame-shaped region surrounding the display region 12 in plan view of the insulating layer LE. The conduction hole HE1 is formed in the first region S1 of the region overlapping the second power supply conductor 42 in plan view. The first region S1 is a rectangular frame-shaped region in plan view as shown in FIG. 13, and the inner peripheral edge and the outer peripheral edge of the second power supply conductor 42 in the peripheral region 14 as shown in part (D) of FIG. Located between. The width of the first region S1 (the distance from the inner peripheral edge to the outer peripheral edge) is, for example, 0.3 mm. The second conductor 58 conducts to the second power supply conductor 42 over the entire periphery of the peripheral region 14 via the conduction hole HE1.

  As illustrated in FIGS. 3 and 4, an optical path adjusting layer 60 is formed on the surface of the insulating layer LE on which the wiring layer WE is formed. The optical path adjustment layer 60 is an element for individually setting the resonance wavelength (display color) of the resonance structure for each display color of the pixel P, and transmits light such as a silicon compound (typically, silicon nitride or silicon oxide). It is formed of a conductive insulating material. Specifically, the optical path length (optical distance) between the first power supply conductor 41 and the second electrode E2 constituting the resonance structure is appropriately adjusted according to the thickness of the optical path adjustment layer 60. The resonance wavelength of the light emitted from the pixel P is set for each display color.

  As illustrated in FIG. 3, on the surface of the optical path adjustment layer 60, the first electrode E1 for each pixel P in the display region 12 and the first conductor 63 in the peripheral region 14 are formed from the same layer. . The first electrode E1 and the first conductor 63 are formed of a light-transmissive conductive material such as ITO (Indium Tin Oxide). As described with reference to FIG. 2, the first electrode E1 is a substantially rectangular electrode (pixel electrode) functioning as an anode of the light emitting element 45, and has a conduction through the optical path adjusting layer 60 as shown in FIG. Conduction is made to the relay electrode QE1 through the hole. That is, the first electrode E1 is electrically connected to the active region 10A (drain) of the light emission control transistor TEL via each relay electrode (QE1, QD1, QB2, QA4) of the multilayer wiring layer.

  The first conductor 63 is formed in an annular shape (rectangular frame shape) similar to the second conductor 58. As shown in part (C) of FIG. 11, the inner periphery of the first conductor 63 is located inside the inner periphery of the second conductor 58 (peripheral side of the substrate 10), and the outer periphery of the first conductor 63. Are located inside the outer peripheral edge of the second conductor 58. The first conductor 63 is electrically connected to the second conductor 58 through a conduction hole HF1 penetrating the optical path adjustment layer 60, as shown in FIG. 3 and FIG. 11C. As shown in FIG. 13, the conduction hole HF1 is a through hole obtained by removing a rectangular frame-shaped region surrounding the display region 12 in the optical path adjustment layer 60 in plan view. The conduction hole HF1 is located closer to the display area 12 than the conduction hole HE1. The first conductor 63 conducts to the second conductor 58 over the entire periphery of the peripheral region 14 via the conduction hole HF1.

  As illustrated in FIG. 3, a pixel defining layer 65 is formed on the entire surface of the substrate 10 on the surface of the optical path adjustment layer 60 on which the first electrode E1 and the first conductor 63 are formed. The pixel definition layer 65 is formed of an insulating inorganic material such as a silicon compound (typically, silicon nitride or silicon oxide). As can be understood from FIG. 3, the pixel definition layer 65 has an opening 65A corresponding to each first electrode E1 in the display area 12.

  As illustrated in FIGS. 3 and 4, the light emitting function layer 46 is formed on the surface of the optical path adjustment layer 60 on which the first electrode E1, the first conductor 63, and the pixel defining layer 65 are formed. The light-emitting function layer 46 includes a light-emitting layer formed of an organic EL material, and emits white light by supplying current. The light emitting layer is formed by a known film forming technique such as a printing technique or a vapor deposition technique. White light is light having a spectrum that covers a blue wavelength range, a green wavelength range, and a red wavelength range, and at least two peaks are observed in the visible light wavelength range. Note that the light-emitting functional layer 46 can include a transport layer or an injection layer for electrons and holes supplied to the light-emitting layer.

  As shown in FIG. 3, the light emitting function layer 46 is continuous over a plurality of pixels P in the display area 12, and the peripheral edge 48 is located in the peripheral area 14 in a plan view. Specifically, the peripheral edge 48 of the light emitting function layer 46 is located in the second region S2, as shown in the part (D) of FIG. The second area S2 is a rectangular frame-shaped area located on the display area 12 side of the first area S1 in plan view. A manufacturing error may occur at the position of the peripheral edge 48 of the light emitting function layer 46. When a film forming technique such as a printing technique having relatively low manufacturing accuracy is employed for forming the light emitting function layer 46, the error in the position of the peripheral edge 48 becomes particularly noticeable. The second area S2 is an area (manufacturing margin) secured to include the error range of the position of the peripheral edge 48. Specifically, the width of the second region S2 is set to be about twice as large as the first region S1 (for example, 0.6 mm), and is preferably not less than 1 and not more than 3 times the first region S1.

  The peripheral edge 48 of the light emitting function layer 46 overlaps with the second conductor 58 as shown from the part (B) to the part (D) in FIG. Specifically, the entire periphery of the peripheral edge 48 overlaps the rectangular frame-shaped second conductor 58 in plan view. In a configuration in which a part of the peripheral edge 48 of the light emitting function layer 46 overlaps the second conductor 58 and another part does not overlap the second conductor 58, a step reflecting the thickness of the second conductor 58 causes a step difference in the light emitting function. It may appear on the surface of layer 46. In the present embodiment, since the entire periphery of the peripheral edge 48 overlaps the single member (the second conductor 58), there is an advantage that the step on the surface of the light emitting function layer 46 is reduced.

  On the surface of the optical path adjusting layer 60 on which the light emitting function layer 46 is formed, a second electrode E2 is formed over the entire display region 12. The second electrode E2 conducts to the first conductor 63 through the conduction hole HG1 of the pixel defining layer 65, as shown in the part (D) of FIG. As shown in FIG. 13, the conduction hole HG1 is a through hole obtained by removing a rectangular frame-like region surrounding the display region 12 in the pixel definition layer 65 in a plan view, and is provided in the first region S1 of the peripheral region 14. To position. The second electrode E2 conducts with the first conductor 63 over the entire periphery of the peripheral region 14 via the conduction hole HG1. The conduction hole HG1 is located closer to the display area 12 than the conduction hole HF1.

  As understood from FIGS. 3 and 11, the second power supply conductor 42 and the second conductor 58 are connected via the conduction hole HE1, and the second conductor 58 and the first conductor 63 are connected to the conduction hole HF1. And the first conductor 63 and the second electrode E2 are connected via the conduction hole HG1. Therefore, the lower power supply potential (second potential) VCT supplied to the second power supply conductor 42 is supplied to the second electrode E2 via the second conductor 58 and the first conductor 63. Each of the conduction holes (HE1, HF1, HG1) used to connect the second power supply conductor 42 and the second electrode E2 is formed in the rectangular frame-shaped first region S1 in plan view. In other words, as shown in FIG. 11, a region surrounded by the outer periphery of the conduction hole HE1 and the inner periphery of the conduction hole HG1 in plan view is defined as the first region S1. The wiring formed in the peripheral region 14 and connected to the second electrode E2 is referred to as "peripheral wiring D" in the following description. The peripheral wiring D of the first embodiment includes a second power supply conductor 42, a second conductor 58, and a first conductor 63, as illustrated in FIG.

  As illustrated in FIG. 3, a region (light emitting region) between the first electrode E1 and the second electrode E2 within the opening 65A of the pixel defining layer 65 in the light emitting function layer 46 emits light. That is, the portion where the first electrode E1, the light emitting function layer 46, and the second electrode E2 are laminated inside the opening 65A functions as the light emitting element 45. As understood from the above description, the pixel definition layer 65 defines the planar shape and size (the area that actually emits light) of the light emitting element 45 of each pixel P. The light emitting device 100 according to the first embodiment is a micro display in which the light emitting elements 45 are arranged with extremely high definition. For example, the area of one light emitting element 45 (the area of one opening 65A) is set to 40 μm 2 or less, and the interval between the adjacent light emitting elements 45 in the X direction is set to 1.5 μm or less.

  The second electrode E2 functions as a semi-transmissive reflective layer having a property (semi-transmissive reflectivity) of transmitting a part of light reaching the surface and reflecting the rest. For example, a semi-transmissive and reflective second electrode E2 is formed by forming a light-reflective conductive material such as an alloy containing silver or magnesium to a sufficiently small thickness. The radiated light from the light emitting function layer 46 reciprocates between the first power supply conductor 41 and the second electrode E2, and passes through the second electrode E2 after a component of a specific resonance wavelength is selectively amplified. Out to the observation side (the side opposite to the substrate 10). That is, a resonance structure is formed between the first power supply conductor 41 functioning as a reflection layer and the second electrode E2 functioning as a semi-transmissive reflection layer to resonate light emitted from the light-emitting function layer 46.

  As described above, the conduction hole HG1 for conduction between the second electrode E2 and the first conductor 63 is formed in the first region S1 and emits light in the second region S2 located closer to the display region 12 than the first region S1. The peripheral edge 48 of the functional layer 46 is located. Therefore, as shown in FIGS. 3 and 11, the light emitting functional layer 46 and the conduction hole HG1 do not overlap each other in plan view.

  FIG. 14 is an explanatory diagram of a configuration (hereinafter, referred to as “comparative example 2”) in which the conduction hole HG1 and the light emitting functional layer 46 overlap in a plan view. In Comparative Example 2, the light emitting functional layer 46 is interposed between the second electrode E2 and the first conductor 63 in the region U in the conduction hole HG1. Therefore, in Comparative Example 2, the conduction between the second electrode E2 and the first conductor 63 may be insufficient. As described above, a manufacturing error may occur at the position of the peripheral edge 48 of the light emitting function layer 46. When the region U is enlarged due to a manufacturing error (when the contact area between the second electrode E2 and the first conductor 63 is reduced), the conduction between the second electrode E2 and the first conductor 63 is insufficient. Is particularly apparent. On the other hand, in the first embodiment, since the light emitting function layer 46 does not overlap with the conduction hole HG1, the light emitting function layer 46 does not contact the first conductor 63. Therefore, the second electrode E2 and the first conductor 63 are sufficiently connected via the conduction hole HG1.

  Further, as described above, the conduction hole HG1 is located closer to the display region 12 than the conduction hole HF1 in plan view, and the conduction hole HF1 is located closer to the display region 12 than the conduction hole HE1. That is, as shown in FIGS. 11 and 13, the conduction hole HE1, the conduction hole HF1, and the conduction hole HG1 are formed at positions shifted from each other in plan view. Part (A) of FIG. 15 is an enlarged cross-sectional view of the through hole HG1 and the through hole HF1 according to the present embodiment. On the other hand, a configuration in which the conduction hole HG1 and the conduction hole HF1 overlap in a plan view (hereinafter, referred to as “comparative example 3”) is illustrated in a portion (B) of FIG. As shown in part (B) of FIG. 15, when the conduction hole HG1 and the conduction hole HF1 overlap in plan view, the surface of the region of the second electrode E2 located outside the conduction hole HG1 and the conduction hole HG1 A step R having a height corresponding to the sum of the thickness of the optical path adjustment layer 60 and the thickness of the pixel definition layer 65 is generated between the inside of the region and the surface of the region. Therefore, in each layer covering the second electrode E2, a step (irregularity) reflecting the step R of the surface of the second electrode E2 may occur. On the other hand, in the first embodiment, as shown in FIG. 15A, the conduction hole HG1 and the conduction hole HF1 do not overlap in plan view. Therefore, there is an advantage that the step on the surface of the second electrode E2 is reduced as compared with Comparative Example 3. Similarly, in the present embodiment, the conduction hole HE1 and the conduction hole HF1 are formed at positions shifted from each other in a plan view, and thus correspond to the sum of the film thickness of the pixel definition layer 65 and the film thickness of the insulating layer LE. There is no step. Therefore, a step on the surface of the first conductor 63 can be reduced.

  Considering only the conduction between the second electrode E2 and the second power supply conductor 42, it is sufficient that the second power supply conductor 42 exists only in the first region S1. However, in the first embodiment, as shown in FIG. 11D, in addition to the first region S1, the second region S2 is provided so as to extend to the second region S2 secured as a manufacturing margin of the light emitting function layer 46. A power conductor 42 is formed. According to the configuration described above, the area of the second power supply conductor 42 is sufficiently ensured as compared with the configuration in which the second power supply conductor 42 is formed only in the first region S1. Has the advantage that the resistance of the substrate is reduced. Since the voltage drop in the second power supply conductor 42 is suppressed by reducing the resistance, the potential VCT supplied to each pixel P in the display area 12 is made uniform, and display unevenness due to an error in the potential VCT is reduced. There is an advantage that it is done.

  As illustrated in FIG. 3, a sealing body 70 is formed over the entire surface of the substrate 10 on the surface of the second electrode E2. In FIG. 4, the illustration of the sealing body 70 is omitted for convenience. The sealing body 70 is a light-transmitting film that seals each element formed on the substrate 10 to prevent invasion of outside air and moisture, and includes a first sealing layer 71 and a second sealing layer. 72 and a third sealing layer 73. The first sealing layer 71 is formed on the surface of the third sealing layer 73, and the second sealing layer 72 is formed on the surfaces of the first sealing layer 71 and the third sealing layer 73.

  The third sealing layer 73 of the sealing body 70 is formed on the surface of the second electrode E2 and directly contacts the surface of the second electrode E2. As understood from FIG. 3, the third sealing layer 73 is formed over the entire area of the substrate 10 including the display area 12 and the peripheral area 14. The third sealing layer 73 is formed of, for example, an insulating inorganic material such as a silicon compound (typically, silicon nitride or silicon oxide) and has a thickness of, for example, about 200 nm to 400 nm. The third sealing layer 73 is preferably formed to have a thickness equal to or greater than the thickness difference (for example, 120 nm) of the optical path adjustment layer 60. For forming the third sealing layer 73, a high-density plasma film forming technique such as a plasma CVD (Chemical Vapor Deposition) method, an ECR (Electron Cyclotron Resonance) plasma sputtering method, or an ion plating method is suitably used. The third sealing layer 73 made of silicon oxynitride can be formed by depositing silicon oxide in a nitrogen atmosphere. In addition, an inorganic oxide typified by a metal oxide such as titanium oxide may be employed as the material of the third sealing layer 73.

  The first sealing layer 71 is an element that seals the light emitting element 45, and includes a sealing surface 82 and a side end surface 84 as shown in FIG. The sealing surface 82 is a surface of the upper surface of the first sealing layer 71 (the surface opposite to the contact surface with the third sealing layer 73) that overlaps the light emitting element 45. The side end surface 84 is a surface that is continuous with the sealing surface 82, is located outside the sealing surface 82 in plan view, and is inclined with respect to the sealing surface 82. The side end surface 84 includes an upper peripheral edge 86 on the sealing surface 82 side and a lower peripheral edge 88 on the substrate 10, and is formed such that the film thickness becomes smaller as it approaches the lower peripheral edge 88. The lower peripheral edge 88 of the first sealing layer 71 is, as shown in part (D) of FIG. 11, a third region on the peripheral side of the substrate 10 in the first region S1 (opposite to the display region 12) in plan view. Located in S3. The third region S3 is a rectangular frame-shaped region having a predetermined width. A manufacturing error may occur at the position of the lower peripheral edge 88 of the first sealing layer 71. When a film forming technique such as a printing technique having a relatively low manufacturing accuracy is employed for forming the first sealing layer 71, an error in the position of the lower peripheral edge 88 becomes particularly significant. The third region S3 is a region (manufacturing margin) secured to include the error range of the position of the lower peripheral edge 88. Specifically, the width of the third region S3 is set to be about twice as large as the first region S1 (for example, 0.6 mm), and is preferably not less than 1 and not more than 3 times the first region S1.

  As shown from the part (B) to the part (D) in FIG. 11, the lower peripheral edge 88 overlaps the second conductor 58. Specifically, similarly to the peripheral edge 48 of the light emitting function layer 46, the lower peripheral edge 88 entirely overlaps the rectangular frame-shaped second conductor 58 in plan view. Therefore, in the same manner as described above for the light emitting functional layer 46, compared to a configuration in which a part of the lower peripheral edge 88 overlaps the second conductor 58 and another part does not overlap the second conductor 58, It is possible to reduce the step on the surface of the one sealing layer 71 (the lower peripheral edge 88).

  As described above, considering only the continuity between the second electrode E2 and the second power supply conductor 42, the second power supply conductor 42 need only be present in the first region S1. However, in the first embodiment, as shown in part (D) of FIG. 11, in addition to the first region S1, the third region S3 secured as a manufacturing margin of the first sealing layer 71 is extended. A second power conductor 42 is formed. According to the configuration described above, the area of the second power supply conductor 42 is sufficiently ensured as compared with the configuration in which the second power supply conductor 42 is formed only in the first region S1. Has the advantage that the resistance of the substrate is reduced. Since the voltage drop in the second power supply conductor 42 is suppressed by reducing the resistance, the potential VCT supplied to each pixel P in the display area 12 is made uniform, and display unevenness due to an error in the potential VCT is reduced. There is an advantage that it is done.

  The first sealing layer 71 functions as a flattening film that fills a step on the surface of the second electrode E2 or the third sealing layer 73. That is, steps are formed on the surfaces of the second electrode E2 and the third sealing layer 73 reflecting the shape of each element below (the substrate 10 side), but the sealing surface 82 of the first sealing layer 71 is , A substantially flat surface with sufficiently reduced steps. It can be stated that the sealing surface 82 of the first sealing layer 71 is flatter than the lower surface (that is, the contact surface with the third sealing layer 73). For example, the first sealing layer 71 covers each of the conduction holes (HE1, HF1, HG1) formed in the first region S1, and the surface of the first region S1 (the second electrode E2, The step generated in the third sealing layer 73) is flattened. The first sealing layer 71 has a sufficiently large film thickness (for example, 1 μm to 5 μm) as compared with the second sealing layer 72 and the third sealing layer 73 so that the planarization function described above is realized. , Particularly preferably 3 μm). The first sealing layer 71 is formed by applying a solution of a light-transmitting organic material such as an epoxy resin to the surface of the second sealing layer 72 by a known coating technique (for example, a printing method or a spin coating method) and performing a heat treatment. Formed by the step of curing. Note that the material of the first sealing layer 71 is not limited to an organic material. For example, the first sealing layer 71 having a thickness sufficient for planarization can be formed by applying an inorganic material such as silicon oxide by a coating technique such as a printing method and drying the applied material. The first sealing layer 71 is formed so as to be continuous over a wider area than the area where the light emitting function layer 46 is formed, and to cover at least the light emitting function layer 46. Further, a configuration in which the first sealing layer 71 covers the second electrode E2 may be adopted.

  As understood from FIG. 3, the second sealing layer 72 is formed over the entire area of the substrate 10 including the display area 12 and the peripheral area 14. The second sealing layer 72 is made of, for example, an inorganic material having excellent water resistance and heat resistance, and is formed to a thickness of, for example, about 300 nm to 700 nm (particularly preferably, about 400 nm). For example, a nitrogen compound (silicon nitride, silicon oxide, silicon oxynitride) is suitable as the material of the third sealing layer 73. For forming the second sealing layer 72, a known film forming technique exemplified for the third sealing layer 73 is arbitrarily adopted. The above is the specific configuration of the sealing body 70.

  The filter layer 90 is formed on the surface of the sealing body 70 (the second sealing layer 72). Here, in FIG. 16, the filter layer 90 is laminated on the surface of the sealing body 70 (the second sealing layer 72). FIG. 16 is a cross-sectional view of the sealing body 70 and the filter layer 90 (the insulating layer 92, the color filter 94, and the protection section 96), and FIG. 17 is a plan view. In FIG. 17, a part of the filter layer 90 (protection part 96) is illustrated by a solid line, and another part of the outer shape is represented by a chain line. 3 and 4, illustration of the filter layer 90 is omitted for convenience.

  The filter layer 90 includes an insulating layer 92, a plurality of color filters 94, and a protection unit 96. The insulating layer 92 is an insulating member formed on the surface of the second sealing layer 72, and is formed over the entire area of the substrate 10. As shown in FIG. 16, an opening (first opening) 92A is formed in the insulating layer 92 of the display region 12 for each pixel P, and an opening (second opening) 92B is formed in the insulating layer 92 of the peripheral region 14. Is formed. The opening 92B is formed in a rectangular frame-like area surrounding the display area 12 in plan view as shown in FIG.

  The color filter 94 and the protection part 96 are formed of a colored layer K (KR, KG, KB) that transmits light of a specific wavelength. Specifically, each color filter 94 and the protection section 96 of the first embodiment are composed of a plurality of colored layers K (KR, KG, KB) that transmit light of different wavelengths. The first colored layer KR transmits red light having a wavelength of about 610 nm, the second colored layer KG transmits green light having a wavelength of about 550 nm, and the third colored layer KB has a blue light having a wavelength of about 470 nm. Through.

  The filter layer 90 of the first embodiment includes a plurality of color filters 94 (94R, 94G, 94B) that transmit monochromatic light having different wavelengths. The first color filter 94R is formed from the first colored layer KR. Similarly, the second color filter 94G is formed from the second colored layer KG, and the third color filter 94B is formed from the third colored layer KB. Each color filter 94 is disposed inside an opening 92A formed for each pixel P in the insulating layer 92, and overlaps the light emitting element 45 of each pixel P in a plan view. Specifically, the first color filter 94R overlaps the light emitting element 45 of the red pixel P (the pixel P whose resonance wavelength is set to the wavelength of red light), and the second color filter 94R overlaps the light emitting element 45 of the green pixel P. The color filter 94G overlaps, and the third color filter 94B overlaps the light emitting element 45 of the blue pixel P. As understood from FIG. 16, the insulating layer 92 functions as a partition of each color filter 94. Light emitted from each light emitting element 45 is colored by a color filter 94 overlapping the light emitting element 45, and then emitted outside the light emitting device 100 to be visually recognized by an observer. Although FIG. 17 illustrates a stripe arrangement in which a plurality of pixels P of the same color are arranged in the Y direction, the arrangement of the pixels P of each display color is arbitrary.

  The protection part 96 is an element for improving the sealing performance of the sealing body 70. As shown in FIGS. 16 and 17, the protection section 96 is formed in a rectangular frame shape in the peripheral area 14 so as to surround the display area 12 over the entire circumference in plan view. Therefore, the display area 12 is located inside the protection section 96, and the mounting area 16 is located outside the protection section 96. That is, the protection unit 96 exists between the display area 12 and the mounting area 16.

  The protective portion 96 overlaps the lower peripheral edge 88 of the side end surface 84 of the first sealing layer 71 located on the substrate 10 side in plan view. In the configuration in which the surface of the sealing body 70 is exposed in the peripheral region 14, the boundary (the lower peripheral edge 88) between the first sealing layer 71 and the ground surface below the first sealing layer 71 (the third sealing layer 73). ), There is a possibility that moisture or outside air enters and reaches the light emitting element 45. In the present embodiment, since the protection portion 96 overlaps the lower peripheral edge 88 of the first sealing layer 71, it is possible to prevent moisture and outside air from entering from the peripheral edge of the first sealing layer 71. That is, the sealing performance of the first sealing layer 71 can be improved.

  As understood from FIG. 16, a portion of the second sealing layer 72 overlapping the upper peripheral edge 86 (hereinafter, referred to as a “corner”) is located on the surface of the sealing surface 82 of the second sealing layer 72. There is a problem that it is susceptible to external force and easily damaged as compared with a flat portion. The protection part 96 (first layer 96R) of the present embodiment overlaps the upper peripheral edge 86 of the first sealing layer 71 on the surface of the second sealing layer 72 (that is, covers the corner of the second sealing layer 72). ). That is, a corner portion of the second sealing layer 72 that is easily damaged is protected by the protection portion 96. Therefore, there is an advantage that the possibility that the corner portion of the second sealing layer 72 is damaged is reduced (the outside air or moisture from the damaged portion of the second sealing layer 72 is prevented from entering).

  As shown in FIG. 16, the protection unit 96 according to the first embodiment is configured by stacking a first layer 96R, a second layer 96G, and a third layer 96B. The first layer 96R is formed on the second sealing layer 72. The second layer 96G is formed on the first layer 96R, and the third layer 96B is formed on the second layer 96G. The first layer 96R is formed from the first colored layer KR. Similarly, the second layer 96G is formed from the second colored layer KG, and the third layer 96B is formed from the third colored layer KB.

  As described above, the first color filter 94R and the first layer 96R of the protection section 96 are formed from the same layer (first colored layer KR). Similarly, the second color filter 94G and the second layer 96G are formed from the same layer (second colored layer KG), and the third color filter 94B and the third layer 96B are formed from the same layer (third colored layer KB). It is formed. According to the above configuration, the protection portion 96 can be formed in the step of forming the color filters 94 of each color. That is, it is not necessary to perform the step of forming the protection portion 96 separately from the formation of the color filter 94. Therefore, as compared with a configuration in which the protection portion 96 and the color filter 94 are separately formed, there is an advantage that the manufacturing process of the light emitting device is simplified.

  As shown in FIG. 16, the protection unit 96 overlaps the peripheral wiring D (the second power supply conductor 42, the second conductor 58, and the first conductor 63) in the peripheral region 14 in a plan view. FIG. 16 illustrates a configuration in which the protection unit 96 overlaps a part of the peripheral wiring D (all of the second power supply conductor 42 and the first conductor 63 and a part of the second conductor 58). When external light enters the peripheral region 14, the external light may be reflected by the peripheral wiring D and perceived by an observer. In the first embodiment, since the peripheral wiring D and the protection unit 96 overlap in a plan view, light traveling from the observation side to the peripheral wiring D and light reflected on the surface of the peripheral wiring D are shielded by the protection unit 96. Therefore, there is an advantage that the reflected light (reflection of the object on the observation side) on the surface of the peripheral wiring D is hardly perceived by the observer. In the first embodiment, in particular, since the protection unit 96 is formed by laminating the first red layer 96R, the second green layer 96G, and the third blue layer 96B, the protection unit 96 may be a single layer or two layers, for example. It is possible to impart sufficient light-shielding performance to the protection portion 96 as compared with the configuration in which is formed. However, it is also possible to configure the protection unit 96 with a single layer or two layers.

  As illustrated in FIG. 16, the sealing substrate 20 is bonded to the surface of the filter layer 90 via the adhesive layer 21. The sealing substrate 20 is a light-transmissive plate-shaped member formed of, for example, glass or quartz. The adhesive layer 21 is formed by curing the adhesive applied to the surface of the filter layer 90. A spin coating method is suitably employed for applying the adhesive. Specifically, the adhesive before curing is dropped on the substrate 10 (the filter layer 90), and the adhesive is caused to flow by rotating the substrate 10, so that the surface of the filter layer 90 (the insulating layer 92 and the third layer 96B) is formed. , The entire surface of each color filter 94). If a step is formed on the surface of the filter layer 90, the flow of the adhesive on the surface of the filter layer 90 is hindered by the step, so that the adhesive is not applied uniformly and a film formation failure of the adhesive layer 21 may occur. . In particular, the larger the step formed on the surface of the filter layer 90, the more likely it is that a film formation failure occurs. FIG. 18 is an explanatory diagram of a configuration in which a protective portion 96 is formed on the surface of the insulating layer 92 without forming an opening 92B in the insulating layer 92 (hereinafter, referred to as “Comparative 4”). In Comparative Example 4, since the protective portion 96 is formed on the surface of the insulating layer 92, the film thickness of the protective portion 96 (the first layer 96R, the second layer 96G, the third layer 96B, and the like) is formed on the surface of the filter layer 90. (The sum of the film thicknesses). On the other hand, in the present embodiment, as shown in FIG. 16, the protection part 96 is located inside the opening 92 </ b> B formed on the insulating layer 92 (on the surface of the second sealing layer 72 below the insulating layer 92). It is formed. Therefore, in the present embodiment, the step formed on the surface of the filter layer 90 has a size obtained by subtracting the film thickness of the insulating layer 92 from the film thickness of the protection portion 96. That is, the step formed on the surface of the filter layer 90 is smaller than that in the comparative example 4, and the film formation failure of the adhesive layer 21 is reduced.

<Second embodiment>
A second embodiment of the present invention will be described. In each of the embodiments described below, elements having the same functions and functions as those of the first embodiment will be denoted by the same reference numerals used in the description of the first embodiment, and detailed description thereof will be omitted as appropriate.

  FIG. 19 is an explanatory diagram of the filter layer 90 formed on the surface of the sealing body 70 of the second embodiment. As illustrated in FIG. 19, the opening 92B described in the first embodiment is not formed in the insulating layer 92 of the second embodiment. The protection part 96 of the second embodiment is different from the first embodiment in the positional relationship of the periphery of each layer (first layer 96R, second layer 96G, third layer 96B). In the first embodiment, the periphery of each layer of the protection unit 96 overlaps in plan view (that is, the side surfaces of each layer are flush), whereas in the second embodiment, the planar position of the periphery of each layer is a plane. Visually different.

  Specifically, as shown in FIG. 19, the inner periphery of the first layer 96R is located on the display area 12 side by a distance L1 from the inner periphery of the second layer 96G, and the outer periphery of the first layer 96R is It is located on the peripheral side of the substrate 10 (the side opposite to the display area 12) by the distance L3 from the outer peripheral edge of the two layers 96G. That is, the second layer 96G is formed to have a smaller area than the first layer 96 so as to be included in a plan view in the area where the first layer 96R immediately below is formed. Similarly, the inner periphery of the second layer 96G is located closer to the display area 12 by a distance L2 than the inner periphery of the third layer 96B, and the outer periphery of the second layer 96G is located at a distance L4 from the outer periphery of the third layer 96B. Only on the peripheral side of the substrate 10. Therefore, the inner peripheral side surface and the outer peripheral side surface of the protection portion 96 are formed in a stepped shape with a step corresponding to the film thickness of each layer. The distance L1 to the distance L4 are set to appropriate sizes, but are preferably formed to have a size equal to or greater than the thickness of the first layer 96R to the third layer 96B. For example, the distance L1 to the distance L4 can be formed to be about 5 μm with respect to the first layer 96R to the third layer 96B having a thickness of about 1 μm.

  In the second embodiment, the same effect as in the first embodiment is realized. Further, for example, in a configuration in which the protection portion 96 is formed on the surface of the insulating layer 92 with the side surfaces of the first layer 96R to the third layer 96B flush (for example, Comparative Example 4 shown in FIG. 18), A step corresponding to the sum of the film thicknesses of the layers (the first layer 96R, the second layer 96G, and the third layer 96B) of the portion 96 is formed on the surface of the filter layer 90. In the second embodiment, as can be understood from FIG. 19, the step of one step on the surface of the filter layer 90 corresponds to the film thickness of each layer (96R, 96G, 96B) constituting the protection section 96, and It is smaller than the sum of the thicknesses of the layers of the portion 96. As described above, according to the second embodiment, the surface of the filter layer 90 (the insulating layer 92, the first layer 96R, the second layer 96G, the third layer 96B, and the Each step (a step that can hinder the flow of the dropped adhesive) occurring on the surface) is smaller than that in Comparative Example 4. Therefore, according to the present embodiment, when the adhesive is applied to the surface of the filter layer 90 by the spin coating method, the possibility that the flow of the adhesive is hindered by the step of the filter layer 90 is reduced, and as a result, Poor film formation of the adhesive layer 21 is reduced.

<Modification>
The form exemplified above can be variously modified. Specific modifications will be described below. Two or more aspects arbitrarily selected from the following examples can be appropriately combined.

(1) From the viewpoint of reducing the step on the surface of the filter layer 90, as shown in FIG. 20, a protective portion 96 having a thickness similar to that of the insulating layer 92 is formed on the opening portion 92 </ b> B formed in the insulating layer 92. It may be formed inside. According to the above configuration, as shown in FIG. 20, the surface of the insulating layer 92 and the surface of the protective portion 96 are located in substantially the same plane, so that the effect of reducing the step on the surface of the filter layer 90 is exceptional. Is remarkable.

  By the way, when the spin coating method is employed for forming the adhesive layer 21, there is a possibility that the adhesive dropped in the display area 12 flows and reaches the mounting area 16 from the display area 12 or the peripheral area 14. When the adhesive reaches the mounting area 16 and adheres to the surface of each mounting terminal 36, there is a possibility that the mounting terminal 36 and the terminal of the external circuit may not be sufficiently conducted. In the first embodiment, the protection part 96 is located between the display area 12 and the mounting area 16, and a step corresponding to the thickness of the protection part 96 appears on the surface of the filter layer 90. In the above configuration, since the flow of the adhesive to the mounting area 16 is blocked by the step of the protection portion 96, the effect that the conduction failure between the mounting terminal 36 and the terminal of the external circuit due to the adhesion of the adhesive can be prevented. Play.

(2) In each of the above-described embodiments, the configuration in which the protection portion 96 covers the side end surface 84 of the first sealing layer 71 is exemplified, but the positional relationship between the first sealing layer 71 and the protection portion 96 is as described above. It is not limited to. For example, a configuration in which the protective portion 96 is formed in a region on the peripheral side of the substrate 10 (the side opposite to the display region 12) when viewed from the peripheral edge (lower peripheral edge 88) of the first sealing layer 71 (that is, the protective portion 96 is viewed in plan) , Which does not overlap the first sealing layer 71). In addition, a configuration in which the protection portion 96 is formed on the sealing surface 82 of the first sealing layer 71 (a configuration in which the protection portion 96 is located in a region on the display region 12 side when viewed from the upper peripheral edge 86 of the first sealing layer 71). Is also adopted. As understood from the above description, it is not questioned in the present invention whether or not the protection portion 96 overlaps the first sealing layer 71 (side end surface 84 of the first sealing layer 71) in plan view.

(3) Each element in each of the above embodiments can be appropriately omitted. For example, in each of the above-described embodiments, the filter layer 90 is configured to include the insulating layer 92. However, the insulating layer 92 may be omitted from the filter layer 90. In addition, the sealing body 70 is configured to include the first sealing layer 71, the second sealing layer 72, and the third sealing layer 73, but each layer is appropriately omitted. For example, when the second sealing layer 72 is omitted, the protection part 96 is formed directly on the surface of the first sealing layer 71. Further, the protection portion 96 is configured to include three layers of the first layer 96R, the second layer 96G, and the third layer 96B. For example, any one or two layers of the first layer 96R to the third layer 96B are provided. May be included.

(4) In each of the above embodiments, the protection portion 96 overlapping both the side end surface 84 of the first sealing layer 71 and the peripheral wiring D is illustrated. However, the protection portion 96 is provided on one of the side end surface 84 and the peripheral wiring D. May be adopted.

(5) In each of the above-described embodiments, the protection portion 96 is formed so as to overlap the periphery of the first sealing layer 71. However, the protection portion 96 may be formed so as to overlap the periphery 48 of the light emitting function layer 46. In the above configuration, as in the first embodiment, the entry of moisture and outside air into the gap between the peripheral edge 48 and the underlayer is reduced.

(6) In each of the embodiments described above, the protection portion 96 is formed so as to overlap the entire periphery of the lower peripheral edge 88, but the protection portion 96 may be overlapped with a part of the lower peripheral edge 88. Similarly, the protection part 96 may be overlapped on a part of the upper peripheral edge 86. Further, in each of the above-described embodiments, the configuration is such that the protection unit 96 overlaps a part of the peripheral wiring D. However, a configuration in which the protection unit 96 overlaps the entire area of the peripheral wiring D in plan view may be employed.

(7) In each of the above embodiments, the protection portion 96 is overlapped on both the upper peripheral edge 86 and the lower peripheral edge 88 of the first sealing layer 71. However, the protective portion 96 may be formed on any of the upper peripheral edge 86 and the lower peripheral edge 88. It may be superimposed on one side.

(8) The type of the coloring layer K of the filter layer 90 is not limited to the above-described embodiments. For example, when the filter layer 90 is added to the first colored layer KR that transmits red light, the second colored layer KG that transmits green light, and the third colored layer KB that transmits blue light, the wavelength is about You may comprise including the 4th coloring layer which permeate | transmits the yellow light of 580 nm. In the above configuration, a pixel P having a yellow display color is formed in the display region 12, and the fourth color filter overlapping the light emitting element 45 of the pixel P and the fourth layer overlapping the third layer 96 B of the protection unit 96 are provided. It is formed from the same layer using a fourth colored layer.

(9) FIG. 11 illustrates a configuration in which the peripheral edge 48 of the light emitting function layer 46 and the peripheral wiring D (the second conductor 58 and the second power supply conductor 42) overlap in a plan view in the second region S2. It is not essential that the peripheral wiring D overlap the peripheral edge 48 of the light emitting function layer 46. Even when the peripheral wiring D and the light emitting function layer 46 do not overlap, the peripheral wiring D is formed only in the first region S1 by forming the peripheral wiring D over both the first region S1 and the second region S2. The expected effect of lowering the resistance of the peripheral wiring D as compared with the configuration is realized.

(10) In each of the above-described embodiments, the light emitting element 45 using the organic EL material is exemplified. However, the present invention is similarly applied to a structure using a light emitting element such as an LED or a light emitting element having a light emitting layer formed of an inorganic EL material. Applied. In each of the above embodiments, the top emission type light emitting device 100 that emits light to the side opposite to the substrate 10 is illustrated. However, the present invention also applies to a bottom emission type light emitting device that emits light to the substrate 10 side. The same applies.

(11) In each of the above-described embodiments, the configuration in which the light-emitting functional layer 46 that emits white light is formed continuously over the entire display region 12 has been described. However, a plurality of portions that emit monochromatic light having different wavelengths (hereinafter, “ The light-emitting function layer 46 may be configured by a “light-emitting portion”. For example, the light-emitting function layer 46 (light-emitting layer) illustrated in FIG. 21 includes a light-emitting unit 47R that emits red light, a light-emitting unit 47G that emits green light, and a light-emitting unit 47B that emits blue light. Is done. FIG. 21 assumes a configuration in which a plurality of pixels P of the same color are arranged in the Y direction (stripe arrangement). Therefore, the red light emitting portion 47R extends linearly in the Y direction along the arrangement of the plurality of red pixels P. Similarly, the light emitting unit 47G extends in the Y direction along the arrangement of the plurality of green pixels P, and the light emitting unit 47B extends in the Y direction along the plurality of blue pixels P. As illustrated in FIG. 21, the peripheral edge 48 of the light emitting function layer 46 in the above configuration is not an individual peripheral edge of each light emitting unit 47 but a light emitting function configured by a plurality of light emitting units 47 (47R, 47G, 47B). The perimeter that is perceived for the entire layer 46 is meant. In the above configuration, the filter layer 90 is omitted.

<Electronic equipment>
The light emitting device 100 exemplified in each of the above embodiments is suitably used as a display device of various electronic devices. FIG. 22 illustrates a head-mounted display device 1 (HMD: Head Mounted Display) using the light-emitting device 100 illustrated in each of the above-described embodiments as an electronic device.

  The display device 1 is an electronic device that can be mounted on the head of the user, and includes a transmission part (lens) 2L overlapping the left eye of the user, a transmission part 2R overlapping the right eye of the user, and a left eye. It includes a light emitting device 100L and a half mirror 4L, and a light emitting device 100R and a half mirror 4R for the right eye. The light emitting device 100L and the light emitting device 100R are arranged such that the emitted light travels in mutually opposite directions. The half mirror 4L for the left eye transmits the light transmitted through the transmission unit 2L to the left eye side of the user and reflects the light emitted from the light emitting device 100L to the left eye side of the user. Similarly, the half mirror 4R for the right eye transmits the light transmitted through the transmission unit 2R to the right eye side of the user and reflects the light emitted from the light emitting device 100R to the right eye side of the user. Therefore, the user perceives an image obtained by superimposing the image observed through the transmission unit 2L and the transmission unit 2R and the display image of each light emitting device 100. Further, by displaying a stereoscopic image (an image for the left eye and an image for the right eye) to which parallax is given to each other on the light emitting device 100L and the light emitting device 100R, the user can perceive the stereoscopic effect of the display image. Is possible.

  Note that the electronic device to which the light emitting device 100 of each of the above embodiments is applied is not limited to the display device 1 in FIG. For example, the light emitting device 100 of the present invention is also suitably used for an electronic view finder (EVF) used for an imaging device such as a video camera and a still camera. In addition, the light emitting device of the present invention can be applied to various electronic devices such as a mobile phone, a portable information terminal (smartphone), a monitor such as a television and a personal computer, and a car navigation device.

10 ... board, 100 ... light emitting device, 12 ... display area, 14 ... peripheral area, 16 ... mounting area, 22 ... scanning line, 24 ... control line, 26 ... signal line, 30 ... Drive circuit 32 scanning line drive circuit 34 signal line drive circuit 36 mounting terminal 41 first power supply conductor 42 second power supply conductor E1 first electrode E2: second electrode, 45: light emitting element, 46: light emitting functional layer, 47: light emitting part, 48: peripheral edge, 58: second conductor, 60: optical path adjusting layer, 63 ... 1 conductor, 65 pixel defining layer, 70 sealing body, 71 first sealing layer, 82 sealing surface, 84 side edge surface, 86 upper peripheral edge, 88 lower Side peripheral edge, 72 second sealing layer, 73 third sealing layer, 90 filter layer, 92 insulating layer, 94R, 94G, 94B color filter , 96... Protection part, 96R... First layer, 96G... Second layer, 96B... Third layer, 20... Sealing substrate, 21. ... Peripheral wiring, TDR ... Driving transistor, TEL ... Light emission control transistor, TSL ... Selection transistor, Q (QA1, QA2, QA3, QA4, QB1, QB2, QD1, QE1) ... Relay electrode, 1 ... Display Apparatus, 2L: transmission section, 2R: transmission section, 4L: half mirror, 4R: half mirror.

Claims (5)

Peripheral wiring,
A first insulating layer covering the peripheral wiring;
A first electrode and a second electrode disposed in a display region of the base, and light emission formed on a surface of the first insulating layer and emitting light in response to a current between the first electrode and the second electrode; A light emitting element including a functional layer,
A first power supply conductor formed in the display area by a light-reflective conductive material and supplied with a higher power supply potential,
The second electrode covers the light emitting function layer in the display area, and is connected to the peripheral wiring via a conduction hole of the first insulating layer in a first area located around the display area in plan view. And
The periphery of the light emitting functional layer is located in a second region located between the display region and the first region in a plan view,
The peripheral wiring is formed over the first region and the second region;
The light emitting functional layer overlaps the peripheral wiring in plan view,
The peripheral wiring,
A second power conductor formed from the same layer as the first power conductor and supplied with a lower power potential;
A conductor formed on a surface of a second insulating layer covering the first power supply conductor and the second power supply conductor and coming into contact with the second power supply conductor through a conduction hole of the second insulation layer; Including
The conductor is Ri Do heavy in plan view in the region of the gap between the first power supply conductor and said second power supply conductor,
The light emitting device , wherein the second electrode is electrically connected to the conductor through a conduction hole of the first insulating layer . Width of the second region in a plan view light emitting device having a width greater than a first aspect of the first region. A sealing layer formed on a surface of the second electrode to seal the light emitting element;
The periphery of the sealing layer is located in a third region located on the opposite side of the first region from the display region in plan view,
The first region and the third region are adjacent to each other with an end portion of the conduction hole of the first insulating layer that is most distant from the display region as a boundary,
The peripheral wiring emitting device according to claim 1 or claim 2 formed with the first region over said third region. The light emitting device according to claim 3 , wherein a width of the third region is larger than a width of the first region in a plan view. An electronic device including any of the light-emitting device of claims 1 to 4.

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