JP2004103691A - Process for fabricating semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for fabricating a semiconductor device in which a planarization level is realized while suppressing variation in film thickness with a small polishing amount by suppressing unevenness of CMP easily in a semiconductor substrate having a trench isolation region and significant roughness and fineness of trenches, and to provide a semiconductor device. <P>SOLUTION: A CMP stopper film of two layers (a silicon nitride film 11 and a silicon oxynitride film 12) having different polishing rates is employed. The upper layer silicon oxynitride film 12 having a higher polishing rate forms a dummy pattern DMP1 of protrusions and recesses. Subsequently, trenches are formed and filled with an oxide film 14 for isolation. Polishing rate of CMP is differentiated depending on the occupation rate of the oxide film 14 for isolation, the silicon oxynitride film 12 and the silicon nitride film 11 thus making the best use of selectivity of polishing rate in polishing pad. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device and a method of manufacturing a semiconductor device in which a groove for an element isolation region is subjected to pre-planarization processing by chemical mechanical polishing on a semiconductor substrate having a remarkably dense / dense groove.
[0002]
[Prior art]
As a method for separating elements formed on a semiconductor substrate from each other, trench isolation is known. In the trench isolation, a groove (trench) is formed in a semiconductor substrate other than the element formation region, and the inside of the groove is filled with an insulator, particularly, a silicon oxide film or the like, thereby realizing element isolation. Trench isolation provides a deeper isolation distance in the substrate than LOCOS isolation (selective oxidation isolation). For this reason, the separation width can be significantly reduced. Trench isolation is referred to as STI (Shallow Trench Isolation) and is a structure advantageous for high integration of a semiconductor integrated circuit.
[0003]
5A to 5D are cross-sectional views showing a conventional STI manufacturing method of a semiconductor device in the order of steps.
First, as shown in FIG. 5A, a mask pattern of a nitride film (silicon nitride film) 52 is formed on a semiconductor substrate 51 through a photolithography process. According to the mask pattern, a groove pattern having a predetermined depth, that is, a trench 53 is formed on the substrate 51 by etching.
[0004]
Next, as shown in FIG. 5B, after oxidizing the trench 53 (not shown), an oxide film (silicon oxide film) 54 is formed by a CVD (Chemical Vapor Deposition) method. The deposition level of the oxide film 54 varies according to the unevenness of the trench 53. That is, with respect to the oxide film 54, the region where the density of the trenches 53 is high has a low deposition level, whereas the region over which the trenches 53 do not exist is wide, and the deposition level is high and the oxide film 54 is thick.
[0005]
Next, as shown in FIG. 5C, the oxide film 54 in a relatively thick state, such as on the element region, is selectively etched by using a photolithography technique to form a region 541 which has been thinned to some extent. create. Thereby, uniformity is achieved in a flattening step performed later.
[0006]
Next, as shown in FIG. 5D, chemical mechanical polishing, a so-called CMP (Chemical Mechanical Polishing) technique, is used as the planarization treatment. That is, the polishing rate is selected by the pressure difference of the polishing pad applied to the uneven portion of the layer to be planarized, and the uneven portion is made smooth after a predetermined time. The nitride film 52 is detected as a CMP stopper film, and then the nitride film 52 is removed. Thus, a trench element isolation insulating film in which the oxide film 54 is embedded in the trench 53 is formed.
[0007]
[Problems to be solved by the invention]
By performing CMP on the trench isolation as in the above configuration, a flattening level with less error can be realized. However, in-plane variation often occurs during CMP due to the density of the trenches 53. If polishing unevenness such as dishing occurs, a region where the nitride film 52 is exposed early appears. As a result, if the end of the CMP process is detected, the residual region of the oxide film 54 is not small. Therefore, the subsequent step of removing the nitride film 52 is hindered.
[0008]
As a countermeasure against such a situation, in the CMP processing, a longer polishing time is required after the detection of the nitride film 52, and excessive polishing is performed such that the oxide film 54 remaining on the nitride film 52 is completely removed. As a result, there are problems such as a decrease in CMP efficiency, progress of deterioration of the polishing pad, and variation in thickness of the oxide film 54 as a trench element isolation film.
[0009]
The present invention has been made in view of the above circumstances, and it is possible to easily suppress CMP polishing unevenness in a semiconductor substrate having a trench element isolation region, particularly in a semiconductor substrate in which the density of a groove for an element isolation region is remarkable. Another object of the present invention is to provide a method of manufacturing a semiconductor device and a semiconductor device which realize a flattening level with a small amount of polishing and a small thickness variation.
[0010]
[Means for Solving the Problems]
The method for manufacturing a semiconductor device according to claim 1 of the present invention includes:
Forming a first layer having a first polishing rate on a semiconductor substrate; and forming a second layer having a second polishing rate higher than the first polishing rate on the first layer. Process and
Forming a dummy pattern of a predetermined depth so that at least the second layer has a plurality of irregularities;
Forming a groove pattern for element isolation on the substrate via lithography technology,
Depositing a separation insulating film for element isolation that embeds the groove pattern including on the second layer;
Planarizing by chemical mechanical polishing until at least the first layer is exposed;
Removing the first layer;
It is characterized by having.
[0011]
According to the method of manufacturing a semiconductor device according to the present invention, the first and second layers having different polishing rates are provided, and the second layer having a higher polishing rate is mainly provided on the first layer. A dummy pattern is formed. Thereby, in the chemical mechanical polishing, the polishing rate is made different between the insulating film for element isolation and the second layer, and between the second layer and the first layer, and bias of the polishing pressure is prevented. This eliminates unevenness in planarization. In addition, the selectivity of the polishing rate in the polishing pad is utilized to realize uniform chemical mechanical polishing without waste such as excessive polishing.
[0012]
A method of manufacturing a semiconductor device according to [claim 2] of the present invention is dependent on [claim 1],
The second layer is formed to be thicker than the first layer. The second layer has a higher polishing rate than that of the first layer, and is more preferable in terms of forming irregularities.
[0013]
A method of manufacturing a semiconductor device according to [Claim 3] of the present invention is dependent on [Claim 1] or [Claim 2],
The first layer is exposed at the bottom of the concave portion in the dummy pattern. It depends on the relationship of the lithography process for forming the unevenness.
[0014]
A method of manufacturing a semiconductor device according to [Claim 4] of the present invention is dependent on any one of [Claim 1] to [Claim 3],
The second layer around the formation of the groove pattern is constituted by only the concave portions or only the convex portions of the dummy pattern. It contributes to the improvement of the accuracy of the lithography process.
[0015]
A method for manufacturing a semiconductor device according to [Claim 5] of the present invention is dependent on any one of [Claim 1] to [Claim 4],
The dummy pattern has a lattice groove pattern.
A method of manufacturing a semiconductor device according to [Claim 6] of the present invention is dependent on any one of [Claim 1] to [Claim 4],
The dummy pattern has a plurality of opening patterns.
These dummy patterns are preferable configurations for realizing uniform chemical mechanical polishing.
[0016]
According to a seventh aspect of the present invention, there is provided a semiconductor device in which an element isolation region and an element region surrounded by the element isolation region are formed by using the method according to any one of the first to sixth aspects. It is characterized by comprising.
[0017]
The semiconductor device according to claim 8 of the present invention is an evaluation device in which an element isolation region and an element region surrounded by the element isolation region are formed by using any one of the methods described in [claim 1] to [claim 6]. It is characterized by constituting a semiconductor wafer.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device and a semiconductor device according to a first embodiment of the present invention in the order of steps.
As shown in FIG. 1A, a first layer having a first polishing rate, for example, a silicon nitride film 11 is formed on a semiconductor substrate 10 as a stopper film for CMP (chemical mechanical polishing). On this silicon nitride film 11, a second layer having a second polishing rate larger than the first polishing rate, which functions as a stopper film but substantially serves to adjust the polishing rate, for example, a silicon oxynitride film 12 is formed.
[0019]
Next, as shown in FIG. 1B, a plurality of irregularities are formed on the silicon oxynitride film 12 by using a resist mask (not shown) formed by a photolithography technique and a reactive ion etching technique. Then, a dummy pattern DMP1 having a predetermined depth is formed. Here, the irregularities of the dummy pattern DMP1 are formed by controlling the etching time so that the silicon nitride film 11 as the first layer is not exposed. In addition, irregularities of the dummy pattern are not arranged around the region where the groove pattern for element isolation is to be formed. In the figure, only the convex portions are not etched, but they may be etched to have only the concave portions.
[0020]
Next, as shown in FIG. 1C, a resist mask RM is newly formed by using a photolithography technique, and a groove pattern for element isolation, that is, a trench 13 is etched by using a reactive ion etching technique. Form. That is, the silicon oxynitride film 12, the silicon nitride film 11, and the substrate 10 are continuously etched with the change of the reaction gas. For example, the silicon oxynitride film 12 and the silicon nitride film 11 are made of CF ₄ or CHF ₃ , and the substrate 10 uses Cl ₂ as an etching gas. Here, a region where a difference in the density of the trench 13 appears due to the relationship of the element region is shown. That is, it includes a portion where the element region A2 having a larger area than the element region A1 is provided.
[0021]
Next, as shown in FIG. 1D, after removing the resist, the trench 13 is thermally oxidized to form an oxide film (not shown), and then an oxide film (silicon oxide film) is formed by a CVD (Chemical Vapor Deposition) method. 14 is formed. The oxide film 14 has a deposition level according to the unevenness formed by the trench 13 and the unevenness of the dummy pattern DMP1. Since the dummy pattern DMP1 also exists on the large-area element region A2, a remarkable change in the deposition level is suppressed.
[0022]
Next, as shown in FIG. 1E, CMP mainly using the oxide film 14 is performed. During the CMP, the bias of the polishing pressure is prevented by the dummy pattern DMP1 of the silicon oxynitride film 12, and the overall polishing rate is reduced. Eventually, polishing is performed in which the silicon oxynitride film 12 and the silicon nitride film 11 coexist, and when the ratio of the silicon oxynitride film 12 becomes extremely small, the polishing rate further decreases and polishing is completed.
[0023]
Thereafter, as shown in FIG. 1F, a step of removing the silicon nitride film 11 by hot phosphoric acid immersion or the like is performed. Thus, a trench element isolation insulating film in which oxide film 14 is embedded in trench 13 is formed.
[0024]
According to the first embodiment and the method, a CMP stopper film of two layers (silicon nitride film 11 and silicon oxynitride film 12) having different polishing rates is used. As a result, the upper silicon oxynitride film 12 having a high polishing rate forms the dummy pattern DMP1, and contributes to preventing uneven polishing pressure. Further, the polishing rate varies depending on the ratio of the oxide film 14, the silicon oxynitride film 12, and the silicon nitride film 11 for element isolation. This makes use of the selectivity of the polishing rate of the polishing pad, and achieves uniform chemical mechanical polishing without waste such as excessive polishing.
[0025]
That is, the concern about the conventional residual oxide film is solved. In addition, it is possible to shift to the step of removing the silicon nitride film 11 in a more appropriate state while minimizing the deterioration of the CMP efficiency and the deterioration of the polishing pad. Therefore, the influence of the variation in the thickness of the oxide film 14 as the trench element isolation film is very small, and high reliability can be maintained in the subsequent element manufacturing process.
[0026]
2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device and a semiconductor device according to a second embodiment of the present invention in the order of steps. The same parts as those in the first embodiment will be described with the same reference numerals.
As shown in FIG. 2A, a first layer having a first polishing rate, for example, a silicon nitride film 11, is formed on a semiconductor substrate 10 and a second layer having a second polishing rate higher than the first polishing rate is formed thereon. Two layers, for example, a silicon oxynitride film 12 are formed. This configuration is the same as FIG. 1A of the first embodiment.
[0027]
Next, as shown in FIG. 2B, a plurality of irregularities are formed on the silicon oxynitride film 12 using a resist mask (not shown) formed by a photolithography technique and a reactive ion etching technique. Then, a dummy pattern DMP2 having a predetermined depth is formed. Here, the silicon nitride film 11, which is the first layer, is exposed at the bottom. In addition, irregularities of the dummy pattern are not arranged around the region where the groove pattern for element isolation is to be formed. In the figure, only the concave portion where the silicon nitride film 11 is exposed by etching is shown, but the state may be only the convex portion without etching.
[0028]
Next, as shown in FIG. 2C, a resist mask RM is newly formed by using a photolithography technique, and a groove pattern for element isolation, that is, a trench 13 is etched by using a reactive ion etching technique. Form. That is, the silicon nitride film 11 and the substrate 10 are continuously etched with switching of the reaction gas. For example, the silicon nitride film 11 is made of CF ₄ or CHF ₃ , and the substrate 10 is made of Cl ₂ as an etching gas. Here, a region where a difference in the density of the trench 13 appears due to the relationship of the element region is shown. That is, it includes a portion where the element region A2 having a larger area than the element region A1 is provided.
[0029]
Next, as shown in FIG. 2D, after removing the resist, the trench 13 is thermally oxidized to form an oxide film (not shown), and then an oxide film (silicon oxide film) is formed by a CVD (Chemical Vapor Deposition) method. 14 is formed. The oxide film 14 has a deposition level according to the unevenness formed by the trench 13 and the unevenness of the dummy pattern DMP2. Since the dummy pattern DMP2 also exists on the large-area element region A2, a remarkable change in the deposition level is suppressed.
[0030]
Next, as shown in FIG. 2E, CMP mainly using the oxide film 14 is performed. During the CMP, the bias of the polishing pressure is prevented by the dummy pattern DMP2 of the silicon oxynitride film 12, and the overall polishing rate is reduced. Eventually, polishing is performed in which the silicon oxynitride film 12 and the silicon nitride film 11 coexist, and when the ratio of the silicon oxynitride film 12 becomes extremely small, the polishing rate further decreases and polishing is completed.
[0031]
Thereafter, as shown in FIG. 2F, a step of removing the silicon nitride film 11 by hot phosphoric acid immersion or the like is performed. Thus, a trench element isolation insulating film in which oxide film 14 is embedded in trench 13 is formed.
[0032]
The same effects as those of the first embodiment can be obtained by the second embodiment and the method. That is, the upper silicon oxynitride film 12 having a higher polishing rate than the lower layer as the two-layer CMP stopper film forms the dummy pattern DMP2, thereby contributing to the prevention of uneven polishing pressure. Further, the polishing rate varies depending on the ratio of the oxide film 14, the silicon oxynitride film 12, and the silicon nitride film 11 for element isolation. This makes use of the selectivity of the polishing rate of the polishing pad, and achieves uniform chemical mechanical polishing without waste such as excessive polishing.
[0033]
Then, the concern about the conventional residual oxide film is solved, and the reduction of the CMP efficiency and the deterioration of the polishing pad are minimized. Therefore, the process can be shifted to the step of removing the silicon nitride film 11 in a more appropriate state. Therefore, the influence of the variation in the thickness of the oxide film 14 as the trench element isolation film is very small, and high reliability can be maintained in the subsequent element manufacturing process.
[0034]
FIGS. 3A and 3B are plan views showing specific examples that can be used for any of the dummy patterns DMP1 and DMP2 shown in FIGS. In FIG. 3A, a lattice groove pattern 31 is formed by a photolithography technique. In FIG. 3B, a plurality of opening patterns 32 are formed by photolithography. That is, the hatched patterns 31 and 32 are both concave groove patterns, which contribute to preventing uneven pressure of the polishing pad and realize more uniform CMP.
[0035]
FIG. 4 is a partial plan view of an evaluation wafer to which the first and second embodiments and the method are adopted. With the design and development of semiconductor integrated circuits including miniaturized elements, it is important to evaluate the lithography technology required for forming gate electrodes and wiring, and to evaluate various conditions such as film quality related to the manufacture of the elements. Is evaluated in. That is, in the evaluation wafer, various element patterns including dimensions, pitches, and the like in accordance with the actual design are formed, and the manufacturing process is evaluated. The chip area portion 42 of the evaluation wafer 41 may be provided with a large-area element region such as a capacitance forming region. That is, it includes a portion where the element region A2 having a larger area than the element region A1 is provided. The element isolation region STI is indicated by oblique lines, and there is a remarkable difference in trench density as shown in the figure. By adopting the first and second embodiments and the method in such a configuration, a highly reliable element isolation region can be obtained, and a proper evaluation wafer can be configured.
[0036]
In each embodiment, as the CMP stopper film, the first layer having the first polishing rate is the silicon nitride film (11), and the second layer is the silicon oxynitride film (12). However, the present invention is not limited to this. . Other materials may be used as long as the second layer having a higher polishing rate has irregularities on the first layer for adjusting the polishing rate.
[0037]
【The invention's effect】
As described above, according to the present invention, as the CMP stopper, the first and second layers having different polishing rates are provided, and the second layer having a higher polishing rate is mainly provided on the first layer. Is formed. Thereby, in the chemical mechanical polishing, the polishing rate is made different between the insulating film for element isolation and the second layer, and between the second layer and the first layer, and bias of the polishing pressure is prevented. This eliminates unevenness in planarization. In addition, the selectivity of the polishing rate in the polishing pad is utilized to realize uniform chemical mechanical polishing without waste such as excessive polishing. As a result, the polishing unevenness of CMP can be easily suppressed in a semiconductor substrate having a trench element isolation region, particularly in a semiconductor substrate in which the trenches for the element isolation region are extremely dense and dense. A method for manufacturing a semiconductor device and a semiconductor device to be realized can be provided.
[Brief description of the drawings]
FIGS. 1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device and a semiconductor device according to a first embodiment of the present invention in the order of steps.
FIGS. 2A to 2F are cross-sectional views illustrating a method for manufacturing a semiconductor device and a semiconductor device according to a second embodiment of the present invention in the order of steps; FIGS.
FIGS. 3A and 3B are plan views showing specific examples that can be used for both dummy patterns DMP1 and DMP2 shown in FIGS. 1 and 2, respectively.
FIG. 4 is a partial plan view of an evaluation wafer to which the first and second embodiments and the method are adopted.
FIGS. 5A to 5D are cross-sectional views showing a conventional STI manufacturing method for a semiconductor device in the order of steps.
[Explanation of symbols]
10, 51: semiconductor substrate, 11, 52: silicon nitride film,
12 ... silicon oxynitride film, 13, 53 ... trench, 14, 54 ... oxide film,
31, 32 ... concave groove pattern, 41 ... evaluation wafer, 42 ... chip area portion,
DMP: dummy pattern, A1, A2: element region

Claims (8)

Forming a first layer having a first polishing rate on the semiconductor substrate;
Forming a second layer having a second polishing rate greater than the first polishing rate on the first layer;
Forming a dummy pattern of a predetermined depth so that at least the second layer has a plurality of irregularities;
Forming a groove pattern for element isolation on the substrate via lithography technology,
Depositing an insulating film for element isolation that embeds the groove pattern including on the second layer;
Planarizing by chemical mechanical polishing until at least the first layer is exposed;
Removing the first layer;
A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the second layer is formed thicker than the first layer. 3. The method according to claim 1, wherein a first layer is exposed at a bottom of the recess in the dummy pattern. 4. The method according to claim 1, wherein the second layer around the formation of the groove pattern includes only a concave portion or a convex portion of the dummy pattern. 5. The method according to claim 1, wherein the dummy pattern has a lattice groove pattern.
Semiconductor device. The method according to claim 1, wherein the dummy pattern has a plurality of opening patterns. A semiconductor device comprising a semiconductor substrate on which an element isolation region and an element region surrounded by the element isolation region are formed by using any one of the above-mentioned [claims 1] to [6]. 7. A semiconductor device, wherein an evaluation semiconductor wafer in which an element isolation region and an element region surrounded by the element isolation region are formed by using any one of the above-mentioned [claims 1] to [6].

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