JP4187426B2 - Semiconductor device manufacturing method, mask pattern design method and program - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, a method for designing a mask pattern used for manufacturing a semiconductor device, and a program for designing a mask pattern. In particular, a method for manufacturing a semiconductor device for performing planarization polishing on a layer to be polished by chemical mechanical polishing while controlling the film thickness of the layer to be polished, a method for designing an exposure mask pattern used in this manufacturing method, and a program therefor About.
[0002]
[Prior art]
In a recent semiconductor integrated circuit technology, as a planarization technology for reducing a level difference caused by wirings and circuit elements formed on a wafer surface, a chemical mechanical polishing method (hereinafter also referred to as a CMP method. Polishing by a CMP method is also used. (Also referred to as CMP polishing) is known (see, for example, Mochikoku 5-30052 and JP-A-7-285050).
[0003]
A CMP apparatus 17 shown in FIG. 5 includes a rotating disk 11 and a polishing head 15 disposed to face the rotating disk 11. A polishing cloth 12 is attached to the rotating disk 11 with an adhesive (not shown), and a packing material 14 is attached to the polishing head 15 with an adhesive (not shown).
When performing the CMP method using such an apparatus, the semiconductor wafer 13 having a surface to be polished formed on the surface (lower surface in the figure) is held on the packing agent 14 by a vacuum adsorption force or a surface tension of water. Next, the rotary disk 11 and the polishing head 15 are rotated around their respective rotation axes. Then, the polishing head 15 is pressed against the rotating disk 11 with a predetermined pressure while supplying the abrasive 16 onto the rotating disk 11. As a result, the polishing layer on the surface of the semiconductor wafer 13 is subjected to CMP polishing.
[0004]
FIG. 6 is a diagram illustrating an example of a manufacturing process of a semiconductor device that performs such CMP polishing. First, as shown in FIG. 6A, an oxide film 22 is formed on the surface layer of the silicon substrate 21 using the silicon nitride film 24 as a mask, and a first diffusion layer 23 is formed under the oxide film 22. Next, as shown in FIG. 6B, an electrode 25 is formed on the oxide film 22, and a second diffusion layer 26 is formed on the exposed surface from which the silicon nitride film 24 has been removed. Thereafter, as shown in FIG. 6C, an interlayer insulating film 27 is formed, and a first wiring 28 is formed in this portion. Next, as shown in FIG. 6D, an interlayer insulating film 29 is formed so as to cover the first wiring 28. Thereafter, as shown in FIG. 6E, the above-described CMP polishing is performed to flatten the surface of the interlayer insulating film 29. After the above, as shown in FIG. 6 (f), the second wiring 30 is formed on the interlayer insulating film 29.
[0005]
Here, before the second wiring 30 is formed, a contact hole 29H is formed in the interlayer insulating film 29 in order to connect the wirings in the vertical direction by etching. In this case, if the interlayer insulating film 29 is thick, the contact hole 29H does not reach the first wiring 28, resulting in poor connection. On the other hand, when the interlayer insulating film 29 is thin, the contact hole 29H penetrates the first wiring 28, causing a problem that the resistance value increases. Therefore, in the step of planarizing the interlayer insulating film 29 described with reference to FIG. 6E, the thickness of the interlayer insulating film 29 on the first wiring 28 is set when performing CMP polishing for product management. It is necessary to measure and detect the film thickness (formed film thickness) when the interlayer insulating film 29 is formed, the amount of polishing, and the film thickness after polishing.
[0006]
As a specific method, for example, in Japanese Patent Laid-Open No. 11-219922, a CMP monitor pattern for film thickness measurement is provided in the same layer as the first wiring 28, so that the interlayer insulating film 29 is formed on the CMP monitor pattern. It is disclosed that the film thickness can be measured and the film thickness can be managed before and after polishing.
[0007]
That is, FIG. 7 is a diagram showing an example of the arrangement of the CMP monitor pattern on the wafer (that is, on the semiconductor substrate). As shown in this figure, the surface side of the wafer 1 is divided into a plurality of chip regions by scribe lines 3. Then, CMP monitor patterns 8 and 9 having a quadrilateral planar shape as viewed from above are provided in the central portion of the scribe line 3 and in the chip region 5. The CMP monitor pattern 8 in the chip area 5 is provided in the inside and the periphery of each functional block area 5a, and further adjacent to the functional block area 5a.
[0008]
A process from the formation of the CMP monitor patterns 8 and 9 to the flattening process will be described with reference to a cross-sectional view of the main part of FIG. First, as shown in FIG. 8A, a base insulating film 2 made of silicon oxide is formed on the surface of a wafer 1 made of silicon, and a surface layer of the base insulating film 2 is etched to form a scribe line 3. . At this time, the island pattern 4 is left near the center of the scribe line 3. This also divides the front side of the wafer 1 into chip regions 5. In the drawing, one scribe line and two chip regions 5 arranged on both sides thereof are shown. Next, as shown in FIG. 8B, a wiring layer 6 made of aluminum or polysilicon is formed on the base insulating film 2. Thereafter, as shown in FIG. 8C, the wiring layer 6 is patterned to form wiring 7 on the line and quadrilateral CMP monitor patterns 8 and 9. Here, the wiring 7 is formed in the chip region 5, and the CMP monitor patterns 8 and 9 are formed in the scribe line 3 above the island pattern 4 or in the chip region 5. Note that the wiring 7 formed in the chip region 5 is not formed with a uniform density. Therefore, in this figure, the wirings 7 are formed relatively densely on the left side in the drawing, and the wirings 7 are relatively sparsely formed on the right side in the drawing.
When a flat surface insulating film is formed on the wafer 1 so as to cover the wiring 7, first, as shown in FIG. 8D, the base 7 is covered with the wiring 7 and the monitor patterns 8 and 9. An interlayer insulating film 10 made of silicon oxide is formed on the insulating film 2. Next, the interlayer insulating film 10 is polished by CMP while measuring the thickness of the interlayer insulating film 10 on the CMP monitor patterns 8 and 9 (see FIG. 8E).
[0009]
[Problems to be solved by the invention]
However, the chemical mechanical polishing method as described above is dependent on the pattern of the base in terms of flatness. In other words, the polishing speed is higher in the portion where the pattern density of the base is low than in the portion where the pattern density is high, the thickness of the portion where the pattern density is high is relatively thick, and the thickness of the portion where the pattern density is low is relatively Thinner.
For this reason, after CMP polishing, the film thickness of the interlayer insulating film 10 on the CMP monitor pattern 9 disposed on the scribe line 3 and the CMP monitor pattern 8 disposed on the chip area 5 is determined by the chip area around the CMP area. The value varies depending on the density of the wiring 7 arranged at 5. For example, in the case of FIG. 8E, in the chip region on the left side in the figure where the pattern density of the wiring 7 is relatively high, the interlayer insulating film 10 is thick, and the pattern density of the wiring 7 is relatively high. In the chip region on the right side in the figure, the thickness of the interlayer insulating film 10 is reduced.
[0010]
Therefore, by measuring the film thickness d1 of the interlayer insulating film 10 on the CMP monitor pattern 9 arranged at one place on the scribe line 3, the film thickness of the interlayer insulating film 10 over the entire wafer or the entire chip region 5 is determined. It cannot be grasped, and it cannot be grasped where the measured value is in the film thickness distribution of the interlayer insulating film 10. For this reason, even if the polishing film thickness of the interlayer insulating film 10 is managed based on this measurement value, and the film thickness in the vicinity of the measurement location is included in the management standard range, the film thickness of other portions exceeds the standard range. There is a case.
[0011]
On the other hand, when the film thicknesses d2, d3, etc. of the interlayer insulating film 10 are measured using a plurality of CMP monitor patterns 8 arranged in the chip region 5, the measurement itself can be performed satisfactorily. However, this reduces the area in which the wiring can be formed in the chip region 5, which imposes restrictions on the circuit design of the semiconductor device and reduces the degree of freedom in circuit design or increases the chip size. Costs are lost.
It is also conceivable that a large number of CMP monitor patterns are arranged in the scribe line 3 and an average value of film thicknesses measured using these patterns is obtained and used. However, since not only the CMP monitor pattern 9 but also various monitor patterns and inspection patterns are formed on the scribe line 3, forming a large number of CMP monitor patterns 9 makes it difficult to form these patterns. Restrictions arise.
[0012]
By the way, in order to form a pattern such as a circuit or a CMP monitor pattern on a semiconductor substrate, many photomasks for exposure are used. In designing the mask pattern of these photomasks using a computer program, it is as shown in FIG. 9 in terms of data processing. That is, a mask pattern (chip area mask pattern) 51 corresponding to a circuit pattern or the like formed in each chip area is created (see FIG. 9A). On the other hand, the mask pattern 54 for the CMP monitor pattern to be formed in the scribe area, the mask pattern 55 corresponding to other monitor patterns and inspection patterns, the mask pattern 56 for photomask alignment, and the like are included. In addition, a process mask pattern 53 for use in a semiconductor device manufacturing process is created (see FIG. 9B). Thereafter, these patterns 51 and 53 are combined and used as data of the mask pattern 57 of the photomask (see FIG. 9C). Each photomask is formed using the data of the mask pattern 57, positioned by alignment marks formed on each photomask, and exposed to form a pattern such as a desired circuit or CMP monitor pattern on the semiconductor substrate. It will be formed sequentially.
[0013]
Among such photomask mask pattern designs, the process mask pattern 53 is created as shown in FIG. 10, for example. That is, the scribe corresponding area corresponding to the scribe area is set in step S62 from the kind processing information 61 such as the kind, chip size, block configuration, and number of arranged chips. Next, in step S64, the mask pattern 54 for the CMP monitor pattern and other monitor patterns and inspection patterns are placed at appropriate positions in the scribe corresponding area set in step S62 based on the creation standard 63 of the process mask pattern 53. A corresponding mask pattern 55, a mask pattern 56 for photomask alignment, and the like are arranged. Thereby, data of the process area mask pattern 53 is completed. The creation standard 63 includes rules for creating these mask patterns 54, 55, and 56 and rules for arranging the CMP monitor pattern.
[0014]
However, when creating data of the process area mask pattern 53 in this way, for example, as shown in FIG. 9A, a chip area mask pattern 51, a DRAM macro area 52 corresponding to the DRAM area, etc. Even if a high-density macro region corresponding to a high-density region with a high pattern density such as wiring or dielectric is included, this information is not referred to, so depending on the arrangement of this high-density macro region The CMP monitor mask pattern 54 could not be disposed at an appropriate position.
[0015]
The present invention has been made to solve the above-described problems, and a method for manufacturing a semiconductor device that can more appropriately measure the thickness of a polished and planarized insulating film, and is used in this manufacturing method. An object of the present invention is to provide a mask pattern design method for exposure and a program therefor.
[0016]
[Means, actions and effects for solving the problems]
But the solution is , Su A first step of forming a device pattern for a semiconductor device in the chip region of a wafer including a scribe region and a chip region partitioned by the scribe region, and forming a plurality of CMP monitor patterns in the scribe region; A second step of forming a layer to be polished in the chip region and the scribe region, and a chemical mechanical polishing of the layer to be polished while controlling the film thickness of the layer to be polished by using the CMP monitor pattern. And a third step of planarizing and polishing the semiconductor device, wherein the chip region includes at least one high-density region having a pattern density relatively higher than the surroundings, such as a DRAM region and a flash memory region. The CMP monitor pattern includes: In the above scribe area Near the high density region Within an area A first CMP monitor pattern formed on In the above scribe area Away from the high density area Outside the above neighborhood And a second CMP monitor pattern formed on the semiconductor device.
[0017]
As described above, in the polishing by the CMP method, the layer to be polished (the film thickness of the remaining film) after polishing is thick in the region where the pattern density is high, and the thickness after polishing in the region where the density is relatively lower than this. Tend to be thinner. That is, in the layer to be polished, the portion located in the high-density region of the chip region tends to be thick, and the other portion tends to be thin.
On the other hand, in the present invention, in the vicinity of the high-density region in the scribe region. Within an area The first CMP monitor pattern is separated from the high density region. Outside the neighborhood A second CMP monitor pattern is formed on each. Near the high density region where the first CMP monitor pattern is located Within an area Then, the thickness of the layer to be polished becomes relatively thick due to the influence of the high density region. On the other hand, away from the high density region where the second CMP monitor pattern is located Outside the neighborhood Then, the thickness of the layer to be polished is relatively thin.
Therefore, by using the first and second CMP monitor patterns, the thickness information of the layer to be polished can be obtained from both the thick remaining portion and the thinned portion, so that the polishing thickness of the layer to be polished can be easily managed.
[0018]
In addition, since the CMP monitor pattern is formed in the scribe region, the chip size may be hindered to form a device pattern, or the chip size may be increased to secure the area of the device pattern, as in the case where the CMP monitor pattern is formed in the chip region. It does not cause problems such as being forced to enlarge. Further, when a large number of CMP monitor patterns are formed in the scribe area and the thickness of the layer to be polished is measured using each CMP monitor pattern, other monitor patterns and inspection patterns to be formed in the scribe area are arranged. It may be difficult to arrange these and the CMP monitor pattern. However, in the present invention using two of the first and second CMP monitor patterns, interference with these can be suppressed, so that other monitor patterns and inspection patterns can be easily arranged.
[0019]
The formation of the CMP monitor pattern is preferably performed at the same time using the same material as the formation of the device pattern using the process process for forming the device pattern.
Further, in this specification, the chip region refers to a region that becomes an individual chip after the wafer is divided and cut. Furthermore, the scribe area refers to an area that is formed so as to surround each chip area and is scheduled to be cut with a cutting blade when the wafer is cut to form each chip area as an individual chip. In addition, the high density region is formed in a region such as a DRAM pattern or a flash memory region in which a functional block having a certain function is formed, such as a wiring pattern or a dielectric pattern, due to the nature of the functional block. Since the pattern density of the pattern to be formed is higher than that of the other functional blocks, it refers to an area having a relatively higher density than the surrounding area when the entire chip area is viewed.
[0020]
Further, in the method of manufacturing the semiconductor device, the first CMP monitor pattern is formed in a range within 1000 μm from the end of the high density region, and the second CMP monitor pattern is formed in a range exceeding 1000 μm from the end of the high density region. A method for manufacturing a semiconductor device is preferable.
[0021]
It was found that due to the presence of a high-density region such as a DRAM region, the range that affects the thickness of the layer to be polished during CMP polishing is approximately 1000 μm from the end of the high-density region. Therefore, the first CMP monitor pattern remains thick by forming it within 1000 μm from the end of the high-density region in the scribe region, and forming the second CMP monitor pattern in a range exceeding 1000 μm from the end of the high-density region in the scribe region. Since the thickness information of the layer to be polished can be obtained from both the portion and the thinned portion, the polishing thickness of the layer to be polished can be easily managed.
[0022]
Yet another solution is , Su CMP corresponding to a CMP monitor pattern disposed on the surface side of a wafer including a scribe region and a chip region partitioned by the scribe region, and for measuring the film thickness of the layer to be polished during chemical mechanical polishing. A method for designing an exposure mask pattern including a monitor mask pattern, the first means for setting a scribe corresponding area corresponding to the scribe area from the kind processing information such as kind, chip size, block configuration, and the like, Second means for extracting a high-density macro area corresponding to a high-density area whose pattern density is relatively higher than the surroundings, such as a DRAM area and a flash memory area, from the functional block arrangement information about the functional blocks formed in the chip area And the set scribing area in the vicinity of the high-density macro area Within an area A first mask region located at a position other than the first mask region And located outside the vicinity of the high-density macro area A third means for dividing into a second mask region and a first CMP monitor mask pattern corresponding to the first CMP monitor pattern are arranged in the first mask region, and a second CMP monitor mask corresponding to the second CMP monitor pattern And a fourth means for arranging the pattern in the second mask region.
[0023]
In the present invention, a scribing area is set from the product type processing information, a high-density macro area is extracted from the functional block arrangement information, the scribing area is divided into a first mask area and a second mask area, and the first CMP monitor is used. A mask pattern is disposed in the first mask region, and a second CMP monitor mask pattern is disposed in the second mask region. For this reason, the vicinity of the high-density macro area corresponding to the high-density area Within an area In addition, the first CMP monitor mask pattern corresponding to the first CMP monitor pattern is separated from the high density macro region corresponding to the high density region. Outside the vicinity of the high-density macro area Second CMP monitor mask pattern corresponding to the second CMP monitor pattern N But , That Each is arranged.
In other words, if an exposure mask pattern manufactured in accordance with this design method is used, the first and second CMP monitor patterns are disposed in the vicinity of the high-density region and at positions away from each other. Since thickness information can be obtained from both the thick and thin portions, the polishing thickness can be easily managed.
[0024]
In addition, since the first and second CMP monitor mask patterns are formed in the scribe-corresponding region, the CMP monitor pattern is formed in the scribe region by using the mask according to this design method. Therefore, unlike the case where the CMP monitor pattern is formed in the chip region, there is no problem that the device pattern is obstructed or the chip size is increased to secure the area of the device pattern.
Furthermore, if functional block arrangement information and product type processing information can be used in mask design, only the scribe area needs to be taken into consideration, and the design can be performed independently of the portion corresponding to the chip area.
It is also conceivable to form a large number of CMP monitor mask patterns in the scribe region by forming a large number of CMP monitor mask patterns in the scribe region. However, it is also necessary to form a mask pattern for forming other monitor patterns and inspection patterns in the scribe corresponding area. On the other hand, in the design method of the present invention that suffices to use two CMP monitor mask patterns, interference with the CMP monitor mask pattern when determining the arrangement of these mask patterns can be suppressed.
[0025]
In the present invention, each means extracts a high-density macro area from the functional block arrangement information, divides the scribe corresponding area, and places the first and second CMP monitor mask patterns in the first and second mask areas, respectively. To do. In other words, the mask can be designed so that the first and second CMP monitor patterns are formed in the vicinity of the high-density region expected to remain thick by polishing and the position away from the high-density region. There is no need to perform a preliminary investigation or trial production such as forming a pattern, measuring the film thickness of each part, and determining which CMP monitor pattern to use, and the research and trial production costs can be reduced.
[0026]
In this specification, the product type processing information is information useful for setting the scribe region and the scribe corresponding region, such as the product type, series name, layer name, suffix, chip size, block configuration, and number of arranged chips. The functional block arrangement information is information useful for extracting the high density area and the high density macro area by specifying the layout of each functional block in the chip area and the position of each functional block. For example, design layout data of the chip area, layout information, and the like can be given. Further, the high-density macro region refers to a region corresponding to a high-density region formed on the wafer in the mask pattern, and includes, for example, a region where a mask pattern for forming DRAM is arranged.
[0027]
Yet another solution is to use a computer , Su A wafer comprising a scribe area and a chip area defined by the scribe area. Ha A program for designing a mask pattern for exposure including a CMP monitor mask pattern corresponding to a CMP monitor pattern arranged and measuring a film thickness of a layer to be polished during chemical mechanical polishing, the computer The first means for setting the scribe corresponding area corresponding to the scribe area from the type processing information such as the type, chip size, block configuration, etc., from the functional block arrangement information about the functional blocks formed in the chip area A second means for extracting a high-density macro region corresponding to a high-density region having a pattern density relatively higher than the surroundings, such as a region and a flash memory region, and the set scribe-corresponding region in the vicinity of the high-density macro region Within an area A first mask region located at a position other than the first mask region And located outside the vicinity of the high-density macro area A third means for dividing into a second mask region, and a first CMP monitor mask pattern corresponding to the first CMP monitor pattern are disposed in the first macro region, and a second CMP monitor mask corresponding to the second CMP monitor pattern It is a program that functions as a fourth means for arranging a pattern in the second macro area.
[0028]
According to the program of the present invention, using a computer, the vicinity of the high-density macro area corresponding to the high-density area Within an area In addition, the first CMP monitor mask pattern corresponding to the first CMP monitor pattern is separated from the high density macro region corresponding to the high density region. Outside the vicinity of the high-density macro area Second CMP monitor mask pattern corresponding to the second CMP monitor pattern But It is possible to easily design the mask patterns for exposure arranged respectively.
Therefore, if an exposure mask pattern designed and manufactured using this program is used, the first and second CMP monitor patterns are arranged in the vicinity of and apart from the high-density region. Since the thickness information can be obtained from both the thick and thin portions of the remaining film thickness, the polishing thickness can be easily managed.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIGS. Also in this embodiment, when designing a mask pattern of a photomask using a computer program, the same processing as described above with reference to FIG. However, in the mask pattern design of the photomask, data creation of the process mask pattern 78 is performed as shown in FIGS. That is, first, from the type processing information 61 such as product type, series name, layer name, suffix, chip size, block configuration, number of arranged chips, etc., the scribe corresponding area 82 corresponding to the scribe area in step S62 (see FIG. 2B). ) Is set.
The computer used for this design may have a known configuration, such as a CPU, ROM, RAM, keyboard, screen display device such as a CRT, output device such as a printer or plotter, and a large-capacity storage medium such as a hard disk. Are provided. A system in which a plurality of computers are connected by a communication line can also be used.
[0030]
On the other hand, step S72 is performed using the function block arrangement information 70 that can detect the arrangement of the function blocks, such as the chip area data 71 and the function macro names such as the DRAM macro and the logic macro, and the layout information 72 of the chip area such as the CAD layer. Thus, the DRAM macro area 52 (see FIG. 2A) is extracted from the chip area mask pattern 51. The DRAM macro region 52 is a high-density macro region corresponding to a high-density region having a high pattern density such as wiring or dielectric.
Next, as indicated by a broken line in FIG. 2A, a region near the DRAM macro region 52, specifically, a region within 1000 μm from the end of the DRAM macro region 52 is set as the DRAM macro near region 81. To do. In the DRAM macro region 52, as described above, since the interlayer insulating film after CMP polishing is thickly polished, the DRAM macro vicinity region 81 in the vicinity thereof is also affected by this influence, and the interlayer insulating film after CMP polishing is affected. This is because the thickness of the film is polished to be thick.
[0031]
Next, the DRAM macro vicinity area 81 is overlapped with the scribe corresponding area 82 set in step S 61, and the first mask area 83 that overlaps the DRAM macro vicinity area 81 and the scribe corresponding area 82 that does not overlap the DRAM macro vicinity area 81. Divided into two mask regions 84. Among these, the first mask area 83 is an area located in the vicinity of the DRAM macro area 52, and the second mask area 84 is an area away from the DRAM macro area 52.
[0032]
Thereafter, in step S77, the mask pattern 85 for the first CMP monitor pattern is arranged at an appropriate position in the first mask region 83 based on the process region mask pattern creation reference 76. On the other hand, a mask pattern 86 for the second CMP monitor pattern is also arranged at an appropriate position in the second mask region 84. Further, a mask pattern 55 corresponding to other monitor patterns and inspection patterns, a mask pattern 56 for photomask alignment, and the like are also arranged. Thereby, data of the process area mask pattern 78 is completed. The creation standard 77 includes rules for creating the mask patterns 85 and 86 for the first and second CMP monitors and the other mask patterns 55 and 56 and the arrangement standard for the CMP monitor pattern.
[0033]
The chip area mask pattern 51 (see FIG. 2A) corresponding to the data of the process mask pattern 78 shown in FIG. ) And the data of the mask pattern 79 of the photomask (see FIG. 2C). By using the data of the mask pattern 79, the photomask 80 shown in FIG. 3 is formed. In the photomask 80, the mask pattern 85 for the first CMP monitor pattern is disposed at a position near the DRAM macro area 52, and the mask pattern 86 for the second CMP monitor pattern is disposed at a position away from the DRAM macro area 52. Has been.
Accordingly, when this photomask 80 is exposed and a pattern such as a desired circuit or CMP monitor pattern is sequentially formed on the semiconductor substrate, the first CMP monitor pattern is in the vicinity of the DRAM region, specifically, the DRAM. The second CMP monitor pattern is formed at a position away from the DRAM region within 1000 μm from the end of the region.
[0034]
The relationship between the circuit element and the CMP monitor pattern formed on the semiconductor substrate thus formed and CMP polishing will be described with reference to FIG.
The silicon substrate 101 is divided into a chip region 121 and a scribe region 124 as indicated by a dashed line in the drawing. Among these, the chip area 121 includes a DRAM area 122 and a logic area 123 as functional blocks. Among these, in the DRAM region 122, a large number of transistors 125, wirings and the like which function as word lines of the DRAM after completion are formed densely, and the pattern density is high. In the logic region 123, a plurality of transistors 126, wirings, and the like that function as logic circuits after completion are formed. However, the transistor 126 is arranged more sparsely than the transistor 125 and the like formed in the DRAM region 122, and the pattern density is low. Further, a first CMP monitor pattern 127B and a second CMP monitor pattern 127C are formed in the scribe region 124.
[0035]
The transistors 125, 126 and the like formed in the DRAM region 122 and the logic region 123 are all formed by a known photolithography technique or the like, and the first and second CMP monitor patterns 127B, 127C are The transistors 125 and 126 are formed using the same material at the same time.
These transistors 125 and 126 have a structure in which a gate oxide layer 103, a gate electrode 104, and a SiN film 105 are sequentially laminated, and spacers 108 are formed on both sides thereof. A portion of the upper surface of the silicon substrate 101 sandwiching the gate oxide layer 103 is an n-type drain region 106 and an n-type source region 107. An element insulating film 102 is also formed on a required portion of the upper surface of the silicon substrate 101. Accordingly, the first and second CMP monitor patterns 127B and 127C also have a three-layer structure, are made of the same material as the gate oxide layer 103, the gate electrode 104, and the SiN film 105, and the height from the top surface of the silicon substrate 101 is the transistors 125 and 126. It is set to 250 μm, which is substantially the same as that of the above.
[0036]
A PSG film 112 to be polished later is deposited as an interlayer insulating film on the upper surface of the silicon substrate 101 including the transistors 125 and 126 and the first and second CMP monitor patterns 127B and 127C to a thickness of about 600 μm. As shown by a two-dot chain line in FIG. 4, the PSG film 112 after deposition is relatively high in the DRAM region 122 having a high pattern density and its vicinity, and in the logic region 123 having a low pattern density and its vicinity, The height is reduced except for the portion where the transistor 126 is located below. That is, in the DRAM region 122, the height of the PSG film 112 from the surface of the silicon substrate 101 is about 850 μm (= 250 + 600), but in the logic region 123, the height of the PSG film 112 is about 600 μm except for a part. .
[0037]
Thereafter, the above-described CMP method is used for CMP to planarize the PSG film 112. In CMP polishing, since polishing proceeds from a high portion of the PSG film 112 at the beginning of polishing, when the intermediate state is viewed, as shown by a broken line in the figure, many high portions are polished and the height is averaged (flattened). Is done. However, as the polishing progresses, the influence of the pattern density of the transistors 125, 126, etc. under the PSG film 112 becomes dominant as described above. As the polishing progresses further, as shown by the solid line. That is, in the DRAM region 122 having a high pattern density and in the vicinity thereof, the PSG film 112 is relatively thick and the film thickness is increased. On the other hand, in the logic region 123 having a low pattern density and in the vicinity thereof, the height is relatively low, and the thickness of the PSG film 112 is thin.
[0038]
However, in the present embodiment, the first CMP monitor pattern 127B is formed in the vicinity of the DRAM region 122 (left side in the drawing), specifically, in the scribe region 124 within 1000 μm from the end of the DRAM region 122. On the other hand, the second CMP monitor pattern 127C is formed in a scribe region 124 at a position away from the DRAM region 122 by 1000 μm or more, specifically, in the vicinity of the logic region 123 (right side in the figure). Therefore, by measuring the film thickness TH1 of the PSG film 112 using the first CMP monitor pattern 127B, it is possible to obtain the film thickness of a relatively thick portion of the PSG film 112 in the chip region 121. On the other hand, if the film thickness TH2 of the PSG film 112 is measured using the second CMP monitor pattern 127C, the film thickness of a relatively thin portion of the PSG film 112 in the chip region 121 can be obtained.
Therefore, by measuring the film thicknesses TH1 and TH2, it is possible to detect a difference in local film thickness and appropriately manage the polishing thickness of the PSG film 112.
The film thickness TH1, TH2, etc. of the PSG film 112 may be measured by a known method such as an optical method.
[0039]
In the above, the present invention has been described with reference to the embodiments. However, the present invention is not limited to the above embodiments, and it is needless to say that the present invention can be appropriately modified and applied without departing from the gist thereof.
For example, the DRAM region is exemplified as the high-density region formed by the chip region. However, it may be a functional block region where the pattern density is high such as a flash memory region and the polishing target layer such as an interlayer insulating film is thickened by CMP polishing. Any of them can be applied.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram illustrating a process for creating process mask pattern data out of mask pattern data of a photomask according to an embodiment.
FIG. 2 is an explanatory diagram showing how photomask mask pattern data is formed using process mask pattern data and chip area data;
FIG. 3 is an explanatory diagram showing an example of a mask pattern of a created photomask.
FIGS. 4A and 4B are explanatory diagrams showing states before and after CMP of an interlayer insulating film formed on an element on a silicon substrate and a CMP monitor pattern. FIGS.
FIG. 5 is an explanatory view showing an outline of polishing by a mechanical chemical polishing method (CMP method).
FIG. 6 is a cross-sectional explanatory diagram for explaining each process of manufacturing a semiconductor device including CMP polishing.
FIG. 7 is an explanatory diagram showing an arrangement of CMP monitor patterns in a conventional semiconductor device.
FIG. 8 is an explanatory cross-sectional view for explaining each process of manufacturing a semiconductor device including CMP polishing.
FIG. 9 is an explanatory diagram showing a method for forming photomask pattern data.
FIG. 10 is an explanatory diagram showing a procedure for creating process pattern data out of photomask pattern data.
[Explanation of symbols]
51 Chip area mask pattern
52 DRAM macro area (high density macro area)
61 Product Processing Information
70 Function block layout information
77 Process area mask pattern creation criteria
80 photomask
81 DRAM macro area
82 Scribe compatible area
83 First mask region
84 Second mask region
86 Mask pattern for first CMP monitor pattern
87 Mask pattern for second CMP monitor pattern
101 Silicon substrate (wafer)
112 PSG film (layer to be polished)
121 chip area
122 DRAM area (high density area)
123 Logic area
123 Scribe area
125, 126 transistor (device pattern)
127 CMP monitor pattern
127B First CMP monitor pattern
127C Second CMP monitor pattern
TH1, TH2 (film to be polished) film thickness

Claims (4)

Of the wafer with a scan Clive region and tip region defined by the scribe area, the chip area to form a device pattern of a semiconductor device, a first step of forming a plurality of CMP monitoring pattern in the scribe region When,
A second step of forming a layer to be polished in the chip region and the scribe region;
A third step of planarizing and polishing the layer to be polished by chemical mechanical polishing while controlling the film thickness of the layer to be polished using the CMP monitor pattern;
A method for manufacturing a semiconductor device comprising:
The chip region includes at least one high-density region having a pattern density relatively higher than the surroundings, such as a DRAM region and a flash memory region,
The CMP monitor pattern is
A first CMP monitor pattern formed in a region near the scribe region and the high-density region;
And a second CMP monitor pattern formed outside the neighboring region which is the scribe region and is separated from the high-density region. A method of manufacturing a semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the first CMP monitor pattern is formed in a range within 1000 μm from the end of the high-density region, and the second CMP monitor pattern is formed in a range exceeding 1000 μm from the end of the high-density region. Scan Clive region and disposed web c and a tip region defined by the scribe region, a chemical mechanical CMP monitor pattern for measuring the film thickness of the polished layer during polishing, CMP monitoring mask corresponding to A mask pattern design method for exposure including a pattern,
A first means for setting a scribe corresponding area corresponding to the scribe area from the type processing information such as type, chip size, block configuration,
A second high-density macro region corresponding to a high-density region having a pattern density relatively higher than the surroundings, such as a DRAM region and a flash memory region, is extracted from the functional block arrangement information on the functional blocks formed in the chip region. Means,
The set the scribe corresponding regions, a first mask region located within the region near the high-density macro area, be other than the first mask region, located outside the proximity region of the high-density macro area A third means for dividing the second mask region into a second mask region;
A first CMP monitor mask pattern corresponding to the first CMP monitor pattern is disposed in the first mask region, and a second CMP monitor mask pattern corresponding to the second CMP monitor pattern is disposed in the second mask region. Means,
A method for designing a mask pattern comprising: A computer, is arranged web c and a tip region defined scan Clive region and the scribe region, a chemical mechanical polishing during CMP monitor pattern for measuring the film thickness of the polished layer, corresponding to the CMP A program for designing a mask pattern for exposure including a mask pattern for monitoring,
The computer
A first means for setting a scribe corresponding area corresponding to the scribe area from the kind processing information such as kind, chip size, block configuration,
A second high-density macro region corresponding to a high-density region having a pattern density relatively higher than the surroundings, such as a DRAM region and a flash memory region, is extracted from the functional block arrangement information on the functional blocks formed in the chip region. means,
The set the scribe corresponding regions, a first mask region located within the region near the high-density macro area, be other than the first mask region, located outside the proximity region of the high-density macro area A third means for dividing into a second mask region, and
A first CMP monitor mask pattern corresponding to the first CMP monitor pattern is disposed in the first macro area, and a second CMP monitor mask pattern corresponding to the second CMP monitor pattern is disposed in the second macro area. means,
Program to function as.

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