JP2000077524A - Pattern formation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pattern formation method, wherein a pattern interval is shortened while maintaining a contact hole to a minimum pattern size. SOLUTION: This method comprises a process where a second inter-layer insulating film 6 which is thinner than a first inter-layer insulating film 1 is deposited on the first inter-layer insulating film 1, a process where a second resist film 7 thinner than the first resist film 3 is formed on the second inter- layer insulating film 6, while a contact hole pattern 7a is formed using a mask wherein a pattern size is reduced with the same pattern arrangement as when a contact hole pattern 3a of the first resist film 3 is formed, a process where a second contact hole 8 is formed at the second inter-layer insulating film 6 by a dry-etching with the second resist film 7 as a mask, and a process where a conductive material 9 is filled in the second contact hole 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern forming method required in a semiconductor device manufacturing process.
The present invention relates to a pattern forming method used when another interlayer insulating film is deposited on an interlayer insulating film in which a contact hole is formed, and a contact hole is formed also in the another interlayer insulating film. The contact holes here include so-called wiring grooves, and are not limited to contact holes in a narrow sense.

[0002]

2. Description of the Related Art Conventionally, in order to realize a multilayer wiring structure in a semiconductor device, a pattern forming method described below with reference to a process sectional view shown in FIG. That is, in this case, the film thickness is 5
A silicon oxide film 21, which is an interlayer insulating film having a thickness of about 00 nm, is deposited on the semiconductor substrate 22 by a CVD method, and is spin-coated on the silicon oxide film 21 to a thickness of 7 nm.
After a resist film 23 having a thickness of about 00 nm is formed, a contact hole pattern 23a is formed in the resist film 23 by employing a lithography technique (see FIG. 4A).

Subsequently, contact hole patterns 23
A contact hole 24 is formed in the silicon oxide film 21 by dry etching using the resist film 23 on which a is formed as a mask, and the resist film 23 is ashed and removed. Embedding a conductive material 25 such as Cu into 24 is performed (see FIG. 4B). The conductor material 2
At the time of embedding 5, for example, a Cu film is formed on the silicon oxide film 21 by the CVD method, and the CMP (Che) is formed.
The removal of the Cu film is performed while leaving Cu only in the contact hole 24 by employing a mechanical mechanical polishing method.

Next, a silicon oxide film 26, which is an interlayer insulating film having a thickness of about 400 nm, is deposited on the silicon oxide film 21 by the CVD method, and is spin-coated on the silicon oxide film 26 to form a film. After a resist film 27 having a thickness of about 600 nm is formed, a contact hole pattern 27a is formed in the resist film 27 by lithography (FIG. 4C).
reference). Further, the contact hole 28 is formed in the silicon oxide film 26 by dry etching using the resist film 27 in which the contact hole pattern 27a is formed as a mask.
After the resist film 27 is ashed and removed, a conductive material 29 such as Cu is buried in the contact hole 28 of the silicon oxide film 26, thereby realizing a multilayer wiring structure (FIG. 4). (D)).

[0005]

In a conventional pattern forming method, a contact hole is formed in a silicon oxide film as an interlayer insulating film by dry etching using a resist film on which a contact hole pattern is formed as a mask. In this case, the resist film needs to have a thickness corresponding to the etching amount of the silicon oxide film. That is, if the thickness of the interlayer insulating film is small, the thickness of the resist film is small, and if the thickness of the interlayer insulating film is large, the thickness of the resist film is large. In order to form a proper resist pattern, it is important to secure a sufficient depth of focus by the thickness of the interlayer insulating film in which the contact hole is formed. The minimum pattern size (diameter) of the contact hole that can secure a sufficient depth of focus is different depending on the thickness of the resist pattern. The smaller the resist pattern thickness, the smaller the pattern size. (Resolution).

On the other hand, when the patterns of the lower layer and the upper layer are overlapped with each other, that is, the contact hole located on the lower side and the contact hole located on the upper side are misaligned at the time of overlapping. It is necessary to set the overlay margin in consideration of the variation in the pattern size and the pattern interval, that is, the pattern interval, which is the interval between the contact holes formed in one interlayer insulating film and adjacent to each other. In order to reduce the size, for example, the pattern size of the lower contact hole may be reduced. However, in practice, the pattern size of the contact holes that can be formed is limited, so that the pattern spacing is also limited at present.

The present invention has been made in view of these disadvantages, and an object of the present invention is to provide a pattern forming method capable of reducing a pattern interval while making a contact hole a minimum pattern size.

[0008]

According to a first aspect of the present invention, there is provided a pattern forming method comprising: depositing a first interlayer insulating film on a semiconductor substrate; and forming a first resist on the first interlayer insulating film. A step of forming a contact hole pattern by forming a film, a step of forming a first contact hole in the first interlayer insulating film by dry etching using the first resist film as a mask, and a step of forming the first contact hole Burying a conductive material in the first interlayer insulating film, depositing a second interlayer insulating film thinner than the first interlayer insulating film on the first interlayer insulating film, A second resist film having a small thickness is formed on the second interlayer insulating film, and the contact is formed using a mask having the same pattern arrangement and reduced pattern size as when forming the contact hole pattern of the first resist film. hole Forming a turn, first by dry etching using the second resist film as a mask 2
Forming a second contact hole in the second interlayer insulating film, embedding a conductive material in the second contact hole, and depositing a third interlayer insulating film on the second interlayer insulating film; A step of forming a third resist film on the third interlayer insulating film to form a contact hole pattern; and a step of forming a third contact on the third interlayer insulating film by dry etching using the third resist film as a mask. The method is characterized by including a step of forming a hole and a step of embedding a conductive material in the third contact hole. The pattern forming method according to a second aspect of the present invention is the method according to the first aspect, and when forming a contact hole pattern in the second resist film, forming a contact hole pattern in the first resist film. It is characterized in that the pattern size is reduced by using a mask that is sometimes used and reducing the exposure amount.

According to the above method, a second interlayer insulating film having a thickness smaller than that of the first interlayer insulating film is deposited on the first interlayer insulating film, and has the same pattern arrangement as the first resist pattern. After forming a second resist pattern having a reduced pattern size on the second interlayer insulating film, a second contact hole is formed in the second interlayer insulating film by dry etching using the second resist pattern as a mask. Therefore, a second contact hole having a smaller pattern size than the first contact hole formed in the first interlayer insulating film is formed in the second interlayer insulating film. In this case, since the overlay margin is increased by the reduction in the pattern size of the second contact hole, the pattern formed on one interlayer insulating film and having the interval between the adjacent contact holes is formed. The interval has been reduced.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a process sectional view showing a former step of a pattern forming method according to the present embodiment, FIG. 2 is a process sectional view showing a subsequent step, and FIG. It is explanatory drawing which is shown schematically. That is, the pattern forming method according to the present embodiment is a method adopted when realizing a multilayer wiring structure in a semiconductor device, and the pattern forming method according to the present embodiment will be described with reference to FIGS. The method is to be described below. In this method, a silicon oxide film 1 as a first interlayer insulating film having a thickness of about 500 nm is
The film is deposited on the semiconductor substrate 2 by the VD method, and is spin-coated on the silicon oxide film 1 to have a thickness of 700 nm to 1 nm.
After the first resist film 3 having a thickness of about μm is formed, a contact hole pattern 3a is first formed in the resist film 3 using lithography technology (FIG. 1A). reference).

Next, a first contact hole 4 is formed in the silicon oxide film 1 by dry etching using the first resist film 3 having the contact hole pattern 3a formed thereon as a mask. Is removed by ashing, and then the contact holes 4 in the silicon oxide film 1 are removed.
, A conductive material 5 such as Cu is embedded (see FIG. 1B). At the time of burying the conductor material 5, for example, a Cu film is formed on the silicon oxide film 1 by the CVD method, and the Cu film is formed while employing the CMP method while leaving Cu only in the contact hole 4. Removal is performed. By the way, the conductor material 5 at this time is not limited to Cu, but may be aluminum, tungsten, or polycrystalline silicon.

Subsequently, the thickness of the silicon oxide film 1 is about 100 nm, which is smaller than that of the silicon oxide
A silicon oxide film 6, which is a second interlayer insulating film having a thickness of about 1/100, is deposited on the silicon oxide film 1 by the CVD method, and is spin-coated on the silicon oxide film 1 to form a film. After forming a second resist film 7 having a thickness of about 150 nm, that is, a resist film 7 thinner than the first resist film 3, a contact hole pattern 7a is formed on the resist film 7 by a lithography technique. Is formed (see FIG. 1C). By the way, these contact hole patterns 7a are
In the formation of the resist film 7, a mask having the same pattern arrangement as that when the contact hole pattern 3 a is formed in the first resist film 3 and having a reduced pattern size is used. That is, at this time, specifically, the mask used to form the contact hole pattern 3a of the first resist film 3 is used as it is, and the pattern size is reduced by reducing the exposure amount. Is done.

Further, a contact hole 8 is formed in the silicon oxide film 6 by dry etching using the resist film 7 on which the contact hole pattern 7a is formed as a mask, and the resist film 7 is removed by ashing. , The contact hole 8 of the silicon oxide film 6
Embedding a conductive material 9 such as u is performed (see FIG. 2A). The conductor material 9 is not limited to Cu, but may be aluminum, tungsten, or the like. Then, subsequently, a silicon oxide film 10 as a third interlayer insulating film having a thickness of about 400 nm is deposited on the silicon oxide film 6 by a CVD method, and is spin-coated on the silicon oxide film 10 by spin coating. After the third resist film 11 having a thickness of about 600 nm is formed, a contact hole pattern 11a is formed in the resist film 11 by employing lithography (FIG. 2 ( b)).

Thereafter, the contact hole pattern 11a
The third contact hole 12 is formed in the silicon oxide film 10 by dry etching using the resist film 11 on which the resist film 11 is formed as a mask, and the resist film 11 is ashed and removed. In addition,
When a conductive material 13 such as Cu is buried in each of the contact holes 12 formed in the silicon oxide film 10, a multilayer wiring structure is realized (see FIG. 2C). In this case, the conductor material 13
Is not limited to Cu, but may be aluminum, tungsten, or polycrystalline silicon.

As described above, in the pattern forming method according to the present embodiment, the first silicon oxide film 1 and the third
A second silicon oxide film 6 having a small thickness is deposited between the silicon oxide film 10 and the contact holes 4 and 12 formed in the silicon oxide film 1 and the silicon oxide film 10.
A contact hole 8 having a smaller pattern size than that of the silicon oxide film 6 is formed.
When such a pattern forming method is adopted, the following advantages are secured. That is, at the time of actual pattern formation, the contact holes 4 and 8 formed in the first and second silicon oxide films 1 and 6 and the contact hole 12 formed in the third silicon oxide film 10 (in FIG.
(It is assumed that the contact hole 12 is a wiring groove.) When the pattern is overlapped with the contact hole 4, 8, and 12, variations in pattern size may occur.

If a displacement occurs during the superposition, the pattern is formed in a state as shown in FIG. 3B becomes defective as shown in FIG. 3B, the silicon oxide film 1
The contact holes (in the drawing, they are wiring grooves) 12 formed in the silicon oxide film 10 overlap both of the contact holes 4 formed adjacent to each other. The body materials 5 are short-circuited. However, as described in the present embodiment, the silicon oxide film 6 is deposited between the silicon oxide film 1 and the silicon oxide film 10, and the contact size of the silicon oxide film 6 is reduced. If the holes 8 are formed, the contact holes (wiring grooves) 12 do not overlap with both of the adjacent contact holes 8 even if a positional shift occurs during superposition, and the conductive material Short-circuiting between the conductor materials 9 via 13 cannot occur.

In the pattern forming method according to the present embodiment, it is assumed that the contact holes 4, 8, and 12 are formed with respect to the silicon oxide films 1, 6, and 10. Includes a so-called wiring groove, and as shown in FIG. 3, any of the contact holes 4, 8, and 12 or all of them may be wiring grooves. It is.

[0018]

As described above, in the pattern forming method according to the present invention, the second interlayer insulating film having a smaller thickness than the first interlayer insulating film is deposited on the first interlayer insulating film. First
Forming a second resist pattern having a reduced pattern size with the same pattern arrangement as that of the second resist pattern on the second interlayer insulating film, and then performing dry etching using the second resist pattern as a mask to form the second interlayer insulating film; Since the second contact hole is formed in the film, the second contact having a smaller pattern size with respect to the second interlayer insulating film than the first contact hole formed in the first interlayer insulating film. A hole is formed. In this case, since the overlay margin is increased by the reduction in the pattern size of the second contact hole, the pattern formed on one interlayer insulating film and having the interval between the adjacent contact holes is formed. The interval has been reduced. As a result, according to the pattern forming method of the present invention, it is possible to reduce the pattern interval while keeping the contact hole to the minimum pattern size, and to reduce the contact hole interval even under the same overlay accuracy. The effect is obtained.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a first step of a pattern forming method according to the present embodiment.

FIG. 2 is a process cross-sectional view showing a latter stage of a pattern forming method according to the embodiment.

FIG. 3 is an explanatory diagram schematically showing a pattern formation state.

FIG. 4 is a process sectional view showing a pattern forming method according to a conventional mode.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first silicon oxide film (interlayer insulating film) 2 semiconductor substrate 3 first resist film 3 a contact hole pattern 4 first contact hole 5 conductive material 6 second silicon oxide film (interlayer insulating film) 7 second Resist film 7a contact hole pattern 8 second contact hole 9 conductive material 10 third silicon oxide film (interlayer insulating film) 11 third resist film 11a contact hole pattern 12 second contact hole 13 conductive material

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 BB01 BB02 BB04 BB18 DD16 DD43 DD65 EE12 FF06 FF21 HH14 HH20 5F033 AA02 AA13 AA29 AA64 AA66 BA02 BA12 BA15 BA17 BA41 CA09 DA02 DA04 DA05 DA32 DA34 DA35 EA33 EA33

Claims (2)

[Claims] A step of depositing a first interlayer insulating film on a semiconductor substrate; a step of forming a first resist film on the first interlayer insulating film to form a contact hole pattern;
Forming a first contact hole in the first interlayer insulating film by dry etching using the first resist film as a mask, embedding a conductive material in the first contact hole, and forming the first interlayer insulating film 2nd thinner than
Depositing an interlayer insulating film on the first interlayer insulating film;
A second resist film having a thickness smaller than that of the first resist film is formed on the second interlayer insulating film, and the pattern size is the same as that of the first resist film when the contact hole pattern is formed. Forming a contact hole pattern using a mask with reduced size, forming a second contact hole in the second interlayer insulating film by dry etching using the second resist film as a mask, Embedding a conductive material in the contact hole;
Depositing a third interlayer insulating film on the second interlayer insulating film, forming a third resist film on the third interlayer insulating film to form a contact hole pattern, Third etching by dry etching using a resist film as a mask
A step of forming a third contact hole in the interlayer insulating film, and a step of embedding a conductive material in the third contact hole. 2. The pattern forming method according to claim 1, wherein, when forming a contact hole pattern in the second resist film, a mask used in forming the contact hole pattern in the first resist film is used. And reducing the pattern size by reducing the amount of exposure.