TWI550697B - Method of manufacturing a semiconductor device and detecting defects thereof - Google Patents

Description

Semiconductor component fabrication and detection method

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device that performs a defect detecting step in a process.

As semiconductor process technology continues to evolve, the size of semiconductor components continues to shrink. In general, in the process of fabricating a semiconductor device, it is necessary to perform a defect detecting step to detect whether the size and pitch of each component in the semiconductor component fall within an allowable range, thereby identifying a possible defective product.

Fig. 1 is a plan view showing a gate structure on a semiconductor substrate. In this process stage, the semiconductor substrate 10 has an active region 12 and an insulating structure 14, wherein the active region 12 is surrounded by the insulating structure 14, and the semiconductor substrate 10 is further provided with gate structures 16, 20, resulting in the gate structure 16, 20 can span the corresponding active area 12. With this design layout, the overlap region of the active region 12 and the gate structures 16, 20 can serve as a carrier flow region for subsequent transistor elements.

It should be noted that the gate structure 16 may cause unexpected defects in the process due to defects in the yellow lithography process and/or the etch process. For example, an unexpected continuation zone, or defect zone 18, may be created between gate structures 16a, 16b that are intended to be separated from each other. This defective region 18 will connect adjacent gate structures 16a, 16b, causing the subsequently fabricated semiconductor component to lose its electrical properties. Therefore, it is necessary to detect and mark this defect area 18 during the process to avoid its phase. The corresponding semiconductor component is misjudged as a good product. However, since the columnar residue 22 is generally present on the semiconductor substrate 10, for example, etching residues generated during the preparation of the gate structures 16, 20, the residue 22 may be severely detected during defect detection. The noise makes it impossible to effectively discriminate the existence of the defective area 18.

Therefore, it is necessary to propose a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device including performing a defect detecting step to solve the above-described inability to discriminate the defect region.

In view of the above, it is necessary to provide a method of fabricating a semiconductor device to overcome the above-described drawbacks of the prior art.

According to an embodiment of the present invention, a method of fabricating a semiconductor device is provided, comprising the following steps. First, a semiconductor substrate is provided on which an element region and a peripheral region are divided. Then, a plurality of first geometric units are formed in the element region, and a plurality of second geometric units are formed in the peripheral region, wherein the critical dimensions of the second geometric units are equal to the critical dimensions of the first geometric units. Thereafter, a dielectric layer is fully deposited to cover each of the first geometric unit and each of the second geometric units. Finally, a plurality of solder pads are formed on the dielectric layer, wherein each solder pad is located directly above the second geometric unit.

10‧‧‧Semiconductor substrate

12‧‧‧Active area

14‧‧‧Insulation structure

16, 20‧‧ ‧ gate structure

16a, 16b‧‧‧ gate structure

18‧‧‧Defect area

22‧‧‧Residues

100‧‧‧Electronic files

102, 104, 106‧‧‧ geometric patterns

106a, 106b‧‧‧ geometric patterns

108‧‧‧Separation area

200‧‧‧first mask

202, 204, 206, 216‧‧‧ geometric patterns

210‧‧‧Blocked area

216a, 216b‧‧‧ geometric patterns

218‧‧‧Separation area

230, 330‧‧‧ central area

232, 332‧‧‧ annular area

300‧‧‧second mask

310‧‧‧Rectangular pattern

400‧‧‧Semiconductor substrate

402, 404, 406‧‧‧ first geometry unit

408, 418‧‧‧ spacing

412‧‧‧Residues

414‧‧‧Shallow trench insulation structure

416‧‧‧Second geometry unit

416a, 416b‧‧‧ geometric units

420‧‧ ‧ gate oxide layer

422‧‧‧gate electrode

424‧‧‧ cushion

426‧‧‧mask layer

430‧‧‧Component area

432‧‧‧ surrounding area

510, 512, 514‧‧ dielectric layers

520‧‧‧Contact pads

524‧‧‧Interconnection

526‧‧‧Contact plug

530‧‧‧ solder pad

801, 802, 803, 804, 805, 806 ‧ ‧ steps

910, 912, 914, 916, 918, 920, 922, 924 ‧ ‧ geometric patterns

FIG. 1 is a plan view showing a gate structure on a semiconductor substrate in a conventional semiconductor process.

Figure 2 is a partial plan view of a semiconductor component design layout stored in a computer-readable storage medium in the form of an electronic file.

Figure 3 is a top plan view of a first mask with a geometric pattern.

Figure 4 is a top plan view of a second mask having a block geometry pattern.

Figure 5 is a top plan view of a geometric pattern on a semiconductor substrate.

Fig. 6 is a schematic cross-sectional view taken along line A-A' and tangent to B-B' in Fig. 5.

Fig. 7 is a schematic plan view showing a solder pad formed on a semiconductor substrate.

Fig. 8 is a flow chart showing a method of fabricating a semiconductor device.

Figure 9 is a schematic illustration of various geometric patterns having critical dimensions.

In the following, the details will be described with reference to the drawings, which also form part of the detailed description of the specification, and are described in the manner of the specific examples in which the embodiment can be practiced. The following examples have been described in sufficient detail to enable those of ordinary skill in the art to practice. Of course, other embodiments may be employed, or any structural, logical, or electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included therein are defined by the scope of the accompanying claims.

Fig. 2 is a partial plan view showing the layout of a semiconductor element stored in a computer-readable storage medium (CRSM) in the form of an electronic file. At this stage, the design layout electronic file 100 of the semiconductor component is stored in a suitable computer readable storage medium for subsequent computer processing. As shown in FIG. 2, the design layout of the electronic file 100 mainly corresponds to the element regions in the semiconductor component, so that the internal geometric patterns 102, 104, 106 can have different contours, sizes and spacings to define the circuits. Source/drain, gate, contact plug, interconnect, etc. According to this embodiment, the geometric patterns 102, 104, 106 in the electronic file 100 are used to define the position of the gate structure in the circuit, wherein the geometric pattern 102 corresponds to a strip-shaped extended gate structure; the geometric pattern 104 Corresponding to the L-shaped gate structure; the geometric pattern 106 corresponds to the gate structure disposed in a T-shaped direction. Further, the geometric pattern 106 further includes two sub-geometric patterns 106a, and the geometric patterns 106a, 106b are T-shaped bottom heads. The manner of the heads is opposite to each other such that there is a separation region 108 between the two.

It should be noted that since the contours, sizes and spacings of the geometric patterns 102, 104, 106 are not the same, when the geometric patterns 102, 104, 106 of different contours, sizes and pitches are transferred to the semiconductor substrate via subsequent processes, When the geometric pattern having a smaller pitch is more likely to cause structural defects than the geometric pattern having a larger pitch, for example, this structural defect may be a defect that causes the separation patterns to be interconnected with each other. However, due to the presence of process residues, these defects cannot be effectively detected. Accordingly, the present invention provides a semiconductor device process that can effectively detect such defects to address the above-mentioned deficiencies, which are further detailed below.

Referring also to FIGS. 2 and 8, FIG. 8 is a flow chart showing a method of fabricating a semiconductor device. Next, step 801 is performed to determine a geometric pattern having a critical dimension in the layout pattern, which may also be referred to as a critical geometric pattern. In particular, since the separation regions 108 between the geometric patterns 106a, 106b have smaller dimensions than the other geometric patterns 102, 104, the geometric patterns 106a, 106b are susceptible to process defects in subsequent processes. In this case, the geometric pattern 106a, 106b having a smaller size can be marked for subsequent detection.

Figure 3 is a top plan view of a first mask with a geometric pattern. After the above-described geometric patterns 106a, 106b are marked, the electronic file 100 output can then be fabricated into the first mask 200 to correspondingly form the geometric pattern described above on the first mask 200. Wherein, the first mask 200 can be divided into a central region 230 and an annular region 232, the central region 230 can correspond to an element region of a subsequent semiconductor component, or a core region, and the annular region 232 can correspond to a subsequent semiconductor component. The surrounding area. In particular, the central region 230 will be provided with geometric patterns 202, 204, 206, the contours and relative positions of the geometric patterns 202, 204, 206 corresponding to the contours of the geometric patterns 102, 104, 106 within the electronic archive 100 and Relative position; and the annular area 232 will have There are geometric patterns 216a, 216b and a separation region 218 between them, the contours of the geometric patterns 216a, 216b being contours corresponding to the geometric patterns 106a, 106b within the electronic archive 100 described above. Preferably, the geometric pattern 216 can be arranged as a unit pattern in a periodic manner in each of the block regions 210 in the annular region 232, and the layout pattern in each of the block regions 210 is further periodic. The central area 230 is surrounded to form another periodic arrangement pattern. It should be noted that the outline and size of the geometric pattern 216 will be the same as the outline and size of the geometric pattern 206.

In addition to the photomask 200 described above, the semiconductor process of the embodiment of the present invention also employs other photomasks to form circuit layout patterns at other levels. Figure 4 is a top plan view of a second mask having a block geometry pattern. The second mask 300 also has a central region 330 and an annular region 332, wherein the annular region 332 has a plurality of rectangular patterns 310 disposed along the circumference of the central region 330. Preferably, the rectangular pattern 310 is used to define a solder pad of a peripheral region of the semiconductor device, for example, a solder pad for wire bonding or a flip chip ball grid array (FCBGA). Solder pad. In a subsequent process, a thin metal wire or solder ball may be placed on the solder pad, so that the semiconductor component can be electrically connected to the external circuit through the solder pad.

It should be noted that the positions of the block regions 210 in the first mask 200 preferably correspond to the positions of the rectangular patterns 310 in the second mask 300. In other words, in preparing the first reticle 200, the position of each rectangular pattern 310 in the reticle 300 must be considered, so that the geometric pattern 216 clustered in the first reticle 200 can be rectangular by the second reticle 300. The pattern 310 is covered.

After the reticle 200, 300 is fabricated, a step 802 can be performed to perform a deposition process, a photoresist coating process, a photolithography process, an etch process, and other suitable semiconductor processes to lay out the layout within the first reticle 200. The pattern is correspondingly transferred into the element region on the semiconductor substrate and the peripheral region surrounding the element region to form a plurality of geometric units on the semiconductor substrate. According to this embodiment, the process is a gate structure process, and the steps may include at least: first, sequentially in the semiconductor An oxide layer, a conductive layer, and a cap layer are deposited on the bulk substrate. Thereafter, a photoresist coating and a photolithography process are performed to transfer the layout pattern in the first mask 200 to the photoresist layer above the cap layer to form a patterned photoresist layer. Subsequent to one or more etching processes, the layout pattern in the patterned photoresist layer is transferred into the underlying cap layer to form a patterned cap layer. Then, under the coverage of the patterned cap layer, an etching process is performed to sequentially form the patterned conductive layer and the patterned oxide layer to obtain structures as shown in FIG. 5 and FIG. It should be noted that before the step 802 is performed, a shallow trench isolation structure may be formed in a partial region on the semiconductor substrate, so that the subsequently formed geometric unit can be disposed on the shallow trench isolation structure.

Wherein, the composition of the oxide layer may be selected from ruthenium oxide or a high-k dielectric layer containing a transition element, which may serve as a gate oxide layer of a subsequent gate structure. The composition of the conductive layer may be selected from a polysilicon layer or other suitable semiconductor conductive material that may serve as a gate electrode layer for a subsequent gate structure. The composition of the cap layer may be selected from the group consisting of tantalum nitride, hafnium oxynitride, tantalum carbide or other suitable dielectric materials as an etch mask for the etching process.

Fig. 5 is a schematic plan view showing a geometric pattern on a semiconductor substrate, and Fig. 6 is a schematic cross-sectional view taken along line A-A' and tangent to B-B' in Fig. 5. After passing through the semiconductor process described above, at least the shallow trench isolation structure 414, the first geometry units 402, 404, 406 and the second geometry unit 416 are disposed on the semiconductor substrate 400. The first geometric units 402, 404, 406 and the second geometric unit 416 are disposed within the component region 430 and the peripheral region 432, respectively, and may be gate structures. The gate structure includes a gate oxide layer 420, a gate electrode 422, a pad layer 424, and a mask layer 426 from bottom to top, but is not limited thereto. It should be noted that since the semiconductor substrate 400 is preferably a die, it can be separated from other peripheral grains of the periphery by a subsequent cutting process. In this case, the peripheral region 432 described above may be surrounded by the scribe lane region such that the second geometry unit 416 may be disposed between the scribe lane region and the component region 430.

Further, the contours of the first geometric unit 402, 404, 406 correspond to the contours of the geometric patterns 202, 204, 206 within the first reticle 200; and the contour of the second geometric unit 416 corresponds to the first reticle The outline of the geometric pattern 216 within 200. Moreover, the first geometry unit 406 and the second geometry unit 416 on the semiconductor substrate 400 will have the same profile and dimensions, and each of them includes sub-geometry units 406a, 406b and sub-geometry units 416a, 416b. In this case, the head-to-head spacing 408 of the last geometry cells 406a, 406b of the semiconductor substrate 400 is preferably the same as the head-to-head spacing 418 of the last geometry cells 416a, 416b of the semiconductor substrate 400. In other words, the critical dimension of each first geometric unit 406 is equal to the critical dimension of each second geometric unit 416.

Next, a defect detection step is performed to determine if the sub-geometry units 406a, 406b within the component region 430 have defects, such as detecting whether the sub-geometry cells 406a, 406b are all separated from each other and/or fall within the process tolerance. However, since the residue 412 generated by the previous polishing or etching process remains on the semiconductor substrate 400 at this time, for example, a rod-shaped etching residue is present, the residue 412 may generate a high-intensity interference signal during the defect detection process. The detection instrument is rendered incapable of effectively determining the contour and/or spacing of the sub-geometry units 406a, 406b within the component region 430.

In contrast, for the sub-geometry units 416a, 416b located in the peripheral region 432, the design layout can generate a strong detection signal to the detecting instrument without being left to be retained due to the dense periodic arrangement of the lines. The noise generated by object 412. In addition, since the critical dimension between each geometric unit 416a, 416b on the semiconductor substrate 400 is equal to the critical dimension of each geometric unit 406a, 406b, the step 803 can be selectively performed on the peripheral region 432. Geometry units 416a, 416b perform defect detection as a basis for determining whether the contours and/or spacing of sub-geometry units 406a, 406 within component region 430 have reached process requirements. If the sub-geometric cells 416a, 416b within the peripheral region 432 have defects, such as interconnect defects of adjacent gate structures, then step 804 is performed to mark the sub-geometry cells 416a, 416b containing the defects. Thereafter, the semiconductor substrate 400 can be selectively etched again to ensure adjacent regions within the component region 430. The gate structures can be separated from one another. In addition, after the defect is marked, the etching process can be selectively stopped, and only the message is recorded in the database for subsequent detection steps.

Thereafter, an ion implantation process may be performed under the coverage of the first geometric unit 402, 404, 406 and the second geometric unit 416 to form a plurality of doped regions in the semiconductor substrate 400 to serve as a source/drain of the semiconductor device. region.

Fig. 7 is a schematic plan view showing a solder pad formed on a semiconductor substrate. Next, performing step 805, dielectric layers 510, 512, 514 may be deposited on the semiconductor substrate 400 to cover the first geometric units 402, 404, 406 and the second geometric unit 416, and the dielectric layers 510, 512, 514 Contact pads 520, interconnects 524, and/or contact plugs 526 can be provided. It should be noted that since the above process does not remove the residue 412 located in the element region 430, the residue 412 may also be covered by the dielectric layers 510, 512, 514.

Thereafter, in step 806, a metal deposition process is performed to form a metal layer on the dielectric layer 514. Following the photolithography and etching process, the rectangular pattern 310 of the second mask 300 is transferred into the metal layer to form a plurality of solder pads 530 on the dielectric layer 514. Since the position of the rectangular pattern 310 in the second mask 300 corresponds to the position of the geometric pattern 216 in the first mask 200, the solder pads 530 defined by the rectangular pattern 310 are correspondingly disposed on the semiconductor substrate 400. Directly above each geometry unit 416.

When solder pads 530 are formed, contact pads 520, interconnects 524, and/or contact plugs 526 are disposed between solder pads 530 and geometry unit 416. It should be noted that since the geometry unit 416 is preferably disposed on the shallow trench isolation structure 414 and it is not electrically connected to the contact pad 520, the interconnect 524, the contact plug 526, and the solder pad 530, the geometry unit 416 Still at one time Electric floating state. In this case, even if the geometry unit 416 is disposed within the peripheral region 432, it does not affect the electrical function of the final semiconductor component.

Finally, after the solder pads 530 and subsequent processes are completed, the dicing around the semiconductor substrate 400 can be diced to form dies. It should be noted that since the geometric unit 416 for detecting in this embodiment is not fabricated in the dicing street, the dielectric layer 510, 512, 514 in the adjacent peripheral region 432 is not peeled off during the cutting process. Therefore, the yield of the process can be increased.

In accordance with the above-described embodiments, a method of fabricating a semiconductor device including a sensing process is provided that can be generated relative to the geometric pattern 406 within the component region 430 since the geometric pattern 416 within the peripheral region 432 exhibits a dense periodic arrangement. The detection signal of the prior art is overcome by the strong detection signal and the use of the solder pad with less interference factors and higher defect detection sensitivity.

It should be noted that the geometric pattern 406 having a critical dimension is not limited to the T-shaped sub-geometric patterns 406a/406b described above, but may have other contours as well. Figure 9 is a schematic illustration of various geometric patterns having critical dimensions. As shown in FIG. 9, the sub-geometric pattern within the geometric pattern may include lateral or longitudinal T-shaped sub-geometric patterns 910, 916; transverse or longitudinal curved comb-like sub-geometric patterns 918, 912, 914; lateral or longitudinal rectangular combs Secondary geometric patterns 922, 920; or convex sub-geometric patterns 924. Therefore, different contour geometric patterns can be formed in each of the block regions 410 of the peripheral region 432, for example, a lateral T-shaped sub-geometric pattern 910 is formed in the block region, and a longitudinal arc comb-like sub-geometry is formed in the other block region. Pattern 912 is used to simultaneously monitor corresponding geometric patterns within component region 430.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

801, 802, 803, 804, 805, 806 ‧ ‧ steps

Claims (14)

A method of fabricating and detecting a semiconductor device, comprising: providing a semiconductor substrate including an element region and a peripheral region; forming a first geometric unit on the semiconductor substrate in the device region; and the semiconductor in the peripheral region Forming a plurality of second geometric units on the substrate, wherein a critical dimension of each of the second geometric units is equal to a critical dimension of the first geometric unit, wherein the first geometric unit and each of the second geometric units are formed The method includes: sequentially depositing an oxide layer, a conductive layer and a cap layer on the semiconductor substrate; and performing an etching process to sequentially pattern the cap layer, the conductive layer and the oxide layer; An electric layer to cover both the first geometric unit and each of the second geometric units; forming a solder pad on the dielectric layer, wherein the solder pad is located directly above the second geometric units; The second geometry unit performs a defect detection. A method of fabricating and detecting a semiconductor device according to claim 1, wherein the peripheral region surrounds the component region. The method of fabricating and detecting a semiconductor device according to claim 1, wherein the first geometric unit and each of the second geometric unit respectively comprise a plurality of sub-geometric units. The method of fabricating and detecting a semiconductor device according to claim 3, wherein each of the geometric units has a separation region, and the size of each of the separation regions corresponds to the critical dimension. The method of fabricating and detecting a semiconductor device according to claim 1, wherein the first geometric unit has an outer contour identical to an outer contour of each of the second geometric units. The method of fabricating and detecting a semiconductor device according to claim 1, wherein when the first geometric unit and each of the second geometric units are formed, an etching residue is simultaneously formed on the semiconductor substrate. The method of fabricating and detecting a semiconductor device according to claim 6, wherein the etching residue is covered by the dielectric layer. The method of fabricating and detecting a semiconductor device according to claim 1, wherein the first geometric unit is a gate structure. The method of fabricating and detecting a semiconductor device according to claim 1, further comprising: performing an ion implantation process under the cover of the first geometric unit to form a plurality of doped regions in the semiconductor substrate. The method of fabricating and detecting a semiconductor device according to claim 1, wherein each of the second geometric units is in an electrically floating state. The method of fabricating and detecting a semiconductor device according to claim 1, before performing the forming of the dielectric layer, further comprising performing a detecting step to determine whether a pattern outline of each of the second geometric units is within a process tolerance. The method of fabricating and detecting a semiconductor device according to claim 1, wherein the peripheral region comprises a block-shaped region, and the second geometric cells are periodically arranged in the block region. The method of fabricating and detecting a semiconductor device according to claim 1, further comprising: forming a shallow trench isolation structure on the semiconductor substrate; The second geometric units are formed on the shallow trench insulation structure. The method of fabricating and detecting a semiconductor device according to claim 1, further comprising a scribe line surrounding the peripheral region.