JPH10125681A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform planarization, while preventing excessive insertion of a dummy pattern into an interlayer formed on an interconnection pattern having random steps by polishing, prior to polishing, a second layer under specified state of occupation area of a first layer and the occupation area of protrusions on the surface of a second patterned layer covering the first layer. SOLUTION: SiO2 11 is deposited on an Si wafer 10, and then Al 12 and TiN 13 are deposited sequentially thereon to form a conductive layer. Subsequently, an interconnection 14 is formed on the TiN 13 of the TiN 13, and the Al 12 and SiO2 15 is deposited on the entire surface. Consequently, protrusions 16 are generated on the surface of the SiO2 15 and steps appear on the SiO2 15. Planarization is then performed by polishing the interlayer by CMP method on condition that the occupation area of protrusions existing in the range of 1mm×1mm at an arbitrary point of an interlayer on the surface of interlayer is 60% or above, prior to polishing and the occupation area of a plurality of first interconnections is 60% or below.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of flattening a surface of a semiconductor device provided with a multi-layer wiring by interposing an interlayer insulating film.

[0002]

2. Description of the Related Art Hitherto, in order to electrically connect elements formed on a Si wafer, wiring mainly made of Al, W, Si or the like has been used. As a method of forming the wiring, a positive resist is applied on an Al film formed by a sputtering method by a spin coating method, a mask pattern is formed by a photolithographic method, and then a pattern space portion is formed by anisotropic etching (RIE). Of Al is generally removed.

Further, an interlayer film is deposited on a wiring, and another wiring is formed on the interlayer film, thereby enabling a multilayer wiring. Further, in order to prevent a short circuit between wirings, the interlayer film needs to be an insulator, and usually, SiO ₂ or the like is used.

[0004] As a method of forming this SiO ₂ film, Si
There is a method of thermally oxidizing a substrate, a chemical vapor deposition (CVD) method using a gas such as monosilane (SiH ₄ ) or tetraethoxysilane (TEOS) as a raw material, and the like.

The thickness of a wiring used in a semiconductor device is generally about 0.4 to 0.8 μm. Therefore, when an interlayer film is formed, a step of a convex portion occurs in the interlayer film on the wiring, and the height thereof is generally equivalent to the film thickness of the wiring at the maximum (0.4 to 0.8).
μm).

On the other hand, with the high integration of semiconductor devices, the design of wiring and contacts has become on the order of submicrons, and the margin of focus for securing the pattern resolution in the photolithographic method is the flatness of the interlayer film under the wiring. The smaller is the larger. In particular, in the case of a multilayer wiring, the flatness in the upper layer is obtained by adding the flatness of each layer.

In order to connect the upper and lower wirings of the interlayer film with each other, a contact hole is previously opened in the interlayer film, a conductive material, for example, W is formed on the lower wiring, and the contact hole is buried. In addition, a method of removing excess conductive material on an interlayer film is often used.

However, in the above method, when the thickness of the interlayer film varies and the flatness is impaired, the respective depths are different when a plurality of contact holes are opened by RIE. Etc. may be over-etched and suffer processing damage. Further, since the depth of the contact hole is different, a difference occurs in the thickness of W to be removed on the interlayer film at the stage of forming W, and W on the interlayer film tends to remain without being completely removed. It is necessary to consider the variation of the interlayer film thickness in all the semiconductor elements in the Si wafer and between the wafers.
It is preferable that the difference in interlayer film thickness of one semiconductor element, that is, the flatness of the interlayer film be 0.2 μm or less.

Conventionally, as a method of flattening the unevenness of the interlayer film, a method of flattening the film by using a PSG or BPSG film as the interlayer film and then melting the film at a high temperature, or a method of anisotropic dry etching ( A method for improving the flatness by applying a resist for masking (RIE) and selectively removing only the protrusions having a reduced resist film thickness by RIE on the entire surface (resist etch back method); (Chemical Mechanical Poli)
shing) method.

Among these methods, the method of melting the PSG or BPSG film at a high temperature or the resist etch-back method uses the unevenness of the surface of the interlayer film formed by the wiring pattern under the interlayer film (hereinafter, this unevenness is referred to as a local step). It cannot be completely flattened.

FIG. 8 shows a process for flattening by such a method. FIG. 8 (a) shows a state before flattening, and FIG. 8 (b) shows a state after flattening. I have. Reference numeral 20 denotes an Si wafer, reference numeral 21 denotes an insulating film, reference numeral 22 denotes a lower wiring, reference numeral 23 denotes an interlayer film made of a PSG or BPSG film, and reference numeral 24 denotes a projection on the surface of the interlayer film. As shown in FIG. 8B, even after flattening, the surface of the interlayer film has some unevenness.

The above-described method of melting a PSG or BPSG film at a high temperature is not preferable because Al is melted when Al is used for wiring. On the other hand, the CMP method can eliminate the local step and perform the flattening. In order to eliminate the local step, the compression elastic modulus of the surface where the polishing pad contacts the interlayer film is set to 40 to 70 MPa.
Is preferable.

When an interlayer film on a wiring pattern is flattened by a CMP method on a semiconductor element (chip) having a wiring pattern of a random size, wiring is performed between the respective patterns in the chip. A state occurs in which the remaining film amount of the upper interlayer film is different (hereinafter, a step caused by this is referred to as a global step).

FIG. 9 shows a flattening step when such a global step occurs. FIG. 9A shows a state before flattening, and FIG. 9B shows a state after flattening. Is shown. 20 is a Si wafer, 21 is an insulating film,
Reference numeral 22 denotes a lower wiring, 23 denotes an interlayer film, and 24 denotes a projection on the surface of the interlayer film.

As shown in FIG. 9B, if there is a portion having a large pattern dimension (wiring width) in the lower wiring,
The global step 25 occurs on the surface of the interlayer film. The size of the global step depends on the amount of elastic deformation of the polishing pad that comes into contact with the interlayer film when planarization is performed by the CMP method, in addition to the difference in the polishing amount between the patterns. It is described in Japanese Patent Application Laid-Open No. 5-285825, for example, that when the stress is constant and the elastic modulus of the polishing pad is large, the amount of elastic deformation of the polishing pad becomes small and the global step becomes small.

However, if the elastic deformation of the polishing pad is too small, the in-plane uniformity of the remaining film amount over the entire Si wafer is deteriorated.
-30 MPa is preferred.

In order to reduce both the local step and the global step as described above, it has been proposed, for example, in Japanese Patent Publication No. 58-33699 and Japanese Patent Application Laid-Open No. 7-164307 to make the polishing pad a two-layer structure. ing.

[0018]

The CMP method is optimal as a process for reducing (flattening) a local step generated in an interlayer film on a wiring pattern. But C
In the MP method, even if the elastic compression ratio of the polishing pad is adjusted, for example, in the case of a logic product in which a circuit is formed with a random wiring pattern, the occupation ratio of the area of the protrusion of the interlayer film on the wiring pattern is reduced. Differently, it is difficult to reduce the global step.

When the interlayer film is planarized by the CMP method, the polishing rate of the interlayer film varies depending on the occupancy of the area of the protrusion of the interlayer film on the wiring pattern. Therefore, in order to optimize the interlayer film thickness after CMP for various products having interlayer films that need to be subjected to CMP and for the layers of each interlayer film,
It is necessary to perform CMP after checking the polishing rate in advance. However, it is not preferable to check the polishing rate for each interlayer film of each product because productivity is poor.

In order to solve the above problem, it is necessary to make the occupation ratio of the area of the convex portion of the interlayer film on the wiring pattern uniform. As a method therefor, there is a method of arranging a dummy pattern in a space portion between wiring patterns. When a wide space exists between random wiring patterns, the elastic deformation of the polishing pad with respect to a load becomes larger than that in a narrow space portion, and the space portion and an interlayer film on an adjacent wiring pattern are easily polished.

On the other hand, when there is no wide space portion and the occupation ratios of the areas of the protrusions of the interlayer film on the wiring pattern are uniform, the global step can be reduced even with a random wiring pattern. Further, when the occupation ratio of the area of the protrusion of the interlayer film on the wiring pattern is made uniform for each interlayer film of each product, the polishing rate of the interlayer film when the interlayer film is planarized by the CMP method becomes constant. .

Further, it is necessary to equalize the occupation ratio of the area of the protrusion of the interlayer film on the wiring pattern for each interlayer film of each product. For example, the occupation ratio of the area of the protrusion of the interlayer film on the wiring pattern at an arbitrary position in the range of 1 mm × 1 mm differs for each product and each interlayer film, and ranges from several% to 100%. Therefore, when making the occupancy rates uniform, the maximum occupancy rate of 10
Preferably, it is adjusted to 0%.

Conventionally, when planarizing an interlayer film on a random wiring pattern by using a CMP method, a method of inserting a dummy pattern so as to fill a space portion has been used. According to this method, the occupation ratio of the area of the convex portion of the interlayer film on the wiring pattern reaches almost 100%, and the global step can be reduced and the polishing rate can be kept constant.

However, in LSI products that require high-speed switching characteristics, the capacitance between the wirings affects the switching speed. For this reason, when a dummy pattern is inserted with a multilayer wiring, the electric capacity between the dummy pattern and the wiring located above or below the dummy pattern becomes large, and excessively inserting the dummy pattern leads to a decrease in switching speed, which is preferable. Absent. In general, semiconductor devices requiring high-speed switching characteristics, such as ASIC and RI
For LSI products such as SC, the occupation ratio of the wiring area at an arbitrary point within the range of 1 mm × 1 mm is 58% or less, and most of the wiring area is 45% or less. It is preferable not to arrange them.

The present invention has been made in consideration of the above-mentioned circumstances, and has as its object to use a polishing pad with an appropriate elastic modulus to form a random wiring pattern having a step of 0.8 μm on a random wiring pattern. An object of the present invention is to provide a method of manufacturing a semiconductor device which can be flattened to a step difference of 0.2 μm or less without excessively inserting a dummy pattern into an interlayer film.

[0026]

According to a method of manufacturing a semiconductor device of the present invention, a first layer having an arbitrary pattern is formed on a semiconductor substrate, and a second layer is formed so as to cover the first layer. A method for manufacturing a semiconductor device, comprising forming and polishing a surface of the second layer using a polishing pad to planarize the second layer, wherein 1 m
In the area of m × 1 mm, the occupation ratio of the area of the convex portion among the irregularities existing on the surface of the second layer before polishing is 60%.
% Or more, and the occupation ratio of the area of the first layer is 60% or more.
%, And polishing the second layer in a state of not more than%.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming a plurality of first wirings having an arbitrary pattern on a semiconductor substrate, and forming an interlayer film so as to cover the plurality of first wirings. A step of flattening the interlayer film by polishing the surface of the interlayer film using a polishing pad, and a plurality of second patterns having an arbitrary pattern on the interlayer film.
Occupying the area of the protrusions of the unevenness existing on the surface of the interlayer film before polishing in a region of 1 mm × 1 mm at an arbitrary position of the interlayer film. The interlayer film is polished in a state where the ratio is 60% or more and the occupation ratio of the area of the plurality of first wirings is 60% or less.

According to the method of manufacturing a semiconductor device of the present invention, a plurality of first wirings having an arbitrary pattern are formed on a semiconductor substrate, and a plurality of first wirings are formed in a space where the plurality of first wirings are not provided. A step of reducing the area occupancy of the first wiring to 60% or less by arranging a dummy pattern; and forming an interlayer film so as to cover the plurality of first wirings, and forming 1 mm at an arbitrary position in the interlayer film. × 1m
a step of making the area occupied by the area of the projections among the irregularities existing on the surface of the interlayer film before polishing in the region of m within 60% or more, and polishing the surface of the interlayer film using a polishing pad And a step of forming a plurality of second wirings having an arbitrary pattern on the interlayer film.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments with reference to the drawings. 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps. Note that the dimensional ratios in the drawings do not always match the actual dimensional ratios.

First, an Si wafer 10 having a diameter of 6 inches
The SiO ₂ film 11 of 0.1μm thickness is formed on the upper, then the Al film 1 on the SiO ₂ film 11 by sputtering
2 and a TiN film 13 were sequentially laminated to form a conductive layer having a thickness of 0.8 μm. Then, an i-line photosensitive positive resist, for example, “IX770” manufactured by Nippon Synthetic Rubber Co., Ltd. is applied on the TiN film 13 by a spin coating method to a thickness of 1 μm. Was formed. further,
Wiring 14 composed of TiN film 12 and Al film 13 was formed by dry etching using this resist pattern as a mask. The width W1 of the wiring 14 at this time is
Was 1 μm (a).

Thereafter, an SiO ₂ film 15 was deposited on the entire surface by CVD using TEOS to which fluorine was added.
At this time, the thickness of the SiO ₂ film 15 is 2 μm,
The thickness of the O ₂ film 15 is set to be 2.5 times as large as the thickness of the lower wiring 14 (b). At this time, as shown in FIG.
_On the surface of the film ₂ , a projection 16 is formed, and the SiO ₂ film 15
Has a step. Then, this step, that is, the convex portion 1
The height of 6 is 0.8 μm, which is the same as the film thickness of the wiring 14.

Next, the wiring 14 is polished by the CMP method.
Convex part 16 existing on the surface of SiO ₂ film 15 formed thereon
(C). Note that another wiring is thereafter formed on the flattened SiO ₂ film 15.

The SiO ₂ film 15 is formed by CVD.
SiO ₂ formed on the side wall side of the wiring 14 when forming
The width of the film (W2 in FIG. 1B) was 0.8 μm.
Therefore, the width (W3 in FIG. 1B) of the protrusion 15 of the SiO ₂ film 15 after forming the SiO ₂ film with respect to the wiring having the width W1 of 1 μm was 2.6 μm.

The polishing pad used for flattening by the CMP method has a structure in which at least two or more kinds of pads having different hardnesses are laminated and adhered in order to eliminate a local step and to maintain in-plane uniformity of a polishing amount. The elastic compression ratio of the polishing pad is 40 to 70 MPa on the polishing surface side, and the elastic compression ratio of the entire laminated and bonded polishing pad is 4 to 30.
Mpa is required. Here, a polishing pad having a two-layer structure having an elastic compression ratio of 48 MPa on the polishing surface side and a total of 16 MPa was used. The thickness of the polishing pad was 1.2 mm on the polishing surface side, and 2.5 mm in total. Further, colloidal silica was used as the abrasive. Also,
The pressing load of the polishing pad on the Si wafer is 300
g / cm ² . Further, the polishing time was set for the Si film formed on the Si wafer by the CVD method using the same TEOS.
The time was set to be equal to the time required for polishing the solid O ₂ film by 0.9 μm.

Here, 1 at an arbitrary position on the Si wafer
Various mask patterns were prepared such that the area occupation ratio of the wiring 14 was 5 to 60% (60% or less) with respect to the area in the range of mm × 1 mm. With respect to a wiring pattern formed on a Si wafer using these mask patterns, a global step with respect to an occupation ratio (%) of an area of a convex portion after formation of an interlayer film in an area of 1 mm × 1 mm at an arbitrary position (Μm) is shown in FIG. Here, the area of the projection after the formation of the interlayer film is 5 to 100%.
And

From these results, it was found that the global step was 0.2 μm or less when the area of the protrusion after forming the interlayer film was 60% or more, but the step was 0.4 μm or more when the area was 5%. That is, in the method according to the present embodiment, the area of the convex portion after the formation of the interlayer film is set to 60% or more within an area of 1 mm × 1 mm at an arbitrary position on the Si wafer, so that 0 The level difference of 0.8 μm could be reduced to 0.2 μm or less after polishing.

As a result, the SiO ₂ film 15 as an interlayer film
After the formation of this, a margin of focus for securing a pattern resolution by a photolithographic method when another wiring (upper wiring) is newly formed on the interlayer film becomes sufficiently large.

Further, when a contact hole is opened in the interlayer film and a conductive material is buried in the lower wiring, there is no risk of processing damage to the lower wiring when the contact hole is opened by RIE, and the opening is formed in the interlayer film. Since the depth of the contact hole becomes uniform, it is possible to prevent the conductor on the interlayer film from remaining without being removed.

Here, as a method of setting the area of the convex portion of the interlayer film after the formation of the interlayer film to 60% or more, it is not always necessary to keep the occupation ratio of the area of the wiring underneath to 60% or more. For example, as shown in FIG.
The space Wb between the wirings is 3 μm
It is assumed that the pattern exists. In this state, FIG.
As shown in (b), when the interlayer film 15 is formed to a thickness of 2 μm by a CVD method using a TEOS gas, the occupation ratio of the area of the lower wiring in the region including the plurality of wirings 14a is 25%. However, the occupation ratio of the area of the protrusion of the interlayer film 15 on the wiring can be set to 65%. Wiring 14a
The reason why the area occupation ratio of the protrusions of the interlayer film 15 is larger than the area occupation ratio is that when the interlayer film 15 is formed, the interlayer film 15 is also excessive on the side wall of the wiring 14a. This is because the protrusions of the interlayer film are formed so that the wiring is apparently thick.

When a wiring pattern having the same 25% occupancy is formed so as to have a space of 30 μm with respect to a wiring width of 10 μm, the interlayer film is formed in the same manner as described above.
Even if the film is formed to a thickness of μm, the occupation ratio of the area of the protrusion of the interlayer film on the wiring is only 29%. in this way,
By subdividing the wiring pattern, the occupancy of the area of the convex portion of the interlayer film on the wiring greatly differs even with the occupancy of the same wiring area. In addition, by arranging the dummy pattern in the space between the wirings, the occupation ratio of the area of the protrusion of the interlayer film on the wiring can be increased. In this case, it is better to make the width of the dummy pattern as small as possible. That is, by arranging a large number of small-width dummy patterns in place of the large-width dummy patterns in the space portion, the occupation ratio of the wiring area in an area of 1 mm × 1 mm at an arbitrary position on the Si substrate is reduced by 60%. % Or less.

As described above, the wiring pattern is subdivided.
By arranging a dummy pattern in a region having no wiring, the occupation ratio of the area of the lower wiring can be reduced to 60% or less. For example, ASIC, RI
It can be applied to LSI products such as SC.

By the way, the occupancy of the area of the convex portion after the formation of the interlayer film is 60 to 100% and 20 to 60% with respect to an arbitrary area of 1 mm × 1 mm on the Si wafer.
When the global step and the polishing rate after CMP were obtained for the two types of masks, the occupancy was 60 to 100%.
In the case of, the result was obtained that the global step was 0.2 μm or less and the polishing rate was 0.4 μm / min. .

From these results, it was found that the global step was as good as 0.2 μm or less even when the occupation ratio of the area of the protrusion after the formation of the interlayer film was 20 to 60% and 60 to 100%. However, as for the polishing rate, the occupancy is 20 to 60.
%, 0.6 μm / min, which is 1.5 times faster than the case of 60 to 100%.

Next, a second embodiment of the present invention will be described. In the method according to the second embodiment, an SOS film formed by a CVD method using TEOS to which fluorine is added is used.
The point that the thickness of the iO ₂ film is 1.5 μm is different from the case of the method according to the first embodiment, and other conditions are the same as those of the method according to the first embodiment. That is, in the method according to the second embodiment, the SiO ₂ film 1
5 is about twice the thickness of the wiring 14 (1.875).
Times). Also in this case, FIG. The same result as in Example 4 was obtained.

Next, a third embodiment of the present invention will be described. In the method according to the third embodiment, using a TEOS without the addition of fluorine is obtained by depositing the SiO ₂ film 15 by the CVD method, the SiO ₂ film thickness, the second It was 1.5 μm as in the method according to the embodiment. Also in this case, FIG. The same result as in Example 4 was obtained. That is, by setting the area of the convex portion after the formation of the interlayer film within an area of 1 mm × 1 mm at an arbitrary position on the Si substrate to 60% or more, the step of 0.8 μm generated before polishing can be reduced after polishing. Could be 0.2 μm or less.

Next, a fourth embodiment of the present invention will be described. The method according to the fourth embodiment is the same as that of the second embodiment except that WSi is used for the wiring 14 and a SiO ₂ film is formed by CVD using BPSG for the interlayer film 15. This is the same as in the case of the method according to.
In this case, the same result as that of FIG. 2 was obtained.

Next, a fifth embodiment of the present invention will be described. In the method according to the fifth embodiment, when arranging the dummy patterns in the spaces between the wirings, as shown in FIG. 4, a large number of 0.6 μm × 0.6 μm square dot-shaped dummy patterns 17 are arranged. Are arranged in a lattice pattern. The distance between adjacent wiring patterns or dummy patterns was set to 3 μm. In the wiring formation mask on which such dummy patterns 17 are arranged, the occupation ratio of the wiring area in an arbitrary area of 1 mm × 1 mm was 9 to 60%. Except that a mask having such a dummy pattern 17 is used, the same conditions as those in the first embodiment are used, and an arbitrary portion of 1 mm × 1 m is used.
When the change of the global step with respect to the occupation ratio of the area of the protrusion in the region of m after the formation of the interlayer film was measured, the same result as that shown in FIG. 2 was obtained. Also, no degradation of the switching characteristics of the device due to insertion of such a dummy pattern was observed.

The method of arranging the dummy pattern 17 is not limited to the above embodiment, but may be a sixth method described below.
An arrangement method as in the above embodiment may be used. In the method according to the sixth embodiment, when arranging a dummy pattern in a space between wirings, as shown in FIG.
A large number of square-dot dummy patterns 17 of m × 0.6 μm are arranged so as to form a row in an oblique direction. Also in this case, the distance between the adjacent wiring pattern or dummy pattern was set to 3 μm. In the wiring formation mask on which such dummy patterns 17 are arranged, the occupation ratio of the wiring area in an arbitrary area of 1 mm × 1 mm was 9 to 60%. Under the same conditions as in the first embodiment except that a mask in which such a dummy pattern is arranged is used.
When the change of the global step with respect to the occupation ratio of the area of the convex portion after the formation of the interlayer film in the area of mm × 1 mm was measured, the same result as that shown in FIG. 2 was obtained. Also, no degradation of the switching characteristics of the device due to insertion of such a dummy pattern was observed.

As shown in FIGS. 4 and 5, a large number of square dot-shaped dummy patterns 17 are arranged, an interlayer film is deposited thereon, and a number of upper-layer linear wirings are further arranged in parallel on the interlayer film. Think about the case of arranging.

FIG. 6A shows that a number of upper-layer linear wirings 19 are arranged in parallel via an interlayer film 18 on a number of square-dot dummy patterns 17 arranged in a grid as shown in FIG. FIG. 6 is a plan view of a pattern in the case where
FIG. 7B is a cross-sectional view along the line VIB-VIB in FIG. When the dummy patterns 17 are arranged in a grid pattern as shown in FIG. 6A, a large number of dummy patterns 17 and interlayer films 18 are formed depending on the wiring intervals of the linear wirings 19 in the upper layer.
, And a wiring 19b which does not overlap the dummy pattern 17 at all is generated. Each wiring 19a that overlaps with the dummy pattern 17 causes capacitive coupling with the dummy pattern 17, so that a signal transmitted on each wiring 19a is affected by these coupling capacitances. However, the wirings 19b that do not overlap with the dummy pattern 17 do not have the above-described capacitive coupling, and thus the signals transmitted on the wirings 19a are not affected at all. That is, when the dummy patterns 17 are arranged in a lattice pattern, there is a possibility that the characteristics of a large number of wirings in the upper layer formed on the interlayer film may be different.

FIG. 7A shows an upper layer of linear wiring on a large number of square dot-shaped dummy patterns 17 arranged in oblique directions as shown in FIG. FIG. 7B is a cross-sectional view taken along the line VIIB-VIIB in FIG. 7A. As shown in FIG. 7A, the angles (elevation angles α, β, γ) between the arrangement direction of the dummy patterns 17 and the extended direction of the wiring 19 are 0 degree and 9 degrees.
It is at an angle other than 0 degrees.

As shown in FIG. 7B, the dummy pattern 1
When the 7s are arranged in a row in an oblique direction, the linear wirings 19 in the upper layer overlap the dummy patterns 17 of substantially the same number via the interlayer film 18 respectively. Therefore, the dummy pattern 1 generated in each wiring 19
7, the value of the capacitive coupling becomes uniform, and the signal transmitted on each wiring 19 is almost equally affected by the coupling capacitance of these equal values. That is, when the dummy patterns 17 are arranged so as to form a row in an oblique direction, the characteristics of the many upper wirings 19 formed on the interlayer film become substantially uniform.

The present invention is not limited to the method of each of the above embodiments, and it goes without saying that various modifications are possible. For example, in the method of each of the above embodiments, the SiO ₂ film 11 is formed on the Si wafer 10, the wiring 14 composed of the laminated film of the Al film 12 and the TiN film 13 is formed thereon, and the coating is further formed thereon. Although the case in which the SiO ₂ film 15 is deposited as the polishing layer has been described, the wiring 14 may be formed of a conductive film containing any one of Al, Si, W, and Ti as a main component. SiO
₂ , an insulating film mainly containing any one of SiN, PI, Si and C may be used.

Further, in the method of each of the above embodiments, the case where the interlayer film formed on the lower wiring is flattened has been described, but this is done by STI (Shallow Trench Isolation).
n) The flattening of the SiO ₂ film and the flattening of W or Al when W or Al is buried in the grooves or holes formed in the SiO ₂ film can be performed.

[0055]

As described above, according to the present invention,
Using a polishing pad with an optimized elastic modulus, a step height of 0.
Even if a dummy pattern is not excessively inserted into an interlayer film on a random wiring pattern of 8 μm, a step of 0.2 μm
A method for manufacturing a semiconductor device that can be planarized to the following can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a characteristic diagram showing a result of measuring a change in a global step with respect to an occupation ratio of an area of a convex portion of an interlayer film in the method according to the first embodiment.

FIG. 3 is a sectional view for explaining the method according to the first embodiment;

FIG. 4 is a plan view showing an arrangement state of dummy patterns by a method according to a fifth embodiment of the present invention.

FIG. 5 is a plan view showing an arrangement state of dummy patterns by a method according to a sixth embodiment of the present invention.

6A and 6B are a plan view and a cross-sectional view showing a positional relationship between the dummy pattern shown in FIG.

FIGS. 7A and 7B are a plan view and a cross-sectional view showing a positional relationship with an upper layer wiring when the arrangement of the dummy patterns shown in FIGS.

FIG. 8 is a cross-sectional view showing a planarization step according to a conventional method.

FIG. 9 is a cross-sectional view showing a planarization step according to a conventional method in which a global step occurs.

[Explanation of symbols]

10 ... Si wafer, 11 ... SiO ₂ film, 12 ... Al film, 13 ... TiN film, 14, 14a ... wire, 15 ... SiO ₂ film, 16 ... protruding portion, 17 ... dummy pattern, 18 ... interlayer film, 19 ... Wiring, 19a: Wiring that overlaps with the dummy pattern, 19b: Wiring that does not overlap with the dummy pattern.

Continuation of front page (72) Inventor Yoshikuni Tateyama 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Inside the Toshiba Yokohama office

Claims (18)

[Claims] 1. A first layer having an arbitrary pattern is formed on a semiconductor substrate, a second layer is formed so as to cover the first layer, and a second layer is formed using a polishing pad. A method for manufacturing a semiconductor device, wherein a surface of a second layer is flattened by polishing a surface, wherein a surface of the second layer before polishing is polished in an area of 1 mm × 1 mm in an arbitrary portion of the second layer. Polishing the second layer in a state where the occupation ratio of the area of the protrusions among the unevenness existing in the area is 60% or more and the occupation ratio of the area of the first layer is 60% or less. A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the pattern of the first layer is subdivided so that the occupation ratio of the area of the first layer is 60% or less and 1 mm × 1 at an arbitrary position of the second layer.
2. The semiconductor device according to claim 1, wherein an occupation ratio of the area of the protrusions among the protrusions and recesses existing on the surface of the second layer before polishing is set to 60% or more in a range of mm. Manufacturing method. 3. The first layer has a space portion, and by arranging a dot-shaped dummy pattern in the space portion, the occupancy of the area of the first layer is 60% or less. 1 mm × 1 m at an arbitrary position of the second layer
2. The semiconductor device according to claim 1, wherein the occupation ratio of the area of the protrusions among the protrusions and recesses existing on the surface of the second layer before polishing is set to 60% or more in the region of m. Manufacturing method. 4. The dot-shaped dummy pattern is arranged in a grid pattern in the space portion.
13. The method for manufacturing a semiconductor device according to item 5. 5. The semiconductor device according to claim 3, wherein said dot-shaped dummy patterns are arranged in said space so as to form a line obliquely to an extension direction of said first layer. Manufacturing method. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the polishing pad has a structure in which at least two or more kinds of pads having different hardnesses are laminated and bonded. 7. The polishing pad according to claim 6, wherein the compression elastic modulus of the polishing pad is 40 to 70 MPa on the polishing surface side, and the compression elastic modulus of the entire polishing pad laminated and bonded is 4 to 30 MPa. Of manufacturing a semiconductor device. 8. The semiconductor device according to claim 1, wherein the first layer is formed of a conductive film containing any one of Al, Si, W, and Ti as a main component. Method. 9. The method according to claim 1, wherein the second layer is made of SiO ₂ , SiN, P
2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed of an insulating film containing any one of I, Si, and C as a main component. 10. A step of forming a plurality of first wirings having an arbitrary pattern on a semiconductor substrate, a step of forming an interlayer film so as to cover the plurality of first wirings, and using a polishing pad. A step of flattening the interlayer film by polishing the surface of the interlayer film; and a step of forming a plurality of second wirings having an arbitrary pattern on the interlayer film; In the area of 1 mm × 1 mm, the occupation ratio of the area of the protrusion among the unevenness existing on the surface of the interlayer film before polishing is 60% or more, and the plurality of first wirings A method of manufacturing a semiconductor device, comprising: polishing the interlayer film in a state where an area occupation ratio is 60% or less. 11. A method of subdividing a pattern of the plurality of first wirings so that an area occupation rate of the plurality of first wirings is 60% or less and 1 mm × 1 mm × 2 mm at an arbitrary position of the interlayer film. 11. The manufacturing method of a semiconductor device according to claim 10, wherein the occupation ratio of the area of the protrusions among the protrusions and recesses existing on the surface of the interlayer film before polishing is set to 60% or more in a region of 1 mm. Method. 12. A plurality of first wirings having an arbitrary pattern are formed on a semiconductor substrate, and the plurality of first wirings are formed.
Arranging a dot-shaped dummy pattern in a space where no wiring is provided to reduce the area occupancy of the first wiring to 60% or less; and forming an interlayer so as to cover the plurality of first wirings. A step of forming a film and making the area occupied by the area of the protrusions among the unevenness existing on the surface of the interlayer film before polishing in an area of 1 mm × 1 mm at an arbitrary position of the interlayer film 60% or more; Polishing the surface of the interlayer film by using a polishing pad to flatten the interlayer film; and forming a plurality of second wirings having an arbitrary pattern on the interlayer film. A method for manufacturing a semiconductor device, comprising: 13. The method according to claim 12, wherein the dot-shaped dummy patterns are arranged in a grid in the space. 14. The device according to claim 12, wherein the dot-shaped dummy patterns are arranged in the space portion so as to form a line obliquely to an extension direction of the first layer.
13. The method for manufacturing a semiconductor device according to item 5. 15. The polishing pad according to claim 1, wherein at least 2
13. The method of manufacturing a semiconductor device according to claim 10, wherein a pad having a structure in which pads of different types or different in hardness are laminated and bonded is used. 16. The polishing pad according to claim 15, wherein the compression elastic modulus of the polishing pad is 40 to 70 MPa on the polishing surface side, and the compression elastic modulus of the entire polishing pad bonded and laminated is 4 to 30 MPa. Of manufacturing a semiconductor device. 17. The method according to claim 17, wherein each of the plurality of first wirings is A
13. The method of manufacturing a semiconductor device according to claim 10, comprising a conductive film mainly containing any one of l, Si, W, and Ti. 18. The method according to claim 18, wherein the interlayer film is made of SiO ₂ , SiN, P
13. The method of manufacturing a semiconductor device according to claim 10, comprising an insulating film containing any one of I, Si, and C as a main component.