JP2012244101A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2012244101A
JP2012244101A JP2011115634A JP2011115634A JP2012244101A JP 2012244101 A JP2012244101 A JP 2012244101A JP 2011115634 A JP2011115634 A JP 2011115634A JP 2011115634 A JP2011115634 A JP 2011115634A JP 2012244101 A JP2012244101 A JP 2012244101A
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bonding
electrode
wiring
junction
semiconductor device
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JP5970747B2 (en
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Keiei Kagawa
恵永 香川
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Sony Corp
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Sony Corp
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Priority to JP2011115634A priority Critical patent/JP5970747B2/en
Application filed by Sony Corp filed Critical Sony Corp
Priority to CN201280021467.3A priority patent/CN103503122B/en
Priority to US14/116,432 priority patent/US9799587B2/en
Priority to KR1020187008423A priority patent/KR102084337B1/en
Priority to KR1020227005881A priority patent/KR102574526B1/en
Priority to EP19167410.0A priority patent/EP3534399A1/en
Priority to KR1020217007969A priority patent/KR102378636B1/en
Priority to EP21217898.2A priority patent/EP4047647A3/en
Priority to PCT/JP2012/062484 priority patent/WO2012161044A1/en
Priority to EP12790013.2A priority patent/EP2717300B1/en
Priority to KR1020207005315A priority patent/KR102235927B1/en
Priority to KR1020237029691A priority patent/KR20230130169A/en
Priority to KR1020137028555A priority patent/KR101952976B1/en
Priority to CN201610307746.6A priority patent/CN105938825B/en
Priority to TW111148764A priority patent/TWI835470B/en
Priority to TW110121515A priority patent/TWI804887B/en
Priority to TW107118686A priority patent/TWI728248B/en
Priority to TW109130275A priority patent/TWI746146B/en
Priority to TW105131747A priority patent/TWI667763B/en
Priority to TW101117629A priority patent/TWI578484B/en
Publication of JP2012244101A publication Critical patent/JP2012244101A/en
Publication of JP5970747B2 publication Critical patent/JP5970747B2/en
Application granted granted Critical
Priority to US15/711,607 priority patent/US10236238B2/en
Priority to US15/945,579 priority patent/US11587857B2/en
Priority to US17/675,902 priority patent/US11626356B2/en
Priority to US18/076,861 priority patent/US11923279B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including a junction interface with higher reliability.SOLUTION: A semiconductor device 100 comprises a first semiconductor part and a second semiconductor part. The first semiconductor part includes a first electrode 16 formed on a surface on the side of a junction interface and extending in a first direction. The second semiconductor part includes a second electrode 26 bonded to the first electrode 16 at the junction interface and extending in a second direction crossing the first direction.

Description

本開示は、半導体装置に関し、より詳細には、製造時に２枚の基板を貼り合わせて配線接合を行う半導体装置に関する。   The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device in which two substrates are bonded at the time of manufacture to perform wiring bonding.

従来、２枚のウエハ（基板）を貼り合わせて、それぞれのウエハに形成された銅配線同士を接合（以下、Ｃｕ−Ｃｕ接合という）する技術が開発されている（例えば、特許文献１参照）。また、従来、このようなＣｕ−Ｃｕ接合技術では、信頼性の高い接合を得るために、様々な技術が提案されている（例えば、特許文献２参照）。   2. Description of the Related Art Conventionally, a technique for bonding two wafers (substrates) and bonding copper wirings formed on the respective wafers (hereinafter referred to as Cu-Cu bonding) has been developed (for example, see Patent Document 1). . Conventionally, in such a Cu—Cu bonding technique, various techniques have been proposed in order to obtain a highly reliable bond (see, for example, Patent Document 2).

通常、Ｃｕ−Ｃｕ接合を行う際、例えば、アライメントずれや接触抵抗の上昇などを抑制するために、大面積のＣｕプレート同士を接合する。しかしながら、各Ｃｕプレートを形成する際には、一般に、Ｃｕプレートの接合面に対してＣＭＰ（化学機械研磨）処理を施す。それゆえ、幅広（例えば５μｍ以上）のＣｕプレートを形成した際には、ＣＭＰ処理によりＣｕプレートの接合面にディッシング（窪み）が発生し易くなる。   Usually, when performing Cu-Cu joining, large-area Cu plates are joined together, for example, in order to suppress misalignment and increase in contact resistance. However, when forming each Cu plate, a CMP (Chemical Mechanical Polishing) process is generally performed on the bonding surface of the Cu plate. Therefore, when a wide (for example, 5 μm or more) Cu plate is formed, dishing (depression) is likely to occur on the bonding surface of the Cu plate by the CMP process.

ここで、図１２に、接合面にディッシングが発生したＣｕプレート同士を接合した際の接合界面付近の様子を示す。なお、図１２には、第１半導体チップ４０１と、第２半導体チップ４０２とをＣｕ−Ｃｕ接合する例を示す。第１半導体チップ４０１の接合パッド４０３の接合面、及び、第２半導体チップ４０２の接合パッド４０４の接合面にディッシングが発生している場合、両者を接合すると、接合界面Ｓｊに気泡等が発生する。この場合、接合界面Ｓｊにおいて、例えば導通不良や接触抵抗の上昇などが発生し、接合性が著しく劣化する可能性がある。   Here, FIG. 12 shows a state in the vicinity of the bonding interface when Cu plates having dishing on the bonding surfaces are bonded to each other. FIG. 12 shows an example in which the first semiconductor chip 401 and the second semiconductor chip 402 are bonded to each other by Cu—Cu. When dishing has occurred on the bonding surface of the bonding pad 403 of the first semiconductor chip 401 and the bonding surface of the bonding pad 404 of the second semiconductor chip 402, bubbles and the like are generated at the bonding interface Sj when both are bonded. . In this case, for example, a conduction failure or an increase in contact resistance may occur at the bonding interface Sj, and the bonding property may be significantly deteriorated.

この問題を解消するため、特許文献２には、接合パッド内に複数の開口を形成することにより、ディッシングの発生を抑制する技術が提案されている。   In order to solve this problem, Patent Document 2 proposes a technique for suppressing the occurrence of dishing by forming a plurality of openings in a bonding pad.

図１３に、特許文献２で提案されている接合パッドの概略上面図を示す。特許文献２で提案されている接合パッド４０５は、プレート状のパッドに複数の矩形状の開口４０６を所定間隔で分散させて形成する。なお、図１３には示さないが、接合パッド４０５の開口４０６内には、絶縁層（誘電体層）が形成される。接合パッド４０５をこのような構成にすることにより、接合パッド４０５内に大面積（幅広）の電極部分が無くなり、ディッシングの発生を抑制することができる。   FIG. 13 shows a schematic top view of the bonding pad proposed in Patent Document 2. As shown in FIG. The bonding pad 405 proposed in Patent Document 2 is formed by dispersing a plurality of rectangular openings 406 at predetermined intervals on a plate-shaped pad. Although not shown in FIG. 13, an insulating layer (dielectric layer) is formed in the opening 406 of the bonding pad 405. With such a configuration of the bonding pad 405, there is no large area (wide) electrode portion in the bonding pad 405, and the occurrence of dishing can be suppressed.

特許第３５３２７８８号明細書Japanese Patent No. 3532788 特開２０１０−１０３５３３号公報JP 2010-103533 A

上述のように、従来、半導体装置の製造手法では、信頼性の高いＣｕ−Ｃｕ接合を得るために、様々な技術が提案されている。しかしながら、この技術分野では、Ｃｕ電極間の接合界面における例えば導通不良や接触抵抗の上昇などの発生をより一層抑制して、より信頼性の高い接合界面を有する半導体装置の開発が望まれている。   As described above, conventionally, various techniques have been proposed for obtaining a highly reliable Cu-Cu junction in a method for manufacturing a semiconductor device. However, in this technical field, there is a demand for the development of a semiconductor device having a more reliable bonding interface by further suppressing, for example, the occurrence of poor conduction or an increase in contact resistance at the bonding interface between Cu electrodes. .

本開示は、上記要望に応えるためになされたものであり、本開示の目的は、製造時に２枚の基板を貼り合わせて配線接合を行う半導体装置において、より信頼性の高い接合界面を得ることである。   The present disclosure has been made to meet the above-described demand, and an object of the present disclosure is to obtain a bonding interface with higher reliability in a semiconductor device in which two substrates are bonded to each other at the time of manufacture to perform wiring bonding. It is.

上記課題を解決するために、本開示の半導体装置は、第１半導体部と、第２半導体部とを備える構成とし、各部の構成を次のようにする。第１半導体部は、接合界面側の表面に形成されかつ第１の方向に延在する第１電極を有する。そして、第２半導体部は、接合界面で第１電極と接合されかつ第１の方向と交差する第２の方向に延在する第２電極を有し、接合界面で第１半導体部と貼り合わせて設けられる。   In order to solve the above problems, a semiconductor device of the present disclosure is configured to include a first semiconductor unit and a second semiconductor unit, and the configuration of each unit is as follows. The first semiconductor portion has a first electrode formed on the surface on the bonding interface side and extending in the first direction. The second semiconductor portion includes a second electrode that is bonded to the first electrode at the bonding interface and extends in a second direction that intersects the first direction, and is bonded to the first semiconductor portion at the bonding interface. Provided.

上述のように、本開示の半導体装置では、接合界面において接合される第１電極の延在方向と第２電極の延在方向とを交差させ、その交差部分に第１電極及び第２電極間の接合領域を形成する。この場合、第１電極及び第２電極間に接合アライメントずれが発生しても、交差部分に形成される第１電極及び第２電極間の接合領域の面積は変動しない。それゆえ、本開示によれば、第１電極及び第２電極間の接合界面における例えば導通不良や配線抵抗の上昇などの発生をより一層抑制することができ、より信頼性の高い接合界面を有する半導体装置を提供することができる。   As described above, in the semiconductor device of the present disclosure, the extending direction of the first electrode and the extending direction of the second electrode that are joined at the joining interface intersect each other, and the first electrode and the second electrode are crossed at the intersecting portion. The junction region is formed. In this case, even if junction misalignment occurs between the first electrode and the second electrode, the area of the junction region between the first electrode and the second electrode formed at the intersection does not change. Therefore, according to the present disclosure, it is possible to further suppress the occurrence of, for example, poor conduction or increase in wiring resistance at the bonding interface between the first electrode and the second electrode, and to have a more reliable bonding interface. A semiconductor device can be provided.

接合アライメントずれの問題を説明するための図である。It is a figure for demonstrating the problem of joining misalignment. 接合アライメントずれの問題を説明するための図である。It is a figure for demonstrating the problem of joining misalignment. 本開示の第１の実施形態に係る半導体装置の各Ｃｕ接合部の概略構成図である。FIG. 3 is a schematic configuration diagram of each Cu bonding portion of the semiconductor device according to the first embodiment of the present disclosure. 第１の実施形態に係る半導体装置における接合界面付近の概略断面図である。1 is a schematic cross-sectional view of a vicinity of a bonding interface in a semiconductor device according to a first embodiment. 第１の実施形態に係る半導体装置のＣｕ−Ｃｕ接合領域の概略構成図である。It is a schematic block diagram of the Cu-Cu junction area | region of the semiconductor device which concerns on 1st Embodiment. 本開示の第２の実施形態に係る半導体装置の各Ｃｕ接合部の概略構成図である。It is a schematic block diagram of each Cu junction part of the semiconductor device which concerns on 2nd Embodiment of this indication. 本開示の第３の実施形態に係る半導体装置の各Ｃｕ接合部の概略構成図である。It is a schematic block diagram of each Cu junction part of the semiconductor device which concerns on 3rd Embodiment of this indication. 第３の実施形態に係る半導体装置のＣｕ−Ｃｕ接合領域の概略構成図である。It is a schematic block diagram of the Cu-Cu junction area | region of the semiconductor device which concerns on 3rd Embodiment. 本開示の第４の実施形態に係る半導体装置（固体撮像素子）の概略構成断面図である。It is a schematic structure sectional view of a semiconductor device (solid imaging device) concerning a 4th embodiment of this indication. 変形例１のＣｕ−Ｃｕ接合領域の概略構成図である。It is a schematic block diagram of the Cu-Cu junction area | region of the modification 1. 本開示の半導体装置（固体撮像素子）を適用した電子機器の一例を示す図である。It is a figure which shows an example of the electronic device to which the semiconductor device (solid-state image sensor) of this indication is applied. 従来のＣｕ−Ｃｕ接合におけるディッシングの影響を説明するための図である。It is a figure for demonstrating the influence of the dishing in the conventional Cu-Cu junction. 従来の接合パッドの概略上面図である。It is a schematic top view of the conventional bonding pad.

以下に、本開示の実施形態に係る半導体装置の具体例を、図面を参照しながら下記の順で説明する。ただし、本開示は下記の例に限定されない。
１．第１の実施形態
２．第２の実施形態
３．第３の実施形態
４．第４の実施形態
５．各種変形例及び応用例 Hereinafter, specific examples of the semiconductor device according to the embodiment of the present disclosure will be described in the following order with reference to the drawings. However, the present disclosure is not limited to the following example.
1. First Embodiment 2. FIG. Second Embodiment 3. Third Embodiment 4. Fourth embodiment 5. Various modifications and application examples

＜１．第１の実施形態＞
まず、上記特許文献２で提案されているような接合パッドを用いた場合に起こり得る接合アライメントずれの問題について、図１、並びに、図２（ａ）及び（ｂ）を参照しながら簡単に説明する。なお、図１は、上記特許文献２で提案されている接合パッドと同様の構成を有する接合パッドを備えたＣｕ接合部の概略斜視図である。また、図２（ａ）は、接合アライメントずれが無い場合の接合界面Ｓｊ付近の概略断面図であり、図２（ｂ）は、接合アライメントずれが有る場合の接合界面Ｓｊ付近の概略断面図である。 <1. First Embodiment>
First, the problem of bonding misalignment that may occur when using a bonding pad as proposed in Patent Document 2 will be briefly described with reference to FIGS. 1 and 2A and 2B. To do. FIG. 1 is a schematic perspective view of a Cu bonding portion provided with a bonding pad having the same configuration as the bonding pad proposed in Patent Document 2. 2A is a schematic cross-sectional view in the vicinity of the bonding interface Sj when there is no bonding alignment deviation, and FIG. 2B is a schematic cross-sectional view near the bonding interface Sj when there is a bonding alignment deviation. is there.

第１Ｃｕ接合部５１０は、複数の開口部５１２が形成された第１接合パッド５１１を有する。一方、第２Ｃｕ接合部５２０は、複数の開口部５２２が形成された第２接合パッド５２１を有する。なお、ここでは、第１Ｃｕ接合部５１０と第２Ｃｕ接合部５２０とは同じ構成であり、接合パッド及び開口部のサイズは同じとする。   The first Cu bonding portion 510 has a first bonding pad 511 in which a plurality of openings 512 are formed. On the other hand, the second Cu bonding portion 520 includes a second bonding pad 521 in which a plurality of openings 522 are formed. Here, the first Cu joint 510 and the second Cu joint 520 have the same configuration, and the size of the joint pad and the opening is the same.

また、第１Ｃｕ接合部５１０は、ビア５０３を介して第１Ｃｕ配線５０１に電気的に接続され、第２Ｃｕ接合部５２０は、ビア５０４を介して第２Ｃｕ配線５０２に電気的に接続される。なお、第１接合パッド５１１の開口部５１２内、及び、第２接合パッド５２１の開口部５２２内には、それぞれ、絶縁膜５１３及び絶縁膜５２３が形成される。   In addition, the first Cu bonding portion 510 is electrically connected to the first Cu wiring 501 through the via 503, and the second Cu bonding portion 520 is electrically connected to the second Cu wiring 502 through the via 504. Note that an insulating film 513 and an insulating film 523 are formed in the opening 512 of the first bonding pad 511 and in the opening 522 of the second bonding pad 521, respectively.

図１に示す構成の第１Ｃｕ接合部５１０と第２Ｃｕ接合部５２０との間において、接合アライメントずれが無い場合、図２（ａ）に示すように、第１接合パッド５１１及び第２接合パッド５２１間の接触面積が最大となり、接合界面Ｓｊでの接触抵抗が最小となる。一方、接合アライメントずれが有る場合には、図２（ｂ）に示すように、第１接合パッド５１１及び第２接合パッド５２１間の接触面積が小さくなり（接合パッド及び絶縁膜間の接触面積が大きくなり）、接合界面Ｓｊでの接触抵抗が増大する。   When there is no misalignment between the first Cu bonding portion 510 and the second Cu bonding portion 520 configured as shown in FIG. 1, as shown in FIG. 2A, the first bonding pad 511 and the second bonding pad 521 are used. The contact area between them is maximized, and the contact resistance at the junction interface Sj is minimized. On the other hand, when there is a bonding misalignment, as shown in FIG. 2B, the contact area between the first bonding pad 511 and the second bonding pad 521 is reduced (the contact area between the bonding pad and the insulating film is smaller). The contact resistance at the bonding interface Sj increases.

すなわち、図１に示す構成例では、上述したディッシングの問題を解消することは可能であるが、接合アライメントずれが発生すると、接合界面Ｓｊでの接触抵抗が著しく変動する可能性がある。また、接合アライメントずれが大きいと、接合界面Ｓｊにおいて、導通不良が発生する可能性もある。そこで、本実施形態では、電極部間に絶縁膜が設けられたＣｕ接合部を有する半導体装置において、２つのＣｕ接合部間に接合アライメントずれが発生しても、接触抵抗の変動や導通不良などの発生を抑制することができる構成例を説明する。   That is, in the configuration example shown in FIG. 1, it is possible to eliminate the above-described dishing problem, but if the bonding alignment shift occurs, the contact resistance at the bonding interface Sj may significantly vary. In addition, if the bonding misalignment is large, a conduction failure may occur at the bonding interface Sj. Therefore, in the present embodiment, even if a bonding misalignment occurs between two Cu junctions in a semiconductor device having a Cu junction where an insulating film is provided between the electrode parts, contact resistance fluctuations, poor conduction, etc. A configuration example that can suppress the occurrence of the above will be described.

［半導体装置の構成］
図３及び４に、第１の実施形態に係る半導体装置の概略構成を示す。図３は、本実施形態の半導体装置における各Ｃｕ接合部の概略斜視図である。また、図４は、本実施形態の半導体装置における接合界面Ｓｊ付近の概略断面図である。なお、図３及び４では、説明を簡略化するため、１つのＣｕ−Ｃｕ接合領域付近の概略構成のみを示す。さらに、図３では、説明を簡略化するため、電極部のみを示し、その周囲に設けられるＣｕバリア層、層間絶縁膜等の構成部の図示を省略する。また、図３では、各Ｃｕ接合部の構成をより明確にするため、各Ｃｕ接合部を分けて図示する。 [Configuration of semiconductor device]
3 and 4 show a schematic configuration of the semiconductor device according to the first embodiment. FIG. 3 is a schematic perspective view of each Cu junction in the semiconductor device of this embodiment. FIG. 4 is a schematic cross-sectional view in the vicinity of the junction interface Sj in the semiconductor device of this embodiment. 3 and 4 show only a schematic configuration in the vicinity of one Cu—Cu junction region for the sake of simplicity. Further, in FIG. 3, only the electrode portion is shown for simplifying the description, and illustration of constituent portions such as a Cu barrier layer and an interlayer insulating film provided around the electrode portion is omitted. Moreover, in FIG. 3, in order to clarify the structure of each Cu junction part, each Cu junction part is illustrated separately.

半導体装置１００は、図４に示すように、第１配線部１０１（第１半導体部）と、第２配線部１０２（第２半導体部）とを備える。そして、本実施形態では、第１配線部１０１の後述する第１層間絶縁膜１５側の面と、第２配線部１０２の後述する第２層間絶縁膜２５側の面とを貼り合わせることにより、半導体装置１００が作製される。   As shown in FIG. 4, the semiconductor device 100 includes a first wiring part 101 (first semiconductor part) and a second wiring part 102 (second semiconductor part). In the present embodiment, by bonding the surface on the first interlayer insulating film 15 side described later of the first wiring part 101 and the surface on the second interlayer insulating film 25 side described later of the second wiring part 102, The semiconductor device 100 is manufactured.

なお、第１配線部１０１及び第２配線部１０２間の接合手法としては、任意の手法を用いることができる。例えば、プラズマ接合、常温接合等の手法を用いて、第１配線部１０１と第２配線部１０２とを接合することができる。また、第１配線部１０１及び第２配線部１０２は、例えば特開２００４−６３８５９号公報等の文献に記載の形成手法を用いて形成することができる。   In addition, as a joining technique between the 1st wiring part 101 and the 2nd wiring part 102, arbitrary techniques can be used. For example, the first wiring unit 101 and the second wiring unit 102 can be bonded using a technique such as plasma bonding or room temperature bonding. Moreover, the 1st wiring part 101 and the 2nd wiring part 102 can be formed using the formation method as described in literature, such as Unexamined-Japanese-Patent No. 2004-63859, for example.

第１配線部１０１は、第１半導体基板（不図示）と、第１ＳｉＯ２層１１と、第１Ｃｕ配線１２（第１配線）と、第１Ｃｕバリア膜１３と、第１Ｃｕ拡散防止膜１４とを備える。さらに、第１配線部１０１は、第１層間絶縁膜１５と、３本の第１接合電極１６（第１電極）を含む第１Ｃｕ接合部１０（第１接合部）と、第１Ｃｕバリア層１７と、３つのビア１８とを備える。 The first wiring part 101 includes a first semiconductor substrate (not shown), a first SiO 2 layer 11, a first Cu wiring 12 (first wiring), a first Cu barrier film 13, and a first Cu diffusion preventing film 14. Prepare. Further, the first wiring part 101 includes a first interlayer insulating film 15, a first Cu bonding part 10 (first bonding part) including three first bonding electrodes 16 (first electrodes), and a first Cu barrier layer 17. And three vias 18.

第１ＳｉＯ２層１１は、第１半導体基板上に形成される。また、第１Ｃｕ配線１２は、第１ＳｉＯ２層１１の第１半導体基板側とは反対側の表面に埋め込むようにして形成される。なお、第１Ｃｕ配線１２は、例えば、図示しない半導体装置１００内の所定の素子、回路等に接続される。 The first SiO 2 layer 11 is formed on the first semiconductor substrate. The first Cu wiring 12 is formed so as to be embedded in the surface of the first SiO 2 layer 11 opposite to the first semiconductor substrate side. The first Cu wiring 12 is connected to, for example, a predetermined element or circuit in the semiconductor device 100 (not shown).

第１Ｃｕバリア膜１３は、第１ＳｉＯ２層１１と第１Ｃｕ配線１２との間に形成される。なお、第１Ｃｕバリア膜１３は、第１Ｃｕ配線１２から第１ＳｉＯ２層１１への銅（Ｃｕ）の拡散を防止するための薄膜であり、例えば、Ｔｉ、Ｔａ、Ｒｕ、又は、それらの窒化物で形成される。 The first Cu barrier film 13 is formed between the first SiO 2 layer 11 and the first Cu wiring 12. The first Cu barrier film 13 is a thin film for preventing the diffusion of copper (Cu) from the first Cu wiring 12 to the first SiO 2 layer 11. For example, Ti, Ta, Ru, or nitrides thereof are used. Formed with.

第１Ｃｕ拡散防止膜１４は、第１ＳｉＯ２層１１、第１Ｃｕ配線１２、及び、第１Ｃｕバリア膜１３の領域上であり、かつ、ビア１８の形成領域以外の領域上に設けられる。なお、第１Ｃｕ拡散防止膜１４は、第１Ｃｕ配線１２から第１層間絶縁膜１５への銅（Ｃｕ）の拡散を防止するための薄膜であり、例えばＳｉＣ、ＳｉＮ、又は、ＳｉＣＮ等の薄膜で構成される。また、第１層間絶縁膜１５は、第１Ｃｕ拡散防止膜１４上に設けられる。 The first Cu diffusion preventing film 14 is provided on the region of the first SiO 2 layer 11, the first Cu wiring 12, and the first Cu barrier film 13 and on the region other than the region where the via 18 is formed. The first Cu diffusion preventing film 14 is a thin film for preventing the diffusion of copper (Cu) from the first Cu wiring 12 to the first interlayer insulating film 15, and is a thin film such as SiC, SiN, or SiCN, for example. Composed. The first interlayer insulating film 15 is provided on the first Cu diffusion preventing film 14.

第１Ｃｕ接合部１０を構成する３本の第１接合電極１６は、第１層間絶縁膜１５の第１Ｃｕ拡散防止膜１４側とは反対側の表面に埋め込むようにして設けられる。なお、この際、各第１接合電極１６は、対応するビア１８に接続される。また、第１接合電極１６は、Ｃｕで形成される。   The three first bonding electrodes 16 constituting the first Cu bonding portion 10 are provided so as to be embedded on the surface of the first interlayer insulating film 15 opposite to the first Cu diffusion preventing film 14 side. At this time, each first bonding electrode 16 is connected to the corresponding via 18. The first bonding electrode 16 is made of Cu.

なお、各第１接合電極１６は、図３に示すように、所定方向（第１の方向）に延在した棒状電極で構成される。各第１接合電極１６の延在方向に直交する断面は矩形状であり、該矩形状の断面の寸法及び形状は延在所方向において一定である。また、本実施形態では、３本の第１接合電極１６を、第１接合電極１６の延在方向に直交する方向に、所定間隔で平行に配置する。   In addition, each 1st joining electrode 16 is comprised with the rod-shaped electrode extended in the predetermined direction (1st direction), as shown in FIG. The cross section orthogonal to the extending direction of each first bonding electrode 16 is rectangular, and the size and shape of the rectangular cross section are constant in the extending direction. In the present embodiment, the three first bonding electrodes 16 are arranged in parallel at a predetermined interval in a direction orthogonal to the extending direction of the first bonding electrodes 16.

第１Ｃｕバリア層１７は、３本の第１接合電極１６及び３つのビア１８と、第１層間絶縁膜１５との間に設けられ、３本の第１接合電極１６及び３つのビア１８を覆うように設けられる。なお、第１Ｃｕバリア層１７は、例えば、Ｔｉ、Ｔａ、Ｒｕ、又は、それらの窒化物で形成される。   The first Cu barrier layer 17 is provided between the three first bonding electrodes 16 and the three vias 18 and the first interlayer insulating film 15 and covers the three first bonding electrodes 16 and the three vias 18. It is provided as follows. The first Cu barrier layer 17 is made of, for example, Ti, Ta, Ru, or a nitride thereof.

ビア１８は、第１Ｃｕ配線１２と第１接合電極１６とを電気的に接続する縦孔配線であり、Ｃｕで形成される。また、本実施形態では、３つのビア１８は、図３及び４に示すように、第１Ｃｕバリア層１７を介して第１Ｃｕ配線１２に電気的にそれぞれ別個に接続される。   The via 18 is a vertical hole wiring that electrically connects the first Cu wiring 12 and the first bonding electrode 16, and is formed of Cu. In the present embodiment, as shown in FIGS. 3 and 4, the three vias 18 are electrically connected to the first Cu wiring 12 via the first Cu barrier layer 17, respectively.

一方、第２配線部１０２は、第２半導体基板（不図示）と、第２ＳｉＯ２層２１と、第２Ｃｕ配線２２（第２配線）と、第２Ｃｕバリア膜２３と、第２Ｃｕ拡散防止膜２４とを備える。さらに、第２配線部１０２は、第２層間絶縁膜２５と、３本の第２接合電極２６（第２電極）を含む第２Ｃｕ接合部２０（第２接合部）と、第２Ｃｕバリア層２７と、３つのビア２８とを備える。なお、第２配線部１０２において、第２Ｃｕ接合部２０以外の構成は、第１配線部１０１の対応する構成と同様であるので、ここでは、第２Ｃｕ接合部２０の構成についてのみ説明する。 On the other hand, the second wiring portion 102 includes a second semiconductor substrate (not shown), a second SiO 2 layer 21, a second Cu wiring 22 (second wiring), a second Cu barrier film 23, and a second Cu diffusion preventing film 24. With. Further, the second wiring portion 102 includes a second interlayer insulating film 25, a second Cu junction portion 20 (second junction portion) including three second junction electrodes 26 (second electrodes), and a second Cu barrier layer 27. And three vias 28. In the second wiring portion 102, the configuration other than the second Cu bonding portion 20 is the same as the corresponding configuration of the first wiring portion 101, and therefore only the configuration of the second Cu bonding portion 20 will be described here.

第２Ｃｕ接合部２０は、３本の第２接合電極２６で構成され、該３本の第２接合電極２６は、第２層間絶縁膜２５の第２Ｃｕ拡散防止膜２４側とは反対側の表面に埋め込むようにして設けられる。なお、この際、各第２接合電極２６は、対応するビア２８に接続される。また、第２接合電極２６は、Ｃｕで形成される。   The second Cu bonding portion 20 is composed of three second bonding electrodes 26, and the three second bonding electrodes 26 are surfaces of the second interlayer insulating film 25 opposite to the second Cu diffusion preventing film 24 side. It is provided so as to be embedded in. At this time, each second bonding electrode 26 is connected to the corresponding via 28. The second bonding electrode 26 is made of Cu.

各第２接合電極２６は、図３に示すように、第１接合電極１６と同様に、所定方向（第２の方向）に延在した棒状電極で構成される。そして、本実施形態では、３本の第２接合電極２６は、第２接合電極２６の延在方向に直交する方向に、所定間隔で平行に配置される。   As shown in FIG. 3, each second bonding electrode 26 is composed of a rod-like electrode extending in a predetermined direction (second direction), like the first bonding electrode 16. In the present embodiment, the three second bonding electrodes 26 are arranged in parallel at a predetermined interval in a direction orthogonal to the extending direction of the second bonding electrodes 26.

そして、本実施形態では、図３に示すように、第２接合電極２６の延在方向が（第２の方向）、第１接合電極１６の延在方向（第１の方向）と交差するように、第２接合電極２６を形成する。なお、本実施形態では、第２接合電極２６の延在方向以外の構成（例えば、形状、サイズ、ピッチ、本数等）は、第１接合電極１６のそれと同様とする。   In the present embodiment, as shown in FIG. 3, the extending direction of the second bonding electrode 26 (second direction) intersects the extending direction of the first bonding electrode 16 (first direction). Then, the second bonding electrode 26 is formed. In the present embodiment, the configuration (for example, shape, size, pitch, number, etc.) other than the extending direction of the second bonding electrode 26 is the same as that of the first bonding electrode 16.

第１接合電極１６の延在方向と第２接合電極２６の延在方向との交差角度αは、０度＜α＜１８０度の範囲内の値に設定される（後述の図５参照）。交差角度αは、例えば、半導体装置１００の用途に応じてＣｕ接合部に求められる仕様（抵抗値、接合ピッチ等）、アライメント装置のアライメント精度、接合時に想定される半導体基板の回転ずれ量等の条件を考慮して適宜設定される。ただし、接合界面Ｓｊの接触抵抗の低減という観点では、交差角度αを０度付近又は１８０度付近に設定して、接触面積をより大きくすることが好ましい。また、接合アライメントの精度の向上という観点では、交差角度αを９０度付近に設定することが好ましい。   The intersection angle α between the extending direction of the first bonding electrode 16 and the extending direction of the second bonding electrode 26 is set to a value within a range of 0 degrees <α <180 degrees (see FIG. 5 described later). The crossing angle α is, for example, specifications (resistance value, bonding pitch, etc.) required for the Cu bonding portion according to the use of the semiconductor device 100, alignment accuracy of the alignment device, and a rotational deviation amount of the semiconductor substrate assumed at the time of bonding. It is set appropriately considering the conditions. However, from the viewpoint of reducing the contact resistance of the bonding interface Sj, it is preferable to set the crossing angle α to around 0 degrees or around 180 degrees to increase the contact area. Further, from the viewpoint of improving the accuracy of the bonding alignment, it is preferable to set the crossing angle α to around 90 degrees.

ここで、上記構成の半導体装置１００において、第１Ｃｕ接合部１０と第２Ｃｕ接合部２０との間に形成されるＣｕ−Ｃｕ接合領域の構成を図５に示す。上述のように、本実施形態では、第１接合電極１６の延在方向と第２接合電極２６の延在方向とが互いに交差するので、第１接合電極１６と第２接合電極２６との交差領域にＣｕ−Ｃｕ接合領域１０３が形成される。   Here, in the semiconductor device 100 having the above-described configuration, a configuration of a Cu—Cu junction region formed between the first Cu junction 10 and the second Cu junction 20 is shown in FIG. 5. As described above, in the present embodiment, the extending direction of the first bonding electrode 16 and the extending direction of the second bonding electrode 26 intersect each other, so that the first bonding electrode 16 and the second bonding electrode 26 intersect. A Cu—Cu bonding region 103 is formed in the region.

なお、本実施形態では、各Ｃｕ接合部（第１Ｃｕ接合部１０又は第２Ｃｕ接合部２０）を３本の接合電極（第１接合電極１６又は第２接合電極２６）で構成する例を説明したが、本開示は、これに限定されない。各Ｃｕ接合部を構成する接合電極の本数は任意に設定することができ、例えば１〜１００本程度の範囲内の本数に設定することができる。   In the present embodiment, an example in which each Cu bonding portion (first Cu bonding portion 10 or second Cu bonding portion 20) is configured by three bonding electrodes (first bonding electrode 16 or second bonding electrode 26) has been described. However, the present disclosure is not limited to this. The number of bonding electrodes constituting each Cu bonding portion can be set arbitrarily, and can be set to a number in the range of about 1 to 100, for example.

また、各接合電極のサイズ（例えば延在長さ、幅、厚さ等）、及び、接合電極の配置間隔（ピッチ）は、例えば、デザインルール、想定される接合アライメントずれ等の条件を考慮して適宜設定される。例えば、各接合電極の幅、及び、接合電極のピッチを、約０．１〜５μｍ程度に設定することができる。ただし、接合界面Ｓｊにおける接触抵抗の低下という観点では、デザインルールで許容される範囲内で各接合電極の幅をできる限り大きくすることが好ましい。また、Ｃｕ接合部の作製容易性という観点では、接合電極の幅と、隣り合う接合電極間の距離との比は１：１とすることが好ましい。   In addition, the size of each bonding electrode (for example, extension length, width, thickness, etc.) and the arrangement interval (pitch) of the bonding electrodes take into account conditions such as design rules and assumed bonding misalignment. Is set as appropriate. For example, the width of each bonding electrode and the pitch of the bonding electrodes can be set to about 0.1 to 5 μm. However, from the viewpoint of lowering the contact resistance at the bonding interface Sj, it is preferable to increase the width of each bonding electrode as much as possible within the range allowed by the design rule. Further, from the viewpoint of easy manufacture of the Cu bonding portion, the ratio between the width of the bonding electrode and the distance between adjacent bonding electrodes is preferably 1: 1.

さらに、本実施形態では、接合電極（第１Ｃｕ接合部１０又は第２Ｃｕ接合部２０）の一方の端部付近にビアを設ける例を説明したが、本開示はこれに限定されず、ビアを接合電極の任意の位置に設けることができる。例えば、接合電極のＣｕ−Ｃｕ接合領域に対応する位置にビアを設けてもよい。   Furthermore, in the present embodiment, the example in which the via is provided near one end of the bonding electrode (the first Cu bonding portion 10 or the second Cu bonding portion 20) has been described. However, the present disclosure is not limited thereto, and the via is bonded. It can be provided at any position of the electrode. For example, a via may be provided at a position corresponding to the Cu—Cu bonding region of the bonding electrode.

上述のように、本実施形態の半導体装置１００では、第１接合電極１６と第２接合電極２６とが互いに交差するように接合するので、接合時に両者間に接合アライメントずれが発生しても、Ｃｕ−Ｃｕ接合領域１０３の面積は変動しない。なお、接合時に回転ずれが生じた場合には、Ｃｕ−Ｃｕ接合領域１０３の面積は、所望の面積から若干変動する。しかしながら、上述のように、各Ｃｕ接合部の構成は、半導体基板の回転ずれ量も考慮して設定されるので、接合時に回転ずれが生じた場合でも、Ｃｕ−Ｃｕ接合領域１０３の面積の変動を想定の範囲内に抑えることができる。   As described above, in the semiconductor device 100 of this embodiment, the first bonding electrode 16 and the second bonding electrode 26 are bonded so as to cross each other. The area of the Cu—Cu bonding region 103 does not vary. Note that when a rotational deviation occurs during bonding, the area of the Cu—Cu bonding region 103 slightly varies from the desired area. However, as described above, the configuration of each Cu bonding portion is set in consideration of the amount of rotational deviation of the semiconductor substrate. Can be kept within the expected range.

それゆえ、本実施形態では、接合アライメントずれが発生しても、所望のＣｕ−Ｃｕ接合領域１０３の面積が得られ、接合界面Ｓｊにおける接触抵抗の変動を十分に抑制することができる。なお、本実施形態では、Ｃｕ接合部の接合面には、接合電極と絶縁部とが交互に配置された構成となるので、幅広の接合電極部分が無くなり、ディッシングの問題も解消することができる。   Therefore, in the present embodiment, even if a bonding misalignment occurs, a desired area of the Cu—Cu bonding region 103 can be obtained, and variation in contact resistance at the bonding interface Sj can be sufficiently suppressed. In the present embodiment, since the bonding electrodes and the insulating portions are alternately arranged on the bonding surface of the Cu bonding portion, there is no wide bonding electrode portion, and the problem of dishing can be solved. .

以上のことから、本実施形態では、接合界面Ｓｊにおける例えば導通不良や接触抵抗の上昇などの発生をより一層抑制することができ、より信頼性の高い接合界面Ｓｊを有する半導体装置１００を提供することができる。また、本実施形態では、接合界面Ｓｊにおける接触抵抗の増大を抑制することができるので、半導体装置１００の消費電力の増大、及び、処理速度の遅延を抑制することができる。   From the above, in the present embodiment, it is possible to further suppress the occurrence of, for example, a conduction failure or an increase in contact resistance at the junction interface Sj, and provide the semiconductor device 100 having the junction interface Sj with higher reliability. be able to. In the present embodiment, an increase in contact resistance at the bonding interface Sj can be suppressed, so that an increase in power consumption of the semiconductor device 100 and a delay in processing speed can be suppressed.

＜２．第２の実施形態＞
図６に、第２の実施形態に係る半導体装置の概略構成を示す。図６は、本実施形態の半導体装置の各Ｃｕ接合部の概略斜視図である。なお、図６では、説明を簡略化するため、１つのＣｕ−Ｃｕ接合領域付近の概略構成のみを示す。また、図６では、説明を簡略化するため、電極部のみを示し、その周囲に設けられるＣｕバリア層、層間絶縁膜等の図示を省略する。さらに、図６では、各Ｃｕ接合部の構成をより明確にするため、各Ｃｕ接合部を分けて図示する。また、図６に示す本実施形態の半導体装置において、図３に示す第１の実施形態の半導体装置１００と同様の構成には、同じ符号を付して示す。 <2. Second Embodiment>
FIG. 6 shows a schematic configuration of the semiconductor device according to the second embodiment. FIG. 6 is a schematic perspective view of each Cu bonding portion of the semiconductor device of this embodiment. In FIG. 6, only a schematic configuration in the vicinity of one Cu—Cu junction region is shown to simplify the description. Further, in FIG. 6, only the electrode portion is shown for simplifying the description, and illustration of a Cu barrier layer, an interlayer insulating film, and the like provided around the electrode portion is omitted. Furthermore, in FIG. 6, in order to clarify the configuration of each Cu junction, each Cu junction is illustrated separately. In the semiconductor device of the present embodiment shown in FIG. 6, the same reference numerals are given to the same components as those of the semiconductor device 100 of the first embodiment shown in FIG.

本実施形態の半導体装置１１０は、図６には示さないが、第１の実施形態と同様に、第１Ｃｕ接合部３０（第１接合部）を含む第１配線部（第１半導体部）と、第２Ｃｕ接合部４０（第２接合部）を含む第２配線部（第２半導体部）とを備える。そして、第１配線部及び第２配線部を、例えばプラズマ接合、常温接合等の手法を用いて貼り合わせる（接合する）ことにより、半導体装置１１０が作製される。   Although not shown in FIG. 6, the semiconductor device 110 according to the present embodiment includes a first wiring portion (first semiconductor portion) including the first Cu bonding portion 30 (first bonding portion), as in the first embodiment. And a second wiring part (second semiconductor part) including the second Cu joining part 40 (second joining part). Then, the semiconductor device 110 is manufactured by bonding (bonding) the first wiring portion and the second wiring portion together using a technique such as plasma bonding or room temperature bonding.

なお、本実施形態では、第１Ｃｕ接合部３０及び第２Ｃｕ接合部４０以外の構成は、上記第１の実施形態（図４）と同様の構成であるので、ここでは、第１Ｃｕ接合部３０及び第２Ｃｕ接合部４０の構成についてのみ説明する。   In the present embodiment, since the configuration other than the first Cu bonding portion 30 and the second Cu bonding portion 40 is the same as that of the first embodiment (FIG. 4), here, the first Cu bonding portion 30 and Only the configuration of the second Cu joint 40 will be described.

第１Ｃｕ接合部３０は、図６に示すように、３つの第１接合電極部３１（第１電極）と、第１引き出し電極部３２（第１引き出し電極）とを備える。なお、本実施形態では、第１Ｃｕ接合部３０は、一つのビア１８を介して第１Ｃｕ配線１２に接続される。   As shown in FIG. 6, the first Cu bonding portion 30 includes three first bonding electrode portions 31 (first electrodes) and first extraction electrode portions 32 (first extraction electrodes). In the present embodiment, the first Cu bonding portion 30 is connected to the first Cu wiring 12 through one via 18.

第１接合電極部３１は、上記第１の実施形態の第１接合電極１６と同様に構成することができる。それゆえ、本実施形態の第１接合電極部３１の例えば形状、サイズ、ピッチ、本数等の構成は、図６に示す例に限定されず、上記第１の実施形態の第１接合電極１６と同様に、適宜変更することができる。   The 1st junction electrode part 31 can be comprised similarly to the 1st junction electrode 16 of the said 1st Embodiment. Therefore, for example, the shape, size, pitch, number, and the like of the first bonding electrode portion 31 of the present embodiment are not limited to the example shown in FIG. 6, and the first bonding electrode 16 of the first embodiment and Similarly, it can be changed as appropriate.

第１引き出し電極部３２は、３つの第１接合電極部３１の一方の端部に接続される。また、第１引き出し電極部３２は、一つのビア１８に接続され、該ビア１８を介して第１Ｃｕ配線１２に電気的に接続される。すなわち、本実施形態では、３つの第１接合電極部３１は、第１引き出し電極部３２及びビア１８を介して第１Ｃｕ配線１２に電気的に接続される。なお、第１引き出し電極部３２の例えば形状、サイズ等の構成は、例えばデザインルール等の条件を考慮して適宜設定される。   The first lead electrode portion 32 is connected to one end portion of the three first bonding electrode portions 31. The first lead electrode portion 32 is connected to one via 18 and is electrically connected to the first Cu wiring 12 through the via 18. In other words, in the present embodiment, the three first bonding electrode portions 31 are electrically connected to the first Cu wiring 12 via the first lead electrode portion 32 and the via 18. Note that the configuration of the first extraction electrode portion 32 such as shape and size is appropriately set in consideration of conditions such as design rules.

一方、第２Ｃｕ接合部４０は、図６に示すように、３つの第２接合電極部４１（第２電極）と、第２引き出し電極部４２（第２引き出し電極）とを備える。なお、本実施形態では、第２Ｃｕ接合部４０は、一つのビア２８を介して第２Ｃｕ配線２２に接続される。   On the other hand, as shown in FIG. 6, the second Cu bonding portion 40 includes three second bonding electrode portions 41 (second electrodes) and a second extraction electrode portion 42 (second extraction electrode). In the present embodiment, the second Cu joint 40 is connected to the second Cu wiring 22 through one via 28.

第２接合電極部４１は、上記第１の実施形態の第２接合電極２６と同様に構成することができる。それゆえ、本実施形態の第２接合電極部４１の例えば形状、サイズ、ピッチ、本数等の構成は、図６に示す例に限定されず、上記第１の実施形態の第２接合電極２６と同様に、適宜変更することができる。また、本実施形態では、第２接合電極部４１の延在方向以外の構成（例えば、形状、サイズ、ピッチ、本数等）は、第１接合電極部３１のそれと同様とする。   The 2nd junction electrode part 41 can be comprised similarly to the 2nd junction electrode 26 of the said 1st Embodiment. Therefore, the configuration of, for example, the shape, size, pitch, number, and the like of the second bonding electrode portion 41 of the present embodiment is not limited to the example illustrated in FIG. 6 and the second bonding electrode 26 of the first embodiment. Similarly, it can be changed as appropriate. In the present embodiment, the configuration (for example, shape, size, pitch, number, etc.) other than the extending direction of the second bonding electrode portion 41 is the same as that of the first bonding electrode portion 31.

第２引き出し電極部４２は、３つの第２接合電極部４１の一方の端部に接続される。また、第２引き出し電極部４２は、一つのビア２８に接続され、該ビア２８を介して第２Ｃｕ配線２２に電気的に接続される。すなわち、本実施形態では、３つの第２接合電極部４１は、第２引き出し電極部４２及びビア２８を介して第２Ｃｕ配線２２に電気的に接続される。なお、第２引き出し電極部４２の例えば形状、サイズ等の構成は、第１引き出し電極部３２と同様に、例えばデザインルール等の条件を考慮して適宜設定される。   The second lead electrode portion 42 is connected to one end of the three second bonding electrode portions 41. Further, the second lead electrode portion 42 is connected to one via 28 and is electrically connected to the second Cu wiring 22 through the via 28. In other words, in the present embodiment, the three second bonding electrode portions 41 are electrically connected to the second Cu wiring 22 via the second lead electrode portion 42 and the via 28. Note that, for example, the configuration of the shape, size, and the like of the second extraction electrode portion 42 is set as appropriate in consideration of conditions such as a design rule, for example, as in the first extraction electrode portion 32.

そして、本実施形態では、図６に示すように、第１Ｃｕ接合部３０の第１接合電極部３１の延在方向と、第２Ｃｕ接合部４０の第２接合電極部４１の延在方向とが互いに交差するように、第１Ｃｕ接合部３０と第２Ｃｕ接合部４０とを接合する。   In the present embodiment, as shown in FIG. 6, the extending direction of the first bonding electrode part 31 of the first Cu bonding part 30 and the extending direction of the second bonding electrode part 41 of the second Cu bonding part 40 are The 1st Cu junction part 30 and the 2nd Cu junction part 40 are joined so that it may mutually cross.

なお、第１接合電極部３１の延在方向と第２接合電極部４１の延在方向との交差角度αは、上記第１の実施形態と同様に、０度＜α＜１８０度の範囲内の値とする。また、本実施形態では、上記第１の実施形態と同様に、例えば、Ｃｕ接合部に求められる仕様、アライメント装置のアライメント精度、接合時に想定される半導体基板の回転ずれ量等の条件を考慮して交差角度αを適宜設定する。   Note that the intersection angle α between the extending direction of the first bonding electrode portion 31 and the extending direction of the second bonding electrode portion 41 is within the range of 0 degree <α <180 degrees, as in the first embodiment. The value of In the present embodiment, as in the first embodiment, for example, conditions such as specifications required for the Cu bonding portion, alignment accuracy of the alignment apparatus, and rotational deviation of the semiconductor substrate assumed at the time of bonding are considered. The crossing angle α is appropriately set.

上述のように、本実施形態においても、第１接合電極部３１の延在方向と第２接合電極部４１の延在方向とが互いに交差するので、両者の接合時に接合アライメントずれが発生しても、両者間の接触面積（接触抵抗）の変動を十分に抑制することができる。それゆえ、本実施形態の半導体装置１１０では、上記第１の実施形態と同様の効果が得られる。   As described above, also in the present embodiment, the extending direction of the first bonding electrode portion 31 and the extending direction of the second bonding electrode portion 41 intersect each other. Moreover, the fluctuation | variation of the contact area (contact resistance) between both can fully be suppressed. Therefore, in the semiconductor device 110 of this embodiment, the same effects as those of the first embodiment can be obtained.

＜３．第３の実施形態＞
図７に、第３の実施形態に係る半導体装置の概略構成を示す。図７は、本実施形態の半導体装置のＣｕ接合部の概略斜視図である。なお、図７では、説明を簡略化するため、１つのＣｕ−Ｃｕ接合領域付近の概略構成のみを示す。また、図７では、説明を簡略化するため、電極部のみを示し、その周囲に設けられるＣｕバリア層、層間絶縁膜等の図示を省略する。さらに、図７では、各Ｃｕ接合部の構成をより明確にするため、各Ｃｕ接合部を分けて図示する。また、図７に示す本実施形態の半導体装置において、図３に示す第１の実施形態の半導体装置１００と同様の構成には、同じ符号を付して示す。 <3. Third Embodiment>
FIG. 7 shows a schematic configuration of a semiconductor device according to the third embodiment. FIG. 7 is a schematic perspective view of the Cu bonding portion of the semiconductor device of this embodiment. In FIG. 7, only a schematic configuration in the vicinity of one Cu—Cu junction region is shown to simplify the description. Further, in FIG. 7, only the electrode portion is shown for simplifying the description, and illustration of a Cu barrier layer, an interlayer insulating film, and the like provided around the electrode portion is omitted. Furthermore, in FIG. 7, in order to clarify the configuration of each Cu junction, each Cu junction is illustrated separately. In the semiconductor device of this embodiment shown in FIG. 7, the same reference numerals are given to the same components as those of the semiconductor device 100 of the first embodiment shown in FIG.

本実施形態の半導体装置１２０は、図７には示さないが、第１の実施形態と同様に、第１Ｃｕ接合部５０（第１接合部）を含む第１配線部（第１半導体部）と、第２Ｃｕ接合部６０（第２接合部）を含む第２配線部（第２半導体部）とを備える。そして、第１配線部及び第２配線部を、例えばプラズマ接合、常温接合等の手法を用いて貼り合わせる（接合する）ことにより、半導体装置１２０が作製される。   Although not shown in FIG. 7, the semiconductor device 120 of this embodiment includes a first wiring portion (first semiconductor portion) including a first Cu junction portion 50 (first junction portion), as in the first embodiment. And a second wiring part (second semiconductor part) including the second Cu joining part 60 (second joining part). Then, the semiconductor device 120 is manufactured by bonding (bonding) the first wiring portion and the second wiring portion together using a technique such as plasma bonding or room temperature bonding.

なお、本実施形態では、第１Ｃｕ接合部５０及び第２Ｃｕ接合部６０以外の構成は、上記第１の実施形態（図４）と同様の構成であるので、ここでは、第１Ｃｕ接合部５０及び第２Ｃｕ接合部６０の構成についてのみ説明する。   In the present embodiment, the configuration other than the first Cu bonding portion 50 and the second Cu bonding portion 60 is the same as that of the first embodiment (FIG. 4). Only the configuration of the second Cu bonding portion 60 will be described.

第１Ｃｕ接合部５０は、図７に示すように、開口形状が矩形状の３つの第１スリット５１が形成された板状の電極部材で構成される。なお、本実施形態では、第１Ｃｕ接合部５０は、一つのビア１８を介して第１Ｃｕ配線１２に接続される。   As shown in FIG. 7, the first Cu bonding portion 50 is configured by a plate-like electrode member in which three first slits 51 having a rectangular opening shape are formed. In the present embodiment, the first Cu bonding portion 50 is connected to the first Cu wiring 12 through one via 18.

３つの第１スリット５１は、第１Ｃｕ接合部５０の面内において、第１スリット５１の短辺方向に沿って所定間隔で配置される。それゆえ、第１Ｃｕ接合部５０は、隣り合う第１スリット５１の長辺部間、及び、最外に位置する第１スリット５１の外側のそれぞれに、第１接合電極部５２（第１電極）が形成された構成となる。すなわち、第１Ｃｕ接合部５０では、第１スリット５１の長辺方向に沿って延在した４つの第１接合電極部５２を、間に第１スリット５１を挟んで、第１スリット５１の短辺方向に沿って配置した構成となる。   The three first slits 51 are arranged at predetermined intervals along the short side direction of the first slit 51 in the plane of the first Cu joint portion 50. Therefore, the first Cu bonding portion 50 is provided between the long side portions of the adjacent first slits 51 and outside the first slit 51 located on the outermost side, respectively. Is formed. That is, in the first Cu bonding part 50, the four first bonding electrode parts 52 extending along the long side direction of the first slit 51 are sandwiched between the first slits 51, and the short sides of the first slits 51 are sandwiched therebetween. It becomes the structure arrange | positioned along a direction.

なお、第１接合電極部５２は、上記第１の実施形態の第１接合電極１６と同様に構成することができる。それゆえ、本実施形態の第１接合電極部５２の例えば形状、サイズ、ピッチ、本数等の構成は、図７に示す例に限定されず、上記第１の実施形態の第１接合電極１６と同様に、適宜変更することができる。   In addition, the 1st junction electrode part 52 can be comprised similarly to the 1st junction electrode 16 of the said 1st Embodiment. Therefore, the configuration of, for example, the shape, size, pitch, number, and the like of the first bonding electrode portion 52 of the present embodiment is not limited to the example illustrated in FIG. 7 and the first bonding electrode 16 of the first embodiment. Similarly, it can be changed as appropriate.

また、第１Ｃｕ接合部５０は、４つの第１接合電極部５２の一方及び他方の端部がそれぞれ２つの第１引き出し電極部５３で接続された構成となる。そして、一方の第１引き出し電極部５３が、一つのビア１８に接続され、該ビア１８を介して第１Ｃｕ配線１２に電気的に接続される。すなわち、本実施形態では、４つの第１接合電極部５２は、第１引き出し電極部５３及びビア１８を介して第１Ｃｕ配線１２に電気的に接続される。なお、各第１引き出し電極部５３の例えば形状、サイズ等の構成は、上記第２の実施形態の第１引き出し電極部３２と同様に構成することができる。   Further, the first Cu bonding portion 50 has a configuration in which one end and the other end of the four first bonding electrode portions 52 are connected by two first lead electrode portions 53, respectively. One of the first lead electrode portions 53 is connected to one via 18 and electrically connected to the first Cu wiring 12 through the via 18. In other words, in the present embodiment, the four first bonding electrode portions 52 are electrically connected to the first Cu wiring 12 via the first lead electrode portion 53 and the via 18. For example, the configuration of each first extraction electrode portion 53 such as shape and size can be configured in the same manner as the first extraction electrode portion 32 of the second embodiment.

一方、第２Ｃｕ接合部６０は、図７に示すように、第１Ｃｕ接合部５０と同様に、開口形状が矩形状の３つの第２スリット６１が形成された板状の電極部材で構成される。なお、本実施形態では、第２Ｃｕ接合部６０は、一つのビア２８を介して第２Ｃｕ配線２２に接続される。   On the other hand, as shown in FIG. 7, the second Cu joint portion 60 is configured by a plate-like electrode member in which three second slits 61 having a rectangular opening shape are formed, like the first Cu joint portion 50. . In the present embodiment, the second Cu bonding portion 60 is connected to the second Cu wiring 22 through one via 28.

３つの第２スリット６１は、第２Ｃｕ接合部６０の面内において、第２スリット６１の短辺方向に沿って所定間隔で配置される。それゆえ、第２Ｃｕ接合部６０は、隣り合う第２スリット６１の長辺部間、及び、最外に位置する第２スリット６１の外側のそれぞれに、第２接合電極部６２（第２電極）が形成された構成となる。すなわち、第２Ｃｕ接合部６０では、第２スリット６１の長辺方向に沿って延在した４つの第２接合電極部６２を、間に第２スリット６１を挟んで、第２スリット６１の短辺方向に沿って配置した構成となる。   The three second slits 61 are arranged at predetermined intervals along the short side direction of the second slit 61 in the plane of the second Cu joint portion 60. Therefore, the second Cu bonding portion 60 is provided between the long side portions of the adjacent second slits 61 and on the outer side of the second slit 61 located on the outermost side. Is formed. In other words, in the second Cu bonding portion 60, four second bonding electrode portions 62 extending along the long side direction of the second slit 61 are sandwiched between the short sides of the second slit 61 with the second slit 61 interposed therebetween. It becomes the structure arrange | positioned along a direction.

なお、第２接合電極部６２は、上記第１の実施形態の第２接合電極２６と同様に構成することができる。それゆえ、本実施形態の第２接合電極部６２の例えば形状、サイズ、ピッチ、本数等の構成は、図７に示す例に限定されず、上記第１の実施形態の第２接合電極２６と同様に、適宜変更することができる。また、本実施形態では、第２接合電極部６２の延在方向以外の構成（例えば、形状、サイズ、ピッチ、本数等）は、第１接合電極部５２のそれと同様とする。   In addition, the 2nd junction electrode part 62 can be comprised similarly to the 2nd junction electrode 26 of the said 1st Embodiment. Therefore, the configuration of, for example, the shape, size, pitch, number, and the like of the second bonding electrode portion 62 of the present embodiment is not limited to the example shown in FIG. 7, and the second bonding electrode 26 of the first embodiment and Similarly, it can be changed as appropriate. In the present embodiment, the configuration (for example, shape, size, pitch, number, etc.) other than the extending direction of the second bonding electrode portion 62 is the same as that of the first bonding electrode portion 52.

また、第２Ｃｕ接合部６０は、４つの第２接合電極部６２の一方及び他方の端部がそれぞれ２つの第２引き出し電極部６３で接続された構成となる。そして、一方の第２引き出し電極部６３が、一つのビア２８に接続され、該ビア２８を介して第２Ｃｕ配線２２に電気的に接続される。すなわち、本実施形態では、４つの第２接合電極部６２は、第２引き出し電極部６３及びビア２８を介して第２Ｃｕ配線２２に電気的に接続される。なお、各第２引き出し電極部６３の例えば形状、サイズ等の構成は、上記第２の実施形態の第２引き出し電極部４２と同様に構成することができる。   Further, the second Cu bonding portion 60 has a configuration in which one end and the other end portion of the four second bonding electrode portions 62 are connected by two second extraction electrode portions 63 respectively. One of the second lead electrode portions 63 is connected to one via 28 and is electrically connected to the second Cu wiring 22 through the via 28. That is, in the present embodiment, the four second bonding electrode portions 62 are electrically connected to the second Cu wiring 22 via the second lead electrode portion 63 and the via 28. The configuration of each second extraction electrode portion 63 such as shape and size can be configured in the same manner as the second extraction electrode portion 42 of the second embodiment.

そして、本実施形態では、図７に示すように、第１Ｃｕ接合部５０の第１接合電極部５２の延在方向と、第２Ｃｕ接合部６０の第２接合電極部６２の延在方向とが互いに交差するように、第１Ｃｕ接合部５０と第２Ｃｕ接合部６０とを接合する。   In the present embodiment, as shown in FIG. 7, the extending direction of the first bonding electrode portion 52 of the first Cu bonding portion 50 and the extending direction of the second bonding electrode portion 62 of the second Cu bonding portion 60 are determined. The 1st Cu junction part 50 and the 2nd Cu junction part 60 are joined so that it may mutually cross.

ここで、上記構成の半導体装置１２０において、第１Ｃｕ接合部５０と第２Ｃｕ接合部６０との間に形成されるＣｕ−Ｃｕ接合領域の構成を、図８に示す。本実施形態では、第１接合電極部５２と第２接合電極部６２との交差領域、及び、各Ｃｕ接合部の外周部に、それぞれＣｕ−Ｃｕ接合領域１２１及び１２２が形成される。   Here, in the semiconductor device 120 having the above configuration, the configuration of the Cu—Cu junction region formed between the first Cu junction 50 and the second Cu junction 60 is shown in FIG. 8. In the present embodiment, Cu—Cu bonding regions 121 and 122 are formed in the intersecting region between the first bonding electrode portion 52 and the second bonding electrode portion 62 and the outer peripheral portion of each Cu bonding portion, respectively.

なお、第１接合電極部５２の延在方向と第２接合電極部６２の延在方向との交差角度αは、上記第１の実施形態と同様に、０度＜α＜１８０度の範囲内の値とする。また、本実施形態では、上記第１の実施形態と同様に、例えば、Ｃｕ接合部に求められる仕様、アライメント装置のアライメント精度、接合時に想定される半導体基板の回転ずれ量等の条件を考慮して交差角度αを適宜設定する。   Note that the intersection angle α between the extending direction of the first bonding electrode portion 52 and the extending direction of the second bonding electrode portion 62 is within the range of 0 degree <α <180 degrees, as in the first embodiment. The value of In the present embodiment, as in the first embodiment, for example, conditions such as specifications required for the Cu bonding portion, alignment accuracy of the alignment apparatus, and rotational deviation of the semiconductor substrate assumed at the time of bonding are considered. The crossing angle α is appropriately set.

上記構成では、第１接合電極部５２及び第２接合電極部６２間の交差領域に形成されるＣｕ−Ｃｕ接合領域１２１の面積は、上記第１の実施形態と同様に、接合アライメントずれが発生しても変化しない。一方、各Ｃｕ接合部の外周部に形成されるＣｕ−Ｃｕ接合領域１２２の面積は、接合アライメントずれが発生した場合、若干変化する。   In the above configuration, the area of the Cu—Cu bonding region 121 formed in the intersecting region between the first bonding electrode portion 52 and the second bonding electrode portion 62 causes a bonding misalignment as in the first embodiment. Even if it does not change. On the other hand, the area of the Cu—Cu bonding region 122 formed on the outer peripheral portion of each Cu bonding portion slightly changes when bonding misalignment occurs.

すなわち、本実施形態では、接合アライメントずれが発生した場合、各Ｃｕ接合部の外周部に形成されるＣｕ−Ｃｕ接合領域１２２の面積の変動分だけ、第１Ｃｕ接合部５０及び第２Ｃｕ接合部６０間の接触面積（接触抵抗）が変動する。しかしながら、例えば、図１に示す構成の半導体装置では、接合アライメントずれが発生した際に、Ｃｕ接合部の外周部だけでなく、絶縁膜間の領域（内部領域）においても接触面積（接触抵抗）が変化する。それゆえ、本実施形態では、例えば、図１に示す構成の半導体装置に比べて、接合界面Ｓｊにおける第１Ｃｕ接合部５０及び第２Ｃｕ接合部６０間の接触面積（接触抵抗）の変動を抑制することができる。   That is, in this embodiment, when a bonding misalignment occurs, the first Cu bonding portion 50 and the second Cu bonding portion 60 are equivalent to the variation in the area of the Cu—Cu bonding region 122 formed on the outer peripheral portion of each Cu bonding portion. The contact area between them (contact resistance) varies. However, for example, in the semiconductor device having the configuration shown in FIG. 1, when a bonding misalignment occurs, the contact area (contact resistance) not only in the outer peripheral portion of the Cu bonding portion but also in the region between the insulating films (inner region). Changes. Therefore, in the present embodiment, for example, the variation in the contact area (contact resistance) between the first Cu junction 50 and the second Cu junction 60 at the junction interface Sj is suppressed as compared with the semiconductor device having the configuration illustrated in FIG. be able to.

上述のように、本実施形態においても、第１接合電極部５２の延在方向と第２接合電極部６２の延在方向とが互いに交差する。それゆえ、接合時に接合アライメントずれが発生しても、第１Ｃｕ接合部５０及び第２Ｃｕ接合部６０間の接触面積（接触抵抗）の変動を十分に抑制することができ、上記第１の実施形態と同様の効果が得られる。   As described above, also in this embodiment, the extending direction of the first bonding electrode portion 52 and the extending direction of the second bonding electrode portion 62 intersect each other. Therefore, even if a bonding misalignment occurs at the time of bonding, the variation in the contact area (contact resistance) between the first Cu bonding portion 50 and the second Cu bonding portion 60 can be sufficiently suppressed, and the first embodiment described above. The same effect can be obtained.

＜４．第４の実施形態＞
上記第１〜第３の実施形態における各Ｃｕ接合部の構成（Ｃｕ−Ｃｕ接合技術）は、２つの半導体部材を貼り合わせて配線接合を行う任意の半導体装置（例えば、固体撮像素子、半導体メモリ等）に適用可能である。第４の実施形態では、上記第１〜第３の実施形態における各Ｃｕ接合部の構成（Ｃｕ−Ｃｕ接合技術）を固体撮像素子に適用した例を説明する。 <4. Fourth Embodiment>
The configuration of each Cu bonding portion (Cu-Cu bonding technology) in the first to third embodiments is an arbitrary semiconductor device (for example, a solid-state imaging device, a semiconductor memory) that bonds two semiconductor members together to perform wiring bonding. Etc.). In the fourth embodiment, an example in which the configuration (Cu-Cu bonding technology) of each Cu bonding portion in the first to third embodiments is applied to a solid-state imaging device will be described.

図９に、第４の実施形態に係る固体撮像素子の要部の概略断面図を示す。なお、図９では、説明を簡略化するため、Ｃｕ接合部及びビアと、層間絶縁膜との間に形成されるＣｕバリア層（Ｃｕバリア膜）の図示は省略する。   FIG. 9 is a schematic cross-sectional view of a main part of a solid-state imaging device according to the fourth embodiment. In FIG. 9, in order to simplify the description, the illustration of the Cu barrier layer (Cu barrier film) formed between the Cu junction and via and the interlayer insulating film is omitted.

本実施形態の固体撮像素子２００は、光電変換部２１０を有する第１半導体部材２０１と、演算回路を構成する各種ＭＯＳ（Metal-Oxide-Semiconductor）トランジスタ２２０を有する第２半導体部材２０２とを備える。また、固体撮像素子２００は、カラーフィルタ２０３と、オンチップマイクロレンズ２０４とを備える。   The solid-state imaging device 200 of the present embodiment includes a first semiconductor member 201 having a photoelectric conversion unit 210 and a second semiconductor member 202 having various MOS (Metal-Oxide-Semiconductor) transistors 220 constituting an arithmetic circuit. In addition, the solid-state imaging device 200 includes a color filter 203 and an on-chip microlens 204.

本実施形態の固体撮像素子２００では、第１半導体部材２０１と、第２半導体部材２０２とが接合界面Ｓｊで接合される。また、本実施形態では、第１半導体部材２０１の第２半導体部材２０２側とは反対側の表面上（光電変換層２１１上）に、カラーフィルタ２０３及びオンチップマイクロレンズ２０４がこの順で積層される。   In the solid-state imaging device 200 of the present embodiment, the first semiconductor member 201 and the second semiconductor member 202 are joined at the joining interface Sj. In the present embodiment, the color filter 203 and the on-chip microlens 204 are laminated in this order on the surface of the first semiconductor member 201 opposite to the second semiconductor member 202 (on the photoelectric conversion layer 211). The

第１半導体部材２０１は、光電変換部２１０を有する光電変換層２１１と、光電変換層２１１のカラーフィルタ２０３側とは反対側に設けられた第１多層配線部２１２とを備える。   The first semiconductor member 201 includes a photoelectric conversion layer 211 having a photoelectric conversion unit 210 and a first multilayer wiring unit 212 provided on the opposite side of the photoelectric conversion layer 211 from the color filter 203 side.

第１多層配線部２１２は、複数の第１Ｃｕ配線層２１３を積層して構成される。各第１Ｃｕ配線層２１３は、層間絶縁膜２１４と、その内部に埋め込まれた第１Ｃｕ接合部２１５と、自身よりカラーフィルタ２０３側に位置する層（第１Ｃｕ配線層２１３又は光電変換層２１１）との電気接続を得るために設けられたビア２１６とを有する。また、本実施形態では、互いに隣り合う第１Ｃｕ配線層２１３間、並びに、第１Ｃｕ配線層２１３及び光電変換層２１１間には、Ｃｕ拡散防止膜２１７が設けられる。   The first multilayer wiring part 212 is configured by stacking a plurality of first Cu wiring layers 213. Each first Cu wiring layer 213 includes an interlayer insulating film 214, a first Cu bonding portion 215 embedded therein, and a layer (the first Cu wiring layer 213 or the photoelectric conversion layer 211) positioned closer to the color filter 203 than itself. And vias 216 provided to obtain the electrical connection. In the present embodiment, the Cu diffusion prevention film 217 is provided between the first Cu wiring layers 213 adjacent to each other and between the first Cu wiring layer 213 and the photoelectric conversion layer 211.

一方、第２半導体部材２０２は、演算回路を構成する各種ＭＯＳトランジスタ２２０が形成されたトランジスタ部２２１と、トランジスタ部２２１の第１半導体部材２０１側に設けられた第２多層配線部２２２とを備える。   On the other hand, the second semiconductor member 202 includes a transistor portion 221 in which various MOS transistors 220 constituting an arithmetic circuit are formed, and a second multilayer wiring portion 222 provided on the first semiconductor member 201 side of the transistor portion 221. .

第２多層配線部２２２は、複数の第２Ｃｕ配線層２２３を積層して構成される。各第２Ｃｕ配線層２２３は、層間絶縁膜２２４と、その内部に埋め込まれた第２Ｃｕ接合部２２５と、自身よりトランジスタ部２２１側に位置する層（第２Ｃｕ配線層２２３又はトランジスタ部２２１）との電気接続を得るために設けられたビア２２６とを有する。また、本実施形態では、互いに隣り合う第２Ｃｕ配線層２２３間、並びに、第２Ｃｕ配線層２２３及びトランジスタ部２２１間には、Ｃｕ拡散防止膜２２７が設けられる。   The second multilayer wiring part 222 is configured by stacking a plurality of second Cu wiring layers 223. Each second Cu wiring layer 223 includes an interlayer insulating film 224, a second Cu junction 225 embedded therein, and a layer (second Cu wiring layer 223 or transistor part 221) located closer to the transistor part 221 than itself. And vias 226 provided to obtain electrical connections. In the present embodiment, the Cu diffusion prevention film 227 is provided between the second Cu wiring layers 223 adjacent to each other, and between the second Cu wiring layer 223 and the transistor portion 221.

上述した構成の固体撮像素子２００では、接合界面Ｓｊを挟んで接合される第１Ｃｕ接合部２１５及び第２Ｃｕ接合部２２５に対して、上記第１〜第３の実施形態のいずれかの第１Ｃｕ接合部及び第２Ｃｕ接合部の構成をそれぞれ適用する。この場合、より信頼性の高い接合界面Ｓｊを有する固体撮像素子２００が得られる。   In the solid-state imaging device 200 having the above-described configuration, the first Cu bonding according to any one of the first to third embodiments is performed on the first Cu bonding portion 215 and the second Cu bonding portion 225 that are bonded with the bonding interface Sj interposed therebetween. And the structure of the second Cu joint are applied. In this case, the solid-state imaging device 200 having the bonding interface Sj with higher reliability is obtained.

＜５．各種変形例及び応用例＞
次に、上記第１〜第３の実施形態の半導体装置の変形例及び応用例（適用例）について説明する。 <5. Various modifications and application examples>
Next, modifications and application examples (application examples) of the semiconductor devices of the first to third embodiments will be described.

［変形例１］
上記第１〜第３の実施形態では、直線状に延在した接合電極（接合電極部）を用いる例を説明したが、本開示はこれに限定されない。第１Ｃｕ接合部の第１接合電極（第１接合電極部）の延在方向と、第２Ｃｕ接合部の第２接合電極（第２接合電極部）の延在方向とが互いに交差する構成であれば、各接合電極（接合電極部）の形状を任意に設定することができる。例えば、接合電極（接合電極部）の延在方向がその途中で曲がっていてもよい。その一例（変形例１）を、図１０に示す。 [Modification 1]
In the first to third embodiments, the example using the bonding electrode (bonding electrode portion) extending linearly has been described, but the present disclosure is not limited thereto. The extending direction of the first bonding electrode (first bonding electrode portion) of the first Cu bonding portion and the extending direction of the second bonding electrode (second bonding electrode portion) of the second Cu bonding portion may intersect each other. For example, the shape of each joining electrode (joining electrode part) can be set arbitrarily. For example, the extending direction of the bonding electrode (bonding electrode portion) may be bent in the middle. An example (Modification 1) is shown in FIG.

この例では、図１０に示すように、第１Ｃｕ接合部の第１接合電極１３１、及び、第２Ｃｕ接合部の第２接合電極１３２をそれぞれ、Ｌ字状に延在した棒状電極で構成する。そして、この例においても、第１接合電極１３１と第２接合電極１３２とが、０度＜α＜１８０度の範囲内の交差角度αで互いに交差するように接合する。ただし、この例では、各接合電極の延在形状がＬ字状であるので、図１０に示すように、１本の第１接合電極１３１と１本の第２接合電極１３２との間には、２つのＣｕ−Ｃｕ接合領域１３３が形成される。   In this example, as shown in FIG. 10, the first bonding electrode 131 of the first Cu bonding portion and the second bonding electrode 132 of the second Cu bonding portion are each configured by a rod-shaped electrode extending in an L shape. Also in this example, the first bonding electrode 131 and the second bonding electrode 132 are bonded so as to intersect each other at an intersection angle α within a range of 0 degree <α <180 degrees. However, in this example, since the extending shape of each bonding electrode is L-shaped, as shown in FIG. 10, there is a gap between one first bonding electrode 131 and one second bonding electrode 132. Two Cu—Cu junction regions 133 are formed.

この例の構成においても、第１接合電極１３１の延在方向と第２接合電極１３２の延在方向とが互いに交差するので、両者の接合時に接合アライメントずれが発生しても、両者間の接触面積（接触抵抗）の変動を十分に抑制することができる。それゆえ、この例の半導体装置においても、上記第１の実施形態と同様の効果が得られる。   Even in the configuration of this example, since the extending direction of the first bonding electrode 131 and the extending direction of the second bonding electrode 132 intersect each other, even if bonding misalignment occurs at the time of bonding, the contact between the two Variation in area (contact resistance) can be sufficiently suppressed. Therefore, also in the semiconductor device of this example, the same effect as the first embodiment can be obtained.

なお、図１０には、第１接合電極１３１及び第２接合電極１３２の両方をＬ字状に延在した棒状電極で構成する例を示したが、本開示はこれに限定されない。例えば、第１接合電極１３１及び第２接合電極１３２の一方を、上記第１の実施形態と同様に、直線状に延在した棒状電極で構成してもよい。   FIG. 10 illustrates an example in which both the first bonding electrode 131 and the second bonding electrode 132 are configured by rod-shaped electrodes extending in an L shape, but the present disclosure is not limited thereto. For example, one of the first bonding electrode 131 and the second bonding electrode 132 may be configured by a rod-like electrode extending linearly, as in the first embodiment.

［変形例２］
上記第１〜第３の実施形態では、第１接合電極（第１接合電極部）の延在方向以外の構成（例えば、形状、サイズ、ピッチ、本数等）は、第２接合電極（第２接合電極部）のそれと同様にする例を説明したが、本開示はこれに限定されない。第１接合電極（第１接合電極部）の延在方向と第２接合電極（第２接合電極部）の延在方向とが互いに交差する構成であれば、両者の延在方向以外の構成は互いに異なっていてもよい。 [Modification 2]
In the first to third embodiments, the configuration (for example, shape, size, pitch, number, etc.) other than the extending direction of the first bonding electrode (first bonding electrode portion) is the second bonding electrode (second bonding electrode). Although the example made to be the same as that of the joining electrode part) was demonstrated, this indication is not limited to this. If the extending direction of the first bonding electrode (first bonding electrode portion) and the extending direction of the second bonding electrode (second bonding electrode portion) intersect each other, the configuration other than the extending direction of both is They may be different from each other.

例えば、第１Ｃｕ接合部の第１接合電極（第１接合電極部）の形状、サイズ、ピッチ及び本数の少なくとも一つの構成が、第２Ｃｕ接合部の第２接合電極（第２接合電極部）のそれと異なっていてもよい。   For example, at least one configuration of the shape, size, pitch, and number of first bonding electrodes (first bonding electrode portions) of the first Cu bonding portion is the same as that of the second bonding electrode (second bonding electrode portion) of the second Cu bonding portion. It may be different.

また、上記第１〜第３の実施形態の各Ｃｕ接合部の構成を適宜組み合わせて、第１Ｃｕ接合部の構成と第２Ｃｕ接合部の構成とが互いに異なるようにしてもよい。例えば、第１Ｃｕ接合部及び第２Ｃｕ接合部の一方に第１の実施形態の構成（図３）を適用し、かつ、他方に第２の実施形態の構成（図６）を適用してもよい。また、例えば、第１Ｃｕ接合部及び第２Ｃｕ接合部の一方に第１の実施形態の構成（図３）を適用し、かつ、他方に第３の実施形態の構成（図７）を適用してもよい。さらに、例えば、第１Ｃｕ接合部及び第２Ｃｕ接合部の一方に第２の実施形態の構成（図６）を適用し、かつ、他方に第３の実施形態の構成（図７）を適用してもよい。   In addition, the configurations of the first and third embodiments may be appropriately combined so that the configuration of the first Cu junction and the configuration of the second Cu junction are different from each other. For example, the configuration of the first embodiment (FIG. 3) may be applied to one of the first Cu junction and the second Cu junction, and the configuration of the second embodiment (FIG. 6) may be applied to the other. . Further, for example, the configuration of the first embodiment (FIG. 3) is applied to one of the first Cu junction and the second Cu junction, and the configuration of the third embodiment (FIG. 7) is applied to the other. Also good. Further, for example, the configuration of the second embodiment (FIG. 6) is applied to one of the first Cu junction and the second Cu junction, and the configuration of the third embodiment (FIG. 7) is applied to the other. Also good.

［変形例３］
上記第１〜第３の実施形態では、接合電極（接合電極部）の形成材料がＣｕである例を説明したが、本開示はこれに限定されない。例えば、Ａｌ、Ｗ、Ｔｉ、ＴｉＮ、Ｔａ、ＴａＮ、Ｒｕ等の材料で接合電極（接合電極部）を形成してもよい。 [Modification 3]
In the first to third embodiments, the example in which the forming material of the bonding electrode (bonding electrode portion) is Cu has been described, but the present disclosure is not limited thereto. For example, the bonding electrode (bonding electrode portion) may be formed of a material such as Al, W, Ti, TiN, Ta, TaN, or Ru.

また、上記各種実施形態では、Ｃｕからなる接合電極（接合電極部）同士を接合する例を説明したが、本開示はこれに限定されない。一方の接合電極（接合電極部）の形成材料が、他方の接合電極（接合電極部）の形成材料と異なっていてもよい。   Moreover, although the said various embodiment demonstrated the example which joins the joining electrodes (joining electrode part) which consist of Cu, this indication is not limited to this. The forming material of one joining electrode (joining electrode part) may differ from the forming material of the other joining electrode (joining electrode part).

［変形例４］
上記第２及び第３の実施形態では、各Ｃｕ接合部を、一つのビアを介して外部のＣｕ配線に電気的に接続する例を説明した。しかしながら、この場合、何らかの要因でそのビアに不具合が生じた場合、Ｃｕ接合部とＣｕ配線との間に導通不良などが発生し、製品の歩留まりが低下する可能性がある。 [Modification 4]
In the second and third embodiments, the example in which each Cu junction is electrically connected to an external Cu wiring via one via has been described. However, in this case, if a defect occurs in the via for some reason, a conduction failure or the like may occur between the Cu junction and the Cu wiring, which may reduce the product yield.

この課題を解消するため、上記第１の実施形態と同様に、上記第２及び第３の実施形態の各Ｃｕ接合部に、複数のビアを接続してもよい（変形例４）。すなわち、上記第２及び第３の実施形態の半導体装置において、Ｃｕ接合部及び外部のＣｕ配線間を複数のビアを介して電気的に接続してもよい。なお、この場合、複数のビアの形成箇所は、任意に設定することができ、例えば、複数のビアを引き出し電極部上に形成することができる。   In order to solve this problem, a plurality of vias may be connected to each Cu junction of the second and third embodiments (Modification 4), as in the first embodiment. That is, in the semiconductor devices of the second and third embodiments, the Cu junction and the external Cu wiring may be electrically connected via a plurality of vias. In this case, the formation positions of the plurality of vias can be arbitrarily set. For example, the plurality of vias can be formed on the extraction electrode portion.

この例の構成では、複数のビアのうち一つのビアに不具合が生じても、他のビアでＣｕ接合部とＣｕ配線との間の電気接続を維持することができるので、上記課題を解決することができる。   In the configuration of this example, even if a failure occurs in one of the plurality of vias, the electrical connection between the Cu junction and the Cu wiring can be maintained by the other via, so the above-described problem is solved. be able to.

［変形例５］
上記第１〜第３の実施形態では、Ｃｕ配線からビア（縦孔配線）を介して接続されたＣｕ接合部同士を接合する際に、本開示のＣｕ−Ｃｕ接合技術（接合電極又は接合電極部を交差させる構成）を適用した例を説明したが、本開示はこれに限定されない。例えば、第１配線部（第１半導体部）の第１Ｃｕ配線１２と、第２配線部（第２半導体部）の第２Ｃｕ配線２２とを、Ｃｕ接合部を介さずに直接接合する場合にも、本開示のＣｕ−Ｃｕ接合技術を適用することができる。 [Modification 5]
In the first to third embodiments, the Cu-Cu bonding technique (bonding electrode or bonding electrode) of the present disclosure is used when bonding Cu bonding portions connected from Cu wiring via vias (vertical hole wiring). However, the present disclosure is not limited to this example. For example, even when the first Cu wiring 12 of the first wiring part (first semiconductor part) and the second Cu wiring 22 of the second wiring part (second semiconductor part) are directly joined without going through the Cu joint part. The Cu—Cu bonding technique of the present disclosure can be applied.

この場合、第１配線部（第１半導体部）の接合面に形成された第１Ｃｕ配線１２（第１電極）の延在方向と、第２配線部（第２半導体部）の接合面に形成された第２Ｃｕ配線２２（第２電極）の延在方向とが互いに交差するように、各Ｃｕ配線を形成すればよい。この例の構成は、特に、各配線部の接合面に形成されるＣｕ配線のパターンがシンプルである場合に有効である。   In this case, the extension direction of the first Cu wiring 12 (first electrode) formed on the bonding surface of the first wiring portion (first semiconductor portion) and the bonding surface of the second wiring portion (second semiconductor portion) are formed. Each Cu wiring may be formed so that the extending direction of the formed second Cu wiring 22 (second electrode) intersects each other. The configuration of this example is particularly effective when the Cu wiring pattern formed on the bonding surface of each wiring portion is simple.

なお、この例の構成では、第１配線部及び第２配線部間の接合界面Ｓｊの全領域に渡ってＣｕ配線同士を直接接合してもよい。また、接合界面Ｓｊの配線パターンに応じて、接合界面Ｓｊの一部の領域では、Ｃｕ配線同士を直接接合し、かつ、その他の領域ではＣｕ接合部を介してＣｕ配線を接合するようにしてもよい。   In the configuration of this example, Cu wires may be directly bonded over the entire region of the bonding interface Sj between the first wiring portion and the second wiring portion. Further, according to the wiring pattern of the bonding interface Sj, the Cu wiring is directly bonded in a part of the bonding interface Sj and the Cu wiring is bonded through the Cu bonding portion in the other area. Also good.

［変形例６］
上記第１〜第３の実施形態では、本開示のＣｕ−Ｃｕ接合技術を半導体装置に適用する例を説明したが、本開示は、これに限定されない。例えば、半導体以外の材料で形成された２枚の基板上にそれぞれ設けられた２つの配線を接合する場合にも、上記第１〜第３の実施形態で説明したＣｕ−Ｃｕ接合技術を適用することができ、同様の効果が得られる。 [Modification 6]
In the first to third embodiments, the example in which the Cu—Cu bonding technology of the present disclosure is applied to a semiconductor device has been described. However, the present disclosure is not limited to this. For example, the Cu—Cu bonding technique described in the first to third embodiments is also applied to bonding two wirings respectively provided on two substrates formed of a material other than a semiconductor. And the same effect can be obtained.

［変形例７］
上記各種変形例では、上記第１〜第３の実施形態に対する変形例を説明したが、本開示はこれに限定されない。例えば半導体装置の用途等の条件に応じて、上述した上記第１〜第３の実施形態及び上記変形例１〜６の構成を適宜組み合わせてもよい。 [Modification 7]
In the various modifications described above, modifications to the first to third embodiments have been described, but the present disclosure is not limited thereto. For example, the configurations of the first to third embodiments and the first to sixth modifications described above may be appropriately combined depending on conditions such as the use of the semiconductor device.

［応用例］
上記各種実施形態及び各種変形例の半導体装置は、各種電子機器に適用可能である。例えば、上記第４の実施形態で説明した固体撮像素子２００は、デジタルカメラやビデオカメラ等のカメラシステム、撮像機能を有する携帯電話、又は、撮像機能を備えた他の機器などの電子機器に適用することができる。ここでは、電子機器の一構成例として、カメラを例に挙げ説明する。 [Application example]
The semiconductor devices of the various embodiments and the various modifications can be applied to various electronic devices. For example, the solid-state imaging device 200 described in the fourth embodiment is applied to an electronic device such as a camera system such as a digital camera or a video camera, a mobile phone having an imaging function, or another device having an imaging function. can do. Here, a camera will be described as an example of a configuration of the electronic device.

図１１に、応用例に係るカメラの概略構成を示す。なお、図１１には、静止画像又は動画を撮影することのできるビデオカメラの構成例を示す。   FIG. 11 shows a schematic configuration of a camera according to the application example. Note that FIG. 11 illustrates a configuration example of a video camera that can capture a still image or a moving image.

この例のカメラ３００は、固体撮像素子３０１と、固体撮像素子３０１の受光センサ（不図示）に入射光を導く光学系３０２と、固体撮像素子３０１及び光学系３０２間に設けられたシャッタ装置３０３と、固体撮像素子３０１を駆動する駆動回路３０４とを備える。さらに、カメラ３００は、固体撮像素子３０１の出力信号を処理する信号処理回路３０５を備える。   The camera 300 in this example includes a solid-state image sensor 301, an optical system 302 that guides incident light to a light receiving sensor (not shown) of the solid-state image sensor 301, and a shutter device 303 provided between the solid-state image sensor 301 and the optical system 302. And a drive circuit 304 for driving the solid-state imaging device 301. Furthermore, the camera 300 includes a signal processing circuit 305 that processes an output signal of the solid-state image sensor 301.

固体撮像素子３０１は、例えば、上記第４の実施形態で説明した固体撮像素子２００で構成することができる。その他の各部の構成及び機能は次の通りである。   The solid-state image sensor 301 can be configured by the solid-state image sensor 200 described in the fourth embodiment, for example. Configurations and functions of other parts are as follows.

光学系（光学レンズ）３０２は、被写体からの像光（入射光）を固体撮像素子３０１の撮像面（不図示）上に結像させる。これにより、固体撮像素子３０１内に、一定期間、信号電荷が蓄積される。なお、光学系３０２は、複数の光学レンズを含む光学レンズ群で構成してもよい。また、シャッタ装置３０３は、入射光の固体撮像素子３０１への光照射期間及び遮光期間を制御する。   The optical system (optical lens) 302 forms image light (incident light) from a subject on an imaging surface (not shown) of the solid-state imaging device 301. Thereby, signal charges are accumulated in the solid-state imaging device 301 for a certain period. The optical system 302 may be composed of an optical lens group including a plurality of optical lenses. The shutter device 303 controls the light irradiation period and the light shielding period of the incident light on the solid-state imaging device 301.

駆動回路３０４は、固体撮像素子３０１及びシャッタ装置３０３に駆動信号を供給する。そして、駆動回路３０４は、供給した駆動信号により、固体撮像素子３０１の信号処理回路３０５への信号出力動作、及び、シャッタ装置３０３のシャッタ動作を制御する。すなわち、この例では、駆動回路３０４から供給される駆動信号（タイミング信号）により、固体撮像素子３０１から信号処理回路３０５への信号転送動作を行う。   The drive circuit 304 supplies drive signals to the solid-state image sensor 301 and the shutter device 303. Then, the drive circuit 304 controls the signal output operation to the signal processing circuit 305 of the solid-state imaging device 301 and the shutter operation of the shutter device 303 by the supplied drive signal. That is, in this example, a signal transfer operation from the solid-state imaging device 301 to the signal processing circuit 305 is performed by a drive signal (timing signal) supplied from the drive circuit 304.

信号処理回路３０５は、固体撮像素子３０１から転送された信号に対して、各種の信号処理を施す。そして、各種信号処理が施された信号（映像信号）は、メモリなどの記憶媒体（不図示）に記憶される、又は、モニタ（不図示）に出力される。   The signal processing circuit 305 performs various types of signal processing on the signal transferred from the solid-state image sensor 301. The signal (video signal) that has been subjected to various signal processing is stored in a storage medium (not shown) such as a memory, or is output to a monitor (not shown).

なお、本開示は、以下のような構成を取ることもできる。
（１）
接合界面側の表面に形成されかつ第１の方向に延在する第１電極を有する第１半導体部と、
前記接合界面で前記第１電極と接合されかつ前記第１の方向と交差する第２の方向に延在する第２電極を有し、前記接合界面で前記第１半導体部と貼り合わせて設けられた第２半導体部と
を備える半導体装置。
（２）
前記第１半導体部が、複数の前記第１電極を含む第１接合部と、該第１接合部と電気的に接続された第１配線とを有し、
前記第２半導体部が、複数の前記第２電極を含む第２接合部と、該第２接合部と電気的に接続された第２配線とを有する
（１）に記載の半導体装置。
（３）
前記複数の第１電極のそれぞれが、別個に前記第１配線に接続されている
（２）に記載の半導体装置。
（４）
前記複数の第２電極のそれぞれが、別個に前記第２配線に接続されている
（２）又は（３）に記載の半導体装置。
（５）
前記第１接合部が、前記複数の第１電極の一方の端部に接続された第１引き出し電極を有し、該第１引き出し電極が前記第１配線と電気的に接続されている
（２）に記載の半導体装置。
（６）
前記第２接合部が、前記複数の第２電極の一方の端部に接続された第２引き出し電極を有し、該第２引き出し電極が前記第２配線と電気的に接続されている
（２）又は（５）に記載の半導体装置。
（７）
前記第１接合部が、前記複数の第１電極の一方及び他方の端部にそれぞれ接続された２つの第１引き出し電極を有し、該２つの第１引き出し電極のうち少なくとも一方が前記第１配線と電気的に接続されている
（２）に記載の半導体装置。
（８）
前記第２接合部が、前記複数の第２電極の一方及び他方の端部にそれぞれ接続された２つの第２引き出し電極を有し、該２つの第２引き出し電極のうち少なくとも一方が前記第２配線と電気的に接続されている
（２）又は（７）に記載の半導体装置。
（９）
前記第１電極及び前記第２電極がともに、Ｃｕで形成されている
（１）〜（８）のいずれか一項に記載の半導体装置。 In addition, this indication can also take the following structures.
(1)
A first semiconductor part having a first electrode formed on a surface on the bonding interface side and extending in a first direction;
A second electrode that is bonded to the first electrode at the bonding interface and extends in a second direction that intersects the first direction, and is bonded to the first semiconductor portion at the bonding interface; And a second semiconductor part.
(2)
The first semiconductor unit includes a first junction including a plurality of the first electrodes, and a first wiring electrically connected to the first junction.
The semiconductor device according to (1), wherein the second semiconductor unit includes a second junction including a plurality of the second electrodes, and a second wiring electrically connected to the second junction.
(3)
The semiconductor device according to (2), wherein each of the plurality of first electrodes is separately connected to the first wiring.
(4)
The semiconductor device according to (2) or (3), wherein each of the plurality of second electrodes is separately connected to the second wiring.
(5)
The first junction has a first lead electrode connected to one end of the plurality of first electrodes, and the first lead electrode is electrically connected to the first wiring. ) Semiconductor device.
(6)
The second junction has a second lead electrode connected to one end of the plurality of second electrodes, and the second lead electrode is electrically connected to the second wiring. Or the semiconductor device according to (5).
(7)
The first joint portion includes two first extraction electrodes connected to one end and the other end of the plurality of first electrodes, respectively, and at least one of the two first extraction electrodes is the first first electrode. The semiconductor device according to (2), which is electrically connected to wiring.
(8)
The second junction has two second extraction electrodes connected to one end and the other end of the plurality of second electrodes, respectively, and at least one of the two second extraction electrodes is the second The semiconductor device according to (2) or (7), which is electrically connected to wiring.
(9)
The semiconductor device according to any one of (1) to (8), wherein both the first electrode and the second electrode are made of Cu.

１０，３０，５０…第１Ｃｕ接合部、１１…第１ＳｉＯ２層、１２…第１Ｃｕ配線、１３…第１Ｃｕバリア層、１４…第１Ｃｕ拡散防止層、１５…第１層間絶縁膜、１６…第１接合電極、１７…第１Ｃｕバリア層、１８…ビア、２０，４０，６０…第２Ｃｕ接合部、２１…第２ＳｉＯ２層、２２…第２Ｃｕ配線、２３…第２Ｃｕバリア層、２４…第２Ｃｕ拡散防止層、２５…第２層間絶縁膜、２６…第２接合電極、２７…第２Ｃｕバリア層、２８…ビア、３１，５２…第１接合電極部、３２，５３…第１引き出し電極部、４１，６２…第２接合電極部、４２，６３…第２引き出し電極部、５１…第１スリット、６１…第２スリット、１００，１１０，１２０…半導体装置、１０１…第１配線部、１０２…第２配線部、１０３，１２１，１２２…Ｃｕ−Ｃｕ接合領域 10, 30, and 50 ... The 1Cu junction 11 ... first 1SiO 2 layer, 12 ... first 1Cu wire, 13 ... first 1Cu barrier layer, 14 ... first 1Cu diffusion preventing layer, 15 ... first interlayer insulating film, 16 ... first DESCRIPTION OF SYMBOLS 1 Junction electrode, 17 ... 1st Cu barrier layer, 18 ... Via, 20, 40, 60 ... 2nd Cu junction part, 21 ... 2nd SiO2 layer, 22 ... 2nd Cu wiring, 23 ... 2nd Cu barrier layer, 24 ... 2nd Cu Diffusion prevention layer, 25 ... second interlayer insulating film, 26 ... second junction electrode, 27 ... second Cu barrier layer, 28 ... via, 31,52 ... first junction electrode portion, 32,53 ... first extraction electrode portion, 41, 62 ... second junction electrode part, 42, 63 ... second lead electrode part, 51 ... first slit, 61 ... second slit, 100, 110, 120 ... semiconductor device, 101 ... first wiring part, 102 ... 2nd wiring part, 103, 121, 12 ... Cu-Cu bonding region

Claims (9)

接合界面側の表面に形成されかつ第１の方向に延在する第１電極を有する第１半導体部と、
前記接合界面で前記第１電極と接合されかつ前記第１の方向と交差する第２の方向に延在する第２電極を有し、前記接合界面で前記第１半導体部と貼り合わせて設けられた第２半導体部と
を備える半導体装置。 A first semiconductor part having a first electrode formed on a surface on the bonding interface side and extending in a first direction;
A second electrode that is bonded to the first electrode at the bonding interface and extends in a second direction that intersects the first direction, and is bonded to the first semiconductor portion at the bonding interface; And a second semiconductor part. 前記第１半導体部が、複数の前記第１電極を含む第１接合部と、該第１接合部と電気的に接続された第１配線とを有し、
前記第２半導体部が、複数の前記第２電極を含む第２接合部と、該第２接合部と電気的に接続された第２配線とを有する
請求項１に記載の半導体装置。 The first semiconductor unit includes a first junction including a plurality of the first electrodes, and a first wiring electrically connected to the first junction.
The semiconductor device according to claim 1, wherein the second semiconductor unit includes a second junction including a plurality of the second electrodes, and a second wiring electrically connected to the second junction. 前記複数の第１電極のそれぞれが、別個に前記第１配線に接続されている
請求項２に記載の半導体装置。 The semiconductor device according to claim 2, wherein each of the plurality of first electrodes is separately connected to the first wiring. 前記複数の第２電極のそれぞれが、別個に前記第２配線に接続されている
請求項３に記載の半導体装置。 The semiconductor device according to claim 3, wherein each of the plurality of second electrodes is separately connected to the second wiring. 前記第１接合部が、前記複数の第１電極の一方の端部に接続された第１引き出し電極を有し、該第１引き出し電極が前記第１配線と電気的に接続されている
請求項２に記載の半導体装置。 The first joint portion includes a first lead electrode connected to one end of the plurality of first electrodes, and the first lead electrode is electrically connected to the first wiring. 2. The semiconductor device according to 2. 前記第２接合部が、前記複数の第２電極の一方の端部に接続された第２引き出し電極を有し、該第２引き出し電極が前記第２配線と電気的に接続されている
請求項５に記載の半導体装置。 The second joint portion includes a second lead electrode connected to one end of the plurality of second electrodes, and the second lead electrode is electrically connected to the second wiring. 5. The semiconductor device according to 5. 前記第１接合部が、前記複数の第１電極の一方及び他方の端部にそれぞれ接続された２つの第１引き出し電極を有し、該２つの第１引き出し電極のうち少なくとも一方が前記第１配線と電気的に接続されている
請求項２に記載の半導体装置。 The first joint portion includes two first extraction electrodes connected to one end and the other end of the plurality of first electrodes, respectively, and at least one of the two first extraction electrodes is the first first electrode. The semiconductor device according to claim 2, wherein the semiconductor device is electrically connected to the wiring. 前記第２接合部が、前記複数の第２電極の一方及び他方の端部にそれぞれ接続された２つの第２引き出し電極を有し、該２つの第２引き出し電極のうち少なくとも一方が前記第２配線と電気的に接続されている
請求項７に記載の半導体装置。 The second junction has two second extraction electrodes connected to one end and the other end of the plurality of second electrodes, respectively, and at least one of the two second extraction electrodes is the second The semiconductor device according to claim 7, wherein the semiconductor device is electrically connected to the wiring. 前記第１電極及び前記第２電極がともに、Ｃｕで形成されている
請求項１に記載の半導体装置。
The semiconductor device according to claim 1, wherein both the first electrode and the second electrode are made of Cu.
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