JP6031765B2 - SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Google Patents

Description

  The present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method of the semiconductor device, and more specifically, a semiconductor device in which two substrates are bonded to each other at the time of manufacturing to perform wiring bonding, an electronic device including the semiconductor device, and a semiconductor The present invention relates to a device manufacturing method.

  2. Description of the Related Art Conventionally, a technique for bonding two semiconductor substrates (wafers) and bonding copper wirings formed on the respective semiconductor substrates (hereinafter referred to as Cu-Cu bonding) has been developed (for example, Patent Document 1). reference).

  FIG. 58 shows a schematic cross-sectional view of the vicinity of the Cu—Cu junction interface of the semiconductor device proposed in Patent Document 1. The semiconductor device 500 of Patent Document 1 includes a first semiconductor member including a semiconductor substrate 501, a wiring layer 503, a through hole 505 (vertical hole wiring portion), an insulating layer 507, a ground wiring layer 509, and an insulating material 512. . The semiconductor device 500 includes a second semiconductor member including a semiconductor substrate 502, a wiring layer 504, a through hole 506, an insulating layer 508, a ground wiring layer 510, and an insulating material 513.

  In the first semiconductor member, the wiring layer 503 is formed so as to be embedded in one surface (surface on the bonding side) of the semiconductor substrate 501. The insulating layer 507 and the ground wiring layer 509 are stacked on one surface of the semiconductor substrate 501 in this order. Further, the through hole 505 is formed in a laminated film including the insulating layer 507 and the ground wiring layer 509. At this time, the through hole 505 is formed so as to penetrate the laminated film along the thickness direction of the laminated film. Note that one end portion of the through hole 505 is connected to the wiring layer 503, and the other end portion is provided so as to be exposed on the surface of the first semiconductor member on the bonding side (surface on the ground wiring layer 509 side). It is done. Further, the insulating material 512 is provided between the through hole 505 and the ground wiring layer 509.

  On the other hand, in the second semiconductor member, the wiring layer 504 is formed so as to be embedded in one surface (surface on the bonding side) of the semiconductor substrate 502. The insulating layer 508 and the ground wiring layer 510 are stacked on one surface of the semiconductor substrate 502 in this order. Further, the through hole 506 is formed in a laminated film including the insulating layer 508 and the ground wiring layer 510. At this time, the through hole 506 is formed so as to penetrate the laminated film along the thickness direction of the laminated film. Note that one end portion of the through hole 506 is connected to the wiring layer 504, and the other end portion is provided so as to be exposed on the bonding-side surface (surface on the ground wiring layer 510 side) of the second semiconductor member. It is done. Further, the insulating material 513 is provided between the through hole 506 and the ground wiring layer 510.

  In Patent Document 1, a semiconductor device is obtained by bonding the surface of the first semiconductor member having the above configuration on the ground wiring layer 509 side and the surface of the second semiconductor member having the above configuration on the ground wiring layer 510 side. 500 is made.

JP 2000-299379 A

  As described above, conventionally, in the technical field of semiconductor devices, a technique for bonding two semiconductor substrates and performing Cu-Cu bonding has been proposed. However, in this technical field, development of a semiconductor device having a more reliable bonding interface by further suppressing deterioration of, for example, electrical characteristics and adhesion at a Cu-Cu bonding interface (hereinafter simply referred to as a bonding interface). Is desired.

  The present disclosure has been made to meet the above-described demand, and an object of the present disclosure is to provide a semiconductor device, an electronic device, and a method for manufacturing the semiconductor device having a more reliable bonding interface. .

In order to solve the above problems, a semiconductor device of the present disclosure includes a first semiconductor section including a first metal film formed on the surface of the bonding interface side, is bonded to the first metal layer at the bonding interface and the bonding interface A second semiconductor part having a second metal film whose surface area on the side is smaller than the surface area on the bonding interface side of the first metal film, and is provided by being bonded to the first semiconductor part at the bonding interface; And an interface barrier portion provided in a region including a surface region that is not bonded to the second metal film in the surface region on the bonding interface side.
The interface barrier portion is formed of an insulating interface barrier film formed flush with the second metal film so as to be bonded to the first semiconductor portion at the bonding interface . An insulating film is provided so as to cover the side of the metal film, and an interface barrier film is formed on the surface of the insulating film on the bonding interface side .

  In addition, an electronic apparatus of the present disclosure includes the semiconductor device of the present disclosure and a signal processing circuit that processes an output signal of the semiconductor device.

Furthermore, the manufacturing method of the semiconductor device of this indication is performed in the procedure shown below.
First, a first semiconductor part having a first metal film formed on the surface on the bonding interface side is produced. Next, the second metal film whose surface area on the bonding interface side is smaller than the surface area on the bonding interface side of the first metal film, and the surface not bonded to the second metal film in the surface area on the bonding interface side of the first metal film in the region including the region, it is formed on the second metal film flush to be bonded to the first semiconductor portion at the bonding interface, and a configured surface barrier section by an interfacial barrier film insulator, second A second semiconductor part is manufactured , which has an insulating film provided so as to cover the side part of the metal film, and the interface barrier film is formed on the surface of the insulating film on the bonding interface side . Then, by bonding the first metal layer-side surface of the first semiconductor section and the second metal layer side of the surface of the second semiconductor section, join the first metal film and the second metal layer step.

  As described above, in the semiconductor device (electronic device) and the manufacturing method thereof according to the present disclosure, the surface area on the bonding side of the second metal film bonded to the first metal film is defined as the surface on the bonding side of the first metal film. Make it smaller than the area. Then, an interface barrier portion is provided in a region including a surface region that is not bonded to the second metal film in the surface region on the bonding interface side of the first metal film. According to the configuration of the present disclosure, it is possible to provide a semiconductor device (electronic device) having a more reliable bonding interface and a method for manufacturing the same, further suppressing deterioration of electrical characteristics at the bonding interface. .

It is a figure for demonstrating the problem which generate | occur | produces at the time of Cu-Cu joining. It is a figure for demonstrating the problem which generate | occur | produces at the time of Cu-Cu joining. 3 is a schematic cross-sectional view of the vicinity of a bonding interface in the semiconductor device according to the first embodiment of the present disclosure. It is a schematic top view of the vicinity of the bonding interface of the semiconductor device according to the first embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 1st Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 1st Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 1st Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 1st Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 1st Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 1st Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 1st Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 1st Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 1st Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 1st Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 1st Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 1st Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 1st Embodiment. 6 is a schematic cross-sectional view of a vicinity of a junction interface in a semiconductor device according to a second embodiment of the present disclosure. FIG. It is a schematic top view of the vicinity of the bonding interface of the semiconductor device according to the second embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 2nd Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 2nd Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 2nd Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 2nd Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 2nd Embodiment. 7 is a schematic cross-sectional view of a vicinity of a bonding interface in a semiconductor device according to a third embodiment of the present disclosure. It is a schematic top view of the vicinity of the junction interface of the semiconductor device according to the third embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 3rd Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 3rd Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 3rd Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 3rd Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 3rd Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 3rd Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 3rd Embodiment. It is a figure for demonstrating the manufacturing procedure of the semiconductor device which concerns on 3rd Embodiment. 10 is a schematic cross-sectional view of a vicinity of a bonding interface in a semiconductor device of Modification 1. FIG. 10 is a diagram for explaining a manufacturing procedure of the semiconductor device of Modification 1. FIG. 10 is a schematic cross-sectional view of the vicinity of a bonding interface in a semiconductor device of Modification 3. FIG. 10 is a schematic cross-sectional view of the vicinity of a bonding interface in a semiconductor device of Modification 4. FIG. 7 is a schematic cross-sectional view of the vicinity of a bonding interface in the semiconductor device of Reference Example 1. FIG. 6 is a schematic cross-sectional view of the vicinity of a bonding interface in a semiconductor device of Reference Example 2. FIG. It is a figure for demonstrating the problem which may generate | occur | produce in the conventional Cu-Cu joining method. It is a figure for demonstrating the problem which may generate | occur | produce in the conventional Cu-Cu joining method. 10 is a schematic cross-sectional view of a vicinity of a bonding interface in a semiconductor device according to a fourth embodiment of the present disclosure. FIG. It is a schematic top view of the vicinity of the bonding interface of the semiconductor device according to the fourth embodiment. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on 4th Embodiment. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on 4th Embodiment. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on 4th Embodiment. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on 4th Embodiment. FIG. 9 is a schematic cross-sectional view near a junction interface in a semiconductor device according to a fifth embodiment of the present disclosure. It is a schematic top view of the vicinity of the junction interface of the semiconductor device according to the fifth embodiment. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on 5th Embodiment. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on 5th Embodiment. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on 5th Embodiment. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on 5th Embodiment. It is a figure which shows the structural example of the semiconductor device of the application example 1 which can apply the Cu-Cu joining technique of this indication. It is a figure which shows the structural example of the semiconductor device of the application example 2 which can apply the Cu-Cu joining technique of this indication. It is a figure which shows the structural example of the electronic device of the application example 3 which can apply the Cu-Cu joint technique of this indication. It is a schematic sectional drawing of the junction interface vicinity in the conventional semiconductor device.

Hereinafter, a semiconductor device according to an embodiment of the present disclosure and an example of a manufacturing method thereof will be described in the following order with reference to the drawings. However, the present disclosure is not limited to the following example.
1. First Embodiment 2. FIG. Second Embodiment 3. Third Embodiment 4. 4. Various modifications and reference examples Fourth embodiment 6. Fifth embodiment Various application examples

<1. First Embodiment>
[Problems of conventional Cu-Cu bonding technology]
First, before describing the semiconductor device according to the first embodiment of the present disclosure, problems that may occur in the conventional Cu-Cu bonding technique are illustrated in FIGS. 1 (a) and 1 (b), and FIG. The description will be given with reference. 1A is a schematic cross-sectional view of each semiconductor member before joining the two semiconductor members, and FIG. 1B is a schematic cross-sectional view of the vicinity of the joined interface after joining. FIG. 2 is a diagram for explaining a problem that may occur when bonding misalignment occurs when two semiconductor members are bonded.

Here, the first semiconductor member 610 including the first SiO ₂ layer 611, the first Cu electrode 612, and the first Cu barrier layer 613, and the second SiO ₂ layer 621, the second Cu electrode 622, and the second Cu barrier layer 623 are included. The example which joins the 2nd semiconductor member 620 is shown.

In the example shown in FIGS. 1A and 1B, in each semiconductor member, the Cu electrode is formed so as to be embedded in one surface of the SiO ₂ layer. That is, the Cu electrode is formed so as to be exposed on one surface of the SiO ₂ layer, and the exposed surface thereof is substantially flush with the one surface of the SiO ₂ layer. The Cu barrier layer is provided between the Cu electrode and the SiO ₂ layer. Then, the surface of the first semiconductor member 610 on the first Cu electrode 612 side and the surface of the second semiconductor member 620 on the second Cu electrode 622 side are bonded together.

When joining of the first semiconductor member 610 and the second semiconductor member 620 causes a misalignment between them, as shown in FIG. 1B, a Cu electrode of one semiconductor member is formed at the joining interface Sj. And a contact region between the other semiconductor member and the SiO ₂ layer.

In this case, as shown in FIG. 2, Cu630 diffuses from each Cu electrode to the SiO ₂ layer due to an annealing process at the time of bonding, and adjacent Cu electrodes may be short-circuited at the bonding interface Sj. In addition, if the amount of Cu630 diffused from each Cu electrode to the SiO ₂ layer is large, the amount of Cu in the Cu electrode is reduced. For example, problems such as an increase in contact resistance and poor conduction may occur.

  When a defect in the electrical characteristics at the bonding interface Sj as described above occurs, the performance of the semiconductor device deteriorates. In view of this, in the present embodiment, a configuration of a semiconductor device capable of eliminating the above-described defects in electrical characteristics at the bonding interface Sj will be described.

[Configuration of semiconductor device]
3 and 4 show a schematic configuration of the semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional view in the vicinity of the bonding interface of the semiconductor device of the first embodiment, and FIG. FIG. In FIGS. 3 and 4, only the configuration near one bonding interface is shown to simplify the description.

  As shown in FIG. 3, the semiconductor device 1 includes a first semiconductor member 10 (first semiconductor portion) and a second semiconductor member 20 (second semiconductor portion). In the semiconductor device 1 of the present embodiment, the surface of the first semiconductor member 10 on the first interlayer insulating film 15 side described later is bonded to the surface of the second semiconductor member 20 on the interface Cu barrier film 28 side described later. .

The first semiconductor member 10 includes a first semiconductor substrate (not shown), a first SiO ₂ layer 11, a first Cu wiring portion 12, a first Cu barrier film 13, a first Cu diffusion prevention film 14, a first interlayer insulating film 15, and a first Cu. The junction 16 and the first Cu barrier layer 17 are included.

The first SiO ₂ layer 11 is formed on the first semiconductor substrate. The first Cu wiring portion 12 is formed so as to be embedded in the surface of the first SiO ₂ layer 11 opposite to the first semiconductor substrate side. As shown in FIG. 4, the first Cu wiring portion 12 is a Cu film extending in a predetermined direction. For example, the first Cu wiring portion 12 is a predetermined device in the semiconductor device 1 and / or an electronic apparatus including the semiconductor device 1 (not shown). Connected to a signal processing circuit or the like.

The first Cu barrier film 13 is formed between the first SiO ₂ layer 11 and the first Cu wiring part 12. The first Cu barrier film 13 is a thin film for preventing the diffusion of Cu (copper) from the first Cu wiring portion 12 to the first SiO ₂ layer 11, for example, Ti, Ta, Ru, or nitridation thereof. It is formed of a material (TiN, TaN, RuN).

The first Cu diffusion preventing film 14 is formed on the region of the first SiO ₂ layer 11 and the first Cu wiring portion 12 and on the region other than the region where the first Cu barrier layer 17 is formed. The first Cu diffusion prevention film 14 is a thin film for preventing diffusion of Cu from the first Cu wiring portion 12 to the first interlayer insulating film 15, and is composed of a thin film such as SiC, SiN, or SiCN, for example. The

The first interlayer insulating film 15 is formed on the first Cu diffusion preventing film 14 and is made of an oxide film such as a SiO ₂ film.

  The first Cu bonding portion 16 (first metal film) is provided so as to be embedded on the surface of the first interlayer insulating film 15 opposite to the first Cu diffusion preventing film 14 side. In the present embodiment, as shown in FIG. 4, the first Cu bonding portion 16 is constituted by a Cu film having a square surface (film surface). However, the present disclosure is not limited to this, and the surface shape of the first Cu bonding portion 16 can be appropriately changed in consideration of conditions such as required contact resistance and design rules.

  The first Cu barrier layer 17 is provided between the first Cu bonding portion 16 and the first Cu wiring portion 12, the first Cu diffusion prevention film 14 and the first interlayer insulating film 15, and is provided so as to cover the first Cu bonding portion 16. It is done. As a result, the first Cu bonding portion 16 is electrically connected to the first Cu wiring portion 12 via the first Cu barrier layer 17. The first Cu barrier layer 17 is a thin film for preventing the diffusion of Cu from the first Cu junction 16 to the first interlayer insulating film 15, and is made of, for example, Ti, Ta, Ru, or a nitride thereof. It is formed.

The second semiconductor member 20 includes a second semiconductor substrate (not shown), a second SiO ₂ layer 21, a second Cu wiring part 22, a second Cu barrier film 23, a second Cu diffusion prevention film 24, a second interlayer insulating film 25, and a second Cu. The bonding portion 26, the second Cu barrier layer 27, and the interface Cu barrier film 28 are included.

In the present embodiment, the second semiconductor substrate, the _second SiO ₂ layer 21 and the second Cu wiring portion 22 of the second semiconductor member 20 are respectively the first semiconductor substrate and the first SiO ₂ layer of the first semiconductor member 10. 11 and the same configuration as the first Cu wiring portion 12. Further, the second Cu barrier film 23, the second Cu diffusion prevention film 24, and the second interlayer insulating film 25 of the second semiconductor member 20 are respectively the first Cu barrier film 13 and the first Cu diffusion prevention film of the first semiconductor member 10. 14 and the same structure as the first interlayer insulating film 15.

  The second Cu bonding portion 26 (second metal film) is provided so as to be embedded on the surface of the second interlayer insulating film 25 (insulating film) opposite to the second Cu diffusion preventing film 24 side. In the present embodiment, as shown in FIG. 4, the second Cu bonding portion 26 is constituted by a Cu film having a square surface. However, the present disclosure is not limited to this, and the surface shape of the second Cu bonding portion 26 can be appropriately changed in consideration of conditions such as required contact resistance and design rules.

  In this embodiment, as shown in FIGS. 3 and 4, the surface area (dimension of the surface on the bonding side) on the bonding side (bonding interface Sj side) of the second Cu bonding portion 26 is made larger than that of the first Cu bonding portion 16. Make it smaller. At this time, even if the maximum bonding misalignment expected between the first semiconductor member 10 and the second semiconductor member 20 occurs, the second Cu bonding portion 26 and the first interlayer insulating film 15 are in contact with each other at the bonding interface Sj. The size of the second Cu joint portion 26 is set so that it does not occur. More specifically, for example, as shown in FIG. 3, when the shortest distance between the side surface of the second Cu bonding portion 26 and the side surface of the first Cu barrier layer 17 is Δa, the maximum bonding misalignment that Δa is assumed is assumed. The size of the 2nd Cu junction part 26 is set so that it may become the above dimension.

  The second Cu barrier layer 27 is provided between the second Cu bonding portion 26 and the second Cu wiring portion 22, the second Cu diffusion preventing film 24, and the second interlayer insulating film 25, and is provided so as to cover the second Cu bonding portion 26. It is done. As a result, the second Cu bonding portion 26 is electrically connected to the second Cu wiring portion 22 through the second Cu barrier layer 27. The second Cu barrier layer 27 is a thin film for preventing the diffusion of Cu from the second Cu junction 26 to the second interlayer insulating film 25, similar to the first Cu barrier layer 17. For example, Ti, Ta, It is made of Ru or a nitride thereof.

The interface Cu barrier film 28 (interface barrier film, interface barrier part) is formed on the second interlayer insulating film 25. At this time, the interface Cu barrier film 28 is formed so that the surface of the interface Cu barrier film 28 and the surface on the bonding side of the second Cu bonding portion 26 are substantially flush with each other. That is, the interface Cu barrier film 28 is provided in a region including a surface region that is not bonded to the second Cu bonding portion 26 in the surface region on the bonding interface Sj side of the first Cu bonding portion 16. By providing the interface Cu barrier film 28 in such a region (position), the interlayer insulating film (from the Cu junction through the opposing region of the first Cu junction 16 and the second interlayer insulating film 25 at the junction interface Sj). It is possible to prevent Cu from diffusing into the (SiO ₂ film).

  The interface Cu barrier film 28 can be formed of a material such as SiN, SiON, SiCN, or organic resin, for example. However, from the viewpoint of improving the adhesion with the Cu film, it is particularly preferable to form the interface Cu barrier film 28 with SiN.

[Semiconductor Device Manufacturing Method]
Next, a method for manufacturing the semiconductor device 1 according to the present embodiment will be described with reference to FIGS. FIGS. 5 to 16 show schematic cross sections near the Cu bonding portion of the semiconductor member manufactured in each step, and FIG. 17 illustrates the bonding process between the first semiconductor member 10 and the second semiconductor member 20. Indicates.

First, a manufacturing method of the first semiconductor member 10 will be described with reference to FIGS. In this embodiment, although not shown, first, a first Cu barrier film 13 and a first Cu wiring portion 12 are formed in this order in a predetermined region on one surface of the first SiO ₂ layer 11 (underlying insulating layer). At this time, the first Cu wiring portion 12 is formed so as to be embedded in one surface of the first SiO ₂ layer 11 (so that the first Cu wiring portion 12 is exposed on the surface).

Next, as shown in FIG. 5, the first Cu diffusion prevention film 14 is formed on the surface of the semiconductor member made of the first SiO ₂ layer 11, the first Cu wiring part 12, and the first Cu barrier film 13 on the first Cu wiring part 12 side. Form. The first SiO ₂ layer 11, the first Cu wiring portion 12, the first Cu barrier film 13, and the first Cu diffusion prevention film 14 are manufactured by a conventional method for manufacturing a semiconductor device such as a solid-state imaging device (for example, Japanese Patent Laid-Open No. 2004-63859 It can be formed in the same manner as in (

Next, a first interlayer insulating film 15 is formed on the first Cu diffusion preventing film 14. Specifically, for example, a SiO ₂ film or a carbon-containing silicon oxide (SiOC) film having a thickness of about 50 to 500 nm is formed on the first Cu diffusion prevention film 14 to form the first interlayer insulating film 15. To do. The first interlayer insulating film 15 can be formed by, for example, a CVD (Chemical Vapor Deposition) method or a spin coating method.

  Next, as shown in FIG. 6, a resist film 150 is formed on the first interlayer insulating film 15. Then, a patterning process is performed on the resist film 150 using a photolithography technique, and the resist film 150 in the formation region of the first Cu bonding portion 16 is removed to form an opening 150a.

  Next, dry etching is performed on the surface of the semiconductor member on which the resist film 150 is formed on the side of the opening 150a using, for example, a conventionally known magnetron etching apparatus. Thereby, the region of the first interlayer insulating film 15 exposed in the opening 150a of the resist film 150 is etched. In this etching process, as shown in FIG. 7, the first interlayer insulating film 15 and the first Cu diffusion prevention film 14 in the region of the opening 150a of the resist film 150 are removed, and the opening of the first interlayer insulating film 15 is removed. The first Cu wiring part 12 is exposed at 15a. In the present embodiment, the opening diameter of the opening 15a of the first interlayer insulating film 15 is, for example, about 4 to 100 μm.

Thereafter, the etched surface is subjected to, for example, an ashing process using oxygen (O ₂ ) plasma and a cleaning process using an organic amine chemical solution. Thereby, the resist film 150 remaining on the first interlayer insulating film 15 and the residual deposits generated by the etching process are removed.

Next, as shown in FIG. 8, Ti, Ta, Ru, or those on the first interlayer insulating film 15 and the first Cu wiring part 12 exposed in the opening 15 a of the first interlayer insulating film 15. A first Cu barrier layer 17 made of nitride is formed. Specifically, for example, by using a technique such as RF (Radio Frequency) sputtering method, the first Cu barrier layer 17 having a thickness of about 5 to 50 nm is formed in the Ar / N ₂ atmosphere with the first interlayer insulating film 15 and It is formed on the first Cu wiring part 12.

  Next, as shown in FIG. 9, a Cu film 151 is formed on the first Cu barrier layer 17 by using a technique such as sputtering or electrolytic plating. With this process, the Cu film 151 is embedded in the region of the opening 15 a of the first interlayer insulating film 15.

  Next, the semiconductor member on which the Cu film 151 is formed is heated at about 100 to 400 ° C. for about 1 to 60 minutes in a nitrogen atmosphere or in vacuum using a heating device such as a hot plate or a sinter annealing device. By this heat treatment, the Cu film 151 is tightened to form a dense Cu film 151.

  Thereafter, as shown in FIG. 10, unnecessary portions of the Cu film 151 and the first Cu barrier layer 17 are removed by a chemical mechanical polishing (CMP) method. Specifically, the surface on the Cu film 151 side is polished by CMP until the first interlayer insulating film 15 is exposed on the surface.

  In this embodiment, the various processes of FIGS. 5 to 10 described above are performed to produce the first semiconductor member 10. Next, a method for manufacturing the second semiconductor member 20 will be described with reference to FIGS.

First, similarly to the first semiconductor member 10 (step of FIG. 5), a second Cu barrier film 23 and a second Cu wiring portion 22 are formed in this order in a predetermined region on one surface of the second SiO ₂ layer 21. To do. Next, a second Cu diffusion prevention film 24 is formed on the surface of the semiconductor member composed of the second SiO ₂ layer 21, the second Cu wiring part 22, and the second Cu barrier film 23 on the second Cu wiring part 22 side.

Next, a second interlayer insulating film 25 is formed on the second Cu diffusion preventing film 24. Specifically, for example, a second interlayer insulating film 25 is formed by forming a SiO ₂ film or a SiOC film having a thickness of about 50 to 500 nm on the second Cu diffusion preventing film 24. Such a second interlayer insulating film 25 can be formed by, for example, a CVD method or a spin coating method. Next, an interfacial Cu barrier film 28 having a thickness of about 5 to 100 nm is formed on the second interlayer insulating film 25 by using a method such as CVD or spin coating. Next, an SiO ₂ film or SiOC film having a thickness of about 50 to 200 nm is formed on the interface Cu barrier film 28 by using a method such as a CVD method or a spin coating method to form an insulating film 152. .

  Next, as illustrated in FIG. 11, a resist film 153 is formed over the insulating film 152. Then, a patterning process is performed on the resist film 153 by using a photolithography technique, and the resist film 153 in the formation region of the second Cu bonding portion 26 is removed to form an opening 153a. Note that the opening diameter of the opening 153a is smaller than that of the opening 150a of the resist film 150 formed in the step of FIG.

  However, the manufacturing process of the semiconductor member in which the opening 153a is formed in the resist film 153 described above is not limited to the example illustrated in FIG. 11. For example, the resist film 153 is provided directly on the interface Cu barrier film 28, and The opening 153a may be formed. FIG. 12 shows a schematic cross-sectional view of the semiconductor member when the opening 153a is formed by this method.

  However, when the technique shown in FIG. 12 is adopted, a Cu film is formed directly on the interface Cu barrier film 28 via the second Cu barrier layer 27, and then the second Cu is polished by CMP treatment. A joint portion 26 is formed. However, since the interface Cu barrier film 28 is usually a film that is difficult to polish by the CMP process, when the technique shown in FIG. 12 is adopted, the uncut portion of the Cu film remains at the interface Cu barrier film 28 during the CMP process. It may occur above.

  In contrast, in the method of forming the opening 153a shown in FIG. 11, since the insulating film 152 is formed on the interface Cu barrier film 28, the insulating film 152 is also polished together during the CMP process of the Cu film, so that the Cu The uncut portion of the film can be eliminated more reliably. That is, from the viewpoint of preventing uncut portions of the Cu film when forming the second Cu bonding portion 26, the formation method of the opening 153a shown in FIG. 11 is more preferable than the formation method of the opening 153a shown in FIG.

  Next, a dry etching process is performed on the surface of the semiconductor member on which the resist film 153 is formed on the opening 153a side using, for example, a conventionally known magnetron etching apparatus. Thereby, the region of the insulating film 152 exposed in the opening 153a of the resist film 153 is etched. In this etching process, as shown in FIG. 13, the insulating film 152, the interfacial Cu barrier film 28, the second interlayer insulating film 25, and the second Cu diffusion prevention film 24 in the region of the opening 153a are removed, and the second interlayer The second Cu wiring part 22 is exposed in the opening 25 a of the insulating film 25. In the present embodiment, the opening diameter of the opening 25a of the second interlayer insulating film 25 is about 1 to 95 μm, for example.

Thereafter, the etched surface is subjected to, for example, an ashing process using oxygen (O ₂ ) plasma and a cleaning process using an organic amine chemical solution. As a result, the resist film 153 remaining on the insulating film 152 and the residual deposit generated in the etching process are removed.

Next, as shown in FIG. 14, Ti, Ta, Ru, or a nitride thereof is formed on the insulating film 152 and on the second Cu wiring portion 22 exposed in the opening 25 a of the second interlayer insulating film 25. A second Cu barrier layer 27 is formed. Specifically, the second Cu barrier layer 27 having a thickness of about 5 to 50 nm is formed on the insulating film 152 and the second Cu wiring part 22 in an Ar / N ₂ atmosphere using a technique such as RF sputtering. Form.

  Next, as shown in FIG. 15, a Cu film 154 is formed on the second Cu barrier layer 27 by using a technique such as sputtering or electrolytic plating. With this process, the Cu film 154 is embedded in the region of the opening 25 a of the second interlayer insulating film 25.

  Next, the semiconductor member on which the Cu film 154 is formed is heated at about 100 to 400 ° C. for about 1 to 60 minutes in a nitrogen atmosphere or in vacuum using a heating apparatus such as a hot plate or a sinter annealing apparatus. By this heat treatment, the Cu film 154 is tightened to form a dense Cu film 154.

  Then, as shown in FIG. 16, unnecessary portions of the Cu film 154, the second Cu barrier layer 27, and the insulating film 152 are removed by a chemical mechanical polishing (CMP) method. Specifically, the surface on the Cu film 154 side is polished by the CMP method until the interface Cu barrier film 28 is exposed on the surface. In this embodiment, the various processes of FIGS. 11 to 16 described above are performed to produce the second semiconductor member 20.

  Next, the first semiconductor member 10 (FIG. 10) and the second semiconductor member 20 (FIG. 16) manufactured by the above procedure are bonded together. The specific processing content of this bonding process (joining process) is as follows.

First, a reduction process is performed on the surface of the first semiconductor member 10 on the first Cu bonding portion 16 side and the surface of the second semiconductor member 20 on the second Cu bonding portion 26 side, and an oxide film on the surface of each Cu bonding portion. (Oxide) is removed. Thereby, clean Cu is exposed on the surface of each Cu junction. At this time, as the reduction process, for example, a wet etching process using a chemical solution such as formic acid or a dry etching process using plasma of Ar, NH ₃ , H ₂ or the like is used.

  Next, as shown in FIG. 17, the surface of the first semiconductor member 10 on the first Cu bonding portion 16 side and the surface of the second semiconductor member 20 on the second Cu bonding portion 26 side are brought into contact (bonded together). At this time, the first Cu bonding portion 16 and the second Cu bonding portion 26 corresponding to the first Cu bonding portion 16 are aligned so that they are bonded together.

Next, in a state where the first semiconductor member 10 and the second semiconductor member 20 are bonded together, the bonded member is annealed using a heating device such as a hot plate or a RTA (Rapid Thermal Annealing) device, for example, and the first Cu bonding portion 16 and the second Cu joint 26 are joined. Specifically, for example, the bonded member is heated in an N ₂ atmosphere at atmospheric pressure or in a vacuum at about 100 to 400 ° C. for about 5 minutes to 2 hours.

  Further, by this bonding process, the interface Cu barrier film 28 is arranged in a region including a surface region that is not bonded to the second Cu bonding portion 26 in the surface region on the bonding interface Sj side of the first Cu bonding portion 16. More specifically, as shown in FIG. 3, the interface Cu barrier film 28 is disposed in a region including the region of the bonding interface Sj where the first Cu bonding portion 16 and the second interlayer insulating film 25 face each other.

  In this embodiment, the Cu—Cu bonding process is performed in this way. The manufacturing process of the semiconductor device 1 other than the above-described bonding process can be the same as the conventional manufacturing method of a semiconductor device such as a solid-state imaging device (see, for example, Japanese Patent Application Laid-Open No. 2007-234725).

  As described above, in the semiconductor device 1 of this embodiment, the first Cu member 16 of the first semiconductor member 10 and the second interlayer insulating film 25 of the second semiconductor member 20 are in a region including the bonding interface region facing each other. The interfacial Cu barrier film 28 is provided. Therefore, in the present embodiment, even when a bonding misalignment occurs at the time of bonding of the semiconductor members, a contact region between the Cu bonding portion and the interlayer insulating film does not occur at the bonding interface Sj. Problems with electrical characteristics can be eliminated.

  Further, in the present embodiment, as described above, the surface area on the bonding side of the first Cu bonding portion 16 is made sufficiently larger than that of the second Cu bonding portion 26. Therefore, in this embodiment, even if a bonding misalignment occurs when the first semiconductor member 10 and the second semiconductor member 20 are bonded, the contact area (contact resistance) between the Cu bonding portions does not change, and the semiconductor device 1 It is possible to suppress the deterioration of the electrical characteristics (performance). That is, in the present embodiment, an increase in contact resistance at the bonding interface Sj can be suppressed, so that an increase in power consumption of the semiconductor device 1 and a delay in processing speed can be suppressed.

  Furthermore, in this embodiment, since the interface Cu barrier film 28 is provided between the first Cu bonding portion 16 and the second interlayer insulating film 25, the adhesion between them can be improved. Thereby, in this embodiment, the joint strength between the 1st semiconductor member 10 and the 2nd semiconductor member 20 can be increased.

  From the above, in the present embodiment, it is possible to further suppress the deterioration of the electrical characteristics at the bonding interface, and it is possible to provide the semiconductor device 1 having the bonding interface Sj with higher reliability.

<2. Second Embodiment>
[Configuration of semiconductor device]
18 and 19 show a schematic configuration of the semiconductor device according to the second embodiment. 18 is a schematic cross-sectional view in the vicinity of the bonding interface of the semiconductor device according to the second embodiment, and FIG. It is. 18 and 19 show only the configuration near one joint interface for the sake of simplicity. Further, in the semiconductor device 2 of the present embodiment shown in FIGS. 18 and 19, the same components as those of the semiconductor device 1 of the first embodiment shown in FIGS.

  As shown in FIG. 18, the semiconductor device 2 includes a first semiconductor member 30 (first semiconductor portion), a second semiconductor member 40 (second semiconductor portion), and an interface Cu barrier film 50 (interface barrier film, interface barrier). Part).

The first semiconductor member 30 includes a first semiconductor substrate (not shown), a first SiO ₂ layer 11, a first Cu wiring portion 12, a first Cu barrier film 13, a first Cu diffusion prevention film 14, a first interlayer insulating film 15, and a first Cu. The junction 16, the first Cu barrier layer 17, and the first Cu seed layer 31 are included.

  As is clear from a comparison between FIG. 18 and FIG. 3, the first semiconductor member 30 of the present embodiment is the same as the first semiconductor member 10 of the first embodiment. The first Cu seed layer 31 is provided between them. The other configuration of the first semiconductor member 30 is the same as the corresponding configuration of the first semiconductor member 10 of the first embodiment. Therefore, only the configuration of the first Cu seed layer 31 will be described here.

  As described above, the first Cu seed layer 31 (seed layer) is provided between the first Cu junction 16 and the first Cu barrier layer 17 and is formed so as to cover the first Cu junction 16.

  The first Cu seed layer 31 is formed of a Cu layer (Cu alloy layer) containing a metal material that easily reacts with oxygen. As the metal material contained in the first Cu seed layer 31, for example, a metal material that reacts more easily with oxygen than oxygen can be used. Specifically, metal materials such as Fe, Mn, V, Cr, Mg, Si, Ce, Ti, and Al can be used. Of these metal materials, Mn, Mg, Ti, or Al is a material suitable for a semiconductor device. Further, from the viewpoint of reducing the wiring resistance of the bonding interface Si, it is particularly preferable to use Mn or Ti as the metal material contained in the first Cu seed layer 31.

The second semiconductor member 40 includes a second semiconductor substrate (not shown), a second SiO ₂ layer 21, a second Cu wiring part 22, a second Cu barrier film 23, a second Cu diffusion prevention film 24, a second interlayer insulating film 25, and a second Cu. The bonding portion 26, the second Cu barrier layer 27, and the second Cu seed layer 41 are included.

  As apparent from the comparison between FIG. 18 and FIG. 3, the second semiconductor member 40 of the present embodiment omits the interface Cu barrier film 28 in the second semiconductor member 20 of the first embodiment, and The second Cu seed layer 41 is provided between the 2Cu joint portion 26 and the second Cu barrier layer 27. Other configurations of the second semiconductor member 40 are the same as the corresponding configurations of the second semiconductor member 20 of the first embodiment. Therefore, only the configuration of the second Cu seed layer 41 will be described here.

  As described above, the second Cu seed layer 41 is provided between the second Cu junction 26 and the second Cu barrier layer 27 and is formed so as to cover the second Cu junction 26. Similar to the first Cu seed layer 31, the second Cu seed layer 41 is formed of a Cu layer (Cu alloy layer) containing a metal material that easily reacts with oxygen. The metal material contained in the second Cu seed layer 41 can be appropriately selected from the various metal materials described for the first Cu seed layer 31. In the present embodiment, the metal material included in the second Cu seed layer 41 is the same as the metal material included in the first Cu seed layer 31.

  The interfacial Cu barrier film 50 is formed by applying a heat treatment (annealing process) when the first semiconductor member 30 and the second semiconductor member 40 are bonded to each other to a metal material included in each Cu seed layer and each interlayer insulating film (mainly the second insulating film). It is a film (self-forming film) produced by reaction with oxygen in the interlayer insulating film 25). Therefore, the interface Cu barrier film 50 is formed in a region of the bonding interface Sj where the first Cu bonding portion 16 of the first semiconductor member 30 and the second interlayer insulating film 25 of the second semiconductor member 40 face each other. It is composed of an oxide film such as MnOx, MgOx, TiOx, AlOx.

  In FIG. 18, in order to clarify the formation position of the interfacial Cu barrier film 50, the interfacial Cu barrier film 50 extends from the side surface of the second Cu bonding portion 26 to the side surface of the first Cu barrier layer 17 along the bonding interface Sj. The example formed over is shown. However, the formation region of the interface Cu barrier film 50 is not limited to this example.

  The interfacial Cu barrier film 50 is a film for preventing Cu from diffusing from the Cu junction to the interlayer insulating film via the opposing region of the first Cu junction 16 and the second interlayer insulating film 25. Therefore, the interface Cu barrier film 50 may be formed at least in the facing region between the first Cu junction 16 and the second interlayer insulating film 25 at the junction interface Sj. The formation region of the interface Cu barrier film 50 adjusts, for example, the annealing conditions during the bonding process between the first semiconductor member 30 and the second semiconductor member 40, the content of the metal material in each Cu seed layer, and the like. Can be set as appropriate.

[Semiconductor Device Manufacturing Method]
Next, a method for manufacturing the semiconductor device 2 of this embodiment will be described with reference to FIGS. 20 to 23 show schematic cross sections in the vicinity of the Cu bonding portion of the semiconductor member manufactured in each step, and FIG. 24 shows a bonding process between the first semiconductor member 30 and the second semiconductor member 40. Indicates. Further, in the following description, in the description of the process similar to the manufacturing method of the semiconductor device of the first embodiment, the drawings (FIGS. 5 to 17) of the process of the first embodiment are appropriately referred to.

First, in the present embodiment, a first Cu barrier film 13 and a first Cu wiring portion are formed on the first SiO ₂ layer 11 in the same manner as the manufacturing process of the first semiconductor member 10 of the first embodiment described in FIG. 12 and the first Cu diffusion barrier film 14 are formed in this order. Next, in the same manner as the manufacturing process of the first semiconductor member 10 of the first embodiment described with reference to FIGS. 6 and 7, the first interlayer insulating film 15 (first oxide film) is formed on the first Cu diffusion preventing film 14. And the opening 15a is formed. Also in this embodiment, the opening diameter of the opening 15a of the first interlayer insulating film 15 is about 4 to 100 μm, for example. Then, in the same manner as the manufacturing process of the first semiconductor member 10 of the first embodiment described in FIG. 8 above, on the first interlayer insulating film 15 and on the first Cu wiring part 12 exposed in the opening 15a. Then, the first Cu barrier layer 17 is formed.

Next, as shown in FIG. 20, the first Cu seed layer 31 (with a thickness of about 5 to 50 nm is formed on the first Cu barrier layer 17 in an Ar / N ₂ atmosphere using a technique such as RF sputtering. For example, a CuMn layer, a CuAl layer, a CuMg layer, a CuTi layer, etc.) are formed.

  Next, as shown in FIG. 21, a Cu film 155 is formed on the first Cu seed layer 31 by using a technique such as sputtering or electrolytic plating. With this process, the Cu film 155 is embedded in the region of the opening 15 a of the first interlayer insulating film 15.

  Next, the semiconductor member on which the Cu film 155 is formed is heated at about 100 to 400 ° C. for about 1 to 60 minutes in a nitrogen atmosphere or in vacuum using a heating device such as a hot plate or a sinter annealing device. By this heat treatment, the Cu film 155 is tightened to form a dense Cu film 155.

  Next, as shown in FIG. 22, unnecessary portions of the Cu film 155, the first Cu seed layer 31, and the first Cu barrier layer 17 are removed by a CMP method. Specifically, the surface on the Cu film 155 side is polished by CMP until the first interlayer insulating film 15 is exposed on the surface.

  In the present embodiment, the first semiconductor member 30 is produced as described above. In the present embodiment, the second semiconductor member 40 is produced in the same manner as the first semiconductor member 30 described above.

  FIG. 23 shows a schematic cross-sectional view of the second semiconductor member 40 manufactured in the present embodiment. However, in the present embodiment, when an opening is formed in the second interlayer insulating film 25 (second oxide film) during the production of the second semiconductor member 40, the opening diameter of the opening will be described with reference to FIG. The opening diameter of the first interlayer insulating film 15 is made smaller (about 4 to 100 μm). Specifically, the opening diameter of the opening in the second interlayer insulating film 25 is set to about 1 to 95 μm.

  Thereafter, the first semiconductor member 30 (FIG. 22) and the second semiconductor member 40 (FIG. 23) manufactured as described above are bonded together in the same manner as in the first embodiment.

Specifically, first, reduction treatment is performed on the surface of the first semiconductor member 30 on the first Cu bonding portion 16 side and the surface of the second semiconductor member 40 on the second Cu bonding portion 26 side, and each Cu bonding portion is subjected to reduction treatment. The oxide film (oxide) on the surface is removed to expose clean Cu on the surface of each Cu junction. At this time, as the reduction process, for example, a wet etching process using a chemical solution such as formic acid or a dry etching process using plasma of Ar, NH ₃ , H ₂ or the like is used.

Next, as shown in FIG. 24, the surface of the first semiconductor member 30 on the first Cu bonding portion 16 side and the surface of the second semiconductor member 40 on the second Cu bonding portion 26 side are brought into contact (bonded together). Then, in a state where the first semiconductor member 30 and the second semiconductor member 40 are bonded together, the bonded member is annealed using a heating device such as a hot plate or an RTA device, for example, and the first Cu bonding portion 16 and the second Cu member are then annealed. The joint portion 26 is joined. Specifically, for example, the bonded member is heated in an N ₂ atmosphere at atmospheric pressure or in a vacuum at about 100 to 400 ° C. for about 5 minutes to 2 hours.

  Further, during the bonding process described above, the metal material (for example, Mn, Mg, Ti, Al, etc.) in each Cu seed layer selectively reacts with oxygen in the interlayer insulating film (mainly the second interlayer insulating film 25). To do. Thereby, the interface Cu barrier film 50 is formed in the region of the bonding interface Sj where the first Cu bonding portion 16 of the first semiconductor member 30 and the second interlayer insulating film 25 of the second semiconductor member 40 face each other. That is, by the bonding process, the interface Cu barrier film 50 is provided in a region including a surface region that is not bonded to the second Cu bonding portion 26 in the surface region on the bonding interface Sj side of the first Cu bonding portion 16.

  In the present embodiment, the Cu—Cu bonding process is performed as described above. Note that the manufacturing process of the semiconductor device 2 other than the above-described bonding process can be the same as a conventional method for manufacturing a semiconductor device such as a solid-state imaging device (see, for example, Japanese Patent Application Laid-Open No. 2007-234725).

  As described above, also in the semiconductor device 2 of the present embodiment, the first Cu bonding portion 16 of the first semiconductor member 30 and the second interlayer insulating film 25 of the second semiconductor member 40 are the same as in the first embodiment. An interface Cu barrier film 50 is provided in the region of the bonding interface Sj facing each other. Therefore, also in this embodiment, the same effect as the first embodiment can be obtained.

  Further, when a Cu seed layer is provided and a Cu junction is formed on the Cu seed layer by electrolytic plating as in this embodiment, Cu in the Cu seed layer becomes the nucleus of the Cu plating film. Therefore, in this embodiment, the adhesion between the Cu junction and the interlayer insulating film can be improved.

<3. Third Embodiment>
[Configuration of semiconductor device]
25 and 26 show a schematic configuration of the semiconductor device according to the third embodiment. FIG. 25 is a schematic cross-sectional view of the vicinity of the bonding interface of the semiconductor device according to the third embodiment, and FIG. 26 is a bonding showing the positional relationship between each Cu bonding portion and the interface layer portion of the second Cu barrier layer described later. It is a schematic top view of the interface vicinity. 25 and 26, only the configuration near one bonding interface is shown for the sake of simplicity. Further, in the semiconductor device 3 of the present embodiment shown in FIGS. 25 and 26, the same components as those of the semiconductor device 1 of the first embodiment shown in FIGS.

  As shown in FIG. 25, the semiconductor device 3 includes a first semiconductor member 10 (first semiconductor portion) and a second semiconductor member 60 (second semiconductor portion). In addition, since the structure of the 1st semiconductor member 10 in the semiconductor device 3 of this embodiment is the same structure as that of the said 1st Embodiment (FIG. 3), description of the 1st semiconductor member 10 is abbreviate | omitted here. To do.

The second semiconductor member 60 includes a second semiconductor substrate (not shown), a second SiO ₂ layer 21, a second Cu wiring portion 22, a second Cu barrier film 23, a second Cu diffusion prevention film 24, a second interlayer insulating film 25, and a second Cu. It has the junction part 26 and the 2nd Cu barrier layer 61 (barrier metal layer).

  As apparent from the comparison between FIG. 25 and FIG. 3, the second semiconductor member 60 of the present embodiment omits the interface Cu barrier film 28 in the second semiconductor member 20 of the first embodiment, and The configuration of the 2Cu barrier layer 27 is changed. The other configuration of the second semiconductor member 60 is the same as the corresponding configuration of the second semiconductor member 20 of the first embodiment. Therefore, only the configuration of the second Cu barrier layer 61 will be described here.

  As shown in FIG. 25, the second Cu barrier layer 61 includes a barrier body 61a provided so as to cover the second Cu joint 26, and a junction interface Sj from an end of the barrier body 61a on the junction interface Sj side. Interface layer part 61b (interface barrier part) formed extending along the surface.

  That is, in the present embodiment, the interface of the second Cu barrier layer 61 is in the region of the junction interface Sj where the first Cu junction 16 of the first semiconductor member 10 and the second interlayer insulating film 25 of the second semiconductor member 60 face each other. The layer part 61b is disposed. Then, the interface layer portion 61b of the second Cu barrier layer 61 prevents Cu from diffusing from the Cu junction portion into the interlayer insulating film via the opposing region between the first Cu junction portion 16 and the second interlayer insulating film 25. . Therefore, in the present embodiment, even if the maximum bonding misalignment expected at the time of bonding occurs, a contact region between the first Cu bonding portion 16 and the second interlayer insulating film 25 does not occur at the bonding interface Sj. The width in the direction along the bonding interface Sj of the interface layer 61b is set. Note that the second Cu barrier layer 61 is formed of, for example, Ti, Ta, Ru, or a nitride thereof as in the first embodiment.

[Semiconductor Device Manufacturing Method]
Next, a method for manufacturing the semiconductor device 3 of this embodiment will be described with reference to FIGS. 27 to 33 show a schematic cross section near the Cu bonding portion of the semiconductor member manufactured in each step, and FIG. 34 shows the bonding process between the first semiconductor member 10 and the second semiconductor member 60. Indicates. Further, in the following description, in the description of the process similar to the manufacturing method of the semiconductor device of the first embodiment, the drawings (FIGS. 5 to 17) of the process of the first embodiment are appropriately referred to. Furthermore, since the manufacturing method of the first semiconductor member 10 of the present embodiment is the same as that of the first embodiment (FIGS. 5 to 10), the manufacturing method of the first semiconductor member 10 will be described here. A description will be given of a manufacturing method of the second semiconductor member 60 and a Cu—Cu bonding method, which are omitted.

First, in the present embodiment, a second Cu barrier film 23 and a second Cu wiring portion are formed on the second SiO ₂ layer 21 in the same manner as the manufacturing process of the first semiconductor member 10 of the first embodiment described in FIG. 22 and the second Cu diffusion prevention film 24 are formed in this order. Next, a second interlayer insulating film 25 is formed on the second Cu diffusion prevention film 24 in the same manner as the manufacturing process of the first semiconductor member 10 of the first embodiment described with reference to FIG.

  Next, as shown in FIG. 27, a resist film 156 is formed on the second interlayer insulating film 25. Then, a patterning process is performed on the resist film 156 using a photolithography technique, and the resist film 156 in the formation region of the second Cu barrier layer 61 is removed to form an opening 156a. As a result, the second interlayer insulating film 25 is exposed in the opening 156 a of the resist film 156.

  Next, a dry etching process is performed on the surface of the semiconductor member on which the resist film 156 is formed on the opening 156a side using, for example, a conventionally known magnetron etching apparatus. Thereby, the region of the second interlayer insulating film 25 exposed in the opening 156a of the resist film 156 is etched. At this time, the second interlayer insulating film 25 is removed by etching to about 10 to 50 nm. As a result, as shown in FIG. 28, a recess 25b having a depth of about 10 to 50 nm is formed on the surface of the second interlayer insulating film 25.

Thereafter, the etched surface is subjected to, for example, an ashing process using oxygen (O ₂ ) plasma and a cleaning process using an organic amine chemical solution. Thus, the resist film 156 remaining on the second interlayer insulating film 25 and the residual deposits generated by the etching process are removed.

  Next, as shown in FIG. 29, a resist film 157 is formed again on the second Cu diffusion preventing film 24. Then, a patterning process is performed on the resist film 157 using a photolithography technique, and the resist film 157 in the formation region of the barrier body 61a of the second Cu barrier layer 61 is removed to form an opening 157a. As a result, the bottom of the recess 25 b of the second interlayer insulating film 25 is exposed in the opening 157 a of the resist film 157.

  Next, a dry etching process is performed on the surface of the semiconductor member on which the resist film 157 is formed on the opening 157a side using, for example, a conventionally known magnetron etching apparatus. Thereby, a partial region of the recess 25b of the second interlayer insulating film 25 exposed in the opening 157a of the resist film 157 is etched.

  In this etching process, as shown in FIG. 30, the second interlayer insulating film 25 and the second Cu diffusion prevention film 24 in the region of the opening 157a are removed, and the second Cu wiring portion is formed in the opening 25a of the second interlayer insulating film 25. 22 is exposed. In the present embodiment, the opening diameter of the opening 25a of the second interlayer insulating film 25 is, for example, about 1 to 95 μm. Note that the region of the recess 25 b of the second interlayer insulating film 25 that is not removed by this etching process becomes the formation region of the interface layer portion 61 b of the second Cu barrier layer 61.

Thereafter, the etched surface is subjected to, for example, an ashing process using oxygen (O ₂ ) plasma and a cleaning process using an organic amine chemical solution. As a result, the resist film 157 remaining on the second interlayer insulating film 25 and the residual deposits generated by the etching process are removed.

Next, as shown in FIG. 31, Ti, Ta, Ru, or those on the second interlayer insulating film 25 and the second Cu wiring part 22 exposed in the opening 25 a of the second interlayer insulating film 25. A second Cu barrier layer 61 made of nitride is formed. Specifically, for example, using a technique such as RF sputtering, a second Cu barrier layer 61 having a thickness of about 5 to 50 nm is formed on the second interlayer insulating film 25 and in the Ar / N ₂ atmosphere. It is formed on the 2Cu wiring part 22. With this process, the barrier body 61 a is formed on the second Cu wiring part 22 exposed in the opening 25 a of the second interlayer insulating film 25 and on the side surface of the second interlayer insulating film 25. In addition, the interface layer portion 61 b is formed on the concave portion 25 b of the second interlayer insulating film 25 by this process.

  Next, as shown in FIG. 32, a Cu film 158 is formed on the second Cu barrier layer 61 by using a technique such as sputtering or electrolytic plating. By this processing, the Cu film 158 is embedded in the region of the opening 25a of the second interlayer insulating film 25.

  Next, the semiconductor member on which the Cu film 158 is formed is heated at about 100 to 400 ° C. for about 1 to 60 minutes in a nitrogen atmosphere or in vacuum using a heating device such as a hot plate or a sinter annealing device. By this heat treatment, the Cu film 158 is tightened to form a dense Cu film 158.

  Then, as shown in FIG. 33, unnecessary portions of the Cu film 158 and the second Cu barrier layer 61 are removed by a chemical mechanical polishing (CMP) method. At this time, the processing conditions of the CMP method are adjusted so that the interface layer portion 61 b remains on the recess 25 b of the second interlayer insulating film 25. Specifically, the surface on the Cu film 158 side is polished by CMP until the second interlayer insulating film 25 is exposed on the surface. In the present embodiment, the second semiconductor member 60 is produced as described above.

  Thereafter, the second semiconductor member 60 (FIG. 33) manufactured as described above and the first semiconductor member 10 (FIG. 10) manufactured in the same manner as the first embodiment are combined with the first semiconductor member 60 (FIG. 10). Bonding is performed in the same manner as in the embodiment.

Specifically, first, reduction treatment is performed on the surface of the first semiconductor member 10 on the first Cu bonding portion 16 side and the surface of the second semiconductor member 60 on the second Cu bonding portion 26 side, and each Cu bonding portion is subjected to reduction treatment. The oxide film (oxide) on the surface is removed to expose clean Cu on the surface of each Cu junction. At this time, as the reduction process, for example, a wet etching process using a chemical solution such as formic acid or a dry etching process using plasma of Ar, NH ₃ , H ₂ or the like is used.

Next, as shown in FIG. 34, the surface of the first semiconductor member 10 on the first Cu bonding portion 16 side and the surface of the second semiconductor member 60 on the second Cu bonding portion 26 side are brought into contact (bonded together). Then, in a state where the first semiconductor member 10 and the second semiconductor member 60 are bonded together, the bonded member is annealed using a heating device such as a hot plate or an RTA device, for example, and the first Cu bonding portion 16 and the second Cu bonding are annealed. The joint portion 26 is joined. Specifically, for example, the bonded member is heated in an N ₂ atmosphere at atmospheric pressure or in a vacuum at about 100 to 400 ° C. for about 5 minutes to 2 hours.

  In addition, by this bonding process, the interface layer portion 61b of the second Cu barrier layer 61 is disposed in a region including a surface region that is not bonded to the second Cu bonding portion 26 in the surface region on the bonding interface Sj side of the first Cu bonding portion 16. . More specifically, as shown in FIG. 25, the interface layer portion 61b of the second Cu barrier layer 61 is formed in a region including the region of the bonding interface Sj where the first Cu bonding portion 16 and the second interlayer insulating film 25 face each other. Be placed.

  In the present embodiment, the Cu—Cu bonding process is performed as described above. Note that the manufacturing process of the semiconductor device 2 other than the above-described bonding process can be the same as a conventional method for manufacturing a semiconductor device such as a solid-state imaging device (see, for example, Japanese Patent Application Laid-Open No. 2007-234725).

  As described above, also in the present embodiment, the first Cu bonding portion 16 of the first semiconductor member 10 and the second interlayer insulating film 25 of the second semiconductor member 60 face each other as in the first embodiment. In the region of the bonding interface Sj, the interface layer portion 61b of the second Cu barrier layer 61 is provided. Therefore, also in this embodiment, the same effect as the first embodiment can be obtained.

<4. Various modifications and reference examples>
Next, modified examples of the semiconductor devices of the various embodiments described above will be described.

[Modification 1]
In the semiconductor device 1 (FIG. 3) of the first embodiment, the second Cu diffusion prevention film 24, the second interlayer insulating film 25, and the interface Cu barrier film are formed on the second Cu wiring portion 22 of the second semiconductor member 20. Although the structural example which provides 28 was demonstrated, this indication is not limited to this. For example, only the interface Cu barrier film may be provided on the second Cu wiring part 22.

  FIG. 35 shows an example (Modification 1). FIG. 35 is a schematic cross-sectional view of the vicinity of the junction interface Sj of the semiconductor device 4 of Modification 1. In the semiconductor device 4 of this example shown in FIG. 35, the same components as those of the semiconductor device 1 of the first embodiment shown in FIG.

  The semiconductor device 4 of this example includes a first semiconductor member 10 and a second semiconductor member 70 as shown in FIG. In addition, since the structure of the 1st semiconductor member 10 in the semiconductor device 4 of this example is the structure similar to that of the said 1st Embodiment (FIG. 3), description of the 1st semiconductor member 10 is abbreviate | omitted here. .

The second semiconductor member 70 includes a second semiconductor substrate (not shown), a second SiO ₂ layer 21, a second Cu wiring part 22, a second Cu barrier film 23, an interface Cu barrier film 71 (interface barrier film, interface barrier part), A 2Cu junction 26 and a second Cu barrier layer 27 are provided. In the second semiconductor member 70 of this example, the configuration other than the interface Cu barrier film 71 is the same as the corresponding configuration of the second semiconductor member 20 of the first embodiment.

The interfacial Cu barrier film 71 (Cu diffusion preventing film) is provided on the second SiO ₂ layer 21, the second Cu wiring part 22, and the second Cu barrier film 23, and is provided so as to cover the side part of the second Cu barrier layer 27. It is done. Therefore, in this example, the interface Cu barrier film 71 not only prevents the diffusion of Cu from the Cu junction to the interlayer insulating film, but also prevents the second Cu diffusion of the second semiconductor member 20 of the first embodiment. It also serves the same role as the film 24 and the second interlayer insulating film 25.

  The interface Cu barrier film 71 can be formed of a material such as SiN, SiON, SiCN, or organic resin, for example, as with the interface Cu barrier film 28 of the first embodiment.

The second semiconductor member 70 of this example can be manufactured as follows, for example. First, the second Cu barrier film 23 and the second Cu wiring portion 22 are formed on the second SiO ₂ layer 21 in the same manner as the manufacturing process of the first semiconductor member 10 of the first embodiment described in FIG. Form in order. Next, an interfacial Cu barrier film 71 having a thickness of about 5 to 500 nm is formed on the second SiO ₂ layer 21, the second Cu wiring portion 22, and the second Cu barrier film 23.

  Next, as shown in FIG. 36, a resist film 159 is formed on the interface Cu barrier film 71. Thereafter, a patterning process is performed on the resist film 159 by using a photolithography technique, and the resist film 159 in the formation region of the second Cu bonding portion 26 is removed to form an opening 159a. As a result, the interface Cu barrier film 71 is exposed in the opening 159 a of the resist film 159. Thereafter, the second semiconductor member 70 of this example is manufactured in the same manner as the manufacturing process of the second semiconductor member 20 of the first embodiment described with reference to FIGS.

  In the configuration of this example, the surface region not bonded to the second Cu bonding portion 26 in the surface region on the bonding interface Sj side of the first Cu bonding portion 16 is in contact with the interface Cu barrier film 71. Therefore, even in the configuration of this example, Cu at each Cu junction does not diffuse into the external oxide film, and thus the same effect as in the first embodiment can be obtained.

[Modification 2]
In the second embodiment, the example in which the Cu seed layer is provided in both the first semiconductor member 30 and the second semiconductor member 40 (see FIG. 18) has been described, but the present disclosure is not limited thereto. A Cu seed layer may be provided at least on the semiconductor member having a larger surface area on the bonding side of the Cu bonding portion. For example, in the semiconductor device 2 shown in FIG. 18, a Cu seed layer may be provided only between the first Cu junction 16 of the first semiconductor member 30 and the first Cu barrier layer 17.

  Also in this case, the second semiconductor member 40 facing the metal material such as Mn, Mg, Ti, Al, etc. in the Cu seed layer of the first semiconductor member 30 with the bonding interface Sj sandwiched by the annealing process at the time of bonding. It reacts with oxygen in the second interlayer insulating film 25. As a result, also in this example, as in the second embodiment, the bonding interface Sj where the first Cu bonding portion 16 of the first semiconductor member 30 and the second interlayer insulating film 25 of the second semiconductor member 40 face each other. An interface barrier film is formed in this region, and the same effect as in the first embodiment can be obtained.

[Modification 3]
In the third embodiment, the example in which the interface layer portion 61b of the second Cu barrier layer 61 is formed so as to be embedded in the bonding-side surface of the second interlayer insulating film 25 in the second semiconductor member 60 has been described. Is not limited to this. For example, the interface layer portion 61b may be provided on the bonding side surface of the second interlayer insulating film 25.

  FIG. 37 shows an example (Modification 3). FIG. 37 is a schematic cross-sectional view of the vicinity of the junction interface Sj of the semiconductor device 5 of Modification 3. In addition, in the semiconductor device 5 of this example shown in FIG. 37, the same components as those of the semiconductor device 3 of the third embodiment shown in FIG.

  The semiconductor device 5 of this example includes a first semiconductor member 10 and a second semiconductor member 80 as shown in FIG. In addition, since the structure of the 1st semiconductor member 10 in the semiconductor device 5 of this example is the same structure as that of the said 3rd Embodiment (FIG. 25), description of the 1st semiconductor member 10 is abbreviate | omitted here. .

The second semiconductor member 80 includes a second semiconductor substrate (not shown), a second SiO ₂ layer 21, a second Cu wiring portion 22, a second Cu barrier film 23, a second Cu diffusion prevention film 24, a second interlayer insulating film 81, and a second Cu. The bonding portion 26, the second Cu barrier layer 61, and the interface Cu barrier film 82 are included.

In the second semiconductor member 80 of this example, the configuration of the second semiconductor substrate (not shown), the _second SiO ₂ layer 21, the second Cu wiring portion 22, the second Cu barrier film 23, and the second Cu diffusion prevention film 24 is as follows. The configuration is the same as the corresponding configuration of the second semiconductor member 60 of the third embodiment. Moreover, the structure of the 2nd Cu junction part 26 of this example and the 2nd Cu barrier layer 61 is a structure similar to the structure corresponding to the 2nd semiconductor member 60 of the said 3rd Embodiment.

  In this example, the interface layer portion 61 b of the second Cu barrier layer 61 is provided on the bonding-side surface of the second interlayer insulating film 81. Therefore, the concave portion 25b is not formed on the surface of the second interlayer insulating film 81 as in the third embodiment.

  Furthermore, in this example, the interface Cu barrier film 82 is formed on the surface of the second interlayer insulating film 81 and is provided so as to cover the side part (side surface) of the interface layer part 61 b of the second Cu barrier layer 61. . At this time, the film thickness of the interface Cu barrier film 82 and the film thickness of the interface layer part 61b are substantially the same, and the surface of the interface Cu barrier film 82 on the bonding interface Sj side and the bonding interface Sj of the interface layer part 61b. The surface on the side should be substantially flush. The interface Cu barrier film 82 can be formed of a material such as SiN, SiON, SiCN, or organic resin, for example, as with the interface Cu barrier film 28 of the first embodiment.

  In this example, in the bonding interface Sj, in the region other than the bonding region between the first Cu bonding portion 16 and the second Cu bonding portion 26, the first Cu bonding portion 16 is connected to the interface layer portion 61b and / or the interface of the second Cu barrier layer 61. The state is in contact with the Cu barrier film 82. Therefore, even in the configuration of this example, it is possible to prevent the Cu at each Cu junction from diffusing into the interlayer insulating film, so that the same effect as in the first embodiment can be obtained.

  In this example, the interface Cu barrier film 82 may not be provided. In this case, a void is formed around the side portion of the interface layer portion 61b of the second Cu barrier layer 61. This void prevents the Cu at each Cu junction from diffusing into the interlayer insulating film. Therefore, the same effect as the first embodiment can be obtained. However, from the viewpoint of the bonding strength of the bonding interface Sj, it is preferable to provide the interface Cu barrier film 82 so as to cover the side part of the interface layer part 61b as shown in FIG.

[Modification 4]
In the above-described various embodiments and various modifications, the example in which the electrode film of each joint portion is formed of a Cu film has been described, but the present disclosure is not limited thereto. For example, the bonding portion may be formed of a metal film formed of Al, W, Ti, TiN, Ta, TaN, Ru, or the like, or a stacked film thereof.

  For example, in the first embodiment, Al (aluminum) can be used as the electrode material of the joint. In this case, the interface Cu barrier film 28 can be formed of a material such as SiN, SiON, SiCN, or resin, as in the first embodiment. In this case, it is preferable that the metal barrier layer covering the Al junction portion is composed of a multilayer film (Ti / TiN laminated film) in which a Ti film and a TiN film are laminated in this order from the Al junction side.

  Further, for example, in the configuration of the second embodiment, Al can be used as the electrode material of the joint portion. However, in this case, since Al is a material that easily reacts with oxygen, it is not necessary to provide a seed layer (Cu seed layer) for generating an interface barrier film.

  Here, FIG. 38 shows a schematic configuration cross section in the vicinity of the junction interface Sj of the semiconductor device when the junction is formed of Al in the configuration of the second embodiment. In FIG. 38, only the configuration near the Al junction is shown, and the configuration of the wiring portion is omitted for the sake of simplicity. In addition, in the semiconductor device 6 shown in FIG. 38, the same components as those in the semiconductor device 2 of the second embodiment shown in FIG.

  As shown in FIG. 38, the semiconductor device 6 of this example includes a first semiconductor member 91, a second semiconductor member 92, and an interface barrier film 97. The first semiconductor member 91 is provided between the first interlayer insulating film 15, the first Al junction 93 formed so as to be embedded in the junction-side surface thereof, and the first interlayer insulating film 15 and the first Al junction 93. And a first barrier metal layer 94. The second semiconductor member 92 includes a second interlayer insulating film 25, a second Al junction 95 formed so as to be embedded in the junction-side surface thereof, and a gap between the second interlayer insulating film 25 and the second Al junction 95. And a second barrier metal layer 96 provided.

  Also in the example shown in FIG. 38, a part of Al in the first Al joint portion 93 is opposed across the joint interface Sj by the annealing process performed when the first semiconductor member 91 and the second semiconductor member 92 are joined. The second semiconductor member 92 reacts with oxygen in the second interlayer insulating film 25. As a result, the interface barrier film 97 is formed in the region of the bonding interface Sj where the first Al bonding portion 93 and the second interlayer insulating film 25 face each other. Therefore, also in this configuration example, as in the first embodiment, the bonding strength between the first semiconductor member 91 and the second semiconductor member 92 can be increased, and a semiconductor having a more reliable bonding interface. A device 6 can be obtained.

  Further, for example, in the first embodiment, for example, W (tungsten) can be used as the electrode material of the bonding portion. In this case, the interface Cu barrier film 28 can be formed of a material such as SiN, SiON, SiCN, or resin, as in the first embodiment. In this case, the metal barrier layer covering the W junction is preferably formed of a multilayer film (Ti / TiN laminated film) in which a Ti film and a TiN film are laminated in this order from the W junction side. Since W is a metal material that hardly reacts with oxygen (it is difficult to self-generate the interface barrier film), it is difficult to use W for the joint portion of the configuration of the second embodiment.

[Modification 5]
In the various embodiments and various modifications described above, the example in which the metal films to which signals are supplied is bonded at the bonding interface Sj has been described, but the present disclosure is not limited thereto. Even when the metal films to which no signal is supplied are bonded at the bonding interface Sj, the Cu-Cu bonding technique described in the various embodiments and various modifications can be applied.

  For example, also when joining dummy electrodes, the Cu-Cu joining technique demonstrated in the said various embodiment and various modifications is applicable. In addition, for example, in a solid-state imaging device, when a light shielding film is formed by bonding metal films between a sensor unit and a logic circuit unit, the Cu—Cu described in the above various embodiments and various modifications. Joining techniques can be applied.

[Reference Example 1]
In the second embodiment, the example in which the dimension (surface area) of the surface of the first Cu bonding portion 16 on the bonding interface Sj side is different from that of the second Cu bonding portion 26 has been described. However, the Cu—Cu bonding technique described in the second embodiment is also applied to a semiconductor device in which the surface shape and dimensions on the bonding interface Sj side of the first Cu bonding portion are the same as those of the second Cu bonding portion. Is possible.

  FIG. 39 shows an example (Reference Example 1). FIG. 39 is a schematic cross-sectional view of the vicinity of the junction interface Sj of the semiconductor device 100 of this example. In addition, in the semiconductor device 100 of this example shown in FIG. 39, the same components as those of the semiconductor device 2 of the second embodiment shown in FIG.

  As shown in FIG. 39, the semiconductor device 100 of this example includes a first semiconductor member 101, a second semiconductor member 40, and an interface Cu barrier film 105. In addition, since the structure of the 2nd semiconductor member 40 in the semiconductor device 100 of this example is the same structure as that of the said 2nd Embodiment (FIG. 18), description of the 2nd semiconductor member 40 is abbreviate | omitted here. .

The first semiconductor member 101 includes a first semiconductor substrate (not shown), a first SiO ₂ layer 11, a first Cu wiring portion 12, a first Cu barrier film 13, a first Cu diffusion prevention film 14, a first interlayer insulating film 15, and a first Cu. A junction 102, a first Cu barrier layer 103, and a first Cu seed layer 104 are provided.

  In this example, the surface shape and dimensions of the first Cu bonding portion 102 on the bonding interface Sj side are the same as those of the second Cu bonding portion 26. The other configuration of the first semiconductor member 101 is the same as the corresponding configuration of the first semiconductor member 30 of the second embodiment.

  Also in this example, similarly to the second embodiment, the surface of the first semiconductor member 101 on the first Cu bonding portion 102 side and the surface of the second semiconductor member 40 on the second Cu bonding portion 26 side are bonded. As a result, the semiconductor device 100 is manufactured. At this time, if a bonding misalignment occurs between the two Cu bonding portions, a metal material such as Mn, Mg, Ti, Al, etc. in each Cu seed layer faces each other with the bonding interface Sj interposed therebetween by an annealing process at the time of bonding. It reacts selectively with oxygen in the interlayer insulating film. As a result, as shown in FIG. 39, the region of the bonding interface Sj where the first Cu bonding portion 102 and the second interlayer insulating film 25 face each other, and the second Cu bonding portion 26 and the first interlayer insulating film 15 face each other. An interface Cu barrier film 105 is formed in each region of the bonding interface Sj.

  As described above, also in the semiconductor device 100 of this example, the interface Cu barrier film 105 is formed in the region of the bonding interface Sj where the Cu bonding portion of one semiconductor member and the interlayer insulating film of the other semiconductor member face each other. Provided. Therefore, also in this example, the same effect as the second embodiment can be obtained.

[Reference Example 2]
In the reference example 1, the Cu—Cu bonding described in the second embodiment is applied to the semiconductor device in which the surface shape and dimensions on the bonding interface Sj side of the first Cu bonding portion are the same as those of the second Cu bonding portion. An example of applying the technology has been described. Here, a configuration example is described in which the semiconductor device 100 of Reference Example 1 is further combined with the Cu—Cu bonding technique described in the first embodiment.

  FIG. 40 shows an example (Reference Example 2). FIG. 40 is a schematic sectional view of the vicinity of the junction interface Sj of the semiconductor device 110 of this example. In addition, in the semiconductor device 110 of this example shown in FIG. 40, the same reference numerals are given to the same components as those of the semiconductor device 100 of Reference Example 1 shown in FIG.

  As shown in FIG. 40, the semiconductor device 110 of this example includes a first semiconductor member 101, a second semiconductor member 120, and a first interface Cu barrier film 121. In addition, since the structure of the 1st semiconductor member 101 in the semiconductor device 110 of this example is the structure similar to that of the said reference example 1 (FIG. 39), description of the 1st semiconductor member 101 is abbreviate | omitted here.

The second semiconductor member 120 includes a second semiconductor substrate (not shown), a second SiO ₂ layer 21, a second Cu wiring portion 22, a second Cu barrier film 23, a second Cu diffusion prevention film 24, a second interlayer insulating film 25, and a second Cu. The bonding portion 26, the second Cu barrier layer 27, and the second Cu seed layer 41 are included. Further, the second semiconductor member 120 has a second interface Cu barrier film 122.

  As apparent from the comparison between FIG. 40 and FIG. 39, the second semiconductor member 120 of this example is the same as the second semiconductor member 40 of Reference Example 1 except that the second interface Cu barrier film is formed on the second interlayer insulating film 25. 122 is provided. In this example, the second interface Cu barrier film 122 is formed so that the surface of the second Cu bonding portion 26 on the bonding interface Sj side is substantially flush with the surface of the second interface Cu barrier film 122. The configuration of the second semiconductor member 120 other than the second interface Cu barrier film 122 is the same as the corresponding configuration of the second semiconductor member 40 of the first reference example.

  The second interface Cu barrier film 122 can be formed of a material such as SiN, SiON, SiCN, or organic resin, for example, as with the interface Cu barrier film 28 of the first embodiment. However, from the viewpoint of adhesion with the Cu film, it is particularly preferable to form the second interface Cu barrier film 122 with SiN.

  Also in this example, similarly to the second embodiment, the surface of the first semiconductor member 101 on the first Cu bonding portion 102 side and the surface of the second semiconductor member 120 on the second Cu bonding portion 26 side are bonded. As a result, the semiconductor device 110 is manufactured. At this time, if a bonding misalignment occurs between the two Cu bonding portions, a metal material such as Mn, Mg, Ti, Al, etc. in each Cu seed layer faces each other with the bonding interface Sj interposed therebetween by an annealing process at the time of bonding. It reacts selectively with oxygen in the interlayer insulating film. As a result, the first interface Cu barrier film 121 is formed in the bonding interface Sj region where the Cu bonding portion of one semiconductor member and the interlayer insulating film of the other semiconductor member face each other.

  However, in this example, as described above, the second interface Cu barrier film 122 is provided on the surface of the bonding interface Sj of the second semiconductor member 120. Therefore, in this example, the region of the bonding interface Sj where the first Cu bonding portion 102 and the second interlayer insulating film 25 face each other, and the bonding interface Sj where the second Cu bonding portion 26 and the first interlayer insulating film 15 face each other. A first interface Cu barrier film 121 is formed in one of the regions. Further, in the other of the region of the bonding interface Sj where the first Cu bonding portion 102 and the second interlayer insulating film 25 face each other and the region of the bonding interface Sj where the second Cu bonding portion 26 and the first interlayer insulating film 15 face each other. The second interface Cu barrier film 122 is disposed. In the example shown in FIG. 40, the second interface Cu barrier film 122 is provided in the former bonding interface Sj region, and the first interface Cu barrier film 121 is provided in the latter bonding interface Sj region.

  As described above, also in the semiconductor device 110 of this example, the first interface Cu barrier film is formed in the region of the bonding interface Sj where the Cu bonding portion of one semiconductor member and the interlayer insulating film of the other semiconductor member face each other. 121 or the second interface Cu barrier film 122 is provided. Therefore, also in this example, the same effect as the first and second embodiments can be obtained.

<5. Fourth Embodiment>
Usually, when Cu-Cu bonding is performed by bonding the first semiconductor member and the second semiconductor member having different areas of the Cu bonding portion, the Cu bonding portion of one semiconductor member and the interlayer insulating film of the other semiconductor member Touch. FIG. 41 shows a schematic cross-sectional view in the vicinity of the bonding interface in the bonding example. In the semiconductor device 650 shown in FIG. 41, the same components as those in the semiconductor device 1 of the first embodiment shown in FIG.

  In this case, as shown in FIG. 41, Cu diffuses from the first Cu junction 16 having a larger area than the second Cu junction 26 into the second interlayer insulating film 25 (dotted arrow in FIG. 41), and at the junction interface Sj. Electrical characteristics deteriorate, and the reliability of the Cu junction and the semiconductor device 650 is impaired. On the other hand, in the various embodiments described above, an interface barrier film is formed at the bonding interface between the first Cu bonding portion 16 and the second interlayer insulating film 25, and Cu from the first Cu bonding portion 16 to the second interlayer insulating film 25 is formed. Can be prevented and the above problem can be solved.

  Further, as another method for preventing the diffusion of Cu at the bonding interface described above, the surface of the interlayer insulating film on the bonding interface side of at least one of the first semiconductor member and the second semiconductor member is made to be more than the bonding side surface of the Cu bonding portion. A method is also conceivable in which the two are bonded together in the retracted state. That is, a method is also conceivable in which both of the first semiconductor member and the second semiconductor member are bonded together in a state in which at least one Cu bonding portion protrudes toward the bonding interface.

  FIG. 42 is a schematic cross-sectional view of the vicinity of the bonding interface when both of the first semiconductor member and the second semiconductor member are bonded together in a state where the Cu bonding portions protrude toward the bonding interface. In the semiconductor device 660 shown in FIG. 42, the same components as those in the semiconductor device 1 of the first embodiment shown in FIG.

  In this case, a gap is formed at the junction interface Sj (between the first interlayer insulating film 663 and the second interlayer insulating film 664) between the first semiconductor member 661 and the second semiconductor member 662. As a result, a gap is formed between the second interlayer insulating film 664 and the first Cu junction 16 and Cu diffusion from the first Cu junction 16 to the second interlayer insulating film 664 is prevented. However, in this case, as shown in FIG. 42, outside air (open arrows) enters the gaps of the bonding interface Sj and contaminates the surface of the first Cu bonding portion 16, thereby causing electrical characteristics at the bonding interface Sj. As a result, the reliability of the Cu junction and the semiconductor device is impaired.

  Therefore, in the fourth embodiment, a configuration example that can prevent the above-described influence of the outside air in a semiconductor device having a configuration in which a gap is formed between the second interlayer insulating film and the first Cu junction will be described.

[Configuration of semiconductor device]
43 and 44 show a schematic configuration of the semiconductor device according to the fourth embodiment. FIG. 43 is a schematic cross-sectional view of the vicinity of the bonding interface of the semiconductor device according to the fourth embodiment, and FIG. 44 is the vicinity of the bonding interface showing the positional relationship between each Cu bonding portion and the void defined in the bonding interface. FIG. 43 and 44, only the configuration near one junction interface is shown for the sake of simplicity. Also, in the semiconductor device 130 of the present embodiment shown in FIG. 43, the same reference numerals are given to the same configurations as those of the semiconductor device 1 of the first embodiment shown in FIG.

  As shown in FIG. 43, the semiconductor device 130 includes a first semiconductor member 131 (first semiconductor portion) and a second semiconductor member 132 (second semiconductor portion).

The first semiconductor member 131 includes a first semiconductor substrate (not shown), a first SiO ₂ layer 11, a first Cu wiring portion 12, a first Cu barrier film 13, a first Cu diffusion prevention film 14, a first interlayer insulating film 15, and a first Cu. The bonding portion 133 and the first Cu barrier layer 17 are provided.

  As is clear from comparison between FIG. 43 and FIG. 3, the first semiconductor member 131 of the present embodiment has a second interlayer insulation in the surface region on the bonding interface Sj side of the first semiconductor member 10 of the first embodiment. The surface area of the first Cu bonding portion 16 facing the film 25 is provided with a recess. The other configuration of the first semiconductor member 131 is the same as the corresponding configuration of the first semiconductor member 10 of the first embodiment.

The second semiconductor member 132 includes a second semiconductor substrate (not shown), a second SiO ₂ layer 21, a second Cu wiring portion 22, a second Cu barrier film 23, a second Cu diffusion prevention film 24, a second interlayer insulating film 25, and A second Cu junction 26 is provided.

  As is clear from a comparison between FIG. 43 and FIG. 3, the second semiconductor member 132 of this embodiment has a configuration in which the interface Cu barrier film 28 is omitted from the second semiconductor member 20 of the first embodiment. The other configuration of the second semiconductor member 132 is the same as the corresponding configuration of the second semiconductor member 20 of the first embodiment.

  In the semiconductor device 130 of the present embodiment, as shown in FIG. 43, in the surface region on the bonding interface Sj side of the first semiconductor member 131, the first Cu junction portion facing the second interlayer insulating film 25 of the second semiconductor member 132. A recess 134 is provided in the surface region 133. As a result, a gap is formed in the region of the bonding interface Sj where the first Cu bonding portion 133 of the first semiconductor member 131 and the second interlayer insulating film 25 of the second semiconductor member 132 face each other, and the first Cu bonding portion 133 is A structure that is not in direct contact with the second interlayer insulating film 25 can be formed.

  That is, in the semiconductor device 130 of the present embodiment, the interface barrier portion is formed by the recess 134 of the first Cu bonding portion 133 and the surface region portion (surface region portion) on the bonding interface Sj side of the second semiconductor member 132 facing the recess 134. Is configured. Further, in the present embodiment, as shown in FIG. 43, voids defined by the recesses 134 of the first Cu bonding portion 133 and the surface of the second interlayer insulating film 25 on the bonding interface Sj side are various films around it. It will be in the state sealed by.

[Semiconductor Device Manufacturing Method]
Next, a method for manufacturing the semiconductor device 130 of this embodiment will be described with reference to FIGS. 45 and 46 show schematic cross sections in the vicinity of the Cu bonding portion of the semiconductor member manufactured in each step, and FIGS. 47 and 48 show the bonding process between the first semiconductor member 131 and the second semiconductor member 132. The state of is shown.

  First, in the present embodiment, the first semiconductor member 131 is manufactured in the same manner as the manufacturing process of the first semiconductor member 10 of the first embodiment described with reference to FIGS.

  Moreover, in this embodiment, the 2nd semiconductor member 132 is produced similarly to the production process of the 1st semiconductor member 10 of 1st Embodiment demonstrated in FIGS. 5-10 (state of FIG. 46). However, at this time, in the step of forming an opening corresponding to the formation region of the second Cu bonding portion 26 and the second Cu barrier layer 27 in the second interlayer insulating film 25 (corresponding to the step of FIG. 7), the opening of the opening is not formed. The aperture is about 1 to 95 μm.

Next, a reduction treatment is performed on the surface of the first semiconductor member 131 on the first Cu bonding portion 133 side and the surface of the second semiconductor member 132 on the second Cu bonding portion 26 side, and an oxide film on the surface of each Cu bonding portion (Oxide) is removed to expose clean Cu on the surface of each Cu junction. At this time, as the reduction process, for example, a wet etching process using a chemical solution such as formic acid or a dry etching process using plasma of Ar, NH ₃ , H ₂ or the like is used.

  Next, as shown in FIG. 47, the surface of the first semiconductor member 131 on the first Cu bonding portion 133 side and the surface of the second semiconductor member 132 on the second Cu bonding portion 26 side are brought into contact (bonded together).

Then, in a state in which the first semiconductor member 131 and the second semiconductor member 132 are bonded together, the bonded member is annealed using a heating device (annealing device) such as a hot plate or an RTA device, for example, and the first Cu bonding portion 133 and the 2nd Cu junction part 26 are joined (state of FIG. 48). Specifically, for example, the bonded member is heated in an N ₂ atmosphere at atmospheric pressure or in a vacuum at about 100 to 400 ° C. for about 5 minutes to 2 hours.

  In the present embodiment, the Cu film of the first Cu bonding portion 133 is further tightened by the annealing process shown in FIG. Note that, in the bonding interface Sj, the contact region between the first Cu bonding portion 133 and the second interlayer insulating film 25 is a region having a weak adhesion compared to other regions. Therefore, the annealing process shown in FIG. 48 causes the first Cu bonding portion 133 to contract in this contact region, and the surface of the first Cu bonding portion 133 moves backward in the direction away from the bonding interface Sj. As a result, as shown in FIG. 48, in the surface region of the first semiconductor member 131 on the bonding interface Sj side, a recess 134 is formed in the surface region of the first Cu bonding portion 133 that faces the second interlayer insulating film 25.

  That is, by the annealing process shown in FIG. 48, voids are formed in the bonding interface Sj between the first Cu bonding portion 133 and the second interlayer insulating film 25, and the voids are formed in the semiconductor device 130 by various films around it. A sealed structure is formed. In the annealing process shown in FIG. 48, in order to form the concave portion 134, for example, at a temperature higher than the annealing temperature of the annealing process performed to form a dense Cu-bonding portion at the time of manufacturing each semiconductor member. It is preferable to anneal.

  In the present embodiment, the Cu—Cu bonding process is performed as described above. The manufacturing process of the semiconductor device 130 other than the above-described bonding process can be performed in the same manner as a conventional method for manufacturing a semiconductor device such as a solid-state imaging device (see, for example, Japanese Patent Application Laid-Open No. 2007-234725).

  As described above, in the semiconductor device 130 of the present embodiment, a gap is formed in the bonding interface Sj between the first Cu bonding portion 133 and the second interlayer insulating film 25, and a structure in which the two are not in direct contact is formed. Therefore, also in this embodiment, similarly to the first embodiment, it is possible to prevent the diffusion of Cu from the first Cu junction 133 to the second interlayer insulating film 25. In addition, since the area | region of the space | gap formed in the joining interface Sj is sufficiently small compared with the whole area | region of the joining interface Sj, the contact | adherence performance of the joining interface Sj in the structure of this embodiment becomes comparable to that of the said various embodiment. .

  Further, in the semiconductor device 130 of the present embodiment, the void formed at the bonding interface Sj between the first Cu bonding portion 133 and the second interlayer insulating film 25 is sealed with various peripheral films. Therefore, in the present embodiment, it is possible to prevent the outside air from entering the Cu junction, and to ensure the reliability of the semiconductor device 130.

<6. Fifth Embodiment>
In the fifth embodiment, another configuration example of the semiconductor device in which a gap is provided at the bonding interface between the first Cu bonding portion of the first semiconductor member and the second interlayer insulating film of the second semiconductor member will be described.

[Configuration of semiconductor device]
49 and 50 show a schematic configuration of the semiconductor device according to the fifth embodiment. FIG. 49 is a schematic cross-sectional view of the vicinity of the bonding interface of the semiconductor device according to the fifth embodiment. FIG. 50 illustrates the space between each Cu bonding portion and the interface Cu barrier film and the void defined in the bonding interface. It is a schematic top view of the vicinity of the bonding interface showing the positional relationship. 49 and 50, only the configuration near one junction interface is shown for the sake of simplicity. In addition, in the semiconductor device 140 of this embodiment shown in FIG. 49, the same reference numerals are given to the same configurations as those of the semiconductor device 130 of the fourth embodiment shown in FIG.

  As shown in FIG. 49, the semiconductor device 140 includes a first semiconductor member 131 (first semiconductor portion) and a second semiconductor member 20 (second semiconductor portion).

  The configuration of the first semiconductor member 131 is the same as that of the fourth embodiment (FIG. 43). That is, the configuration of the first semiconductor member 131 is opposed to the second interlayer insulating film 25 of the second semiconductor member 20 in the surface region on the bonding interface Sj side of the first semiconductor member 10 of the first embodiment (FIG. 3). It becomes the structure which provided the recessed part 134 in the surface area | region of the 1st Cu junction part 133 to do. On the other hand, the configuration of the second semiconductor member 20 is the same as that of the first embodiment (FIG. 3), and the interface Cu barrier film 28 is provided on the surface of the second interlayer insulating film 25 on the junction interface Sj side. It becomes the composition which was made.

  In the semiconductor device 140 of the present embodiment, as described above, the surface of the first Cu bonding portion 133 facing the interface Cu barrier film 28 of the second semiconductor member 20 in the surface region on the bonding interface Sj side of the first semiconductor member 131. A recess 134 is provided in the region. As a result, a void is formed at the bonding interface Sj where the first Cu bonding portion 133 of the first semiconductor member 131 and the interface Cu barrier film 28 of the second semiconductor member 20 face each other. In the present embodiment, as shown in FIG. 49, the voids defined by the recesses 134 of the first Cu bonding portion 133 and the surface on the bonding interface Sj side of the interface Cu barrier film 28 are formed by various peripheral films. It becomes sealed.

  That is, also in the present embodiment, the interface barrier portion is configured by the concave portion 134 of the first Cu bonding portion 133 and the surface region portion (surface region portion) on the bonding interface Sj side of the second semiconductor member 20 facing the concave portion 134. The In the present embodiment, the diffusion of Cu from the first Cu bonding portion 133 to the second interlayer insulating film 25 is prevented by the gap defined in the interface barrier portion and the interface Cu barrier film 28.

[Semiconductor Device Manufacturing Method]
Next, a method for manufacturing the semiconductor device 140 according to the present embodiment will be described with reference to FIGS. 51 and 52 show a schematic cross section near the Cu bonding portion of the semiconductor member manufactured in each step, and FIGS. 53 and 54 show the bonding process between the first semiconductor member 131 and the second semiconductor member 20. The state of is shown.

  First, in the present embodiment, the first semiconductor member 131 is manufactured in the same manner as the manufacturing process of the first semiconductor member 10 of the first embodiment described with reference to FIGS.

  Moreover, in this embodiment, the 2nd semiconductor member 20 is produced similarly to the production process of the 2nd semiconductor member 20 of 1st Embodiment demonstrated in FIGS. 11-16 (state of FIG. 52). However, in this embodiment, the interface Cu barrier film 28 (for example, a SiN film, a SiCN film, etc.) has a thickness of about 10 to 100 nm, and the interface Cu barrier film 28 is formed by a CVD method or a spin coating method. Further, in the present embodiment, in the step of forming openings corresponding to the formation regions of the second Cu bonding portion 26 and the second Cu barrier layer 27 in the second interlayer insulating film 25 (step of FIG. 13), the opening of the openings is opened. The aperture is about 4 to 100 μm.

Next, a reduction process is performed on the surface of the first semiconductor member 131 on the first Cu bonding portion 133 side and the surface of the second semiconductor member 20 on the second Cu bonding portion 26 side, and an oxide film on the surface of each Cu bonding portion (Oxide) is removed to expose clean Cu on the surface of each Cu junction. At this time, as the reduction process, for example, a wet etching process using a chemical solution such as formic acid or a dry etching process using plasma of Ar, NH ₃ , H ₂ or the like is used.

  Next, as shown in FIG. 53, the surface of the first semiconductor member 131 on the first Cu bonding portion 133 side and the surface of the second semiconductor member 20 on the second Cu bonding portion 26 side are brought into contact (bonded together).

Then, in a state in which the first semiconductor member 131 and the second semiconductor member 20 are bonded together, the bonded member is annealed using a heating device (annealing device) such as a hot plate or an RTA device, for example, and the first Cu bonding portion 133 and the 2nd Cu junction part 26 are joined (state of FIG. 54). Specifically, for example, the bonded member is heated in an N ₂ atmosphere at atmospheric pressure or in a vacuum at about 100 to 400 ° C. for about 5 minutes to 2 hours.

  Also in this embodiment, the Cu film of the first Cu bonding portion 133 is further tightened by the annealing process shown in FIG. 54, as in the fourth embodiment. At this time, at the bonding interface Sj, in the contact region between the first Cu bonding portion 133 and the interface Cu barrier film 28, the first Cu bonding portion 133 in the region contracts and the surface of the first Cu bonding portion 133 moves away from the bonding interface Sj. Retreat in the direction. As a result, as shown in FIG. 54, in the surface region on the bonding interface Sj side of the first semiconductor member 131, a recess 134 is formed in the surface region of the first Cu bonding portion 133 that faces the interface Cu barrier film 28.

  That is, by the annealing process shown in FIG. 54, a void is formed in the bonding interface Sj between the first Cu bonding portion 133 and the interface Cu barrier film 28, and the void is formed in the semiconductor device 140 by various films around it. A sealed structure is formed. In the annealing process shown in FIG. 54, in order to form the concave portion 134, for example, at a temperature higher than the annealing temperature of the annealing process performed to form a dense Cu-bonding portion at the time of manufacturing each semiconductor member. It is preferable to anneal.

  In the present embodiment, the Cu—Cu bonding process is performed as described above. The manufacturing process of the semiconductor device 140 other than the bonding process described above can be the same as the conventional manufacturing method of a semiconductor device such as a solid-state imaging device (see, for example, Japanese Patent Application Laid-Open No. 2007-234725).

  As described above, in the semiconductor device 140 of the present embodiment, a gap is formed in the region of the bonding interface Sj between the first Cu bonding portion 133 and the interface Cu barrier film 28, and a structure in which the two are not in direct contact is formed. In the present embodiment, the interface Cu barrier film 28 is formed in a region facing the concave portion 134 of the first Cu bonding portion 133. Therefore, in this embodiment, the diffusion of Cu from the first Cu junction 133 to the second interlayer insulating film 25 can be more reliably prevented.

  Further, in the semiconductor device 140 of the present embodiment, the gap formed at the bonding interface Sj between the first Cu bonding portion 133 and the interface Cu barrier film 28 is sealed by various films around it. Therefore, in the present embodiment, as in the fourth embodiment, it is possible to prevent the intrusion of outside air into the Cu bonding portion, and to ensure the reliability of the semiconductor device 140.

  In the present embodiment, the example in which the technology for forming the interface barrier portion described in the fourth embodiment is applied to the semiconductor device 1 (FIG. 3) of the first embodiment has been described. It is not limited to. For example, the interface barrier portion forming technique described in the fourth embodiment is applied to the semiconductor device 2 (FIG. 18) of the second embodiment and the semiconductor device 3 (FIG. 25) of the third embodiment. Also good. Furthermore, for example, the interface barrier portion formation technique described in the fourth embodiment may be applied to the semiconductor devices of the various modifications (FIGS. 35 to 38 and the like).

  The interface barrier portion formation technique described in the fourth embodiment can also be applied to the semiconductor devices of the various reference examples (FIGS. 39 and 49). However, in this case, at the bonding interface Sj, not only the surface region of the first Cu bonding portion facing the second interlayer insulating film but also the surface region of the second Cu bonding portion facing the first interlayer insulating film. A recess is formed.

<7. Various application examples>
The semiconductor device described in the various embodiments and various modifications, and the manufacturing method (Cu-Cu bonding method) are various electronic devices that require a Cu-Cu bonding process by bonding two substrates together during manufacturing. It is applicable to. In particular, the Cu—Cu bonding methods of the various embodiments and the various modifications described above are suitable for manufacturing a solid-state imaging device, for example.

[Application Example 1]
FIG. 55 shows a configuration example of the semiconductor device described in the various embodiments and various modifications and a semiconductor image sensor module to which the manufacturing method can be applied. The semiconductor image sensor module 200 shown in FIG. 55 is configured by joining a first semiconductor chip 201 and a second semiconductor chip 202.

  The first semiconductor chip 201 includes a photodiode forming region 203, a transistor forming region 204, and an analog / digital converter array 205. The transistor formation region 204 and the analog / digital converter array 205 are stacked in this order on the photodiode formation region 203.

  In addition, a through contact portion 206 is formed in the analog / digital converter array 205. The through contact portion 206 is formed so that one end thereof is exposed on the surface of the analog / digital converter array 205 on the second semiconductor chip 202 side.

  On the other hand, the second semiconductor chip 202 is constituted by a memory array, and a contact portion 207 is formed therein. The contact portion 207 is formed so that one end thereof is exposed on the surface of the second semiconductor chip 202 on the first semiconductor chip 201 side.

  Then, the first semiconductor chip 201 and the second semiconductor chip 202 are joined by thermocompression bonding in a state where the through contact portion 206 and the contact portion 207 are in contact with each other, and the semiconductor image sensor module 200 is manufactured. In the semiconductor image sensor module 200 having such a configuration, the number of pixels per unit area can be increased and the thickness thereof can be reduced.

  In the semiconductor image sensor module 200 of this example, for example, in the bonding process of the first semiconductor chip 201 and the second semiconductor chip 202, the Cu—Cu bonding methods of the above-described various embodiments and various modifications can be applied. In this case, the reliability of the bonding interface between the first semiconductor chip 201 and the second semiconductor chip 202 can be further improved.

[Application 2]
FIG. 56 is a schematic cross-sectional view of a main part of a backside illumination type solid-state imaging device to which the semiconductor device described in the above various embodiments and various modifications and its manufacturing method can be applied.

  A solid-state imaging device 300 illustrated in FIG. 56 is configured by bonding a first semiconductor substrate 310 having a pixel array in a semi-finished product state and a second semiconductor substrate 320 having a logic circuit in a semi-finished product state. . In the solid-state imaging device 300 shown in FIG. 56, the planarization film 330, the on-chip color filter 331, and the on-chip are formed on the surface of the first semiconductor substrate 310 opposite to the second semiconductor substrate 320 side. Microlenses 332 are stacked in this order.

  The first semiconductor substrate 310 has a P-type semiconductor well region 311 and a multilayer wiring layer 312, and the semiconductor well region 311 is disposed on the planarizing film 330 side. In the semiconductor well region 311, for example, a photodiode (PD), a floating diffusion (FD), MOS transistors (Tr1, Tr2) constituting pixels, and MOS transistors (Tr3, Tr4) constituting control circuits are formed. The Further, in the multilayer wiring layer 312, a plurality of metal wirings 314 formed via the interlayer insulating film 313 and the interlayer insulating film 313 formed to connect the metal wiring 314 and the corresponding MOS transistor are formed. A connection conductor 315 is formed.

  On the other hand, the second semiconductor substrate 320 includes, for example, a semiconductor well region 321 formed on the surface of a silicon substrate, and a multilayer wiring layer 322 formed on the first semiconductor substrate 310 side of the semiconductor well region 321. In the semiconductor well region 321, MOS transistors (Tr6, Tr7, Tr8) constituting a logic circuit are formed. Further, in the multilayer wiring layer 322, a plurality of metal wirings 324 formed via the interlayer insulating film 323 and the interlayer insulating film 323 are formed to connect the metal wiring 324 and the corresponding MOS transistor. A connection conductor 325 is formed.

  The various embodiments according to the present disclosure described above and the Cu—Cu bonding techniques of the various modifications described above can also be applied to the back-illuminated solid-state imaging device 300 configured as described above.

[Application Example 3]
The solid-state imaging device to which the above-described various embodiments and various modifications are applied is a solid-state imaging device, for example, a camera system such as a digital camera or a video camera, a mobile phone having an imaging function, or other devices having an imaging function. It can be applied to electronic devices such as devices. In Application Example 3, a camera will be described as an example of a configuration of an electronic device.

  FIG. 57 shows a schematic configuration of a camera according to Application Example 3. Note that FIG. 57 illustrates a configuration example of a video camera that can capture still images or moving images.

  The camera 400 in this example includes a solid-state imaging device 401, an optical system 402 that guides incident light to the light receiving sensor unit of the solid-state imaging device 401, a shutter device 403 provided between the solid-state imaging device 401 and the optical system 402, And a drive circuit 404 that drives the imaging device 401. Furthermore, the camera 400 includes a signal processing circuit 405 that processes an output signal of the solid-state imaging device 401.

  The solid-state imaging device 401 is manufactured using the above-described various embodiments and various modifications of the Cu—Cu bonding technology according to the present disclosure. Configurations and functions of other parts are as follows.

  The optical system (optical lens) 402 forms image light (incident light) from a subject on an imaging surface (not shown) of the solid-state imaging device 401. Thereby, signal charges are accumulated in the solid-state imaging device 401 for a certain period. The optical system 402 may be composed of an optical lens group including a plurality of optical lenses. The shutter device 403 controls the light irradiation period and the light shielding period of the incident light to the solid-state imaging device 401.

  The drive circuit 404 supplies drive signals to the solid-state imaging device 401 and the shutter device 403. The drive circuit 404 controls the signal output operation to the signal processing circuit 405 of the solid-state imaging device 401 and the shutter operation of the shutter device 403 by the supplied drive signal. That is, in this example, a signal transfer operation from the solid-state imaging device 401 to the signal processing circuit 405 is performed by a drive signal (timing signal) supplied from the drive circuit 404.

  The signal processing circuit 405 performs various signal processes on the signal transferred from the solid-state imaging device 401. The signal (video signal) that has been subjected to various signal processing is stored in a storage medium (not shown) such as a memory, or is output to a monitor (not shown).

In addition, this indication can also take the following structures.
(1)
A first semiconductor portion having a first metal film formed on the surface on the bonding interface side;
A second metal film bonded to the first metal film at the bonding interface and having a surface area on the bonding interface side smaller than a surface area of the first metal film on the bonding interface side; A second semiconductor portion provided by being bonded to one semiconductor portion;
A semiconductor device comprising: an interface barrier portion provided in a region including a surface region not bonded to the second metal film in a surface region on the bonding interface side of the first metal film.
(2)
The second semiconductor part has an interface barrier film provided in a region including a surface region that is not bonded to the second metal film in a surface region on the bonding interface side of the first metal film,
The semiconductor device according to (1), wherein the interface barrier portion is configured by the interface barrier film.
(3)
The second semiconductor portion has an insulating film provided so as to cover a side portion of the second metal film;
The semiconductor device according to (2), wherein the interface barrier film is formed on a surface on the bonding interface side of the insulating film.
(4)
The semiconductor device according to (2), wherein the interface barrier film is formed of any one of SiN, SiON, SiCN, and an organic resin material.
(5)
The first semiconductor portion includes a first oxide film provided so as to cover a side portion of the first metal film, and a predetermined metal material provided between the first oxide film and the first metal film. A seed layer,
The second semiconductor part has a second oxide film provided so as to cover a side part of the second metal film;
The semiconductor device according to (2), wherein the interface barrier film includes an oxide film of the predetermined metal material.
(6)
The semiconductor device according to (5), wherein the predetermined metal material is any one of Mn, Mg, Ti, and Al.
(7)
A barrier body provided so that the second semiconductor part covers a side of the second metal film and a surface of the second metal film opposite to the bonding interface; and the barrier body A barrier metal layer including an interface layer portion formed extending from the end portion on the bonding interface side along the bonding interface;
The semiconductor device according to (1) or (2), wherein the interface barrier section includes the interface layer section of the barrier metal layer.
(8)
The semiconductor device according to (7), wherein the barrier metal layer is formed of any one of Ti, Ta, Ru, TiN, TaN, and RuN.
(9)
Of the surface region on the bonding interface side of the first semiconductor portion, a concave portion is provided in a surface region of the first metal film that is not bonded to the second metal film,
The interface barrier portion is configured by the concave portion of the first metal film and a surface region portion on the bonding interface side of the second semiconductor portion facing the concave portion, and the concave portion and the surface are formed on the interface barrier portion. The semiconductor device according to any one of (1) to (8), wherein an air gap defined and sealed by the region portion is formed.
(10)
The second semiconductor portion has an insulating film provided so as to cover a side portion of the second metal film;
The semiconductor device according to (9), wherein a surface region portion on the bonding interface side of the second semiconductor portion facing the concave portion is configured by the insulating film.
(11)
The second semiconductor part has an interface barrier film provided in a region including a surface region that is not bonded to the second metal film in a surface region on the bonding interface side of the first metal film,
The semiconductor device according to (9), wherein a surface region portion on the bonding interface side of the second semiconductor portion facing the recess is configured by the interface barrier film.
(12)
The semiconductor device according to any one of (1) to (11), wherein the first metal film and the second metal film are both Cu films.
(13)
A first semiconductor portion having a first metal film formed on a surface on the bonding interface side; and a surface area on the bonding interface side bonded to the first metal film at the bonding interface and the bonding of the first metal film A second semiconductor film having a second metal film smaller than the surface area on the interface side, the second semiconductor part being bonded to the first semiconductor part at the bonding interface, and a surface area on the bonding interface side of the first metal film A semiconductor device having an interface barrier portion provided in a region including a surface region that is not bonded to the second metal film,
An electronic device comprising: a signal processing circuit that processes an output signal of the semiconductor device.
(14)
Producing a first semiconductor part having a first metal film formed on the surface on the bonding interface side;
Producing a second semiconductor part having a second metal film whose surface area on the bonding interface side is smaller than the surface area on the bonding interface side of the first metal film;
The surface of the first semiconductor part on the first metal film side and the surface of the second semiconductor part on the second metal film side are bonded together to join the first metal film and the second metal film. And a step of providing an interface barrier portion in a region including a surface region not bonded to the second metal film in a surface region of the first metal film on the bonding interface side.

1,130 ... semiconductor device, 10,131 ... first semiconductor member, 11 ... first 1SiO ₂ layer, 12 ... first 1Cu wiring portion 13 ... second 1Cu barrier film, 14 ... first 1Cu diffusion preventing film, 15 ... first interlayer Insulating film 16, 133 ... 1st Cu junction, 17 ... 1st Cu barrier layer, 20, 132 ... 2nd semiconductor member, 21 ... _2nd SiO2 layer, 22 ... 2nd Cu wiring part, 23 ... 2nd Cu barrier film, 24 2nd Cu diffusion prevention film, 25 ... 2nd interlayer insulation film, 26 ... 2nd Cu junction part, 27 ... 2nd Cu barrier layer, 28 ... Interface Cu barrier film, 134 ... Recessed part

Claims (4)

A first semiconductor portion having a first metal film formed on the surface on the bonding interface side;
A second metal film bonded to the first metal film at the bonding interface and having a surface area on the bonding interface side smaller than a surface area of the first metal film on the bonding interface side; A second semiconductor portion provided by being bonded to one semiconductor portion;
An interface barrier portion provided in a region including a surface region not bonded to the second metal film in a surface region on the bonding interface side of the first metal film,
The interface barrier portion is composed of an insulating interface barrier film formed flush with the second metal film to be bonded to the first semiconductor portion at the bonding interface ;
The second semiconductor part has an insulating film provided so as to cover a side part of the second metal film, and the interface barrier film is formed on a surface of the insulating film on the bonding interface side.
Semiconductor device. The interface barrier film is formed of any one of SiN, SiON, SiCN, and an organic resin material .
The semiconductor device according to claim 1 . An electronic device comprising a semiconductor device and a signal processing circuit for processing an output signal of the semiconductor device ,
The semiconductor device includes:
A first semiconductor portion having a first metal film formed on the surface on the bonding interface side;
A second metal film bonded to the first metal film at the bonding interface and having a surface area on the bonding interface side smaller than a surface area of the first metal film on the bonding interface side; A second semiconductor portion provided by being bonded to one semiconductor portion;
An interface barrier portion provided in a region including a surface region not bonded to the second metal film in a surface region of the first metal film on the bonding interface side;
The interface barrier portion is composed of an insulating interface barrier film formed flush with the second metal film to be bonded to the first semiconductor portion at the bonding interface ;
The second semiconductor part has an insulating film provided so as to cover a side part of the second metal film, and the interface barrier film is formed on a surface of the insulating film on the bonding interface side.
Electronics. Producing a first semiconductor part having a first metal film formed on the surface on the bonding interface side;
A second metal film having a surface area on the bonding interface side smaller than a surface area on the bonding interface side of the first metal film, and the second metal film in a surface area on the bonding interface side of the first metal film; An interfacial barrier portion formed of an insulating interfacial barrier film that is formed flush with the second metal film so as to be joined to the first semiconductor portion at the joining interface in a region including a surface region that is not joined; An insulating film provided so as to cover a side portion of the second metal film, and the interface barrier film is formed on a surface of the insulating film on the bonding interface side.
Producing a second semiconductor part;
The surface of the first semiconductor part on the first metal film side and the surface of the second semiconductor part on the second metal film side are bonded together to join the first metal film and the second metal film. And steps
A method of manufacturing a semiconductor device including:

Images