JP2010129693A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which suppresses electromigration. <P>SOLUTION: The semiconductor device includes: a semiconductor substrate on which a semiconductor element is formed; an interlayer dielectric which is formed above the semiconductor substrate, contains moisture, and has a recessed part; a first barrier metal layer formed on an inner surface of the recessed part and having crystallinity of either one of amorphous or polycrystal; a second barrier metal layer formed on the first barrier metal layer and having other crystallinity of amorphous or polycrystal; a copper wiring formed on the second barrier metal layer; a copper diffusion preventing insulation film covering the copper wiring and formed on the interlayer dielectric; and a metal oxide layer formed on an interface of the copper wiring and copper diffusion preventing insulation film. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a copper wiring and a manufacturing method thereof.

  In copper multilayer wiring of semiconductor devices, defects due to electromigration are a problem. One factor of electromigration is insufficient adhesion between the insulating film covering the copper wiring and the copper wiring.

  Along with the miniaturization of wiring, a low dielectric constant material (so-called low-k material) having a low dielectric constant is applied to the interlayer insulating film in order to suppress signal delay. By using a porous structure having pores, the dielectric constant of the insulating film can be reduced, but the wiring material can easily diffuse into the insulating film. In particular, copper is likely to diffuse into an insulating film containing Si—O.

In order to prevent such diffusion, a barrier metal layer is formed as a base of the copper wiring (see, for example, Japanese Patent Application Laid-Open Nos. 2008-47675 and 2007-251164 for the barrier metal layer). Generally, Ta, Ti, TaN, TiN, etc. are used as the barrier metal layer, but these have higher resistance than copper. The specific resistance of copper is 1.7 × 10 ⁻⁶ Ω · cm, while the specific resistances of Ta and Ti are 15 × 10 ⁻⁶ Ω · cm and 80 × 10 ⁻⁶ Ω · cm, respectively.

As the wiring becomes finer and the proportion of the barrier metal layer in the wiring increases, the resistance of the entire wiring increases. According to the technology roadmap indicated by ITRS 2006, the specific resistance of the wiring of the hp32 nm generation (wiring pitch 64 nm) is 4.83 × 10 ⁻⁶ Ω · cm.

JP 2008-47675 A JP 2007-251164 A

  An object of the present invention is to provide a semiconductor device in which electromigration is suppressed and a method for manufacturing the same.

  According to one aspect of the present invention, a semiconductor substrate having a semiconductor element formed thereon, an interlayer insulating film containing moisture and having a recess formed above the semiconductor substrate, an inner surface of the recess, A first barrier metal layer having one of crystalline and polycrystallinity, and a second barrier metal formed on the first barrier metal layer and having the other crystallinity of amorphous and polycrystal A copper wiring formed on the second barrier metal layer, a copper diffusion preventing insulating film formed on the interlayer insulating film so as to cover the copper wiring, and the copper wiring and the copper diffusion preventing insulation A semiconductor device having a metal oxide layer formed at an interface with a film is provided.

  According to another aspect of the present invention, a step of forming a semiconductor element on a semiconductor substrate, a step of forming an interlayer insulating film containing moisture above the semiconductor substrate, and a step of forming a recess in the interlayer insulating film And forming a first barrier metal layer having one of amorphous and polycrystalline on the inner surface of the recess, and amorphous and polycrystalline on the first barrier metal layer. Forming a second barrier metal layer having the other crystallinity, forming a seed layer on the second barrier metal layer with copper containing a metal that forms an oxide, and There is provided a method for manufacturing a semiconductor device, comprising: a step of forming a copper layer on a seed layer; and a step of forming a copper diffusion prevention insulating film in a heated state on the interlayer insulating film so as to cover the copper layer. .

  The metal oxide layer formed on the interface between the copper wiring and the copper diffusion prevention insulating film improves the adhesion between the copper wiring and the copper diffusion prevention insulating film, thereby suppressing electromigration.

  Moisture that reaches the seed layer from the interlayer insulating film through the first and second barrier metal layers reacts with the metal contained in the copper of the seed layer due to heat during the formation of the copper diffusion prevention insulating film. It is possible to form such a metal oxide layer by generating a metal oxide and moving the generated metal oxide to reach the interface between the copper wiring and the copper diffusion prevention insulating film. is there.

  A semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described.

  FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. An element isolation insulating film 2 by shallow trench isolation (STI) is formed on a semiconductor substrate 1 which is a silicon substrate. A MOS transistor 3 is formed in the active region surrounded by the element isolation insulating film 2. The MOS transistor 3 is formed including a source region 3S, a drain region 3D, and a gate electrode 3G. The MOS transistor 3 can be formed by a known method.

  An interlayer insulating film 5 having a thickness of 1.5 μm is formed on the semiconductor substrate 1 by chemical vapor deposition (CVD) on the semiconductor substrate 1 so as to cover the MOS transistor 3. Via holes 4S and 4D are formed in the interlayer insulating film 5, and the via holes 4S and 4D are filled with conductive plugs 6S and 6D, respectively. The source region 3S and the drain region 3D of the MOS transistor 3 are electrically connected to the conductive plugs 6S and 6D, respectively.

  The conductive plugs 6S and 6D are formed of, for example, a laminated structure of a barrier metal layer made of TiN and a W layer. After depositing a TiN layer and a W layer on the entire surface of the substrate, unnecessary W layers and TiN layers are chemically mechanically polished ( It is formed by removing by CMP.

  An etching stopper film 11 is formed on the interlayer insulating film 5. The etching stopper film 11 is formed of, for example, silicon oxycarbide and has a thickness of 30 nm. The relative dielectric constant of silicon oxycarbide in the etching stopper film is 3.6.

  On the etching stopper film 11, an interlayer insulating film 12 having a porous structure made of a low dielectric constant material having a relative dielectric constant of 2.6 or less is formed. Moisture exists in the pores of the porous structure. The interlayer insulating film 12 is a SiOC film formed by CVD, for example. As such an insulating material, for example, Black Diamond of AMAT, Coral of Novellus System, AuroraULK of ASM (both are trade names of respective companies), and the like can be given.

  Use of silsesquioxane, C-doped oxide containing atoms of Si, C, O, and H, or thermosetting polyarene ether as a SiOC film material having a dielectric constant of 2.6 or less and a porous structure it can.

  In this embodiment, both the etching stopper film and the interlayer insulating film are films containing Si, O, and C. However, the interlayer insulating film has a porous structure, and the density difference between the two causes a difference in etching selectivity. Has occurred.

  A wiring groove 13 is formed in the etching stopper film 11 and the interlayer insulating film 12. A barrier metal layer 14 is formed on the inner surface of the wiring groove 13, and copper wiring 15 is formed on the barrier metal layer 14 by being filled with copper. The lower conductive plug is electrically connected to the copper wiring 15. An etching stopper film 21 is formed on the interlayer insulating film 12 so as to cover the copper wiring 15.

  Here, the manufacturing process of the copper wiring 15 will be described in detail.

  2A to 2G are schematic cross-sectional views showing the manufacturing process of the copper wiring 15. However, a cross section of a portion where the copper wiring 15 is not connected to the upper and lower wirings is shown.

  As shown in FIG. 2A, an interlayer insulating film 12 is formed on the etching stopper film 11.

  Next, as shown in FIG. 2B, a wiring trench 13 is formed in the interlayer insulating film 12.

  Next, as shown in FIG. 2C, a first barrier metal layer 14 a is formed of amorphous Ru on the interlayer insulating film 12 so as to cover the inner surface of the wiring trench 13. Next, a second barrier metal layer 14b is formed of polycrystalline Ru on the first barrier metal layer 14a. The barrier metal layer 14 according to the embodiment is formed by stacking first and second barrier metal layers 14a and 14b.

By using Ru, a barrier metal layer with reduced specific resistance can be obtained. For example, while the conventionally used barrier metal layer materials Ta and Ti have specific resistances of 15 × 10 ⁻⁶ Ω · cm and 80 × 10 ⁻⁶ Ω · cm, amorphous Ru and polycrystalline Ru The specific resistance is as low as 9 × 10 ⁻⁶ Ω · cm and 7 × 10 ⁻⁶ Ω · cm. Amorphous Ru has a slightly higher specific resistance than polycrystalline Ru.

  It is desirable that the amorphous first barrier metal layer 14a has such a thickness that a defect in the barrier metal layer 14a allows moisture to permeate moderately. The thickness is, for example, equal to or less than the roughness of the bottom of the wiring trench 13 and is preferably about 0.5 nm to 5 nm (eg, 3 nm).

The first barrier metal layer 14a can be formed by sputtering, CVD, atomic layer deposition (ALD), or the like, for example. As film formation conditions for sputtering, for example, a Ru target is used, a process gas is a mixed gas of Ar and N ₂ , a gas flow rate is about Ar / N ₂ = 10/70 sccm, a pressure in a sputtering atmosphere is 3000 mTorr, DC The power can be 800W. In order to obtain amorphous Ru, it is desirable that the N ₂ flow rate during film formation be about 10 sccm to 80 sccm.

The polycrystalline second barrier metal layer 14b has a large number of grain boundaries, and the grain boundaries become pores that allow water molecules to pass through. The thickness of the second barrier metal layer 14b is desirably about 3 nm to 15 nm. The second barrier metal layer 14b can also be formed by sputtering, CVD, ALD, or the like, for example. A polycrystalline film can be obtained by removing N ₂ under the film formation conditions of the first barrier metal layer 14a made amorphous as the film formation conditions for sputtering.

  Next, as shown in FIG. 2D, a seed layer 15a is formed on the second barrier metal layer 14b using, for example, copper containing 2% Ti. The seed layer 15a has a thickness of 30 nm, for example, and can be formed by sputtering using a target having a desired composition of the seed layer 15a.

  Next, as shown in FIG. 2E, a copper layer 15b is formed on the seed layer 15a by plating or the like.

  Next, as shown in FIG. 2F, the unnecessary copper layer 15b, seed layer 15a, second barrier metal layer 14b, and first barrier metal layer 14a on the interlayer insulating film 12 are removed by CMP. The seed layer 15 a and the copper layer 15 b form the copper wiring 15.

  Next, as shown in FIG. 2G, an etching stopper film 21 is formed on the interlayer insulating film 12 so as to cover the copper wiring 15. The etching stopper film 21 is formed of, for example, silicon oxycarbide and has a thickness of 30 nm. The etching stopper film 21 functions as a copper diffusion preventing insulating film that suppresses copper diffusion from the copper wiring 15 to the upper interlayer insulating film.

  The etching stopper film 21 can be formed by, for example, CVD using tetramethylsilane and carbon dioxide gas as source gases. The film formation conditions are, for example, a temperature of 400 ° C., a tetramethylsilane flow rate of 500 sccm, a carbon dioxide gas flow rate of 150 sccm, a pressure of about 600 Pa (4.5 Torr), a 13.56 MHz RF power of 600 W, and a 400 kHz RF power of 10 W. Note that the sample substrate used in the examples has a diameter of 300 mm, and the area of the parallel plate electrode for supplying RF power is substantially equal to the substrate area.

  The barrier metal layer 14 of the embodiment has a laminated structure of first and second barrier metal layers 14a and 14b, and both the barrier metal layers 14a and 14b have holes through which water in the interlayer insulating film 12 passes. .

  When the barrier metal layer 14 is only the second barrier metal layer 14b, which is a polycrystalline film, the holes in the grain boundaries allow water to pass from the interlayer insulating film 12 side to the copper wiring 15 side and from the copper wiring 15 side to the interlayer. It is easy to pass copper through the insulating film 12 side. By forming the first barrier metal layer 14a, which is an amorphous film, to an appropriate thickness, it is easy for water to pass through the defect holes from the interlayer insulating film 12 side to the copper wiring 15 side. Therefore, it is possible to make copper difficult to pass through to the interlayer insulating film 12 side. If the barrier metal layer 14 is made of only an amorphous film, it is difficult to sufficiently pass moisture when the barrier metal layer 14 is thickened to an appropriate thickness as the barrier metal layer.

When the etching stopper film 21 is formed, the water in the interlayer insulating film 12 reacts with Ti contained in the copper seed layer 15a through the barrier metal layers 14a and 14b in a heated temperature atmosphere, and TiO _2. Produces. Further, the generated TiO ₂ is self-diffused and is also distributed at the interface between the copper wiring 15 and the etching stopper film 21 to form the metal oxide layer 16. It is considered that the adhesion between the copper wiring 15 and the etching stopper film 21 is enhanced by the interposition of the metal oxide layer 16. The diffusion of TiO ₂ is presumed to occur mainly at the interface between the copper wiring 15 and the member in contact therewith (the diffusion of TiO ₂ along the interface is called self-diffusion). It is considered that TiO ₂ is also distributed at the bottom of the copper wiring 15.

The TiO ₂ remaining at the interface between the copper wiring 15 and the second barrier metal layer 14a functions so as to close the grain boundary hole after the generation of TiO ₂ , so that the interlayer insulating film 12 and the copper wiring 15 are connected. It is considered that the movement of water and the movement of copper from the copper wiring 15 to the interlayer insulating film 12 are suppressed and the barrier property is improved.

  Thus, in the copper wiring in the interlayer insulating film containing moisture, the barrier metal layer is formed by stacking the amorphous film and the polycrystalline film, and the copper seed layer contains the metal that forms the metal oxide. By forming, when forming an etching stopper film (copper diffusion prevention insulating film) covering the wiring, the metal contained in the copper seed layer reacts with the water in the interlayer insulating film, a metal oxide is generated, The generated metal oxide diffuses and is distributed also at the interface between the copper wiring and the etching stopper film. By interposing the metal oxide layer between the copper wiring and the etching stopper film, the adhesion between the copper wiring and the etching stopper film is enhanced, and the electromigration resistance is improved.

  Returning to FIG. 1, the description will be continued. On the etching stopper film 21, an interlayer insulating film 22, a middle stopper film 23, and an interlayer insulating film 24 are formed in order from the bottom. Each of the interlayer insulating films 22 and 24 is a low dielectric constant insulating film having a porous structure like the interlayer insulating film 12, and has a thickness of, for example, 150 nm. The middle stopper film 23 is, for example, a silicon oxycarbide film and has a thickness of 30 nm.

  A wiring groove 26 is formed in the interlayer insulating film 24, and a via hole 25 is formed in the middle stopper film 23, the interlayer insulating film 22, and the etching stopper film 21. A barrier metal layer 27 is formed on the inner surfaces of the via hole 25 and the wiring groove 26, and copper is filled on the barrier metal layer 27 to form a wiring 28. The insulating film from the etching stopper film 21 to the interlayer insulating film 24, the barrier metal layer 27, and the copper wiring 28 constitute one wiring layer. Note that the structure in which the middle stopper film 23 is left at the bottom of the wiring trench 26 is illustrated, but the dielectric constant can be further reduced as a structure in which the middle stopper film 23 is not left.

  The barrier metal layer 27 and the copper wiring 28 in the via hole 25 and the wiring groove 26 can be formed in the same manner as the barrier metal layer 14 and the copper wiring 15 in the wiring groove 13 described above. That is, a barrier metal layer 27 is formed by stacking a first barrier metal layer made of amorphous Ru and a second barrier metal layer made of polycrystalline Ru, and plated on a copper seed layer containing Ti. The copper wiring 28 is formed by forming a copper layer. The formation of the copper wiring 15 is a single damascene process, whereas the formation of the copper wiring 28 is a dual damascene process.

  An etching stopper film 31 is formed on the interlayer insulating film 24 so as to cover the copper wiring 28. The etching stopper film 31 is a silicon oxycarbide film, for example, like the etching stopper film 21. Similarly to the case of the lower copper wiring 15, the titanium oxide generated at the time of forming the etching stopper film 31 and diffused at the interface between the etching stopper film 31 and the copper wiring 28 is used to form the etching stopper film 31 and the copper wiring 28. Adhesion can be improved.

  Similarly, a wiring layer is further formed above. On the uppermost wiring layer, an etching stopper film 51 is formed by silicon oxycarbide, and an interlayer insulating film 52 is formed thereon by SiOC formed by CVD. A via hole 53 is formed in the etching stopper film 51 and the interlayer insulating film 52, and a conductive plug 54 using W is filled in the via hole 53. The lower layer wiring 49 is electrically connected to the conductive plug 54.

  A pad 55 made of aluminum is formed on the interlayer insulating film 52 and connected to the conductive plug 54. A protective film 56 is formed of silicon nitride so as to cover the interlayer insulating film 52 and the pad 55. The protective film 56 has an opening on the upper surface of the pad 55, and the pad 55 is exposed in the opening. As described above, the semiconductor device of the example is manufactured.

  A copper wiring sample formed by the same method as in the example was prepared and an electromigration test was performed.

  FIG. 3 is a schematic cross-sectional view showing a wiring pattern of a sample used in the electromigration test. The wiring pattern has a chain shape in which first-layer wiring portions 61 and second-layer wiring portions 62 are alternately arranged with end portions connected by via portions 63. Each of the first layer wiring portion 61 and the second layer wiring portion 62 has a width of 70 nm, a length of 200 nm, and a thickness of 100 nm, and each via portion has a diameter of 70 nm and a height of 100 nm. Both ends of the wiring pattern are connected to pads.

  100 chips having such a wiring pattern were prepared, and an electromigration test was performed for 200 hours at a temperature of 150 ° C. and a current of 0.2 mA. In addition, the sample of the comparative example was prepared and the same test was done. In the sample of the comparative example, the barrier metal layer was a single polycrystalline Ru layer, and the seed layer was made of only copper without containing other metals.

  In the sample of the example, the number of open defects in 100 chips was 0, whereas in the sample of the comparative example, the number of open defects in 100 chips was 25. Thus, it was found that electromigration is suppressed by the wiring formation method of the example.

  In addition, although the said Example demonstrated the case where the metal contained in a copper seed layer was Ti, the same effect was confirmed by the electromigration test also about the case where Mn is contained.

  Under appropriate heating conditions associated with the formation of the etching stopper film covering the copper wiring, moisture moves from the interlayer insulating film beyond the barrier metal layer, and the metal contained in the copper seed layer is oxidized, resulting in metal oxidation. Things are thought to diffuse. An appropriate temperature at this time is not limited to the above-mentioned 400 ° C., and a range of 250 ° C. to 450 ° C. is preferable. This is the same in both cases where the metal contained in the copper seed layer is Ti or Mn.

  In this embodiment, silicon oxycarbide is used as an etching stopper film (copper diffusion prevention insulating film) that covers the copper wiring. However, the etching stopper film is not limited to a silicon oxycarbide (SiOC) film. In addition, a SiC film, a SiCN film, a SiN film, a SiOCN film, or the like can be used as a film having excellent copper barrier properties.

  It should be noted that metals suitable for inclusion in the copper seed layer are not limited to Ti and Mn. For example, in particular, a transition metal of the same or adjacent group in the periodic table with Ti or Mn is considered to exhibit behavior similar to that of Ti and Mn, and may be suitable as a metal to be included in the copper seed layer. Specific examples include Zr, Hf, Sc, Y, V, Nb, Re, Mo, W, and Ta. Furthermore, as other metals, Li, Be, B, Mg, Al, Si, Cr, Ni, Zn, Ga, Ge, Se, Br, Rb, Sr, Ag, In, Sn, Sb, Te, Ba, Au , Ir, Pt, Pb, etc. can be used.

  The film thickness of the copper seed layer is desirably about 2 nm to 50 nm, and the content of metal contained in copper is desirably about 0.5% to 5%.

  In the above embodiment, the first barrier metal layer on the interlayer insulating film side is amorphous and the second barrier metal layer on the copper wiring side is polycrystalline, but the interlayer insulating film side is polycrystalline and the copper wiring. Even if the side is amorphous, suitable moisture permeability and copper barrier properties will be obtained. However, when the copper wiring side is polycrystalline, the grain part with good wettability with Cu is exposed in the wiring recess, resulting in better adhesion between the copper wiring and the barrier metal layer and improved electromigration resistance. To do.

In the above embodiment, Ru is used as the first and second barrier metal layers, but other metals can also be used. For example, Co (specific resistance of 6. 2 × 10 ⁻⁶ Ω · cm).

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

The following additional notes are further disclosed with respect to the embodiment including the examples described above.
(Appendix 1)
A semiconductor substrate on which a semiconductor element is formed;
An interlayer insulating film containing moisture and having a recess formed above the semiconductor substrate;
A first barrier metal layer formed on the inner surface of the recess and having one of amorphous and polycrystalline properties;
A second barrier metal layer formed on the first barrier metal layer and having the other crystallinity of amorphous and polycrystalline;
A copper wiring formed on the second barrier metal layer;
A copper diffusion prevention insulating film formed on the interlayer insulating film so as to cover the copper wiring;
A semiconductor device having a metal oxide layer formed at an interface between the copper wiring and the copper diffusion prevention insulating film.
(Appendix 2)
The semiconductor device according to appendix 1, wherein the first barrier metal layer is amorphous and the second barrier metal layer is polycrystalline.
(Appendix 3)
The semiconductor device according to appendix 2, wherein the thickness of the first barrier metal layer is in the range of 0.5 nm to 5 nm.
(Appendix 4)
4. The semiconductor device according to appendix 2 or 3, wherein the thickness of the second barrier metal layer is in the range of 3 nm to 15 nm.
(Appendix 5)
The metal oxide layer includes any one of appendices 1 to 4 including at least one oxide of Ti, Mn, Zr, Hf, Sc, Y, V, Nb, Re, Mo, W, and Ta. The semiconductor device described.
(Appendix 6)
The semiconductor device according to any one of appendices 1 to 5, wherein the first and second barrier metal layers include Ru or Co.
(Appendix 7)
7. The semiconductor device according to any one of appendices 1 to 6, wherein the interlayer insulating film includes a porous structure.
(Appendix 8)
Forming a semiconductor element on a semiconductor substrate;
Forming an interlayer insulating film containing moisture above the semiconductor substrate;
Forming a recess in the interlayer insulating film;
Forming a first barrier metal layer having one of amorphous and polycrystalline on the inner surface of the recess;
Forming a second barrier metal layer having a crystallinity of the other of amorphous and polycrystalline on the first barrier metal layer;
Forming a seed layer on the second barrier metal layer with copper containing a metal that forms an oxide;
Forming a copper layer on the seed layer;
And a step of forming a copper diffusion prevention insulating film in a heated state on the interlayer insulating film so as to cover the copper layer.
(Appendix 9)
The step of forming the first barrier metal layer includes forming a first barrier metal layer having amorphous crystallinity, and the step of forming the second barrier metal layer includes polycrystalline crystallinity. 9. The method for manufacturing a semiconductor device according to appendix 8, wherein the second barrier metal layer is formed.
(Appendix 10)
The method for manufacturing a semiconductor device according to appendix 8 or 9, wherein in the step of forming the seed layer, the content of the metal contained in the seed layer is in the range of 0.5% to 5%.
(Appendix 11)
The method of manufacturing a semiconductor device according to any one of appendices 8 to 10, wherein in the step of forming the copper diffusion prevention insulating film, the deposition temperature of the copper diffusion prevention insulating film is in a range of 250 to 450 ° C.

FIG. 1 is a schematic sectional view showing a semiconductor device according to an embodiment of the present invention. 2A to 2D are cross-sectional views illustrating a process of forming a copper wiring of the semiconductor device of the example. 2E to 2G are cross-sectional views illustrating steps of forming the copper wiring of the semiconductor device of the example, following FIGS. 2A to 2D. FIG. 3 is a schematic cross-sectional view showing a wiring pattern of a sample used in the electromigration test.

Explanation of symbols

5, 12 Interlayer insulating films 11, 21 Etching stopper film 13 Wiring groove 14a First barrier metal layer 14b Second barrier metal layer 14 Barrier metal layer 15a Copper seed layer 15b Copper layer 15 Copper wiring 16 Metal oxide layer

Claims (5)

A semiconductor substrate on which a semiconductor element is formed;
An interlayer insulating film containing moisture and having a recess formed above the semiconductor substrate;
A first barrier metal layer formed on the inner surface of the recess and having one of amorphous and polycrystalline properties;
A second barrier metal layer formed on the first barrier metal layer and having the other crystallinity of amorphous and polycrystalline;
A copper wiring formed on the second barrier metal layer;
A copper diffusion prevention insulating film formed on the interlayer insulating film so as to cover the copper wiring;
A semiconductor device having a metal oxide layer formed at an interface between the copper wiring and the copper diffusion prevention insulating film.   2. The semiconductor device according to claim 1, wherein the first barrier metal layer is amorphous and the second barrier metal layer is polycrystalline. 3. Forming a semiconductor element on a semiconductor substrate;
Forming an interlayer insulating film containing moisture above the semiconductor substrate;
Forming a recess in the interlayer insulating film;
Forming a first barrier metal layer having one of amorphous and polycrystalline on the inner surface of the recess;
Forming a second barrier metal layer having the other crystallinity of amorphous and polycrystalline on the first barrier metal layer;
Forming a seed layer on the second barrier metal layer with copper containing a metal that forms an oxide;
Forming a copper layer on the seed layer;
And a step of forming a copper diffusion prevention insulating film in a heated state on the interlayer insulating film so as to cover the copper layer.   4. The method of manufacturing a semiconductor device according to claim 3, wherein, in the step of forming the seed layer, the content of the metal contained in the seed layer is in a range of 0.5% to 5%.   5. The method of manufacturing a semiconductor device according to claim 3, wherein in the step of forming the copper diffusion prevention insulating film, the deposition temperature of the copper diffusion prevention insulating film is in a range of 250 to 450 ° C. 6.

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