JP5407660B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device .

  With the higher integration of LSIs, the miniaturization and multilayering of internal wiring are progressing. However, the cost increase of semiconductor manufacturing devices accompanying the miniaturization has greatly affected the cost of LSIs. In addition, logic, memory, image sensors, etc. are mixedly mounted on a single chip, but in order to make the maximum possible use of the characteristics of the process required for each device, the process is complicated. Increase in cost and cost cannot be avoided.

  Under such circumstances, the integration of LSIs with single functions (logic, memory, image sensor) at the wafer level and chip level and stacking them, sacrifices the degree of integration of highly functional LSIs. One chip is starting to be used. Studies are also being conducted on a structure in which insulating films are bonded to each other to obtain electrical continuity between wafers and chips laminated by through vias. Further, three-dimensional mounting in which metal wirings are directly bonded to each other without using such through vias has been studied.

  For example, when copper wiring is used as the metal wiring and the copper wirings are joined to each other (see, for example, Non-Patent Document 1), as shown in FIG. There is also a concern that (125) directly contacts the interlayer insulating film 112 (122) on the other side. For example, when the copper of the copper wiring 115 comes into contact with the interlayer insulating film 112, the copper of the copper wiring 115 is oxidized (the copper oxide film 131 is formed), thereby increasing the electrode resistance and the subsequent thermal process. Copper ions diffuse into the interlayer insulating film 112 and cause a problem of reliability such as leakage.

There is a method for preventing such oxidation of the copper wiring 115 (125) and diffusion into the interlayer insulating film 112 (122).
For example, as shown in FIG. 9, as the diffusion prevention layer 114 (124) having a characteristic of preventing copper diffusion in the surface layer of the interlayer insulating film 112 (122), for example, a silicon nitride (SiN) film or silicon carbide oxide (SiOC) A film may be formed. However, when the diffusion prevention layer 114 (124) is formed, the above problem due to misalignment is solved, but there is a concern about an increase in inter-wiring capacitance. If the surface silicon nitride (SiN) film or silicon carbide oxide (SiOC) film is thinned, it is possible to prevent an increase in capacitance between wirings, but the diffusion preventing layer 114 (124) is eliminated by erosion during CMP. There is a fear. Therefore, it is difficult to form the diffusion prevention layer 114 (124) to a thickness that does not cause a problem with interlayer capacitance.

Lea Di Cioccio, Pierric Gueguen, Thomas Signamarcheix, Maurice Rivoire, D Scevola, Regis Cahours, Patrick Leduc, M Assous, Laurent Clavelier. “Enabling 3D Interconnects with Metal Direct Bonding” IITC (International Interconnect Technology Conference) 2009, proc.p152- 154 (2009)

  The problem to be solved is that when electrodes formed on different substrates are joined together, if the misalignment occurs, the electrodes directly contact the interlayer insulating film, which may cause an increase in electrode resistance or current leakage. There is a point.

  The present invention makes it possible to prevent an increase in electrode resistance or current leakage without increasing the interlayer capacitance even when misalignment occurs when electrodes formed on different substrates are joined. .

  According to a method of manufacturing a semiconductor device of the present invention (first manufacturing method), a first interlayer insulating film is formed on a first substrate, and a first metal electrode is formed in a first groove formed in the first interlayer insulating film. A second substrate in which a first embedded substrate is prepared, a second interlayer insulating film is formed on the second substrate, and a second metal electrode is embedded in a second groove formed in the second interlayer insulating film Preparing a first diffusion preventing layer on the first interlayer insulating film side, forming a second diffusion preventing layer on the second interlayer insulating film side, the first metal electrode, and the first Forming a first opening in the first diffusion prevention layer in the formation region of each of the first metal electrode and the second metal electrode when joining the two metal electrodes facing each other; and Each shape of the first metal electrode and the second metal electrode when the metal electrode and the second metal electrode are joined to face each other. Forming a second opening in the second diffusion barrier layer in the region, and performing heat treatment with the first opening and the second opening facing each other, so that the first metal electrode and the second metal electrode Joining the first opening and the second opening by thermal expansion.

  In the method for manufacturing a semiconductor device according to the present invention (first manufacturing method), when the first metal electrode and the second metal electrode are joined, the first diffusion is provided between the first metal electrode and the second metal electrode. A prevention layer and a second diffusion prevention layer are formed. For this reason, even if the positions of the first metal electrode and the second metal electrode shift due to misalignment, the bonding surface side of the first metal electrode and the second metal electrode includes the first diffusion prevention layer and the bonding portion. The second diffusion prevention layer is covered. Therefore, it is avoided that the bonding surface side of the first metal electrode and the second metal electrode is in direct contact with the interlayer insulating film including the bonding portion.

  According to a method of manufacturing a semiconductor device of the present invention (second manufacturing method), a first interlayer insulating film is formed on a first substrate, and a first metal electrode is formed in a first groove formed in the first interlayer insulating film. A second substrate in which a first embedded substrate is prepared, a second interlayer insulating film is formed on the second substrate, and a second metal electrode is embedded in a second groove formed in the second interlayer insulating film Preparing a diffusion prevention layer on the interlayer insulating film on at least one side of the first interlayer insulating film or the second interlayer insulating film, and opposing the first metal electrode and the second metal electrode. Forming an opening in the diffusion prevention layer in each of the formation regions of the first metal electrode and the second metal electrode, and bonding the first metal electrode and the first metal electrode with the opening interposed therebetween. Heat treatment is performed with the second metal electrode facing each other, and the first metal electrode and the second metal electrode are heated. A step of bonding through the opening by Zhang.

  In the semiconductor device manufacturing method (second manufacturing method) of the present invention, when the first metal electrode and the second metal electrode are joined, the first diffusion is provided between the first metal electrode and the second metal electrode. A prevention layer is formed. For this reason, even if the positions of the first metal electrode and the second metal electrode are shifted due to misalignment, the bonding surface side of the first metal electrode and the second metal electrode is included in the first diffusion prevention layer including the bonding portion. It is covered. Therefore, it is avoided that the bonding surface side of the first metal electrode and the second metal electrode is in direct contact with the interlayer insulating film including the bonding portion.

Semi conductor arrangement includes a first interlayer insulating film formed on the first substrate, a first metal electrode buried in the first groove formed in the first interlayer insulating film, formed on the second substrate A second interlayer insulating film, a second metal electrode embedded in a second groove formed in the second interlayer insulating film, and between the first interlayer insulating film and the second interlayer insulating film. A diffusion prevention layer formed, and an opening formed in the diffusion prevention layer in a formation region of the first metal electrode and the second metal electrode, and the first metal wiring and the first metal through the opening. Two metal wirings are joined.

Semi conductor device, the bonding side of the first metal electrode and the second metal electrode, the bonding portion is also included, it is covered in the first diffusion preventing layer. Therefore, even if the positions of the first metal electrode and the second metal electrode are shifted due to misalignment, the bonding surface side of the first metal electrode and the second metal electrode includes the bonding portion. Thus, direct contact with the interlayer insulating film is avoided.

In the method of manufacturing a semiconductor device according to the present invention, since the joint surfaces of the first metal electrode and the second metal electrode are avoided from directly contacting the interlayer insulating film including the joint portion, the electrode resistance due to oxidation of the metal electrode is avoided. Can be prevented from occurring and current leakage.
Therefore, highly reliable interelectrode bonding is possible, and a highly reliable semiconductor device can be manufactured.

Semi conductor arrangement, the bonding surface of the first metal electrode and the second metal electrode, since the can be avoided that the bonding portion is also included in direct contact with the interlayer insulating film, due to the oxidation of the first, second metal electrodes It is possible to prevent an increase in electrode resistance and current leakage.
Therefore, highly reliable interelectrode bonding is possible, and a highly reliable semiconductor device can be provided.

It is a manufacturing process figure showing the 1st example of the manufacturing method of the semiconductor device concerning a 1st embodiment of the present invention. It is a manufacturing process figure showing the 1st example of the manufacturing method of the semiconductor device concerning a 1st embodiment of the present invention. It is a manufacturing process figure showing the 1st example of the manufacturing method of the semiconductor device concerning a 1st embodiment of the present invention. It is a manufacturing process figure showing the 2nd example of the manufacturing method of the semiconductor device concerning a 1st embodiment of the present invention. It is a manufacturing process figure showing the 2nd example of the manufacturing method of the semiconductor device concerning a 1st embodiment of the present invention. It is a manufacturing process figure showing the 2nd example of the manufacturing method of the semiconductor device concerning a 1st embodiment of the present invention. It is a schematic structure sectional view showing an example of a semiconductor device concerning a 2nd embodiment of the present invention. It is schematic structure sectional drawing which showed the trouble of the prior art. It is schematic structure sectional drawing which showed the trouble of the prior art.

  Hereinafter, modes for carrying out the invention (hereinafter referred to as embodiments) will be described.

<1. First Embodiment>
[First Example of Manufacturing Method of Semiconductor Device]
A first example of a method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to manufacturing process diagrams of FIGS. In the manufacturing process diagrams of FIGS. 1 and 2, a plan view is shown in an upper diagram of each figure, and a cross-sectional view taken along line AA ′ in the plan view is shown in a lower diagram. The manufacturing process diagram of FIG. 3 shows a cross-sectional view.

As shown in FIG. 1A, a first interlayer insulating film 12 is formed on a first substrate 11, and a first barrier metal layer 14 is formed in a first groove 13 formed in the first interlayer insulating film 12. A first metal electrode 15 is embedded through the gap. Such a first substrate 11 is prepared.
For example, a silicon substrate is used as the first substrate 11, and a semiconductor element (not shown) is formed, a wiring (not shown) is formed by a normal LSI process, and then an interlayer insulating film is formed. Has been. A first metal electrode 15 is formed in the first groove 13 on the first interlayer insulating film 12 as the uppermost layer of the interlayer insulating film by a normal trench wiring forming technique (for example, damascene processing method, dual damascene processing method, etc.). To do.
The first metal electrode 15 is, for example, a 50 μm square having a thickness of 500 nm, and the surface thereof is formed at the same height as the surface of the first interlayer insulating film 12. That is, the surface of the first interlayer insulating film 12 and the surface of the first metal electrode 15 are not stepped and are on the same plane. The first metal electrode 15 is made of copper, for example. Of course, another metal, for example, one of copper, gold, and silver, or an alloy using two or more of these metals may be used. Alternatively, an alloy containing these metals as a main material may be used.

Further, as shown in FIG. 2A, a second interlayer insulating film 22 is formed on the second substrate 21, and a second barrier metal layer is formed in the second groove 23 formed in the second interlayer insulating film 22. A second metal electrode 25 is embedded via 24. Such a second substrate 21 is prepared.
For example, a silicon substrate is used as the second substrate 21, and after forming a semiconductor element (not shown), forming a wiring (not shown), etc. by a normal LSI process, an interlayer insulating film is formed. Has been. A second metal electrode 25 is formed in the second groove 23 on the second interlayer insulating film 22 as the uppermost layer of the interlayer insulating film by a normal trench wiring forming technique (for example, a damascene processing method, a dual damascene processing method, etc.). To do.
The second metal electrode 25 is, for example, a 50 μm square having a thickness of 500 nm, and the surface thereof is formed at the same height as the surface of the second interlayer insulating film 22. That is, the surface of the second interlayer insulating film 22 and the surface of the second metal electrode 25 have no step and are on the same plane. The second metal electrode 25 is made of, for example, copper. Of course, another metal, for example, one of copper, gold, and silver, or an alloy using two or more of these metals may be used. Alternatively, an alloy containing these metals as a main material may be used.

Next, a diffusion prevention layer is formed on the interlayer insulating film on at least one side of the first interlayer insulating film 12 or the second interlayer insulating film 22. Here, a diffusion prevention layer is formed on both interlayer insulating films.
As shown in FIG. 1B, a first diffusion prevention layer 16 that covers the first metal electrode 15 is formed on the surface of the first interlayer insulating film 12. The first diffusion preventing layer 16 is formed of a material that prevents copper diffusion. For example, it is formed of a silicon nitride compound or a carbonized silicon oxide compound. Examples of the silicon nitride compound include silicon nitride (SiN), examples of the silicon carbide oxide compound include silicon carbide oxide (SiOC), and silicon nitride carbonized oxide (SiOCN) can also be used. The film thickness may be any film thickness that prevents copper diffusion and prevents oxygen from entering the first metal electrode 15, and is, for example, 35 nm to 50 nm.
For example, as a film forming condition when the first diffusion preventing layer 16 is formed of silicon nitride, a plasma CVD method is used as an example. The process conditions include, for example, the process gas and ammonia (NH _3), nitrogen (N ₂₎ with ammonia in the film forming atmosphere (NH ₃₎ to 50 cm ³ / min, nitrogen (N ₂₎ to 500 cm ³ / min Supply at a flow rate of. The pressure of the film formation atmosphere is set to 665 Pa, the substrate temperature is set to 350 ° C., and the RF power of the plasma CVD apparatus is set to 1000 W (13.56 MHz). Under this condition, the first diffusion preventing layer 16 was formed to a thickness of 50 nm.

Similarly, as shown in FIG. 2 (2), a second diffusion prevention layer 26 that covers the second metal electrode 25 is formed on the surface of the second interlayer insulating film 22. The second diffusion prevention layer 26 is formed of a material that prevents diffusion of copper. For example, it is formed of a silicon nitride compound or a carbonized silicon oxide compound. Examples of the silicon nitride compound include silicon nitride (SiN), examples of the silicon carbide oxide compound include silicon carbide oxide (SiOC), and silicon nitride carbonized oxide (SiOCN) can also be used. The film thickness may be any film thickness that prevents copper diffusion and prevents oxygen from entering the second metal electrode 25 side. For example, the film thickness is 30 nm or more and 50 nm or less.
For example, as a film forming condition when the second diffusion preventing layer 26 is formed of silicon nitride, a plasma CVD method is used as an example. The process conditions include, for example, the process gas and ammonia (NH _3), nitrogen (N ₂₎ with ammonia in the film forming atmosphere (NH ₃₎ to 50 cm ³ / min, nitrogen (N ₂₎ to 500 cm ³ / min Supply at a flow rate of. The pressure of the film formation atmosphere is set to 665 Pa, the substrate temperature is set to 350 ° C., and the RF power of the plasma CVD apparatus is set to 1000 W (13.56 MHz). Under this condition, the second diffusion preventing layer 26 was formed to a thickness of 50 nm.

As the first diffusion preventing layer 16 and the second diffusion preventing layer 26, a silicon nitride film formed by plasma CVD is used as a film for preventing copper copper from being diffused. However, other manufacturing methods (for example, high-frequency sputtering or high density plasma) are used. (High density plasma method) may be used for film formation. In addition to the silicon nitride film, as described above, a silicon carbide oxide (SiOC) film or a nitrided silicon carbide oxide (SiOCN) film can also be used.
There is no difference in barrier properties between the silicon nitride film, the silicon carbide oxide (SiOC) film, and the silicon nitride carbonized oxide (SiOCN) film. For example, the diffusion of copper into the silicon nitride film, silicon carbide oxide film, and silicon nitride oxide (SiOCN) film by heat treatment at 400 ° C. is about 20 nm. Therefore, if the silicon nitride film, the silicon carbide oxide film, and the silicon nitride carbide oxide (SiOCN) film have a film thickness of 30 nm or more, the barrier property of copper can be sufficiently secured.

Next, as shown in FIG. 1 (3), when the first metal electrode 15 and the second metal electrode 25 (see FIG. 2 (2)) are bonded to each other, the first metal electrode 15 is joined. A first opening 17 is formed in the first diffusion preventing layer 16 in each of the formation regions of the second metal electrode 25.
The first opening 17 is formed in, for example, a 30 μm square in plan layout. The size of the first opening 17 is appropriately determined. For example, when the first metal electrode 15 is thermally expanded during the heat treatment in a later process, the first opening 17 is formed in a size that can be embedded. Here, the size satisfying the above conditions was a 30 μm square.
For example, when the first diffusion prevention layer 16 is formed of a silicon nitride film, the first opening 17 is formed by, for example, reactive ion etching (RIE) using a fluorine-based etching gas.

Further, as shown in FIG. 2 (3), when the first metal electrode 15 (see FIG. 1 (2)) and the second metal electrode 25 are joined to face each other, A second opening 27 is formed in the second diffusion prevention layer 26 in each formation region of the second metal electrode 25.
The second opening 27 is formed in, for example, a 10 μm square that is smaller than the first opening 17 (see FIG. 1 (3)) in plan layout. The size of the second opening 27 is determined as appropriate. For example, when the second metal electrode 25 is thermally expanded during a heat treatment in a later process, the second opening 27 is formed to be embedded. Here, the size satisfying the above conditions was a 10 μm square. Of course, it may be the same size as the first opening 17.
For example, when the second diffusion prevention layer 26 is formed of a silicon nitride film, the second opening 27 is formed by reactive ion etching (RIE) using a fluorine-based etching gas, for example.

  Note that by making the first opening 17 and the second opening 27 different in size, the metal filled in the second opening 27 having a small opening size in the subsequent heat treatment step is the first opening. It protrudes to the opening 17 side. Thereby, the joining by the thermal expansion of the 1st metal electrode 15 and the 2nd metal electrode 25 becomes firm. At this time, even if the metal filled in the second opening 27 protrudes to the first opening 17 side, there is a spatial margin on the first opening 17 side. It does not enter between the first diffusion prevention layer 16 and the second diffusion prevention layer 26.

Next, as shown in FIG. 1 (4), a pretreatment for removing the oxide film formed on the surface of the first metal electrode 15 is performed. This pretreatment is, for example, by reduction treatment by hydrogen plasma treatment.
For example, when the first metal electrode 15 is made of copper, hydrogen (H ₂ ) and argon (Ar) are used as a process gas, and hydrogen is supplied at a flow rate of 100 cm ³ / min, for example, in a reduction treatment atmosphere. Argon is supplied at a flow rate of 170 cm ³ / min. Further, the microwave power of hydrogen plasma treatment was 2.8 kW (2.45 GHz), the pressure of the reducing atmosphere was 0.4 Pa, the substrate temperature was 400 ° C., and the reduction treatment time was 1 minute. This condition is an example and can be changed as appropriate. Further, when the oxide film is not formed on the surface of the first metal electrode 15, for example, when the first metal electrode 15 is formed of gold, it is not necessary to perform the hydrogen reduction treatment.

Similarly, as shown in FIG. 2 (4), a pretreatment for removing the oxide film formed on the surface of the second metal electrode 25 is performed. This pretreatment is, for example, by reduction treatment by hydrogen plasma treatment.
For example, when the second metal electrode 25 is made of copper, hydrogen (H ₂ ) and argon (Ar) are used as a process gas, and hydrogen is supplied at a flow rate of 100 cm ³ / min, for example, in a reduction treatment atmosphere. Argon is supplied at a flow rate of 170 cm ³ / min. Further, the microwave power of hydrogen plasma treatment was 2.8 kW (2.45 GHz), the pressure of the reducing atmosphere was 0.4 Pa, the substrate temperature was 400 ° C., and the reduction treatment time was 1 minute. This condition is an example and can be changed as appropriate. Further, when the oxide film is not formed on the surface of the second metal electrode 25, for example, when the second metal electrode 25 is formed of gold, it is not necessary to perform the hydrogen reduction treatment.
Further, instead of the pretreatment with hydrogen plasma as described above, for example, hydrogen annealing, annealing with forming gas (nitrogen (N ₂ ) / hydrogen (H ₂ )), reduction with ammonia (NH ₃ ) plasma, formic acid plasma, etc. Processing may be performed.

  Next, as shown in FIG. 3 (5), the first metal electrode 15 and the second metal electrode 25 are opposed to each other with the first opening 17 and the second opening 27 interposed therebetween.

Then, as shown in FIG. 3 (6), the first opening 17 and the second opening 27 are opposed to each other, and the first diffusion preventing layer 16 and the second diffusion preventing layer 26 are pressed and joined. Then, heat treatment is performed. Then, due to thermal expansion of the first metal electrode 15 and the second metal electrode 25, the first metal electrode 15 and the second metal electrode 25 are joined through the first opening 17 and the second opening 27.
That is, the first metal electrode 15 expands due to the heat treatment. At this time, since the first metal electrode 15 is fixed by the first interlayer insulating film 12 except for the first opening 17, the first metal electrode 15 expands toward the first opening 17. Similarly, the second metal electrode 25 expands. At this time, since the second metal electrode 25 is fixed by the second interlayer insulating film 22 except for the second opening 27, the second metal electrode 25 expands toward the second opening 27.
And the 1st metal electrode 15 and the 2nd metal electrode 25 which mutually expanded are joined in the 1st opening part 17 and the 2nd opening part 27, and are crimped | bonded by the pressure of expansion | swelling.
At this time, since the first diffusion preventing layer 16 and the second diffusion preventing layer 26 are pressed and joined, the metal of the expanded metal electrode is in contact with the first diffusion preventing layer 16 and the second diffusion. It does not enter between the prevention layer 26.
The first opening 17 and the second opening 27 are preferably filled with the expanded portions of the first metal electrode 15 and the second metal electrode 25 by the heat treatment. Therefore, it is preferable to determine the sizes of the first opening 17 and the second opening 27 in consideration of the volume expansion amounts of the first metal electrode 15 and the second metal electrode 25.

  In the semiconductor device manufacturing method, since the thermal expansion (volume expansion) of the first metal electrode 15 and the second metal electrode 25 is used, it is not necessary to heat the metal at a high temperature, for example, 500 ° C. or higher. The heating temperature can be about 450 ° C. or lower, preferably 400 ° C. or lower. Then, due to the volume expansion of the first metal electrode 15 and the second metal electrode 25, the first opening 17 and the second opening 27 are filled with the metal of the first metal electrode 15 and the second metal electrode 25 in a self-aligning manner. It becomes possible to join.

For example, in the case of the first metal electrode 15 (a square having a size of 50 μm square and a thickness of 500 nm), the linear expansion coefficient α of copper is 16.8 × 10 ⁻⁶ (1 / T), and the volume of copper The expansion coefficient β is 3α. For example, assuming that the first metal electrode 15 is heated from 23 ° C. to 400 ° C., the expansion volume X of the first metal electrode 15 is as follows.

X = β × (400-23) × 50 μm × 50 μm × 0.5 μm = 23.8 μm ³

For example, when heated to 450 ° C., X = 26.9 μm ³ . At this time, when the 30 μm square first opening 17 is formed on the first metal electrode 15, the first diffusion preventing layer 16 has a thickness of 50 nm, so that it expands into the first opening 17. The first metal electrode 15 thus expanded expands to a position recessed by about 20 nm from the surface of the first diffusion prevention layer 16. Accordingly, the remaining first opening 17 where the copper of the first metal electrode 15 is expanded is about 18 μm ³ .
Further, when the 10 μm square second opening 27 is formed on the second metal electrode 25, the second diffusion prevention layer 26 has a thickness of 50 nm, and therefore the expansion of the second metal electrode 25 is caused by the second diffusion. From the surface of the prevention layer 26, the shape is convex about 156 nm. That is, the expansion of copper protruding from the second opening 27 is about 18 μm ³ . By controlling the temperature in this way, the first opening 17 and the second opening 27 can be filled without excess or deficiency.

  Therefore, by determining the respective volumes of the first metal electrode 15 and the second metal electrode 25 and the respective areas of the first opening 17 and the second opening 27, the shapes of the joint portions of both are controlled by the heating temperature. It becomes possible.

  In the semiconductor device manufacturing method, even if misalignment occurs between the first substrate 11 and the second substrate 21, the first opening 17 side of the first metal electrode 15 is located on the first diffusion prevention layer. 16 is covered. The second opening 27 side of the second metal electrode 25 is covered with the first diffusion preventing layer 16. That is, the first metal electrode 15 is surrounded by the first barrier metal layer 14 and the first diffusion prevention layer 16. The second metal electrode 25 is surrounded by the second barrier metal layer 24 and the first diffusion prevention layer 16. For this reason, the problem of misalignment can be solved.

[Second Example of Manufacturing Method of Semiconductor Device]
A second example of the method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described with reference to the manufacturing process diagrams of FIGS. In the manufacturing process diagrams of FIGS. 4 and 5, a plan view is shown in the upper diagram of each figure, and a cross-sectional view along the line AA ′ in the plan view is shown in the lower diagram. The manufacturing process diagram of FIG. 6 shows a cross-sectional view.

As shown in FIG. 4A, a first interlayer insulating film 12 is formed on the first substrate 11, and the first barrier metal layer 14 is formed in the first groove 13 formed in the first interlayer insulating film 12. A first metal electrode 15 is embedded through the gap. Such a first substrate 11 is prepared.
For example, a silicon substrate is used as the first substrate 11, and a semiconductor element (not shown) is formed, a wiring (not shown) is formed by a normal LSI process, and then an interlayer insulating film is formed. Has been. A first barrier metal layer 14 is formed in the first trench 13 by a normal trench wiring forming technique (for example, a damascene processing method, a dual damascene processing method, etc.) on the first interlayer insulating film 12 as the uppermost layer of the interlayer insulating film. A first metal electrode 15 is formed therethrough.
The first metal electrode 15 is, for example, a 50 μm square having a thickness of 500 nm, and the surface thereof is formed at the same height as the surface of the first interlayer insulating film 12. That is, the surface of the first interlayer insulating film 12 and the surface of the first metal electrode 15 are not stepped and are on the same plane. The first metal electrode 15 is made of copper, for example. Of course, another metal, for example, one of copper, gold, and silver, or an alloy using two or more of these metals may be used. Alternatively, an alloy containing these metals as a main material may be used.

Further, as shown in FIG. 5A, a second interlayer insulating film 22 is formed on the second substrate 21, and a second barrier metal layer is formed in the second groove 23 formed in the second interlayer insulating film 22. A second metal electrode 25 is embedded via 24. Such a second substrate 21 is prepared.
For example, a silicon substrate is used as the second substrate 21, and after forming a semiconductor element (not shown), forming a wiring (not shown), etc. by a normal LSI process, an interlayer insulating film is formed. Has been. A second barrier metal layer 24 is formed in the second groove 23 on the second interlayer insulating film 22 which is the uppermost layer of the interlayer insulating film by a normal trench wiring forming technique (for example, damascene processing method, dual damascene processing method, etc.). A second metal electrode 25 is formed therethrough.
The second metal electrode 25 is, for example, a 50 μm square having a thickness of 500 nm, and the surface thereof is formed at the same height as the surface of the second interlayer insulating film 22. That is, the surface of the second interlayer insulating film 22 and the surface of the second metal electrode 25 have no step and are on the same plane. The second metal electrode 25 is made of, for example, copper. Of course, another metal, for example, one of copper, gold, and silver, or an alloy using two or more of these metals may be used. Alternatively, an alloy containing these metals as a main material may be used.

Next, a diffusion prevention layer is formed on the interlayer insulating film on at least one side of the first interlayer insulating film 12 or the second interlayer insulating film 22. Here, a diffusion prevention layer is formed on both interlayer insulating films.
As shown in FIG. 4B, a first diffusion prevention layer 16 is formed on the surface of the first interlayer insulating film 12. The first diffusion preventing layer 16 is formed of a material that prevents copper diffusion. For example, it is formed of a silicon nitride compound or a carbonized silicon oxide compound. Examples of the silicon nitride compound include silicon nitride (SiN), examples of the silicon carbide oxide compound include silicon carbide oxide (SiOC), and silicon nitride carbonized oxide (SiOCN) can also be used. The film thickness may be any film thickness that prevents copper diffusion and prevents oxygen from entering the first metal electrode 15 side. For example, the film thickness is 30 nm or more and 50 nm or less.
For example, as a film forming condition when the first diffusion preventing layer 16 is formed of silicon nitride, a plasma CVD method is used as an example. The process conditions include, for example, the process gas and ammonia (NH _3), nitrogen (N ₂₎ with ammonia in the film forming atmosphere (NH ₃₎ to 50 cm ³ / min, nitrogen (N ₂₎ to 500 cm ³ / min Supply at a flow rate of. The pressure of the film formation atmosphere is set to 665 Pa, the substrate temperature is set to 350 ° C., and the RF power of the plasma CVD apparatus is set to 1000 W (13.56 MHz). Under this condition, the first diffusion preventing layer 16 was formed to a thickness of 50 nm.

As the first diffusion preventing layer 16, a silicon nitride film formed by plasma CVD is used as a film for preventing copper diffusion. However, other manufacturing methods (for example, high-frequency sputtering or high density plasma) are used. It may be used to form a film. In addition to the silicon nitride film, as described above, a silicon carbide oxide (SiOC) film or a nitrided silicon carbide oxide (SiOCN) film can also be used.
There is no difference in barrier properties between the silicon nitride film, the silicon carbide oxide (SiOC) film, and the silicon nitride carbonized oxide (SiOCN) film. For example, the diffusion of copper into the silicon nitride film and the silicon nitride film by heat treatment at 400 ° C. is about 20 nm. Therefore, if the silicon nitride film, the silicon carbide oxide film, and the silicon nitride carbide oxide (SiOCN) film have a film thickness of 30 nm or more, the barrier property of copper can be sufficiently secured.

Next, as shown in FIG. 4 (3), when the first metal electrode 15 and the second metal electrode 25 (see FIG. 5 (1)) are joined to face each other, the first metal electrode 15 is joined. A first opening 17 is formed in the first diffusion preventing layer 16 in each of the formation regions of the second metal electrode 25.
The first opening 17 is formed in, for example, a 30 μm square in plan layout. The size of the first opening 17 is appropriately determined. For example, when the first metal electrode 15 is thermally expanded during the heat treatment in a later process, the first opening 17 is formed in a size that can be embedded. Here, the size satisfying the above conditions was a 30 μm square.
For example, when the first diffusion prevention layer 16 is formed of a silicon nitride film, the first opening 17 is formed by, for example, reactive ion etching (RIE) using a fluorine-based etching gas.

Next, as shown in FIG. 4 (4), a pretreatment for removing the oxide film formed on the surface of the first metal electrode 15 is performed. This pretreatment is, for example, by reduction treatment by hydrogen plasma treatment.
For example, when the first metal electrode 15 is made of copper, hydrogen (H ₂ ) and argon (Ar) are used as a process gas, and hydrogen is supplied at a flow rate of 100 cm ³ / min, for example, in a reduction treatment atmosphere. Argon is supplied at a flow rate of 170 cm ³ / min. Further, the microwave power of hydrogen plasma treatment was 2.8 kW (2.45 GHz), the pressure of the reducing atmosphere was 0.4 Pa, the substrate temperature was 400 ° C., and the reduction treatment time was 1 minute. This condition is an example and can be changed as appropriate. Further, when the oxide film is not formed on the surface of the first metal electrode 15, for example, when the first metal electrode 15 is formed of gold, it is not necessary to perform the hydrogen reduction treatment.

Similarly, as shown in FIG. 5B, a pretreatment for removing the oxide film formed on the surface of the second metal electrode 25 is performed. This pretreatment is, for example, by reduction treatment by hydrogen plasma treatment.
For example, when the second metal electrode 25 is made of copper, hydrogen (H ₂ ) and argon (Ar) are used as a process gas, and hydrogen is supplied at a flow rate of 100 cm ³ / min, for example, in a reduction treatment atmosphere. Argon is supplied at a flow rate of 170 cm ³ / min. Further, the microwave power of hydrogen plasma treatment was 2.8 kW (2.45 GHz), the pressure of the reducing atmosphere was 0.4 Pa, the substrate temperature was 400 ° C., and the reduction treatment time was 1 minute. This condition is an example and can be changed as appropriate. Further, when the oxide film is not formed on the surface of the second metal electrode 25, for example, when the second metal electrode 25 is formed of gold, it is not necessary to perform the hydrogen reduction treatment.
Further, instead of the pretreatment with hydrogen plasma as described above, for example, hydrogen annealing, annealing with forming gas (nitrogen (N ₂ ) / hydrogen (H ₂ )), reduction with ammonia (NH ₃ ) plasma, formic acid plasma, etc. Processing may be performed.

  Next, as shown in FIG. 6 (5), the first metal electrode 15 and the second metal electrode 25 are opposed to each other with the first opening 17 interposed therebetween.

Then, as shown in FIG. 6 (6), heat treatment is performed in a state where the first diffusion preventing layer 16, the second metal electrode 25, and the second interlayer insulating film 22 are pressed and joined. Then, due to thermal expansion of the first metal electrode 15 and the second metal electrode 25, the first metal electrode 15 and the second metal electrode 25 are joined through the first opening 17.
That is, the first metal electrode 15 expands due to the heat treatment. At this time, since the first metal electrode 15 is fixed by the first interlayer insulating film 12 except for the first opening 17, the first metal electrode 15 expands toward the first opening 17. Similarly, the second metal electrode 25 expands. At this time, since the second metal electrode 25 is fixed by the second interlayer insulating film 22 except for the first opening 17, it expands toward the first opening 17.
And the 1st metal electrode 15 and the 2nd metal electrode 25 which were mutually expanded are joined in the 1st opening part 17, and are crimped | bonded by the pressure of expansion | swelling.
At this time, since the first diffusion preventing layer 16, the second metal electrode 25, and the second interlayer insulating film 22 are pressed and joined, the metal of the expanded metal electrode diffuses into the first diffusion. It does not enter between the prevention layer 16 and the second interlayer insulating film 22.
The first opening 17 is preferably filled with the expanded portions of the first metal electrode 15 and the second metal electrode 25 by the heat treatment. Therefore, it is preferable to determine the size of the first opening 17 in consideration of the volume expansion amounts of the first metal electrode 15 and the second metal electrode 25.

  In the semiconductor device manufacturing method (second example), even if misalignment occurs between the first substrate 11 and the second substrate 21, the first openings of the first metal electrode 15 and the second metal electrode 25. The 17 side is covered with the first diffusion preventing layer 16. That is, the first metal electrode 15 is surrounded by the first barrier metal layer 14 and the first diffusion prevention layer 16. The second metal electrode 25 is surrounded by the second barrier metal layer 24 and the first diffusion prevention layer 16. For this reason, the problem of misalignment can be solved.

  Further, since the thermal expansion (volume expansion) of the first metal electrode 15 and the second metal electrode 25 is used, the heating temperature at the time of bonding can be set to about 400 ° C. or less. Further, the first opening 17 is filled with the metal of the first metal electrode 15 and the second metal electrode 25 in a self-aligned manner by the volume expansion amount of the first metal electrode 15 and the second metal electrode 25 and joined. Is possible.

  In both the first and second examples, the heat treatment can be performed using a normal electric furnace, lamp heating furnace, or the like. The atmosphere during the heat treatment may be a vacuum state or an inert gas atmosphere. Microwave heating can also be used.

<2. Second Embodiment>
[Example of configuration of semiconductor device]
An example of the configuration of the semiconductor device according to the second embodiment of the present invention will be described with reference to the schematic cross-sectional view of FIG.

As shown in FIG. 7, a first interlayer insulating film 12 is formed on the first substrate 11, and the first trench 13 formed in the first interlayer insulating film 12 has a first barrier metal layer 14 interposed therebetween. One metal electrode 15 is embedded.
For example, a silicon substrate is used as the first substrate 11. A semiconductor element (not shown), wiring (not shown), and the like are formed on the silicon substrate, and an interlayer insulating film is further formed. The uppermost interlayer insulating film of the interlayer insulating film is the first interlayer insulating film 12.
The first metal electrode 15 is, for example, a 50 μm square and a thickness of 500 nm. The first metal electrode 15 is made of copper, for example. Of course, another metal, for example, one of copper, gold, and silver, or an alloy using two or more of these metals may be used. Alternatively, an alloy containing these metals as a main material may be used.

In addition, a second interlayer insulating film 22 is formed on the second substrate 21, and the second metal electrode 25 is formed in the second groove 23 formed in the second interlayer insulating film 22 via the second barrier metal layer 24. Embedded.
For example, a silicon substrate is used as the second substrate 21. A semiconductor element (not shown), wiring (not shown), and the like are formed on the silicon substrate, and an interlayer insulating film is further formed. The uppermost interlayer insulating film of this interlayer insulating film is the second interlayer insulating film 22.
The second metal electrode 25 is, for example, a 50 μm square and a thickness of 500 nm. The second metal electrode 25 is made of, for example, copper. Of course, another metal, for example, one of copper, gold, and silver, or an alloy using two or more of these metals may be used. Alternatively, an alloy containing these metals as a main material may be used.

  A first diffusion prevention layer 16 is formed between the first interlayer insulating film 12 and the second interlayer insulating film 22. The first diffusion preventing layer 16 is formed of a material that prevents copper diffusion. For example, it is formed of a silicon nitride film. The film thickness may be any film thickness that prevents copper diffusion and prevents oxygen from entering both the first metal electrode 15 and the second metal electrode 25. For example, the film thickness is 35 nm or more and 50 nm or less. ing.

  As the first diffusion preventing layer 16, a silicon nitride film formed by plasma CVD is used as a film for preventing copper diffusion. However, other manufacturing methods (for example, high-frequency sputtering or high density plasma) are used. The film used may be used. In addition to the silicon nitride film, a silicon carbide oxide (SiOC) film can also be used.

In the first diffusion preventing layer 16, a first opening 17 is formed in the formation region of each of the first metal electrode 15 and the second metal electrode 25.
The first opening 17 is formed in, for example, a 30 μm square in plan layout. The size of the first opening 17 is appropriately determined. For example, when the first metal electrode 15 and the second metal electrode 25 are thermally expanded during a heat treatment in a later process, the first opening 17 is formed in such a size as to be embedded. Here, the size satisfying the above conditions was a 30 μm square.

The first metal electrode 15 and the second metal electrode 25 are opposed to each other with the first opening 17 interposed therebetween. This joining is performed by thermocompression bonding by the thermal expansion of the first metal electrode 15 and the second metal electrode 25, for example.
The first opening 17 is preferably filled with the expanded portions of the first metal electrode 15 and the second metal electrode 25.

  In the semiconductor device, even if misalignment occurs between the first substrate 11 and the second substrate 21, the first opening 17 side of the first metal electrode 15 and the second metal electrode 25 has the first diffusion. It is covered with a prevention layer 16. That is, the first metal electrode 15 is surrounded by the first barrier metal layer 14 and the first diffusion prevention layer 16. The second metal electrode 25 is surrounded by the second barrier metal layer 24 and the first diffusion prevention layer 16. For this reason, the problem of misalignment can be solved.

  DESCRIPTION OF SYMBOLS 11 ... 1st board | substrate, 12 ... 1st interlayer insulation film, 13 ... 1st groove | channel, 15 ... 1st metal electrode, 16 ... 1st diffusion prevention layer, 17 ... 1st opening part, 21 ... 2nd board | substrate, 22 ... Second interlayer insulating film, 23 ... second groove, 25 ... second metal electrode, 26 ... second diffusion prevention layer, 27 ... second opening

Claims (6)

Preparing a first substrate in which a first interlayer insulating film is formed on a first substrate, and a first metal electrode is embedded in a first groove formed in the first interlayer insulating film;
Preparing a second substrate in which a second interlayer insulating film is formed on the second substrate, and a second metal electrode is embedded in a second groove formed in the second interlayer insulating film;
Forming a first diffusion barrier layer on the first interlayer insulating film side;
Forming a second diffusion barrier layer on the second interlayer insulating film side;
When the first metal electrode and the second metal electrode are joined to face each other, a first opening is formed in the first diffusion prevention layer in each formation region of the first metal electrode and the second metal electrode. Forming, and
When the first metal electrode and the second metal electrode are joined to face each other, a second opening is formed in the second diffusion prevention layer in each formation region of the first metal electrode and the second metal electrode. Forming, and
Performing a heat treatment with the first opening and the second opening facing each other, and joining the first metal electrode and the second metal electrode through the first opening and the second opening by thermal expansion; A method for manufacturing a semiconductor device.   The method of manufacturing a semiconductor device according to claim 1, wherein the first diffusion prevention layer and the second diffusion prevention layer are made of a silicon nitride compound or a silicon carbide oxide compound.   The method for manufacturing a semiconductor device according to claim 1, wherein the first opening and the second opening have an opening area difference. Preparing a first substrate in which a first interlayer insulating film is formed on a first substrate, and a first metal electrode is embedded in a first groove formed in the first interlayer insulating film;
Preparing a second substrate in which a second interlayer insulating film is formed on the second substrate, and a second metal electrode is embedded in a second groove formed in the second interlayer insulating film;
Forming a diffusion prevention layer on the interlayer insulating film on at least one side of the first interlayer insulating film or the second interlayer insulating film;
Forming an opening in the diffusion preventing layer in each of the formation regions of the first metal electrode and the second metal electrode when the first metal electrode and the second metal electrode are joined to face each other; ,
A step of heat-treating the first metal electrode and the second metal electrode facing each other with the opening interposed therebetween, and joining the first metal electrode and the second metal electrode through the opening by thermal expansion; Device manufacturing method.   The method of manufacturing a semiconductor device according to claim 4, wherein the diffusion prevention layer is made of a silicon nitride compound or a silicon carbide oxide compound.   6. The semiconductor device manufacturing method according to claim 1, wherein the first metal electrode and the second metal electrode are made of copper, gold, or silver, or a plurality of types of alloys thereof. 7. Method.

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