JP6127360B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Semiconductor device and manufacturing method of semiconductor device Download PDF

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JP6127360B2
JP6127360B2 JP2011210142A JP2011210142A JP6127360B2 JP 6127360 B2 JP6127360 B2 JP 6127360B2 JP 2011210142 A JP2011210142 A JP 2011210142A JP 2011210142 A JP2011210142 A JP 2011210142A JP 6127360 B2 JP6127360 B2 JP 6127360B2
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substrate
thin film
film
insulating thin
semiconductor device
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JP2013073988A (en
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賢哉 萩本
賢哉 萩本
宣年 藤井
藤井　　宣年
青柳　健一
健一 青柳
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Sony Corp
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Sony Corp
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Priority to TW101121190A priority patent/TWI495041B/en
Priority to US13/533,526 priority patent/US8896125B2/en
Priority to KR1020120069684A priority patent/KR102030852B1/en
Priority to CN201210233277.XA priority patent/CN102867847B/en
Publication of JP2013073988A publication Critical patent/JP2013073988A/en
Priority to US14/467,852 priority patent/US9111763B2/en
Priority to US14/718,942 priority patent/US9443802B2/en
Priority to US15/228,860 priority patent/US10038024B2/en
Priority to US15/228,894 priority patent/US9911778B2/en
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Publication of JP6127360B2 publication Critical patent/JP6127360B2/en
Priority to US15/992,908 priority patent/US10431621B2/en
Priority to US16/410,877 priority patent/US10985102B2/en
Priority to KR1020190069266A priority patent/KR20190071647A/en
Priority to KR1020200069977A priority patent/KR102298787B1/en
Priority to US17/194,641 priority patent/US11569123B2/en
Priority to KR1020210112763A priority patent/KR102439964B1/en
Priority to KR1020220109225A priority patent/KR102673911B1/en
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Description

本技術は、半導体装置および半導体装置の製造方法に関する。より詳細には、電極同士が電気的に接合された状態で２枚の基板を貼り合わせてなる半導体装置、およびその半導体装置の製造方法に関する。   The present technology relates to a semiconductor device and a method for manufacturing the semiconductor device. More specifically, the present invention relates to a semiconductor device in which two substrates are bonded together in a state where electrodes are electrically bonded, and a method for manufacturing the semiconductor device.

従来、２次元構造の半導体装置の高集化は、微細プロセスの導入と実装密度の向上によって実現されてきたが、これらによる２次元構造の高集化には物理的な限界がある。そこで、さらなる半導体装置の小型化および画素の高密度化を実現するため、３次元構造の半導体装置が開発されている。例えば、特許文献１には、光電変換部を有するセンサ基板と周辺回路部を有する回路基板とを積層させて貼り合わせてなる３次元構造の半導体装置が提案されている。   Conventionally, high concentration of a semiconductor device having a two-dimensional structure has been realized by introduction of a fine process and improvement in mounting density. However, high concentration of a two-dimensional structure by these has physical limitations. Therefore, in order to realize further downsizing of the semiconductor device and higher density of pixels, a semiconductor device having a three-dimensional structure has been developed. For example, Patent Document 1 proposes a three-dimensional semiconductor device in which a sensor substrate having a photoelectric conversion unit and a circuit substrate having a peripheral circuit unit are stacked and bonded together.

上述の３次元構造の半導体装置は、Ｃｕ電極と絶縁膜とを露出させた貼合せ面を有する基板を２枚用いて、貼合せ面を対向させた状態でＣｕ電極同士を位置合わせし、さらに熱処理をすることにより、基板同士を貼り合わせて作製される。このようにＣｕ電極を直接接合（Ｃｕ−Ｃｕ接合）することによって、基板を積層して貼り合わせてなる３次元構造の半導体装置がある。   The semiconductor device having the above-described three-dimensional structure uses two substrates having a bonding surface exposing a Cu electrode and an insulating film, aligns the Cu electrodes with the bonding surfaces facing each other, and By performing heat treatment, the substrates are bonded to each other. As described above, there is a semiconductor device having a three-dimensional structure in which substrates are stacked and bonded together by directly bonding Cu electrodes (Cu-Cu bonding).

特開２００６−１９１０８１号公報JP 2006-191081 A

しかしながら、上述した３次元構造の半導体装置は、製造工程中のＣｕ電極同士の位置合わせにおいて生じるズレや、またはＣｕ電極の形状や大きさの違い等により、Ｃｕ電極と絶縁膜との接合面が形成される。このＣｕ電極と絶縁膜が接合される接合面おいては、ボイドが発生する。そのため、接合面の貼合せ強度の低下による基板間の剥がれ等の問題点が生じる。   However, in the semiconductor device having the above-described three-dimensional structure, the bonding surface between the Cu electrode and the insulating film is caused by misalignment that occurs in the alignment of the Cu electrodes during the manufacturing process or the difference in the shape and size of the Cu electrode. It is formed. Voids are generated at the bonding surface where the Cu electrode and the insulating film are bonded. For this reason, problems such as peeling between the substrates due to a decrease in the bonding strength of the bonding surfaces occur.

そこで本技術は、２枚の基板を貼り合わせて電極同士を接合させた構成において、基板の接合面でのボイドの発生を防止して、基板間の貼合せ強度の向上が図られた３次元構造の半導体装置を提供することを目的とする。また本技術は、この半導体装置の製造方法を提供することを目的とする。   Therefore, in the present technology, in a configuration in which two substrates are bonded to each other and the electrodes are bonded to each other, generation of voids at the bonding surface of the substrates is prevented, and the bonding strength between the substrates is improved. An object is to provide a semiconductor device having a structure. Another object of the present technology is to provide a method for manufacturing the semiconductor device.

上記課題を解決するため、本技術の半導体装置は、第１基板と、絶縁性薄膜と、第２基板とを備えている。まず、第１基板は、第１電極および第１絶縁膜を露出させた貼合せ面を有する。一方、第２基板は、第２電極および第２絶縁膜を露出させた貼合せ面を有しており、この第２基板の貼合せ面と第１基板の貼合せ面とで絶縁性薄膜を挟持している。そして、第１電極と第２電極が絶縁性薄膜を介して電気的に接続された状態で、第１基板と第２基板とが貼り合わせられている。   In order to solve the above problems, a semiconductor device of the present technology includes a first substrate, an insulating thin film, and a second substrate. First, a 1st board | substrate has the bonding surface which exposed the 1st electrode and the 1st insulating film. On the other hand, the second substrate has a bonding surface in which the second electrode and the second insulating film are exposed, and an insulating thin film is formed between the bonding surface of the second substrate and the bonding surface of the first substrate. It is pinched. Then, the first substrate and the second substrate are bonded together in a state where the first electrode and the second electrode are electrically connected via the insulating thin film.

また本技術は、上述した構成の半導体装置の製造方法でもあり、次の手順を含む。まず電極および絶縁膜を露出させた貼合せ面を有する２枚の基板を用意する。次に、この２枚の基板のうち少なくとも一方の貼合せ面を覆う状態で、絶縁性薄膜を成膜する。その後、この絶縁性薄膜を介して２枚の基板の貼合せ面同士を対向配置し、２枚の基板の電極同士が絶縁性薄膜を介して電気的に接続される状態に位置合わせをして、２枚の基板を貼り合わせる。以上の手順により、上述した構成の半導体装置が得られる。   The present technology is also a method for manufacturing a semiconductor device having the above-described configuration, and includes the following procedure. First, two substrates having a bonding surface with an electrode and an insulating film exposed are prepared. Next, an insulating thin film is formed in a state where at least one of the two substrates is covered. Thereafter, the bonding surfaces of the two substrates are placed opposite to each other through the insulating thin film, and the electrodes of the two substrates are aligned to be electrically connected via the insulating thin film. Two substrates are bonded together. With the above procedure, the semiconductor device having the above-described configuration is obtained.

以上のような構成の半導体装置およびその製造方法では、絶縁性薄膜を介して第１基板と第２基板とが貼り合わせられたことにより、第１基板の貼合せ面と第２基板の貼合せ面とが直接接合されることがない。したがって、これらの貼合せ面が直接接合された構成において接合界面に生じていたボイドの発生が防止される。   In the semiconductor device having the above-described configuration and the manufacturing method thereof, the first substrate and the second substrate are bonded to each other through the insulating thin film, whereby the bonding surface of the first substrate and the second substrate are bonded. The surface is not directly joined. Therefore, generation | occurrence | production of the void which had arisen in the joining interface in the structure by which these bonding surfaces were joined directly is prevented.

以上の結果、本技術によれば、２枚の基板を貼り合わせて電極同士を接続させた構成において、接合界面におけるボイドの発生を防止でき、これにより２枚の基板間の接合強度が増して信頼性の向上が図られた半導体装置を得ることが可能になる。   As a result of the above, according to the present technology, in the configuration in which two substrates are bonded to each other and the electrodes are connected to each other, generation of voids at the bonding interface can be prevented, thereby increasing the bonding strength between the two substrates. A semiconductor device with improved reliability can be obtained.

本技術が適用される半導体装置の一例を示す概略構成図である。It is a schematic structure figure showing an example of a semiconductor device to which this art is applied. 本実施形態の半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device of this embodiment. 本実施形態の半導体装置の製造における第１基板（センサ基板）の作製手順（その１）を示す断面工程図である。It is sectional process drawing which shows the preparation procedure (the 1) of the 1st board | substrate (sensor substrate) in manufacture of the semiconductor device of this embodiment. 本実施形態の半導体装置の製造における第１基板（センサ基板）の作製手順（その２）を示す断面工程図である。It is sectional process drawing which shows the preparation procedure (the 2) of the 1st board | substrate (sensor substrate) in manufacture of the semiconductor device of this embodiment. 本実施形態の半導体装置の製造における第２基板（回路基板）の作製手順を示す断面工程図である。It is sectional process drawing which shows the preparation procedures of the 2nd board | substrate (circuit board | substrate) in manufacture of the semiconductor device of this embodiment. 本実施形態の半導体装置の製造における貼り合わせを示す断面図（その１）である。It is sectional drawing (the 1) which shows the bonding in manufacture of the semiconductor device of this embodiment. 本実施形態の半導体装置の製造における貼り合わせを示す断面図（その２）である。It is sectional drawing (the 2) which shows bonding in manufacture of the semiconductor device of this embodiment. 本技術を適用して得られた半導体装置を用いた電子機器の構成図である。It is a block diagram of the electronic device using the semiconductor device obtained by applying this technique.

以下、本技術の実施の形態を、図面に基づいて次に示す順に説明する。
１．本実施形態の半導体装置の概略構成例
２．本実施形態の半導体装置の構成
３．本実施形態の半導体装置の製造における第１基板（センサ基板）の作製手順
４．本実施形態の半導体装置の製造における第２基板（回路基板）の作製手順
５．本実施形態の半導体装置の製造における基板の貼り合わせ手順
６．本実施形態の半導体装置を用いた電子機器の一例 Hereinafter, embodiments of the present technology will be described in the following order based on the drawings.
1. 1. Schematic configuration example of semiconductor device of this embodiment 2. Configuration of semiconductor device according to this embodiment 3. Manufacturing procedure of first substrate (sensor substrate) in manufacturing semiconductor device of this embodiment 4. Manufacturing procedure of second substrate (circuit board) in manufacturing semiconductor device of this embodiment 5. Substrate bonding procedure in manufacturing the semiconductor device of this embodiment An example of an electronic apparatus using the semiconductor device of this embodiment

≪１．本実施形態の半導体装置の概略構成例≫
図１に、本技術が適用される半導体装置の一例として、固体撮像装置の概略構成を示す。
この図１に示す半導体装置１は、センサ基板としての第１基板２と、この第１基板２に対して積層された状態で貼り合せらされた回路基板としての第２基板７とを含む、いわゆる３次元構造の半導体装置（固体撮像装置）である。 << 1. Schematic configuration example of semiconductor device of this embodiment >>
FIG. 1 shows a schematic configuration of a solid-state imaging device as an example of a semiconductor device to which the present technology is applied.
The semiconductor device 1 shown in FIG. 1 includes a first substrate 2 as a sensor substrate, and a second substrate 7 as a circuit substrate bonded to the first substrate 2 in a stacked state. This is a so-called three-dimensional semiconductor device (solid-state imaging device).

このうち、第１基板２には、光電変換部を含む複数の画素３が規則的に２次元配列された画素領域４が設けられている。この画素領域４には、複数の画素駆動線５が行方向に配線され、複数の垂直信号線６が列方向に配線されており、１つの画素３が１本の画素駆動線５と１本の垂直信号線６とに接続される状態で配置されている。これらの各画素３には、光電変換部と、フローティングディフュージョンと、複数のトランジスタ（いわゆるＭＯＳトランジスタ）および容量素子等で構成された画素回路とが設けられている。なお、複数の画素で画素回路の一部を共有している場合もある。   Among these, the first substrate 2 is provided with a pixel region 4 in which a plurality of pixels 3 including a photoelectric conversion unit are regularly arranged two-dimensionally. In the pixel region 4, a plurality of pixel drive lines 5 are wired in the row direction, a plurality of vertical signal lines 6 are wired in the column direction, and one pixel 3 is connected to one pixel drive line 5 and one pixel line. It is arranged in a state of being connected to the vertical signal line 6. Each of these pixels 3 is provided with a photoelectric conversion unit, a floating diffusion, a pixel circuit composed of a plurality of transistors (so-called MOS transistors), a capacitor element, and the like. Note that a part of the pixel circuit may be shared by a plurality of pixels.

また、第２基板７には、第１基板２に設けられた各画素３を駆動するための垂直駆動回路８、カラム信号処理回路９、水平駆動回路１０、およびシステム制御回路１１などの周辺回路が設けられている。   The second substrate 7 includes peripheral circuits such as a vertical drive circuit 8, a column signal processing circuit 9, a horizontal drive circuit 10, and a system control circuit 11 for driving each pixel 3 provided on the first substrate 2. Is provided.

≪２．本実施形態の半導体装置の構成≫
図２は、本実施形態の半導体装置の構成を示す要部断面図であり、図１における３画素分の断面図である。以下、この要部断面図に基づいて、本実施形態の半導体装置の詳細な構成を説明する。 ≪2. Configuration of Semiconductor Device of this Embodiment >>
FIG. 2 is a cross-sectional view of the main part showing the configuration of the semiconductor device of this embodiment, and is a cross-sectional view of three pixels in FIG. The detailed configuration of the semiconductor device according to the present embodiment will be described below based on the cross-sectional view of the main part.

図２に示す半導体装置１は、絶縁性薄膜１２を挟持する状態で第１基板２の貼合せ面４１と第２基板７の貼合せ面７１が対向配置されて、第１基板２と第２基板７とが貼り合わせられた３次元構造の固体撮像装置である。本実施形態においては、絶縁性薄膜１２を介して第１基板２と第２基板７とが貼り合わせられた構造が特徴的である。   In the semiconductor device 1 shown in FIG. 2, the bonding surface 41 of the first substrate 2 and the bonding surface 71 of the second substrate 7 are arranged to face each other with the insulating thin film 12 interposed therebetween, so that the first substrate 2 and the second substrate 2 A solid-state imaging device having a three-dimensional structure in which a substrate 7 is bonded. In the present embodiment, the structure in which the first substrate 2 and the second substrate 7 are bonded together with the insulating thin film 12 is characteristic.

ここで、第１基板２は、半導体層２ａ、配線層２ｂ、および電極層２ｃが、第２基板７とは反対側から順に積層されており、さらに電極層２ｃの表面が第２基板７に対する貼合せ面４１として構成されている。一方、第２基板７は、半導体層７ａ、配線層７ｂ、および電極層７ｃが、第１基板２の反対側から順に積層されており、さらに電極層７ｃの表面が第１基板２に対する貼合せ面７１として構成されている。   Here, in the first substrate 2, the semiconductor layer 2a, the wiring layer 2b, and the electrode layer 2c are laminated in order from the side opposite to the second substrate 7, and the surface of the electrode layer 2c is further to the second substrate 7. It is configured as a bonding surface 41. On the other hand, in the second substrate 7, the semiconductor layer 7a, the wiring layer 7b, and the electrode layer 7c are laminated in order from the opposite side of the first substrate 2, and the surface of the electrode layer 7c is bonded to the first substrate 2. It is configured as a surface 71.

また、第１基板２における第２基板７と反対側の面には、保護膜１５、カラーフィルタ層１７、およびオンチップレンズ１９が図示される順に積層されている。   A protective film 15, a color filter layer 17, and an on-chip lens 19 are stacked in the order shown in the figure on the surface of the first substrate 2 opposite to the second substrate 7.

次に、第１基板２および第２基板７を構成する各層、および絶縁性薄膜１２の詳細な構成を順次説明し、さらに、保護膜１５、カラーフィルタ層１７、およびオンチップレンズ１９の構成を順次説明する。   Next, detailed configurations of the layers constituting the first substrate 2 and the second substrate 7 and the insulating thin film 12 will be described in order, and further, the configurations of the protective film 15, the color filter layer 17, and the on-chip lens 19 will be described. A description will be made sequentially.

［半導体層２ａ（第１基板２側）］
第１基板２側の半導体層２ａは、例えば単結晶シリコンからなる半導体基板２０を薄膜化したものである。この半導体層２ａにおいて、カラーフィルタ層１７やオンチップレンズ１９等が配置されている第１面側には、例えばｎ型不純物層（またはｐ型不純物層）からなる光電変換部２１が画素毎に設けられている。一方、半導体層２ａの第２面側には、ｎ＋型不純物層からなるフローティングディフュージョンＦＤおよびトランジスタＴｒのソース／ドレイン２３、さらにはここでの図示を省略した他の不純物層などが設けられている。 [Semiconductor layer 2a (first substrate 2 side)]
The semiconductor layer 2a on the first substrate 2 side is obtained by thinning a semiconductor substrate 20 made of, for example, single crystal silicon. In the semiconductor layer 2a, on the first surface side where the color filter layer 17, the on-chip lens 19 and the like are arranged, a photoelectric conversion unit 21 made of, for example, an n-type impurity layer (or a p-type impurity layer) is provided for each pixel. Is provided. On the other hand, on the second surface side of the semiconductor layer 2a, a floating diffusion FD composed of an n + type impurity layer, a source / drain 23 of the transistor Tr, and other impurity layers not shown here are provided. .

[配線層２ｂ（第１基板２側）］
第１基板２において半導体層２ａ上に設けられた配線層２ｂは、半導体層２ａとの界面側に、ゲート絶縁膜２５を介して設けられた転送ゲートＴＧおよびトランジスタＴｒのゲート電極２７、さらにはここでの図示を省略した他の電極を有している。これらの転送ゲートＴＧおよびゲート電極２７は、層間絶縁膜２９で覆われており、層間絶縁膜２９に形成された溝パターン内には埋込配線３１が設けられている。この埋込配線３１は、溝パターンの内壁を覆うバリアメタル層３１ａと、バリアメタル層３１ａを介して溝パターンに埋め込まれた銅（Ｃｕ）からなる配線層３１ｂとにより構成されている。 [Wiring layer 2b (first substrate 2 side)]
The wiring layer 2b provided on the semiconductor layer 2a in the first substrate 2 has a transfer gate TG and a gate electrode 27 of the transistor Tr provided on the interface side with the semiconductor layer 2a via the gate insulating film 25, and further It has other electrodes which are not shown here. The transfer gate TG and the gate electrode 27 are covered with an interlayer insulating film 29, and a buried wiring 31 is provided in a groove pattern formed in the interlayer insulating film 29. The embedded wiring 31 includes a barrier metal layer 31a covering the inner wall of the groove pattern, and a wiring layer 31b made of copper (Cu) embedded in the groove pattern via the barrier metal layer 31a.

なお、以上のような配線層２ｂは、さらに積層された多層配線層として構成されていてもよい。   The wiring layer 2b as described above may be configured as a multilayer wiring layer that is further laminated.

［電極層２ｃ（第１基板２側）］
第１基板２において配線層２ｂ上に設けられた電極層２ｃは、配線層２ｂとの界面側に、銅（Ｃｕ）に対する拡散防止絶縁膜３２と、これに積層された第１絶縁膜３５とを備えている。第１絶縁膜３５は、例えばＴＥＯＳ膜からなり、第１絶縁膜３５に形成された溝パターン内には、埋込電極として第１電極３３が設けられている。なおＴＥＯＳ膜とは、ＴＥＯＳガス（Tetra Ethoxy Silaneガス：組成Ｓｉ（ＯＣ２Ｈ５）４）を原料ガスとする化学気相成長法（Chemical Vapor Deposition：以下ＣＶＤ法）により成膜された酸化シリコン膜である。そして、第１電極３３は、溝パターンの内壁を覆うバリアメタル層３３ａと、バリアメタル層３３ａを介して溝パターンに埋め込まれた銅（Ｃｕ）からなる第１電極膜３３ｂとにより構成されている。
このような構成の電極層２ｃの表面が、第２基板７に対する第１基板２側の貼合せ面４１となっている。貼合せ面４１は、第１電極３３および第１絶縁膜３５が露出して構成されており、例えば化学的機械研磨（Chemical Mechanical Polishing：以下ＣＭＰ）によって平坦化された状態となっている。 [Electrode layer 2c (first substrate 2 side)]
The electrode layer 2c provided on the wiring layer 2b in the first substrate 2 has a diffusion preventing insulating film 32 for copper (Cu) and a first insulating film 35 laminated thereon on the interface side with the wiring layer 2b. It has. The first insulating film 35 is made of, for example, a TEOS film, and a first electrode 33 is provided as a buried electrode in the groove pattern formed in the first insulating film 35. The TEOS film is silicon oxide formed by a chemical vapor deposition method (hereinafter referred to as a CVD method) using TEOS gas (Tetra Ethoxy Silane gas: composition Si (OC 2 H 5 ) 4 ) as a source gas. It is a membrane. The first electrode 33 includes a barrier metal layer 33a covering the inner wall of the groove pattern, and a first electrode film 33b made of copper (Cu) embedded in the groove pattern via the barrier metal layer 33a. .
The surface of the electrode layer 2 c having such a configuration serves as a bonding surface 41 on the first substrate 2 side with respect to the second substrate 7. The bonding surface 41 is configured such that the first electrode 33 and the first insulating film 35 are exposed, and is flattened by, for example, chemical mechanical polishing (hereinafter CMP).

なお、ここでの図示は省略したが、第１絶縁膜３５に設けられた溝パターンの一部は、配線層２ｂに設けた埋込配線３１に達しており、この溝パターン内部に埋め込まれた第１電極３３が必要に応じて埋込配線３１に接続された状態となっている。   Although illustration is omitted here, a part of the groove pattern provided in the first insulating film 35 reaches the embedded wiring 31 provided in the wiring layer 2b and is embedded in the groove pattern. The first electrode 33 is connected to the embedded wiring 31 as necessary.

［半導体層７ａ（第２基板７側）］
一方、第２基板７側の半導体層７ａは、例えば単結晶シリコンからなる半導体基板５０を薄膜化したものである。この半導体層７ａにおいて、第１基板２側の表面層には、トランジスタＴｒのソース／ドレイン５１、さらにはここでの図示を省略した不純物層などが設けられている。 [Semiconductor layer 7a (second substrate 7 side)]
On the other hand, the semiconductor layer 7a on the second substrate 7 is formed by thinning a semiconductor substrate 50 made of, for example, single crystal silicon. In the semiconductor layer 7a, the source / drain 51 of the transistor Tr, an impurity layer not shown here, and the like are provided on the surface layer on the first substrate 2 side.

[配線層７ｂ（第２基板７側）］
第２基板７において半導体層７ａ上に設けられた配線層７ｂは、半導体層７ａとの界面側に、ゲート絶縁膜５３を介して設けられたゲート電極５５、さらにはここでの図示を省略した他の電極を有している。これらのゲート電極５５および他の電極は、層間絶縁膜５７で覆われており、層間絶縁膜５７に形成された溝パターン内には埋込配線５９が設けられている。埋込配線５９は、溝パターンの内壁を覆うバリアメタル層５９ａと、バリアメタル層５９ａを介して溝パターンに埋め込まれた銅（Ｃｕ）からなる配線層５９ｂとにより構成されている。
なお、以上のような配線層７ｂは、多層配線層構造としてもよい。 [Wiring layer 7b (second substrate 7 side)]
The wiring layer 7b provided on the semiconductor layer 7a in the second substrate 7 has a gate electrode 55 provided via the gate insulating film 53 on the interface side with the semiconductor layer 7a, and further illustration is omitted here. It has other electrodes. These gate electrodes 55 and other electrodes are covered with an interlayer insulating film 57, and a buried wiring 59 is provided in a groove pattern formed in the interlayer insulating film 57. The embedded wiring 59 includes a barrier metal layer 59a that covers the inner wall of the groove pattern, and a wiring layer 59b made of copper (Cu) embedded in the groove pattern via the barrier metal layer 59a.
Note that the wiring layer 7b as described above may have a multilayer wiring layer structure.

［電極層７ｃ（第２基板７側）］
第２基板７において配線層７ｂ上に設けられた電極層７ｃは、配線層７ｂとの界面側に、銅（Ｃｕ）に対する拡散防止絶縁膜６１と、この上部に積層された第２絶縁膜６９とを備えている。第２絶縁膜６９は例えばＴＥＯＳ膜からなり、第２絶縁膜６９に形成された溝パターン内には、埋込電極として第２電極６７が設けられている。第２電極６７は、溝パターンの内壁を覆うバリアメタル層６７ａと、バリアメタル層６７ａを介して溝パターンに埋め込まれた銅（Ｃｕ）からなる第２電極膜６７ｂとにより構成されている。この第２電極６７は、第１基板２側の第１電極３３と対応するように配置され、絶縁性薄膜１２を介した状態で第１基板２側の第１電極３３と電気的に接続されている。
このような電極層７ｃの表面が、第１基板２に対する第２基板７側の貼合せ面７１となっている。貼合せ面７１は、第２電極６７および第２絶縁膜６９が露出して構成されており、例えばＣＭＰによって平坦化された状態となっている。 [Electrode layer 7c (second substrate 7 side)]
The electrode layer 7c provided on the wiring layer 7b in the second substrate 7 has a diffusion prevention insulating film 61 for copper (Cu) on the interface side with the wiring layer 7b, and a second insulating film 69 laminated thereon. And. The second insulating film 69 is made of, for example, a TEOS film, and a second electrode 67 is provided as a buried electrode in the groove pattern formed in the second insulating film 69. The second electrode 67 includes a barrier metal layer 67a covering the inner wall of the groove pattern, and a second electrode film 67b made of copper (Cu) embedded in the groove pattern via the barrier metal layer 67a. The second electrode 67 is disposed so as to correspond to the first electrode 33 on the first substrate 2 side, and is electrically connected to the first electrode 33 on the first substrate 2 side through the insulating thin film 12. ing.
The surface of such an electrode layer 7 c is a bonding surface 71 on the second substrate 7 side with respect to the first substrate 2. The bonding surface 71 is configured by exposing the second electrode 67 and the second insulating film 69, and is flattened by, for example, CMP.

［絶縁性薄膜１２］
絶縁性薄膜１２は、第１基板２側の貼合せ面４１と第２基板７側の貼合せ面７１との間に狭持されており、貼合せ面４１および貼合せ面７１の全面を覆っている。すなわち、第１基板２と第２基板７とは、この絶縁性薄膜１２を介して貼り合わせられている。 [Insulating thin film 12]
The insulating thin film 12 is sandwiched between the bonding surface 41 on the first substrate 2 side and the bonding surface 71 on the second substrate 7 side, and covers the entire surface of the bonding surface 41 and the bonding surface 71. ing. That is, the first substrate 2 and the second substrate 7 are bonded together via the insulating thin film 12.

上述のような絶縁性薄膜１２は、例えば、酸化膜および窒化膜からなり、半導体に一般的に使用されている酸化膜および窒化膜が用いられる。以下に、絶縁性薄膜１２の構成材料について詳しく説明する。   The insulating thin film 12 as described above is made of, for example, an oxide film and a nitride film, and an oxide film and a nitride film generally used for semiconductors are used. Below, the constituent material of the insulating thin film 12 is demonstrated in detail.

絶縁性薄膜１２が酸化膜からなる場合は、例えば、酸化シリコン（ＳｉＯ２）、ハフニア（ＨｆＯ２）を用いる。絶縁性薄膜１２が酸化膜からなり、第１電極３３および第２電極６７が銅（Ｃｕ）からなる場合は、これら電極材料である銅（Ｃｕ）が絶縁性薄膜１２中に拡散しやすい。このような銅（Ｃｕ）の拡散によって絶縁性薄膜１２の電気抵抗が下がるので、絶縁性薄膜１２を介した第１電極３３と第２電極６７との間の導電性が向上する。それゆえ、絶縁性薄膜１２が酸化膜からなる場合には、絶縁性薄膜１２を多少厚く成膜してもよい。 When the insulating thin film 12 is made of an oxide film, for example, silicon oxide (SiO 2 ) or hafnia (HfO 2 ) is used. When the insulating thin film 12 is made of an oxide film and the first electrode 33 and the second electrode 67 are made of copper (Cu), copper (Cu) as these electrode materials is likely to diffuse into the insulating thin film 12. Since the electrical resistance of the insulating thin film 12 decreases due to such diffusion of copper (Cu), the conductivity between the first electrode 33 and the second electrode 67 through the insulating thin film 12 is improved. Therefore, when the insulating thin film 12 is made of an oxide film, the insulating thin film 12 may be formed somewhat thick.

絶縁性薄膜１２が窒化膜からなる場合は、例えば、窒化シリコン（ＳｉＮ）を用いる。窒化膜からなる絶縁性薄膜１２は、第１電極３３および第２電極６７に対する拡散防止性を有する。
これにより、同一基板内においては、絶縁性薄膜１２を介して同一基板の電極間に生じるリーク電流を防止できる。すなわち、第１基板２においては、絶縁性薄膜１２を介して生じる隣接する第１電極３３間のリーク電流を防止できる。これと同様に、第２基板７においては、絶縁性薄膜１２を介して生じる隣接する第２電極６７間のリーク電流を防止できる。
一方、異なる基板間においては、電極材料が対向する基板側の絶縁膜に拡散することを防止できる。すなわち、第１基板２側の第１電極３３が、対向する第２基板７側の第２絶縁膜６９に拡散することを防止できる。同様に、第２基板７側の第２電極６７が、対向する第１基板２側の第１絶縁膜３５に拡散することを防止できる。それゆえ、各基板の貼合せ面における絶縁膜が露出している部分に、対向する基板側の電極に対する拡散防止材料からなるバリア膜を設ける必要がない。 When the insulating thin film 12 is made of a nitride film, for example, silicon nitride (SiN) is used. The insulating thin film 12 made of a nitride film has a diffusion preventing property for the first electrode 33 and the second electrode 67.
Thereby, in the same board | substrate, the leak current produced between the electrodes of the same board | substrate through the insulating thin film 12 can be prevented. That is, in the first substrate 2, the leakage current between the adjacent first electrodes 33 that occurs through the insulating thin film 12 can be prevented. Similarly, in the second substrate 7, the leakage current between the adjacent second electrodes 67 generated through the insulating thin film 12 can be prevented.
On the other hand, between different substrates, the electrode material can be prevented from diffusing into the insulating film on the opposite substrate side. That is, the first electrode 33 on the first substrate 2 side can be prevented from diffusing into the second insulating film 69 on the second substrate 7 side facing the first electrode 33. Similarly, the second electrode 67 on the second substrate 7 side can be prevented from diffusing into the first insulating film 35 on the opposite first substrate 2 side. Therefore, it is not necessary to provide a barrier film made of a diffusion preventing material for the electrode on the opposite substrate side in the exposed portion of the insulating film on the bonding surface of each substrate.

また特に本実施形態では、絶縁性薄膜１２を介した状態で、第１基板２側の第１電極３３と第２基板７側の第２電極６７とが電気的に接続されていることが重要である。そのため、絶縁性薄膜１２の膜厚は極めて薄い。その膜厚は、絶縁性薄膜１２の材料により異なるものの、例えば、酸化シリコン（ＳｉＯ２）、ハフニア（ＨｆＯ２）等の酸化物や、その他のほとんどの材料において、およそ２ｎｍ以下である。ただし、絶縁性薄膜１２の膜質によっては、さらに厚い膜を用いた場合もある。このような絶縁性薄膜１２を介して対向配置された第１電極３３と第２電極６７との間には、トンネル電流が流れる。また、一定以上の電圧を印加して絶縁破壊を起こすことにより、これら第１電極３３と第２電極６７との間は完全な導通状態となり電流が流れる。 In particular, in the present embodiment, it is important that the first electrode 33 on the first substrate 2 side and the second electrode 67 on the second substrate 7 side are electrically connected through the insulating thin film 12. It is. Therefore, the thickness of the insulating thin film 12 is extremely thin. Although the film thickness varies depending on the material of the insulating thin film 12, it is about 2 nm or less in, for example, oxides such as silicon oxide (SiO 2 ) and hafnia (HfO 2 ) and most other materials. However, a thicker film may be used depending on the quality of the insulating thin film 12. A tunnel current flows between the first electrode 33 and the second electrode 67 that are arranged to face each other with the insulating thin film 12 interposed therebetween. In addition, by applying a voltage higher than a certain level to cause dielectric breakdown, the first electrode 33 and the second electrode 67 are in a completely conductive state, and a current flows.

なお、本実施形態の半導体装置１において、絶縁性薄膜１２は、上述の一層の構造に限らず、同じ材料による積層構造であってもよく、また異なる材料による積層構造であってもよい。   In the semiconductor device 1 of this embodiment, the insulating thin film 12 is not limited to the single-layer structure described above, and may be a laminated structure made of the same material or a laminated structure made of different materials.

［保護膜１５、カラーフィルタ層１７、オンチップレンズ１９］
保護膜１５は、第１基板２の光電変換部２１を覆って設けられている。この保護膜１５は、パッシベーション性を有する材料膜で構成され、例えば酸化シリコン膜、窒化シリコン膜、または酸窒化シリコン膜などが用いられる。
カラーフィルタ層１７は、各光電変換部２１に対応して１対１で設けられた各色のカラーフィルタで構成されている。各色のカラーフィルタの配列が限定されることはない。
オンチップレンズ１９は、各光電変換部２１およびカラーフィルタ層１７を構成する各色のカラーフィルタに対応して１対１で設けられ、各光電変換部２１に入射光が集光されるように構成されている。 [Protective film 15, color filter layer 17, on-chip lens 19]
The protective film 15 is provided so as to cover the photoelectric conversion unit 21 of the first substrate 2. The protective film 15 is made of a material film having passivation properties. For example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is used.
The color filter layer 17 is composed of color filters of the respective colors provided on a one-to-one basis corresponding to the photoelectric conversion units 21. The arrangement of the color filters for each color is not limited.
The on-chip lens 19 is provided in a one-to-one correspondence with the color filters of each color that constitute each photoelectric conversion unit 21 and the color filter layer 17, and is configured so that incident light is condensed on each photoelectric conversion unit 21. Has been.

［本実施形態の半導体装置の構成による効果］
上述のように構成された本実施形態の半導体装置１は、図２に示すように、絶縁性薄膜１２を介して第１基板２と第２基板７とが貼り合わせられたことにより、第１基板２の貼合せ面４１と第２基板７の貼合せ面７１とが直接接することはない。したがって、これらの貼合せ面が直接接合された構成において接合界面に生じていたボイドの発生が防止される。これにより、２枚の基板間の接合強度が増して信頼性の向上が図られた半導体装置を得ることが可能になる。 [Effects of the configuration of the semiconductor device of this embodiment]
As shown in FIG. 2, the semiconductor device 1 of the present embodiment configured as described above has the first substrate 2 and the second substrate 7 bonded together via the insulating thin film 12. The bonding surface 41 of the substrate 2 and the bonding surface 71 of the second substrate 7 are not in direct contact. Therefore, generation | occurrence | production of the void which had arisen in the joining interface in the structure by which these bonding surfaces were joined directly is prevented. As a result, it is possible to obtain a semiconductor device in which the bonding strength between the two substrates is increased and the reliability is improved.

特に第１絶縁膜３５および第２絶縁膜６９がＴＥＯＳ膜からなる場合には、ＴＥＯＳ膜表面にＯＨ基が多く存在するため、ＴＥＯＳ膜からなる絶縁膜同士が直接接合する接合界面において、脱水縮合によるボイドが発生する。このように絶縁膜がＴＥＯＳ膜である場合においても、本実施形態の半導体装置１では、絶縁性薄膜１２を介して基板を貼り合わせるので、ＴＥＯＳ膜同士が直接接合することはなく、脱水縮合によるボイドの発生を防止できる。これにより、２枚の基板間の接合強度が増して信頼性の向上が図られた半導体装置を得ることが可能になる。   In particular, when the first insulating film 35 and the second insulating film 69 are made of a TEOS film, there are many OH groups on the surface of the TEOS film. Therefore, dehydration condensation is performed at the bonding interface where the insulating films made of the TEOS film are directly bonded to each other. A void is generated. Thus, even when the insulating film is a TEOS film, in the semiconductor device 1 of the present embodiment, the substrates are bonded together via the insulating thin film 12, so the TEOS films are not directly bonded to each other, and dehydration condensation occurs. Generation of voids can be prevented. As a result, it is possible to obtain a semiconductor device in which the bonding strength between the two substrates is increased and the reliability is improved.

≪３．本実施形態の半導体装置の製造における第１基板（センサ基板）の作製手順≫
図３は上述した本実施形態の半導体装置の製造に用いる第１基板２の作製手順を示す断面工程図（その１）であり、図４はこの図３に続く断面工程図（その２）である。以下、これらの図に基づいて本実施形態に用いる第１基板２（センサ基板）の作製手順を説明する。 ≪3. Manufacturing Procedure of First Substrate (Sensor Substrate) in Manufacturing Semiconductor Device of this Embodiment >>
FIG. 3 is a cross-sectional process diagram (part 1) showing a manufacturing procedure of the first substrate 2 used for manufacturing the semiconductor device of the present embodiment described above, and FIG. 4 is a cross-sectional process diagram (part 2) subsequent to FIG. is there. Hereinafter, a manufacturing procedure of the first substrate 2 (sensor substrate) used in the present embodiment will be described based on these drawings.

図３Ａに示すように、例えば単結晶シリコンからなる半導体基板２０を用意する。この半導体基板２０の所定深さにｎ型不純物層からなる光電変換部２１を形成し、さらに光電変換部２１の表面層に、ｎ＋型不純物層からなる電荷転送部やｐ＋型不純物層からなる正孔用の電荷蓄積部を形成する。また半導体基板２０の表面層に、ｎ＋型不純物層からなるフローティングディフュージョンＦＤ、およびソース／ドレイン２３、さらにはここでの図示を省略した他の不純物層を形成する。 As shown in FIG. 3A, a semiconductor substrate 20 made of, for example, single crystal silicon is prepared. A photoelectric conversion portion 21 made of an n-type impurity layer is formed at a predetermined depth of the semiconductor substrate 20, and further, a charge transfer portion made of an n + -type impurity layer and a p + -type impurity layer are formed on the surface layer of the photoelectric conversion portion 21. The charge storage part for holes is formed. Further, a floating diffusion FD composed of an n + -type impurity layer, a source / drain 23, and other impurity layers not shown here are formed on the surface layer of the semiconductor substrate 20.

次に、半導体基板２０上に、ゲート絶縁膜２５を成膜し、さらにこの上部に転送ゲートＴＧおよびゲート電極２７を形成する。ここで、転送ゲートＴＧはフローティングディフュージョンＦＤと光電変換部２１との間に形成され、ゲート電極２７は、ソース／ドレイン２３間に形成される。またこれと同一工程により、ここでの図示を省略した他の電極を形成する。
なお、ここまでの工程は、通常の作製手順を適宜選択して行なってもよい。 Next, a gate insulating film 25 is formed on the semiconductor substrate 20, and a transfer gate TG and a gate electrode 27 are formed thereon. Here, the transfer gate TG is formed between the floating diffusion FD and the photoelectric conversion unit 21, and the gate electrode 27 is formed between the source / drain 23. Further, another electrode not shown here is formed by the same process.
Note that the steps up to here may be performed by appropriately selecting a normal manufacturing procedure.

その後、ゲート絶縁膜２５上に、転送ゲートＴＧおよびゲート電極２７を覆う状態で、例えば酸化シリコンからなる層間絶縁膜２９を成膜する。さらに層間絶縁膜２９に溝パターンを形成し、この溝パターン内にバリアメタル層３１ａを介して配線層３１ｂを埋め込んでなる埋込配線３１を形成する。この埋込配線３１は、必要箇所で転送ゲートＴＧに接続して形成される。またここでの図示は省略したが、一部の埋込配線３１は、必要箇所でソース／ドレイン２３に接続して形成される。以上により、埋込配線３１を備えた配線層２ｂを得る。なお、この埋込配線３１の形成には、図３Ｂ以下を用いて説明する埋込配線技術を適用する。   Thereafter, an interlayer insulating film 29 made of, for example, silicon oxide is formed on the gate insulating film 25 so as to cover the transfer gate TG and the gate electrode 27. Further, a groove pattern is formed in the interlayer insulating film 29, and an embedded wiring 31 is formed by embedding the wiring layer 31b in the groove pattern via the barrier metal layer 31a. The embedded wiring 31 is formed at a necessary location so as to be connected to the transfer gate TG. Although not shown here, some of the embedded wirings 31 are formed so as to be connected to the source / drain 23 at necessary portions. As described above, the wiring layer 2b including the embedded wiring 31 is obtained. It should be noted that the embedded wiring technique described with reference to FIG.

続いて、配線層２ｂ上に、拡散防止絶縁膜３２を成膜し、さらにこの上に第１絶縁膜３５を成膜する。例えばＴＥＯＳガスを用いたＣＶＤ法により、ＴＥＯＳ膜からなる第１絶縁膜３５を成膜する。その後、この第１絶縁膜３５に、以下に説明する埋込配線技術を適用して、第１電極３３を形成する。   Subsequently, a diffusion preventing insulating film 32 is formed on the wiring layer 2b, and a first insulating film 35 is further formed thereon. For example, the first insulating film 35 made of a TEOS film is formed by a CVD method using TEOS gas. Thereafter, the first electrode 33 is formed on the first insulating film 35 by applying a buried wiring technique described below.

図３Ｂに示すように、第１絶縁膜３５に溝パターン３５ａを形成する。ここでの図示は省略したが、溝パターン３５ａは、必要な箇所では埋込配線３１に達する形状で形成される。   As shown in FIG. 3B, a groove pattern 35 a is formed in the first insulating film 35. Although illustration is omitted here, the groove pattern 35a is formed in a shape reaching the embedded wiring 31 at a necessary location.

図３Ｃに示すように、溝パターン３５ａの内壁を覆う状態でバリアメタル層３３ａを成膜し、この上部に溝パターン３５ａを埋め込む状態で第１電極膜３３ｂを成膜する。バリアメタル層３３ａは、第１電極膜３３ｂが第１絶縁膜３５に拡散することを防ぐようなバリア性のある材料で構成され、一方、第１電極膜３３ｂは銅（Ｃｕ）からなるが、これに限らず、導電性のある材料により構成される。   As shown in FIG. 3C, a barrier metal layer 33a is formed in a state of covering the inner wall of the groove pattern 35a, and a first electrode film 33b is formed in a state of embedding the groove pattern 35a thereon. The barrier metal layer 33a is made of a material having a barrier property that prevents the first electrode film 33b from diffusing into the first insulating film 35, while the first electrode film 33b is made of copper (Cu). Not limited to this, it is made of a conductive material.

図４Ｄに示すように、ＣＭＰ法により、バリアメタル層３３ａが露出するまで第１電極膜３３ｂを平坦化除去し、さらに、第１絶縁膜３５が露出するまでバリアメタル層３３ａを平坦化除去する。これにより、溝パターン３５ａ内にバリアメタル層３３ａを介して第１電極膜３３ｂを埋め込んでなる第１電極３３を形成する。以上により、第１電極３３を備えた電極層２ｃを得る。   As shown in FIG. 4D, the first electrode film 33b is planarized and removed by CMP until the barrier metal layer 33a is exposed, and further, the barrier metal layer 33a is planarized and removed until the first insulating film 35 is exposed. . Thus, the first electrode 33 is formed by embedding the first electrode film 33b in the groove pattern 35a via the barrier metal layer 33a. As a result, the electrode layer 2 c including the first electrode 33 is obtained.

以上の工程により、第１電極３３と第１絶縁膜３５とが露出された平坦な貼合せ面４１を有する第１基板２が、センサ基板として作製される。なお、必要に応じて、貼合せ面４１に対して、ウェット処理またはプラズマ処理による前処理を施しておく。
ここまでの工程は、通常の工程手順で行えばよく、また特に工程手順が限定されることはなく、適宜の手順で行うことができる。本技術では、次の絶縁性薄膜の成膜が特徴的な工程となる。 Through the above steps, the first substrate 2 having the flat bonding surface 41 from which the first electrode 33 and the first insulating film 35 are exposed is manufactured as a sensor substrate. In addition, the pre-processing by wet processing or plasma processing is given with respect to the bonding surface 41 as needed.
The steps up to here may be performed according to a normal process procedure, and the process procedure is not particularly limited, and can be performed according to an appropriate procedure. In the present technology, the following process of forming an insulating thin film is a characteristic process.

［絶縁性薄膜の成膜手順］
図４Ｅに示すように、第１基板２における貼合せ面４１の全面を覆う状態で、原子層堆積法（Atomic Layer Deposition：以下ＡＬＤ法）によって絶縁性薄膜１２ａを成膜する。 [Insulating thin film deposition procedure]
As shown in FIG. 4E, the insulating thin film 12a is formed by atomic layer deposition (hereinafter referred to as ALD method) while covering the entire bonding surface 41 of the first substrate 2.

ＡＬＤ法の手順について、概略を説明する。
まず、成膜される薄膜の構成元素を含有する第１反応物と第２反応物とを準備する。成膜工程として、基板上に、第１反応物を含むガスを供給して吸着反応させる第１工程と、第２反応物を含むガス供給して吸着反応させる第２工程とがあり、この工程の間には不活性ガスを流して、未吸着の反応物をパージする。この成膜工程を１サイクル行なうことで原子層１層を堆積させ、繰り返すことにより所望膜厚の成膜をする。なお、第１工程と第２工程は、どちらを先に行なってもよい。
以上のような成膜方法がＡＬＤ法であり、次のような特徴がある。 An outline of the procedure of the ALD method will be described.
First, a first reactant and a second reactant containing constituent elements of a thin film to be formed are prepared. As the film forming process, there are a first process in which a gas containing a first reactant is supplied and subjected to an adsorption reaction on the substrate, and a second process in which a gas containing a second reactant is supplied and subjected to an adsorption reaction. In the meantime, an inert gas is allowed to flow to purge unadsorbed reactants. By performing this film forming process for one cycle, one atomic layer is deposited and repeated to form a film with a desired film thickness. Note that either the first step or the second step may be performed first.
The film formation method as described above is the ALD method and has the following characteristics.

ＡＬＤ法は、上述のように、成膜工程のサイクルを繰り返して成膜する方法であり、このサイクル数の調整によって、成膜する膜厚を原子層単位で高精度に制御した成膜が可能である。このようなＡＬＤ法を絶縁性薄膜１２ａの成膜に適用すると、極めて薄い絶縁性薄膜１２ａであっても膜厚制御性よく成膜できる。   As described above, the ALD method is a method of forming a film by repeating the cycle of the film forming process. By adjusting the number of cycles, the film thickness can be controlled with high accuracy in units of atomic layers. It is. When such an ALD method is applied to the formation of the insulating thin film 12a, even an extremely thin insulating thin film 12a can be formed with good film thickness controllability.

ＡＬＤ法は、さらに約５００℃以下の低温プロセスでの成膜が可能な方法である。絶縁性薄膜１２ａの成膜時には、すでに電極層２ｃが形成されているため、電極層２ｃを構成する金属への耐熱性を考慮する必要があり、絶縁性薄膜１２ａの成膜には低温プロセスが要求される。そこで、このようなＡＬＤ法を絶縁性薄膜１２ａの成膜に適用すると、低温プロセスにより電極層２ｃを劣化させることなく絶縁性薄膜１２ａを成膜できる。   The ALD method is a method capable of forming a film at a low temperature process of about 500 ° C. or lower. Since the electrode layer 2c has already been formed when the insulating thin film 12a is formed, it is necessary to consider the heat resistance of the metal constituting the electrode layer 2c. A low temperature process is required for forming the insulating thin film 12a. Required. Therefore, when such an ALD method is applied to the formation of the insulating thin film 12a, the insulating thin film 12a can be formed without deteriorating the electrode layer 2c by a low temperature process.

ＡＬＤ法は、上述のように、原子層を１層ずつ堆積させて成膜する方法である。このようなＡＬＤ法を絶縁性薄膜１２ａの成膜に適用すると、ＣＭＰにより超平坦化された基板表面の凹凸を悪化させることなく、平坦かつ均一な絶縁性薄膜１２で貼合せ面４１の全面を覆うことができる。   As described above, the ALD method is a method of forming a film by depositing atomic layers one by one. When such an ALD method is applied to the formation of the insulating thin film 12a, the entire surface of the bonding surface 41 is covered with the flat and uniform insulating thin film 12 without deteriorating the unevenness of the substrate surface that has been super flattened by CMP. Can be covered.

以下に、一例として、酸化膜または窒化膜からなる絶縁性薄膜１２ａのＡＬＤ法による成膜条件について、具体的に説明する。   Hereinafter, as an example, film formation conditions by the ALD method of the insulating thin film 12a made of an oxide film or a nitride film will be specifically described.

絶縁性薄膜１２ａが酸化膜（ＳｉＯ２、ＨｆＯ２等）からなる場合、上述のＡＬＤ法において、第１反応物をＳｉ含有反応物またはＨｆ含有反応物とし、第２反応物をＯ含有反応物とする。これらの反応物を供給して吸着反応させる工程を交互に繰り返すことによって、酸化膜（ＳｉＯ２またはＨｆＯ２）からなる絶縁性薄膜１２ａを貼合せ面４１上に成膜する。ここで、Ｓｉ含有反応物は、例えば、シラン（ＳｉＨ４）、ジクロロシラン（Ｈ２ＳｉＣｌ２）等のガス状で供給可能な物質を用いる。Ｈｆ含有反応物は、テトラキスジメチルアミノハフニウム（Ｈｆ［Ｎ（ＣＨ３）２］４等を用いる。Ｏ含有反応物は、水蒸気ガス、オゾンガス等を用いる。 When the insulating thin film 12a is made of an oxide film (SiO 2 , HfO 2, etc.), in the ALD method described above, the first reactant is an Si-containing reactant or an Hf-containing reactant, and the second reactant is an O-containing reactant. And An insulating thin film 12a made of an oxide film (SiO 2 or HfO 2 ) is formed on the bonding surface 41 by alternately repeating the steps of supplying these reactants and causing an adsorption reaction. Here, Si-containing reactant, for example silane (SiH 4), using the supplied substance at dichlorosilane (H 2 SiC l2) such like gas. Tetrakisdimethylaminohafnium (Hf [N (CH 3 ) 2 ] 4 or the like is used as the Hf-containing reactant, and water vapor gas, ozone gas, or the like is used as the O-containing reactant.

一方、絶縁性薄膜１２ａが窒化膜（ＳｉＮ等）からなる場合、上述のＡＬＤ法において、第１反応物をＳｉ含有反応物とし、第２反応物をＮ含有反応物とする。これらの反応物を供給して吸着反応させる工程を交互に繰り返すことによって、窒化膜（ＳｉＮ）からなる絶縁性薄膜１２ａを貼合せ面４１上に成膜する。ここで、Ｎ含有反応物は、例えば、窒素ガスやアンモニアガス等を用いる。Ｏ含有反応物は、水蒸気ガス、オゾンガス等を用いる。   On the other hand, when the insulating thin film 12a is made of a nitride film (SiN or the like), in the above-described ALD method, the first reactant is an Si-containing reactant and the second reactant is an N-containing reactant. The insulating thin film 12a made of a nitride film (SiN) is formed on the bonding surface 41 by alternately repeating the process of supplying these reactants and causing the adsorption reaction. Here, for example, nitrogen gas or ammonia gas is used as the N-containing reactant. As the O-containing reactant, steam gas, ozone gas, or the like is used.

以上により、第１基板２上に、貼合せ面４１の全面を覆う状態で、極めて薄い均一な絶縁性薄膜１２ａを成膜する。   As described above, the extremely thin uniform insulating thin film 12a is formed on the first substrate 2 so as to cover the entire surface of the bonding surface 41.

≪４．本実施形態の半導体装置の製造における第２基板（回路基板）の作製手順≫
図５は、上述した本実施形態の半導体装置の製造に用いる第２基板７の作製手順を説明するための断面工程図である。以下、この図に基づいて本実施形態に用いる第２基板７（回路基板）の作製手順を説明する。 << 4. Manufacturing Procedure of Second Substrate (Circuit Substrate) in Manufacturing Semiconductor Device of this Embodiment >>
FIG. 5 is a cross-sectional process diagram for explaining a procedure for manufacturing the second substrate 7 used for manufacturing the semiconductor device of the present embodiment described above. Hereinafter, a procedure for manufacturing the second substrate 7 (circuit board) used in the present embodiment will be described with reference to this drawing.

図５Ａに示すように、例えば単結晶シリコンからなる半導体基板５０を用意する。この半導体基板５０の表面層に、各導電型のソース／ドレイン５１、およびここでの図示を省略した他の不純物層を形成する。これにより、半導体層７ａを得る。   As shown in FIG. 5A, a semiconductor substrate 50 made of, for example, single crystal silicon is prepared. On the surface layer of the semiconductor substrate 50, the source / drain 51 of each conductivity type and other impurity layers not shown here are formed. Thereby, the semiconductor layer 7a is obtained.

次に、半導体層７ａの上に、ゲート絶縁膜５３を成膜し、さらにこの上部にゲート電極５５を形成する。ゲート電極５５は、ソース／ドレイン５１間に形成される。また、これと同一工程で、ここでの図示を省略した他の電極を形成する。   Next, a gate insulating film 53 is formed on the semiconductor layer 7a, and a gate electrode 55 is formed thereon. The gate electrode 55 is formed between the source / drain 51. Further, in the same process as this, another electrode not shown here is formed.

続いて、ゲート絶縁膜５３の上に、ゲート電極５５を覆う状態で、例えば酸化シリコンからなる層間絶縁膜５７を成膜する。この層間絶縁膜５７の溝パターン内にバリアメタル層５９ａを介して配線層５９ｂを埋め込んでなる埋込配線５９を形成し、埋込配線５９を備えた配線層７ｂを得る。ここでの埋込配線５９の形成は、上述した第１電極３３の形成と同様に、埋込配線技術を適用して行なう。   Subsequently, an interlayer insulating film 57 made of, for example, silicon oxide is formed on the gate insulating film 53 so as to cover the gate electrode 55. An embedded wiring 59 is formed by burying the wiring layer 59b through the barrier metal layer 59a in the groove pattern of the interlayer insulating film 57, and the wiring layer 7b including the embedded wiring 59 is obtained. The formation of the embedded wiring 59 here is performed by applying the embedded wiring technique in the same manner as the formation of the first electrode 33 described above.

その後、配線層７ｂ上に拡散防止絶縁膜６１を介して、例えばＴＥＯＳ膜からなる第２絶縁膜６９を積層させて成膜する。これにより、第２絶縁膜６９の溝パターン内にバリアメタル層６７ａを介して第２電極膜６７ｂを埋め込んでなる第２電極６７を形成し、第２電極６７を備えた電極層７ｃを得る。ここでの第２電極６７の形成は、上述した第１電極３３の形成と同様にして行なう。   Thereafter, a second insulating film 69 made of, for example, a TEOS film is laminated on the wiring layer 7b with the diffusion preventing insulating film 61 interposed therebetween. Thus, the second electrode 67 is formed by embedding the second electrode film 67b in the groove pattern of the second insulating film 69 via the barrier metal layer 67a, and the electrode layer 7c provided with the second electrode 67 is obtained. The formation of the second electrode 67 here is performed in the same manner as the formation of the first electrode 33 described above.

以上の工程により、第２電極６７と第２絶縁膜６９とが露出された平坦な貼合せ面７１を有する第２基板７が、回路基板として作製される。
ここまでの工程は、通常の工程手順で行えばよく、また特に工程手順が限定されることはなく、適宜の手順で行うことができる。本技術では、次の絶縁性薄膜の成膜、および基板の貼り合わせが特徴的な工程となる。 Through the above steps, the second substrate 7 having the flat bonding surface 71 from which the second electrode 67 and the second insulating film 69 are exposed is manufactured as a circuit substrate.
The steps up to here may be performed according to a normal process procedure, and the process procedure is not particularly limited, and can be performed according to an appropriate procedure. In the present technology, the following process is a characteristic process of forming an insulating thin film and bonding the substrates.

図５Ｂに示すように、第１基板２側の絶縁性薄膜１２ａと同様にして、貼合せ面７１の上に、ＡＬＤ法により絶縁性薄膜１２ｂを成膜する。
これにより、第２基板７上に、貼合せ面７１の全面を覆う状態で、極めて薄い均一な絶縁性薄膜１２ｂを成膜する。なお、絶縁性薄膜１２ｂは、第１基板２側の絶縁性薄膜１２ａと異なる膜でもよいが、同じ膜でもよい。 As shown in FIG. 5B, the insulating thin film 12b is formed on the bonding surface 71 by the ALD method in the same manner as the insulating thin film 12a on the first substrate 2 side.
Thus, an extremely thin uniform insulating thin film 12b is formed on the second substrate 7 so as to cover the entire surface of the bonding surface 71. The insulating thin film 12b may be a film different from the insulating thin film 12a on the first substrate 2 side, but may be the same film.

≪５．本実施形態の半導体装置の製造における基板の貼り合わせ手順≫
図６および図７を用いて、貼合せ面４１上に絶縁性薄膜１２ａを成膜した第１基板２と、貼合せ面７１上に絶縁性薄膜１２ｂを成膜した第２基板７との貼り合わせ手順を説明する。 ≪5. Procedure for bonding substrates in manufacturing the semiconductor device of this embodiment >>
6 and 7, the first substrate 2 having the insulating thin film 12a formed on the bonding surface 41 and the second substrate 7 having the insulating thin film 12b formed on the bonding surface 71 are bonded. The alignment procedure will be described.

図６に示すように、絶縁性薄膜を介した状態で第１基板２の貼合せ面４１と第２基板７の貼合せ面７１とを対向配置させ、さらに、第１基板２の第１電極３３と、第２基板７の第２電極６７とが対応するように位置合わせする。図示した例では、第１電極３３と第２電極６７とが１：１で対応している状態を示したが、対応状態はこれに限定されることはない。   As shown in FIG. 6, the bonding surface 41 of the first substrate 2 and the bonding surface 71 of the second substrate 7 are arranged to face each other with the insulating thin film interposed therebetween, and further, the first electrode of the first substrate 2 is arranged. 33 is aligned with the second electrode 67 of the second substrate 7. In the illustrated example, a state in which the first electrode 33 and the second electrode 67 correspond 1: 1 is shown, but the correspondence state is not limited to this.

図７に示すように、第１基板２上の絶縁性薄膜１２ａと、第２基板７上の絶縁性薄膜１２ｂとを対向させた状態で熱処理を行うことにより、絶縁性薄膜１２ａと絶縁性薄膜１２ｂとの間の接合をする。このような熱処理は、第１基板２および第２基板７に形成された素子や配線に影響のない範囲で、絶縁性薄膜１２同士が十分に接合する温度および時間で行われる。   As shown in FIG. 7, the insulating thin film 12a and the insulating thin film 12a and the insulating thin film are obtained by performing heat treatment in a state where the insulating thin film 12a on the first substrate 2 and the insulating thin film 12b on the second substrate 7 face each other. It joins between 12b. Such heat treatment is performed at a temperature and a time at which the insulating thin films 12 are sufficiently bonded to each other within a range that does not affect the elements and wirings formed on the first substrate 2 and the second substrate 7.

例えば、第１電極３３および第２電極６７が、銅（Ｃｕ）を主とする材料で構成される場合、２００℃〜６００℃で１〜５時間程度の熱処理が行われる。このような熱処理は、加圧雰囲気下で行ってもよく、または、第１基板２と第２基板７とを両面側から押圧した状態で行ってもよい。一例として、４００℃で４時間の熱処理を行うことで、絶縁性薄膜１２を介した第１電極３３と第２電極６７との間の接続を行なう。これにより、絶縁性薄膜１２ａと絶縁性薄膜１２ｂとの間が接合され、第１基板２と第２基板７とが貼り合わせられる。   For example, when the 1st electrode 33 and the 2nd electrode 67 are comprised with the material which mainly has copper (Cu), the heat processing for about 1 to 5 hours are performed at 200 to 600 degreeC. Such heat treatment may be performed in a pressurized atmosphere, or may be performed in a state where the first substrate 2 and the second substrate 7 are pressed from both sides. As an example, the connection between the first electrode 33 and the second electrode 67 through the insulating thin film 12 is performed by performing a heat treatment at 400 ° C. for 4 hours. Thereby, between the insulating thin film 12a and the insulating thin film 12b is joined, and the 1st board | substrate 2 and the 2nd board | substrate 7 are bonded together.

ここで、上述のように第１基板２および第２基板７の両方の貼合せ面４１，７１上に絶縁性薄膜１２ａ，１２ｂが成膜される場合は、その絶縁性薄膜１２ａ，１２ｂが同じ材料であっても、異なる材料であってもよい。
なお、本実施形態の半導体装置の製造方法では、第１基板２および第２基板７のうちどちらか一方の基板の貼合せ面のみに絶縁性薄膜を成膜してもよい。例えば、第１基板２の貼合せ面４１上のみに絶縁性薄膜１２ａを成膜して、第１基板２側の絶縁性薄膜１２ａと第２基板７側の貼合せ面７１との間の接合により、第１基板２と第２基板７を貼り合わせてもよい。 Here, when the insulating thin films 12a and 12b are formed on the bonding surfaces 41 and 71 of both the first substrate 2 and the second substrate 7 as described above, the insulating thin films 12a and 12b are the same. It may be a material or a different material.
In the semiconductor device manufacturing method of the present embodiment, an insulating thin film may be formed only on the bonding surface of one of the first substrate 2 and the second substrate 7. For example, the insulating thin film 12a is formed only on the bonding surface 41 of the first substrate 2, and the bonding between the insulating thin film 12a on the first substrate 2 side and the bonding surface 71 on the second substrate 7 side is performed. Thus, the first substrate 2 and the second substrate 7 may be bonded together.

以上のように、第１基板２と第２基板７とを貼り合わせた後、第１基板２側の半導体基板２０を薄膜化して半導体層２ａとし、光電変換部２１を露出させる。また必要に応じて、第２基板７側の半導体層７ａにおいて、半導体基板５０を薄膜化してもよい。   As described above, after bonding the first substrate 2 and the second substrate 7, the semiconductor substrate 20 on the first substrate 2 side is thinned to form the semiconductor layer 2a, and the photoelectric conversion unit 21 is exposed. If necessary, the semiconductor substrate 50 may be thinned in the semiconductor layer 7a on the second substrate 7 side.

その後は図２に示すように、第１基板２における光電変換部２１の露出面上に保護膜１５を成膜し、さらに保護膜１５上にカラーフィルタ層１７およびオンチップレンズ１９を形成し、半導体装置（固体撮像装置）１を完成させる。   Thereafter, as shown in FIG. 2, a protective film 15 is formed on the exposed surface of the photoelectric conversion unit 21 in the first substrate 2, and a color filter layer 17 and an on-chip lens 19 are formed on the protective film 15, A semiconductor device (solid-state imaging device) 1 is completed.

［本実施形態の半導体装置の製造方法による効果］
上述のような本実施形態の半導体装置の製造方法では、第１基板２および第２基板７の上にそれぞれ絶縁性薄膜１２ａ，１２ｂを成膜し、この絶縁性薄膜１２ａ，１２ｂが成膜された面同士を接合することにより、第１基板２と第２基板７を貼り合わせている。このため、ＣＭＰにより平坦化処理された貼合せ面４１，７１同士を直接接合する場合と比較して、絶縁性薄膜１２ａ，１２ｂが成膜された面同士の接合によって、第１基板２と第２基板７を貼り合わせる本実施形態の半導体装置１は接合性がよい。なお、第１基板２の貼合せ面４１上にのみ絶縁性薄膜１２ａを成膜した場合であっても、第１基板２側の絶縁性薄膜１２ａと第２基板７側の貼合せ面７１との間の接合になり、貼合せ面４１，７１同士を直接接合する場合よりも基板の接合性がよい。 [Effects of Semiconductor Device Manufacturing Method of Present Embodiment]
In the manufacturing method of the semiconductor device according to the present embodiment as described above, the insulating thin films 12a and 12b are formed on the first substrate 2 and the second substrate 7, respectively, and the insulating thin films 12a and 12b are formed. The first substrate 2 and the second substrate 7 are bonded together by bonding the two surfaces. For this reason, compared with the case where the bonding surfaces 41 and 71 planarized by CMP are directly bonded together, the first substrate 2 and the first substrate 2 are bonded to each other by bonding the surfaces on which the insulating thin films 12a and 12b are formed. The semiconductor device 1 of this embodiment in which the two substrates 7 are bonded together has good bonding properties. Even if the insulating thin film 12a is formed only on the bonding surface 41 of the first substrate 2, the insulating thin film 12a on the first substrate 2 side and the bonding surface 71 on the second substrate 7 side The bonding property of the substrate is better than the case where the bonding surfaces 41 and 71 are directly bonded to each other.

例えば、ＣＭＰにより平坦化処理された貼合せ面４１，７１は、ＣＭＰの工程において貼合せ面４１，７１を構成する第１絶縁膜３５および第２絶縁膜６９が含水する可能性がある。また、この貼合せ面４１，７１を構成する第１絶縁膜３５および第２絶縁膜６９がＴＥＯＳ膜からなる場合であれば、そのＴＥＯＳ膜の成膜条件ゆえに、もともと含水率の高い膜として第１絶縁膜３５および第２絶縁膜６９が形成される。したがって、このような含水している貼合せ面４１，７１同士を直接接合する場合、貼合せ後の熱処理において、脱ガスが接合界面に集中しボイドを形成する。しかしながら、本実施形態では、貼合せ面４１，７１の全面を絶縁性薄膜１２ａ，１２ｂで覆うことにより、脱ガスが接合界面に集中することを防止しボイドの発生を抑えることが可能である。   For example, the bonding surfaces 41 and 71 that have been planarized by CMP may contain water in the first insulating film 35 and the second insulating film 69 that form the bonding surfaces 41 and 71 in the CMP process. In addition, if the first insulating film 35 and the second insulating film 69 constituting the bonding surfaces 41 and 71 are made of a TEOS film, the first insulating film 35 and the second insulating film 69 are originally films having a high water content because of the TEOS film forming conditions. A first insulating film 35 and a second insulating film 69 are formed. Therefore, in the case where the bonding surfaces 41 and 71 containing such water are directly bonded, degassing concentrates on the bonding interface and forms voids in the heat treatment after bonding. However, in this embodiment, by covering the entire surfaces of the bonding surfaces 41 and 71 with the insulating thin films 12a and 12b, it is possible to prevent degassing from concentrating on the bonding interface and suppress the generation of voids.

特に、第１基板２の貼合せ面４１上の絶縁性薄膜１２ａと第２基板７の貼合せ面７１上の絶縁性薄膜１２ｂが、同一材料膜で構成されている場合は、同一材料膜同士の接合となるので、より強固な接合が可能になる。これにより、基板の接合強度が増して信頼性の向上が図られた半導体装置を得ることができる。   In particular, when the insulating thin film 12a on the bonding surface 41 of the first substrate 2 and the insulating thin film 12b on the bonding surface 71 of the second substrate 7 are made of the same material film, the same material films Therefore, stronger bonding is possible. Thereby, a semiconductor device in which the bonding strength of the substrate is increased and the reliability is improved can be obtained.

さらには、絶縁性薄膜１２ａ，１２ｂの成膜をＡＬＤ法により行なったことにより、次のような効果もある。   Furthermore, since the insulating thin films 12a and 12b are formed by the ALD method, there are the following effects.

まず、ＡＬＤ法は原子層単位の成膜により膜厚制御性のよい方法なので、極めて薄い絶縁性薄膜を成膜できる。これにより、第１基板２側の第１電極３３と第２基板７側の第２電極６７とが絶縁性薄膜１２を介して対向配置された構造であっても、この絶縁性薄膜１２が極めて薄い膜厚であるので、第１電極３３と第２電極６７との間の電気的な接続が可能となる。   First, since the ALD method is a method with good film thickness controllability by film formation in units of atomic layers, an extremely thin insulating thin film can be formed. Thus, even if the first electrode 33 on the first substrate 2 side and the second electrode 67 on the second substrate 7 side are arranged to face each other with the insulating thin film 12 therebetween, the insulating thin film 12 is extremely Since the film thickness is small, electrical connection between the first electrode 33 and the second electrode 67 is possible.

次に、ＡＬＤ法は原子層単位の成膜により膜厚均一性のよい方法なので、ＣＭＰにより平坦化された貼合せ面４１，７１の平坦性を維持して、均一な絶縁性薄膜１２ａ，１２ｂを第１基板２および第２基板７の上に成膜する。このような絶縁性薄膜１２ａ，１２ｂの成膜された平坦な接合面同士によって接合が図られるので、密着性に優れた接合が行なわれ、接合強度の向上した基板の接合が可能となる。   Next, since the ALD method is a method with good film thickness uniformity by film formation in units of atomic layers, the flatness of the bonding surfaces 41 and 71 flattened by CMP is maintained, and the uniform insulating thin films 12a and 12b are maintained. Is formed on the first substrate 2 and the second substrate 7. Bonding is achieved by the flat bonding surfaces on which the insulating thin films 12a and 12b are formed, so that bonding with excellent adhesion is performed, and bonding of substrates with improved bonding strength becomes possible.

続いて、ＡＬＤ法は低温プロセスでの成膜をする方法なので、第１基板２側の電極層２ｃおよび第２基板７側の電極層７ｃを構成する金属が高熱により劣化することなく、第１基板２および第２基板７の上に絶縁性薄膜１２ａ，１２ｂを成膜できる。   Subsequently, since the ALD method is a method of forming a film by a low temperature process, the metal constituting the electrode layer 2c on the first substrate 2 side and the electrode layer 7c on the second substrate 7 side is not degraded by high heat, and the first Insulating thin films 12 a and 12 b can be formed on the substrate 2 and the second substrate 7.

最後に、ＡＬＤ法は原子層単位の成膜方法なので、成膜された絶縁性薄膜１２ａ，１２ｂは緻密な膜であって含水率が極めて低い。含水率の低い絶縁性薄膜１２ａ，１２ｂの成膜された接合面同士による接合となるので、接合面にボイドの発生する虞は全くない。
以上により、基板の接合強度が増して信頼性の向上が図られた半導体装置が得られる。 Finally, since the ALD method is a film formation method in units of atomic layers, the formed insulating thin films 12a and 12b are dense films and have a very low water content. Since bonding is performed by the bonding surfaces on which the insulating thin films 12a and 12b having a low moisture content are formed, there is no possibility that voids are generated on the bonding surfaces.
Thus, a semiconductor device in which the bonding strength of the substrate is increased and the reliability is improved can be obtained.

≪６．本実施形態の半導体装置を用いた電子機器の一例≫
上述の本実施形態で説明した本技術に係る半導体装置（固体撮像装置）は、例えばデジタルカメラやビデオカメラ等のカメラシステム、さらには撮像機能を有する携帯電話、あるいは撮像機能を備えた他の機器などの電子機器に適用することができる。 ≪6. Example of Electronic Device Using Semiconductor Device of this Embodiment >>
The semiconductor device (solid-state imaging device) according to the present technology described in the above-described embodiment is, for example, a camera system such as a digital camera or a video camera, a mobile phone having an imaging function, or another device having an imaging function. It can be applied to such electronic devices.

図８は、本技術に係る電子機器の一例として、固体撮像装置を用いたカメラの構成図を示す。本実施形態に係るカメラ９１は、静止画像又は動画撮影可能なビデオカメラを例としたものである。このカメラ９１は、固体撮像装置９２と、固体撮像装置９２の光電変換部に入射光を導く光学系９３と、シャッタ装置９４と、固体撮像装置９２を駆動する駆動回路９５と、固体撮像装置９２の出力信号を処理する信号処理回路９６とを有する。   FIG. 8 is a configuration diagram of a camera using a solid-state imaging device as an example of an electronic apparatus according to the present technology. The camera 91 according to the present embodiment is an example of a video camera capable of capturing still images or moving images. The camera 91 includes a solid-state imaging device 92, an optical system 93 that guides incident light to the photoelectric conversion unit of the solid-state imaging device 92, a shutter device 94, a drive circuit 95 that drives the solid-state imaging device 92, and a solid-state imaging device 92. And a signal processing circuit 96 for processing the output signal.

固体撮像装置９２は、上述した本実施形態で説明した構成の半導体装置（１）が適用される。光学系（光学レンズ）９３は、被写体からの像光（入射光）を固体撮像装置９２の撮像面上に結像させる。これにより、固体撮像装置９２内に、一定期間信号電荷が蓄積される。このような光学系９３は、複数の光学レンズから構成された光学レンズ系としてもよい。シャッタ装置９４は、固体撮像装置９２への光照射期間および遮光期間を制御する。駆動回路９５は、固体撮像装置９２およびシャッタ装置９４に駆動信号を供給し、供給した駆動信号（タイミング信号）により、固体撮像装置９２の信号処理回路９６への信号出力動作の制御、およびシャッタ装置９４のシャッタ動作を制御する。すなわち、駆動回路９５は、駆動信号（タイミング信号）の供給により、固体撮像装置９２から信号処理回路９６への信号転送動作を行う。信号処理回路９６は、固体撮像装置９２から転送された信号に対して、各種の信号処理を行う。信号処理が行われた映像信号は、メモリなどの記憶媒体に記憶され、或いは、モニタに出力される。   As the solid-state imaging device 92, the semiconductor device (1) having the configuration described in the above-described embodiment is applied. The optical system (optical lens) 93 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 92. As a result, signal charges are accumulated in the solid-state imaging device 92 for a certain period. Such an optical system 93 may be an optical lens system including a plurality of optical lenses. The shutter device 94 controls a light irradiation period and a light shielding period for the solid-state imaging device 92. The drive circuit 95 supplies drive signals to the solid-state imaging device 92 and the shutter device 94, and controls the signal output operation to the signal processing circuit 96 of the solid-state imaging device 92 and the shutter device by the supplied drive signal (timing signal). 94 shutter operation is controlled. That is, the drive circuit 95 performs a signal transfer operation from the solid-state imaging device 92 to the signal processing circuit 96 by supplying a drive signal (timing signal). The signal processing circuit 96 performs various types of signal processing on the signal transferred from the solid-state imaging device 92. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

以上説明した本実施形態に係る電子機器によれば、センサ基板と回路基板とを積層させた信頼性の高い３次元構造の半導体装置１を固体撮像装置として用いたことにより、撮像機能を有する電子機器の小型化および信頼性の向上を図ることが可能になる。   According to the electronic device according to the present embodiment described above, an electronic device having an imaging function is obtained by using the highly reliable three-dimensional semiconductor device 1 in which a sensor substrate and a circuit board are stacked as a solid-state imaging device. It becomes possible to reduce the size of the device and improve the reliability.

なお、本技術は以下のような構成も取ることができる。
（１）
第１電極および第１絶縁膜を露出させた貼合せ面を有する第１基板と、
前記第１基板の貼合せ面を覆う絶縁性薄膜と、
第２電極および第２絶縁膜を露出させた貼合せ面を有し、当該貼合せ面と前記第１基板の貼合せ面との間で前記絶縁性薄膜を挟持すると共に、前記第１電極と当該第２電極が前記絶縁性薄膜を介して電気的に接続された状態で前記第１基板に貼り合わせられた第２基板と
を備える半導体装置。 In addition, this technique can also take the following structures.
(1)
A first substrate having a bonding surface exposing the first electrode and the first insulating film;
An insulating thin film covering the bonding surface of the first substrate;
A bonding surface exposing the second electrode and the second insulating film; and sandwiching the insulating thin film between the bonding surface and the bonding surface of the first substrate; and the first electrode; A semiconductor device comprising: a second substrate bonded to the first substrate in a state where the second electrode is electrically connected via the insulating thin film.

（２）
前記絶縁性薄膜は酸化膜である
（１）記載の半導体装置。 (2)
The semiconductor device according to (1), wherein the insulating thin film is an oxide film.

（３）
前記絶縁性薄膜は窒化膜である
（１）記載の半導体装置。 (3)
The semiconductor device according to (1), wherein the insulating thin film is a nitride film.

（４）
前記絶縁性薄膜は、積層構造である
（１）〜（３）の何れかに記載の半導体装置。 (4)
The semiconductor device according to any one of (1) to (3), wherein the insulating thin film has a laminated structure.

（５）
前記絶縁性薄膜は、前記各貼合せ面の全面を覆う状態で設けられた
（１）〜（４）の何れかに記載の半導体装置。 (5)
The semiconductor device according to any one of (1) to (4), wherein the insulating thin film is provided in a state of covering the entire surface of each bonding surface.

（６）
前記第１基板の貼合せ面、および前記第２基板の貼合せ面は、平坦化面である
（１）〜（５）の何れかに記載の半導体装置。 (6)
The bonding surface of the first substrate and the bonding surface of the second substrate are planarized surfaces. The semiconductor device according to any one of (1) to (5).

（７）
電極および絶縁膜が露出された貼合せ面を有する２枚の基板を用意することと、
前記２枚の基板のうち少なくとも一方の貼合せ面を覆う状態で、絶縁性薄膜を成膜することと、
前記絶縁性薄膜を介して前記２枚の基板の貼合せ面同士を対向配置し、前記２枚の基板の電極同士が前記絶縁性薄膜を介して電気的に接続される状態に位置合わせをして、前記２枚の基板を貼り合わせることとを行なう
半導体装置の製造方法。 (7)
Preparing two substrates having a bonding surface with electrodes and insulating films exposed;
Forming an insulating thin film in a state of covering at least one bonding surface of the two substrates;
The bonding surfaces of the two substrates are arranged opposite to each other via the insulating thin film, and the electrodes of the two substrates are aligned to be electrically connected via the insulating thin film. And bonding the two substrates together. A method for manufacturing a semiconductor device.

（８）
前記２枚の基板の両方に、前記絶縁性薄膜を成膜する
（７）記載の半導体装置の製造方法。 (8)
The method for manufacturing a semiconductor device according to (7), wherein the insulating thin film is formed on both of the two substrates.

（９）
前記２枚の基板の両方に、同じ材料からなる前記絶縁性薄膜を成膜する
（７）または（８）記載の半導体装置の製造方法。 (9)
The method for manufacturing a semiconductor device according to (7) or (8), wherein the insulating thin film made of the same material is formed on both of the two substrates.

（１０）
原子層蒸着法により前記絶縁性薄膜を成膜する
（７）〜（９）の何れかに記載の半導体装置の製造方法。 (10)
The method for manufacturing a semiconductor device according to any one of (7) to (9), wherein the insulating thin film is formed by an atomic layer deposition method.

（１１）
前記２枚の基板の貼合せ面は、平坦化処理によって形成されている
（７）〜（１０）の何れかに記載の半導体装置の製造方法。 (11)
The method for manufacturing a semiconductor device according to any one of (7) to (10), wherein the bonding surface of the two substrates is formed by a planarization process.

１…半導体装置、２…第１基板（センサ基板）、７…第２基板（回路基板）、１２…絶縁性薄膜、３３…第１電極、３５…第１絶縁膜、４１，７１…貼合せ面、６７…第２電極、６９…第２絶縁膜   DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... 1st board | substrate (sensor board | substrate), 7 ... 2nd board | substrate (circuit board | substrate), 12 ... Insulating thin film, 33 ... 1st electrode, 35 ... 1st insulating film, 41, 71 ... Bonding Surface, 67 ... second electrode, 69 ... second insulating film

Claims (10)

第１絶縁膜、および当該第１絶縁膜に形成された溝パターンの内壁を覆うバリアメタル層とバリアメタル層を介して当該溝パターン内に埋め込まれた銅（Ｃｕ）からなる第１電極を露出させた貼合せ面を有する第１基板と、
前記第１基板の貼合せ面を覆う絶縁性薄膜と、
第２絶縁膜、および当該第２絶縁膜に形成された溝パターンの内壁を覆うバリアメタル層とバリアメタル層を介して当該溝パターン内に埋め込まれた銅（Ｃｕ）からなる第２電極を露出させた貼合せ面を有し、当該貼合せ面と前記第１基板の貼合せ面との間で前記絶縁性薄膜を挟持すると共に、前記第１電極と当該第２電極が絶縁破壊された前記絶縁性薄膜を介して導通して電気的に接続された状態で前記第１基板に貼り合わせられた第２基板とを備え、
前記絶縁性薄膜が、銅（Ｃｕ）に対するバリア性を有する
を備える半導体装置。 A first insulating film and a barrier metal layer covering an inner wall of the groove pattern formed in the first insulating film and a first electrode made of copper (Cu) embedded in the groove pattern through the barrier metal layer are exposed. A first substrate having a bonded surface,
An insulating thin film covering the bonding surface of the first substrate;
A second insulating film and a barrier metal layer covering an inner wall of the groove pattern formed in the second insulating film and a second electrode made of copper (Cu) embedded in the groove pattern through the barrier metal layer are exposed. The insulating thin film is sandwiched between the bonding surface and the bonding surface of the first substrate, and the first electrode and the second electrode are dielectrically broken. A second substrate bonded to the first substrate in a state of being electrically connected and electrically connected through an insulating thin film;
A semiconductor device comprising: the insulating thin film having a barrier property against copper (Cu). 前記絶縁性薄膜は窒化膜である
請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the insulating thin film is a nitride film. 前記絶縁性薄膜は、積層構造である
請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the insulating thin film has a laminated structure. 前記絶縁性薄膜は、前記各貼合せ面の全面を覆う状態で設けられた
請求項１〜３の何れかに記載の半導体装置。 The insulating thin film, the semiconductor device according to any one of claims 1 to 3 provided so as to cover the entire surface of each lamination surface. 前記第１基板の貼合せ面、および前記第２基板の貼合せ面は、平坦化面である
請求項１〜４の何れかに記載の半導体装置。 The cemented surface of the first substrate, and lamination surface of the second substrate is a semiconductor device according to any one of claims 1-4 is planarized surface. 絶縁膜、および当該絶縁膜に形成された溝パターンの内壁を覆うバリアメタル層とバリアメタル層を介して当該溝パターン内に埋め込まれた銅（Ｃｕ）からなる電極が露出された貼合せ面を有する２枚の基板を用意することと、
前記２枚の基板のうち少なくとも一方の貼合せ面を覆う状態で、銅（Ｃｕ）に対してバリア性を有する絶縁性薄膜を成膜することと、
前記絶縁性薄膜を介して前記２枚の基板の貼合せ面同士を対向配置し、前記２枚の基板の電極同士が前記絶縁性薄膜を介して導通して電気的に接続される状態に位置合わせをして、前記２枚の基板を貼り合わせることと、
前記２枚の基板の電極間に電圧を印加することにより前記絶縁性薄膜を絶縁破壊させ、当該２枚の基板の電極間を電気的に導通させることを行なう
半導体装置の製造方法。 An insulating film, a barrier metal layer covering an inner wall of the groove pattern formed in the insulating film, and a bonding surface on which an electrode made of copper (Cu) embedded in the groove pattern is exposed via the barrier metal layer Preparing two substrates having,
Forming an insulating thin film having a barrier property against copper (Cu) in a state of covering at least one bonding surface of the two substrates;
The bonding surfaces of the two substrates are arranged opposite to each other through the insulating thin film, and the electrodes of the two substrates are electrically connected and electrically connected through the insulating thin film. And bonding the two substrates together,
A method of manufacturing a semiconductor device, comprising applying a voltage between the electrodes of the two substrates to cause dielectric breakdown of the insulating thin film and electrically connecting the electrodes of the two substrates. 前記２枚の基板の両方に、前記絶縁性薄膜を成膜する
請求項６記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 6 , wherein the insulating thin film is formed on both of the two substrates. 前記２枚の基板の両方に、同じ材料からなる前記絶縁性薄膜を成膜する
請求項６または７記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 6 , wherein the insulating thin film made of the same material is formed on both of the two substrates. 原子層蒸着法により前記絶縁性薄膜を成膜する
請求項６〜８の何れかに記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 6 , wherein the insulating thin film is formed by an atomic layer deposition method. 前記２枚の基板の貼合せ面は、平坦化処理によって形成されている
請求項６〜９の何れかに記載の半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 6 , wherein a bonding surface of the two substrates is formed by a planarization process.
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US14/467,852 US9111763B2 (en) 2011-07-05 2014-08-25 Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
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US15/228,860 US10038024B2 (en) 2011-07-05 2016-08-04 Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
US15/992,908 US10431621B2 (en) 2011-07-05 2018-05-30 Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
US16/410,877 US10985102B2 (en) 2011-07-05 2019-05-13 Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10748886B2 (en) 2018-10-01 2020-08-18 Samsung Electronics Co., Ltd. Semiconductor devices

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013232473A (en) * 2012-04-27 2013-11-14 Nikon Corp Imaging device and chip laminated structure
JP6963873B2 (en) 2017-05-26 2021-11-10 ソニーセミコンダクタソリューションズ株式会社 Solid-state image sensor, manufacturing method of solid-state image sensor and electronic equipment
KR20230119268A (en) 2017-06-29 2023-08-16 소니 세미컨덕터 솔루션즈 가부시키가이샤 Wafer bonded back illuminated imager
JP2017216480A (en) * 2017-09-01 2017-12-07 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of the same
WO2020044943A1 (en) 2018-08-31 2020-03-05 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device
US11742374B2 (en) 2018-10-05 2023-08-29 Sony Semiconductor Solutions Corporation Semiconductor device, method of manufacturing semiconductor device, and imaging element
JP2020191334A (en) * 2019-05-20 2020-11-26 ソニーセミコンダクタソリューションズ株式会社 Solid-state imaging device and electronic device
US20230026052A1 (en) * 2021-07-22 2023-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Atomic layer deposition bonding layer for joining two semiconductor devices

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2816063B2 (en) * 1992-10-06 1998-10-27 松下電器産業株式会社 Charge transfer device
JPH08227980A (en) * 1995-02-21 1996-09-03 Toshiba Corp Semiconductor device and fabrication of the same
KR100610481B1 (en) * 2004-12-30 2006-08-08 매그나칩 반도체 유한회사 Image sensor with enlarged photo detecting area and method for fabrication thereof
JP5009124B2 (en) * 2007-01-04 2012-08-22 コバレントマテリアル株式会社 Manufacturing method of semiconductor substrate
US8552358B2 (en) * 2007-12-18 2013-10-08 Marek T. Michalewicz Quantum tunneling photodetector array including electrode nano wires
JP4835710B2 (en) * 2009-03-17 2011-12-14 ソニー株式会社 Solid-state imaging device, method for manufacturing solid-state imaging device, driving method for solid-state imaging device, and electronic apparatus
JP5187284B2 (en) * 2009-06-26 2013-04-24 ソニー株式会社 Manufacturing method of semiconductor device
JP5407660B2 (en) * 2009-08-26 2014-02-05 ソニー株式会社 Manufacturing method of semiconductor device
JP5521721B2 (en) * 2009-08-28 2014-06-18 ソニー株式会社 Image sensor and camera system
CN102668081B (en) * 2009-12-26 2016-02-03 佳能株式会社 Solid-state image pickup apparatus and image picking system

Cited By (4)

* Cited by examiner, † Cited by third party
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US10748886B2 (en) 2018-10-01 2020-08-18 Samsung Electronics Co., Ltd. Semiconductor devices
US11270987B2 (en) 2018-10-01 2022-03-08 Samsung Electronics Co., Ltd. Semiconductor devices
US11664362B2 (en) 2018-10-01 2023-05-30 Samsung Electronics Co., Ltd. Semiconductor devices
US11942463B2 (en) 2018-10-01 2024-03-26 Samsung Electronics Co., Ltd. Semiconductor devices

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