WO2013054739A1 - Method for producing semiconductor device, and semiconductor device - Google Patents

Method for producing semiconductor device, and semiconductor device Download PDF

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Publication number
WO2013054739A1
WO2013054739A1 PCT/JP2012/075845 JP2012075845W WO2013054739A1 WO 2013054739 A1 WO2013054739 A1 WO 2013054739A1 JP 2012075845 W JP2012075845 W JP 2012075845W WO 2013054739 A1 WO2013054739 A1 WO 2013054739A1
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film
semiconductor
wiring
region
manufacturing
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PCT/JP2012/075845
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French (fr)
Japanese (ja)
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井上　啓司
完 清水
博久 内田
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ソニー株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device, and more specifically, a method for manufacturing a semiconductor device in which two semiconductor members are bonded together and then electrically joined together by Cu wiring, and the manufacturing method thereof.
  • the present invention relates to a semiconductor device.
  • miniaturization technology In the field of semiconductor device miniaturization technology, the flow of miniaturization technology called “more Moore”, which aims at higher integration by further miniaturization of the mask process, has recently slowed down, and instead called “beyond Moore” Miniaturization technology is attracting attention. With the miniaturization technology called “beyond Moore”, the resistance value and capacitance value between elements can be reduced by stacking a plurality of elements constituting the semiconductor device in the vertical direction and providing wiring in three dimensions. .
  • Patent Document 1 proposes a method for manufacturing a semiconductor device as follows. First, in the manufacturing process of the first wafer, a buried wiring made of, for example, tungsten (W) or polysilicon is formed on the surface of the Si substrate. Next, after the manufacturing process of the first wafer is completed, the back surface of the Si substrate is ground to expose the embedded wiring, and bumps are formed. Then, the second wafer manufactured in the same manner as the first wafer and the first wafer are bonded together, and both are electrically connected.
  • W tungsten
  • Non-Patent Document 1 In the technique described in Non-Patent Document 1, first, after bonding circuits between two wafers, a vertical hole that comes into contact with a conductive pad portion formed by embedding in advance in each wafer, or A vertical hole penetrating the pad portion is formed. Next, the circuit is electrically connected between the two wafers by embedding the formed vertical hole with a conductive material.
  • Patent Document 2 proposes a manufacturing method in which a three-dimensional technique is applied to a back-illuminated solid-state imaging device.
  • a first semiconductor wafer provided with a pixel array and a second semiconductor wafer provided with a logic circuit are bonded together, and a TSV (through-silicon via) is provided between the pixel array and the logic circuit. ) To make an electrical connection.
  • the chip of each solid-state imaging device is divided from a wafer member on which a plurality of solid-state imaging devices in a finished product state are formed.
  • the manufacturing method of a semiconductor device is performed according to the following procedure. First, an insulating film is formed on one surface of a semiconductor member to which the first semiconductor portion and the second semiconductor portion are bonded. Next, a stopper film having resistance to prevent the predetermined chemical solution from permeating the insulating film when treated with the predetermined chemical solution is formed on the insulating film. Next, in the surface of the semiconductor member on the stopper film side, a vertical hole is formed in a region corresponding to the formation region of the Cu wiring junction for electrically connecting the first semiconductor portion and the second semiconductor portion. Next, Cu is buried in the vertical hole to form a Cu wiring junction. Next, a Cu diffusion prevention film is formed on the surface of the semiconductor member on the Cu wiring joint side.
  • the Cu diffusion preventing film in a region other than the predetermined region including the formation region of the Cu wiring bonding portion is removed to expose an unnecessary Cu portion existing in the region. Then, an unnecessary Cu portion is removed using a predetermined chemical solution.
  • a semiconductor device includes a semiconductor member, an insulating film, a Cu wiring bonding portion, a Cu diffusion prevention film, and a stopper film, and the configuration of each portion is as follows.
  • the semiconductor member includes a first semiconductor part and a second semiconductor part provided to be bonded to the first semiconductor part.
  • the insulating film is provided on one surface of the semiconductor member.
  • the Cu wiring junction part electrically connects the first semiconductor part and the second semiconductor part provided so as to penetrate the insulating film.
  • the Cu diffusion preventing film is formed on the Cu wiring junction.
  • the stopper film is formed on a region of the insulating film corresponding to at least a region where the Cu diffusion preventing film is formed, and is formed on a region of the insulating film where no Cu wiring junction is formed. Further, the stopper film has a resistance such that a predetermined chemical solution does not penetrate into the insulating film when an unnecessary Cu portion existing in a region other than the formation region of the Cu wiring junction is removed with a predetermined chemical solution.
  • an insulating film is formed on one surface of a semiconductor member to which the first semiconductor portion and the second semiconductor portion are bonded. Then, on the insulating film, a stopper film having a resistance that prevents the predetermined chemical solution from penetrating into the insulating film when an unnecessary Cu portion is removed with the predetermined chemical solution is formed. Thereby, damage to the semiconductor member due to the chemical treatment can be prevented in the subsequent step of removing unnecessary Cu portions remaining in the region other than the formation region of the Cu wiring bonding portion with a predetermined chemical solution. Therefore, according to the present disclosure, the yield of products can be further improved.
  • a schematic configuration of the semiconductor device according to the first embodiment will be described.
  • a back-illuminated solid-state imaging device will be described as an example of a semiconductor device.
  • an application example of the technology of the present disclosure described below is not limited to a solid-state imaging device.
  • any defect that may occur with Cu wiring as described below (Cu contamination) may occur. It can be applied to a semiconductor device.
  • FIG. 1 is a schematic cross-sectional view of a main part of the solid-state imaging device according to the first embodiment.
  • the solid-state imaging device 100 includes a bonding member 1 (semiconductor member), a first interlayer film 30 (insulating film), a stopper film 31, a second interlayer film 32, and a Cu diffusion prevention film 33. And a Cu wiring joint 34.
  • the bonding member 1 includes a first semiconductor part 10 (CMOS (Complementary Metal-Oxide-Semiconductor) image sensor part) and a second semiconductor part 20 (logic circuit part), which are joined at a joining interface Sj.
  • the first interlayer film 30 is formed on the surface of the first semiconductor unit 10 opposite to the second semiconductor unit 20 (on the Si substrate 13 described later). Further, the stopper film 31, the second interlayer film 32, and the Cu diffusion prevention film 33 are laminated in this order on the convex portion of the first interlayer film 30 (a predetermined region including the formation region of the Cu wiring junction 34).
  • the Cu wiring bonding portion 34 is constituted by a vertical hole wiring that electrically connects the first semiconductor portion 10 and the second semiconductor portion 20 as shown in FIG. It is formed in the region of 30 convex portions.
  • the manufacturing process of the solid-state imaging device 100 first, the first interlayer film 30, the stopper film 31, the second interlayer film 32, and the Cu diffusion prevention film 33 are first formed in the first semiconductor unit. 10 is formed so as to cover the entire surface. Then, a part of the Cu diffusion prevention film 33, the second interlayer film 32, the stopper film 31, and the first interlayer film 30 in the pixel region (the upper region of the photodiode 11a described later) is removed by dry etching (engraving) Included). Therefore, in the completed product of the solid-state imaging device 100, as shown in FIG. 1, a convex portion is formed in a predetermined region including the formation region of the Cu wiring junction 34, and the stopper film 31 and the second film are formed only on the convex portion. The interlayer film 32 and the Cu diffusion preventing film 33 remain.
  • the solid-state imaging device 100 includes a color filter and an on-chip microlens formed on the first interlayer film 30 in the pixel portion region including the photodiode 11a. Further, although not shown in FIG. 1, the solid-state imaging device 100 includes a light shielding film (OPB: OpticalBlack) formed on the first interlayer film 30. The light shielding film is formed on the first interlayer film 30 so as not to disturb the path of incident light to the photodiode 11a.
  • OPB OpticalBlack
  • the first semiconductor unit 10 includes a photoelectric conversion layer 11 having a photodiode 11a, and a first multilayer wiring layer 12 provided on the opposite side of the photoelectric conversion layer 11 from the first interlayer film 30 side. Is provided.
  • the photoelectric conversion layer 11 is electrically connected to the first multilayer wiring layer 12 by a vertical hole wiring 11b provided therein.
  • the first multilayer wiring layer 12 is configured by laminating a plurality of Cu wiring layers 14.
  • Each Cu wiring layer 14 includes a via 17 provided to obtain electrical connection between the interlayer insulating film 15, the Cu wiring portion 16 embedded therein, and a layer located on the first interlayer film 30 side from itself. And have. Further, a Cu diffusion prevention film 18 is provided between two adjacent Cu wiring layers 14.
  • the second semiconductor section 20 includes a transistor section 21 in which various MOS transistors 21a constituting an arithmetic circuit are formed, and a second multilayer wiring layer 22 provided on the first semiconductor section 10 side of the transistor section 21.
  • the transistor portion 21 is electrically connected to the second multilayer wiring layer 22 by a vertical hole wiring 21b provided therein.
  • the second multilayer wiring layer 22 is formed by laminating a plurality of Cu wiring layers 24.
  • Each Cu wiring layer 24 includes an interlayer insulating film 25, a Cu wiring part 26 embedded therein, and a via 27 provided to obtain electrical connection with a layer located closer to the transistor part 21 than itself. Have. Further, a Cu diffusion preventing film 28 is provided between two adjacent Cu wiring layers 24.
  • the first interlayer film 30 is made of an insulating film such as a SiO 2 film.
  • the convex portion is formed in the formation region of the Cu wiring joint 34 as described above.
  • the stopper film 31 removes an unnecessary Cu portion (hereinafter referred to as Cu residue) remaining in a region other than the formation region of the Cu wiring bonding portion 34 with a chemical solution
  • the chemical solution is used as the first interlayer film 30 (first semiconductor). It is a film provided to prevent penetration into the Si substrate 13) of the part 10. Therefore, the material for forming the stopper film 31 is formed of a material that is highly resistant to the chemical used for the Cu removal process.
  • the stopper film 31 is formed of a material having a higher etching resistance (lower etching rate) than Cu with respect to the wet chemical used. Further, when removing Cu residue by lift-off method as in the second embodiment to be described later, the stopper film is made of a material more resistant to the chemical solution used than the first interlayer film 30 and the second interlayer film 32. 31 is formed.
  • the stopper film 31 having the above-described resistance can be composed of, for example, a film containing C (carbon) such as a SiN film, a SiCN film, a SiC film, a SiCO film, or the like.
  • C carbon
  • by providing such a stopper film 31 in the manufacturing process of the solid-state imaging device 100 it is possible to prevent damage to the Si substrate 13 that occurs due to the removal process of Cu residue. Yield can be improved.
  • the second interlayer film 32 is formed of an insulating film such as a SiO 2 film.
  • an example in which the second interlayer film 32 is formed on the stopper film 31 will be described.
  • the present disclosure is not limited to this, and the second interlayer film 32 may not be provided.
  • the Cu diffusion preventing film 33 is made of an insulating film such as a SiN film.
  • the Cu wiring junction 34 is a Cu wiring that electrically connects the first semiconductor unit 10 (CMOS image sensor unit) and the second semiconductor unit 20 (logic circuit unit), and includes a first via 34 a and a second via. 34b and a via junction 34c.
  • CMOS image sensor unit CMOS image sensor unit
  • second semiconductor unit 20 logic circuit unit
  • the first via 34a is a vertical hole wiring that penetrates the second interlayer film 32, the stopper film 31, the first interlayer film 30, and the photoelectric conversion layer 11, and is formed of Cu.
  • One end of the first via 34a (the end on the first multilayer wiring layer 12 side) is connected to the Cu wiring part 16 of the Cu wiring layer 14 located closest to the photoelectric conversion layer 11 of the first multilayer wiring layer 12. Is done.
  • the other end of the first via 34a (the end opposite to the first multilayer wiring layer 12 side) is connected to the via junction 34c.
  • the second via 34 b is a vertical hole wiring that penetrates the second interlayer film 32, the stopper film 31, the first interlayer film 30, the photoelectric conversion layer 11, and the first multilayer wiring layer 12 (that is, the first semiconductor unit 10). , Cu.
  • One end portion (the end portion on the second multilayer wiring layer 22 side) of the second via 34 b is connected to the Cu wiring portion 26 of the Cu wiring layer 24 located closest to the first semiconductor portion 10 side of the second multilayer wiring layer 22.
  • the other end of the second via 34b (the end opposite to the second multilayer wiring layer 22 side) is connected to the via junction 34c.
  • the via junction 34c is a wiring portion that joins the first via 34a and the second via 34b, and is formed of Cu.
  • the first semiconductor unit 10 and the second semiconductor unit 20 are electrically connected by the via junction 34c.
  • the via junction 34 c is formed so as to be embedded in the surface of the second interlayer film 32.
  • a wiring unit (Cu wiring) that electrically connects the two after bonding the two.
  • a junction 34 is formed.
  • the wiring part for obtaining conduction between the first semiconductor part 10 and the second semiconductor part 20 is composed of Cu wiring having low resistance characteristics as described above. Since Cu wiring is generally difficult to process by dry etching, it is formed by a damascene process that combines a plating process and a CMP (Chemical-Mechanical-Polishing) process.
  • defects (concave portions) and pinholes are generated on the surface of the first semiconductor part due to the bonding between the first semiconductor part and the second semiconductor part.
  • a Cu film is also formed on such defects and pinholes.
  • Such a defect or a Cu portion remaining in the pinhole (Cu residue) may cause metal contamination in a subsequent process. In this case, the yield of product chips is lowered, and in the worst case, Cu contamination may occur in the production line.
  • FIGS. 2 to 7 are schematic cross-sectional views of the bonding member after various processing steps are performed on the bonding members of the first semiconductor portion and the second semiconductor portion.
  • the same components as those of the solid-state imaging device 100 of the first embodiment shown in FIG. 2 to 7 show only the configuration in the vicinity of the interface between the interlayer film and the first semiconductor portion for the sake of simplicity.
  • defect example 1 a problem that may occur when a light shielding film is formed on an interlayer film will be described with reference to FIGS.
  • the first semiconductor portion and the second semiconductor portion are bonded together, and then the interlayer film 200 is formed over the entire surface of the Si substrate 13 of the first semiconductor portion.
  • a Cu wiring junction 34 is formed by a damascene process in a predetermined region of the interlayer film 200 and the bonding member of the first semiconductor part and the second semiconductor member.
  • a Cu diffusion preventing film 33 is formed on the interlayer film 200 and the Cu wiring bonding portion 34 (state shown in FIG. 2).
  • the Cu residue 210 is also formed on the defects (concave portions) and pinholes generated on the surface of the bonded member on the first semiconductor portion side. That is, the Cu residue 210 is scattered in a region other than the region where the Cu wiring bonding portion 34 is formed.
  • the Cu residue 210 penetrates the interlayer film 200 as shown in FIG. 13 extending to a predetermined depth.
  • the Cu diffusion prevention film 33 and a part of the interlayer film 200 formed in the region of the pixel portion (not shown) are removed by dry etching (state shown in FIG. 3).
  • the reason for carrying out this step is as follows.
  • the Cu diffusion preventing film 33 is composed of, for example, a SiN film or a SiCN film, if these insulating films are present on the light incident side of the pixel portion, pixel characteristics such as sensitivity deterioration are likely to occur.
  • the distance between the photodiode and the lens is preferably as short as possible.
  • the engraving process cavity etching process
  • the region of the pixel portion the region other than the predetermined region (projection) including the formation region of the Cu wiring joint 34).
  • the region of the pixel portion is engraved so that the interlayer film 200 with a predetermined thickness remains on the Si substrate 13.
  • a convex portion is formed in a region other than the pixel portion of the interlayer film 200, for example, a formation region of the Cu wiring junction 34, and a step is formed at the boundary between the region of the Cu wiring junction 34 and the region of the pixel portion. Defined. Further, by this cavity etching process, as shown in FIG. 3, the Cu residue 210 is exposed on the surface of the bonded member on the side of the interlayer film 200.
  • a hole for grounding the light shielding film (light shielding film grounding hole 220) is formed by dry etching in a part of the formation region of the light shielding film ( The state of FIG. At this time, the light shielding film grounding hole 220 is formed by carving from the interlayer film 200 to a predetermined depth of the Si substrate 13 by dry etching.
  • the light shielding film 221 is formed in the formation region of the light shielding film grounding hole 220 (the state shown in FIG. 5), the following problems occur. As shown in FIG. 5, when a part of the light shielding film 221 is formed on the Cu residue 210, a part (Cu) of the Cu residue 210 is diffused into the light shielding film 221, react. In this case, it becomes difficult to process the light shielding film 221 into a desired pattern in the subsequent etching process of the light shielding film 221.
  • FIG. 6 shows a schematic cross-sectional view of the bonded member after the cavity etching process is performed on the pixel portion (not shown). 6 shows not only the Cu residue 210 formed to extend from the surface of the interlayer film 200 to a predetermined depth of the Si substrate 13, but also the Cu residue 211 remaining in the defect (concave portion) of the interlayer film 200. .
  • a chemical such as a hydrofluoric acid / hydrogen peroxide (FPM) solution or a sulfuric acid / hydrogen peroxide solution is used on the exposed surface.
  • FPM hydrofluoric acid / hydrogen peroxide
  • sulfuric acid / hydrogen peroxide solution is used on the exposed surface.
  • the remaining wet etching process is performed to remove Cu residues 210 and 211 (state shown in FIG. 7).
  • the chemical solution penetrates into minute defects (pinholes and the like) in the interlayer film 200, and when the chemical solution reaches the Si substrate 13, the Si substrate 13 is also etched.
  • a minute hole 212 penetrating to a predetermined depth of the Si substrate 13 is formed in a part of the interlayer film 200.
  • Cu diffuses into the Si substrate 13 via the chemical solution, and the Si substrate 13 is contaminated with Cu.
  • the interlayer film 200 may be altered by the penetration of the chemical solution.
  • the normal chip region (the pixel portion region where the Cu residues 210 and 211 are not formed) is also damaged, and the normal chip is damaged. There is a possibility of deteriorating characteristics.
  • FIGS. 8 to 19 are diagrams showing procedures of various processes from the polishing process of the Si substrate 13 to the bonding member 1 to the light shielding film forming process. Each figure shows the bonding member 1 after the various processes. It is a schematic sectional drawing. 8 to 19 show only the configuration in the vicinity of the surface on which various films of the Si substrate 13 (first semiconductor portion 10) are formed in order to simplify the description.
  • FIGS. 13 to 17 show Cu remaining in defects (concave portions) and pinholes in order to facilitate understanding of the characteristics and effects of the manufacturing method of the solid-state imaging device 100 of the present embodiment.
  • region in which 210 is formed is shown.
  • a schematic cross-sectional view of the bonding member 1 in a region where no defect (concave portion) or pinhole is generated is shown.
  • the first semiconductor unit 10 and the second semiconductor unit 20 are respectively produced in the same manner as in the conventional method of manufacturing a backside illumination type solid-state imaging device, and further, the two are bonded together to form a bonding member. 1 is produced.
  • the surface of the bonding member 1 on the Si substrate 13 (first semiconductor portion 10) side is ground and polished to reduce the thickness of the Si substrate 13 to a predetermined thickness (state shown in FIG. 8).
  • a first interlayer film 30 (for example, a SiO 2 film) is formed over the entire polished surface of the Si substrate 13 by using, for example, a CVD (Chemical Vapor Deposition) method (state of FIG. 9). .
  • CVD Chemical Vapor Deposition
  • the stopper film 31 is formed on the first interlayer film 30 by using a technique such as RF (Radio Frequency) sputtering method (state of FIG. 10).
  • RF Radio Frequency
  • a film having higher etching resistance (lower etching rate) than Cu for example, a SiN film, a SiCN film, a SiC film, with respect to a wet etching chemical (acid chemical) used when removing Cu residue described below,
  • the stopper film 31 is composed of a SiCO film or the like.
  • the film thickness of the stopper film 31 can be set to 30 nm or more, for example.
  • the thickness of the stopper film 31 is not limited to this, and is appropriately set according to, for example, the selection ratio of the chemical solution to be used (the etching rate ratio between the Cu film and the stopper film 31).
  • the etching rate ratio between the Cu film and the stopper film 31 is 10 times or more. It becomes. Therefore, in this case, considering the etching rate ratio, the film thickness of the stopper film 31 is set so that a sufficient thickness of the stopper film 31 remains even if the Cu residues 210 and 211 are completely removed. Set.
  • a second interlayer film 32 (for example, a SiO 2 film) is formed on the stopper film 31 using a technique such as a CVD method (state of FIG. 11).
  • a vertical hole 40 is formed in the formation region of the Cu wiring bonding portion 34 (see FIG. 13 described later) on the surface of the bonding member 1 on the second interlayer film 32 side using a technique such as dry etching (see FIG. 13). 12 states).
  • the first via 34 a extends from the second interlayer film 32 to the Cu wiring portion 16 of the Cu wiring layer 14 positioned closest to the photoelectric conversion layer 11 of the first multilayer wiring layer 12.
  • a vertical hole is formed, and the Cu wiring portion 16 is exposed at the opening of the vertical hole.
  • a vertical hole extending from the second interlayer film 32 to the Cu wiring part 26 of the Cu wiring layer 24 positioned closest to the first semiconductor part 10 of the second multilayer wiring layer 22. And the Cu wiring part 26 is exposed at the opening of the vertical hole.
  • the region of the second interlayer film 32 corresponding to the formation region of the via junction 34c is also engraved using a technique such as a dry etching method.
  • an insulating film made of, for example, a SiO 2 film is formed on the side wall surface defining the vertical hole 40 in order to ensure insulation between the Cu wiring bonding portion 34 and the Si substrate 13.
  • a Cu film is formed on the second interlayer film 32 by using a technique such as an electrolytic plating method. By this process, the Cu film is embedded in the vertical hole 40. Thereafter, unnecessary portions of the Cu film are removed by a chemical mechanical polishing (CMP) method. Specifically, the surface of the Cu film is polished by CMP until the second interlayer film 32 is exposed on the surface.
  • CMP chemical mechanical polishing
  • Cu residues 210 and 211 are also formed in pinholes and defects (concave portions) generated on the surface of the bonding member 1 on the first semiconductor portion 10 side (state of FIG. 13).
  • a Cu diffusion prevention film 33 (for example, a SiN film) is formed on the second interlayer film 32 and the Cu wiring bonding portion 34 by using a technique such as an RF sputtering method (state of FIG. 14).
  • an insulating film such as a SiO 2 film may be further formed on the Cu diffusion preventing film 33 as a protective film.
  • first cavity etching process dry etching is performed on the region of the Cu diffusion prevention film 33 corresponding to the pixel portion, and the Cu diffusion prevention film 33 and a part of the second interlayer film 32 in the region are removed (first cavity). Etching process). However, this first cavity etching process is performed until the Cu residues 210 and 211 are exposed on the etched surface (state of FIG. 15).
  • wet etching is performed on the bonding member 1 on which the Cu residues 210 and 211 are exposed on the surface using, for example, an acidic chemical solution containing an oxidizing agent such as a hydrofluoric acid / hydrogen peroxide solution or a sulfuric acid / hydrogen peroxide solution. Processing is performed to remove Cu residues 210 and 211 (state shown in FIG. 16).
  • the normal chip region (Cu residues 210 and 211 in the second interlayer film 32).
  • a microhole 41 is also generated in a pixel area where no symbol exists and damage occurs.
  • the stopper film 31 having high etching resistance against the chemical solution is provided between the first interlayer film 30 and the second interlayer film 32, the microhole 41 is formed in the Si substrate 13 (first interlayer film). It does not reach the membrane 30). Therefore, in this embodiment, in the above removal processing of the Cu residues 210 and 211, a part of the Cu residues 210 and 211 does not diffuse into the Si substrate 13 in the normal chip region, and Cu contamination does not occur.
  • the stopper film 31 that may cause deterioration of the pixel characteristics is removed in the pixel portion region.
  • the region is engraved so that the first interlayer film 30 having a predetermined thickness remains on the region corresponding to the pixel portion of the Si substrate 13. .
  • the protrusion including the formation region of the Cu wiring junction 34 is formed. Two steps are defined at the boundary between the pixel portion and the pixel portion region.
  • a light shielding film is formed on the first interlayer film 30 in the same manner as in the conventional manufacturing method. Specifically, first, as shown in FIG. 18, a light shielding film ground hole 42 is formed by dry etching in a part of the light shielding film formation region of the first interlayer film 30. At this time, dry etching is performed from the surface of the first interlayer film 30 to a predetermined depth of the Si substrate 13 to form a light shielding film grounding hole 42. Further, in this embodiment, the Cu residues 210 and 211 are removed before the formation process of the light shielding film grounding hole 42. Therefore, unlike the manufacturing method of the comparative example, Cu contamination occurs in the etching process. do not do.
  • a Ta-based metal film is laminated on the region of the first interlayer film 30 where the light shielding film ground hole 42 is formed, using a technique such as RF sputtering.
  • a light shielding film 43 is formed.
  • a color filter, an on-chip microlens, and the like are formed in the pixel portion in the same manner as in the conventional method of manufacturing a backside illumination type solid-state imaging device.
  • the solid-state imaging device 100 is manufactured as described above.
  • the stopper film 31 having high etching resistance against the chemical solution is provided between the first interlayer film 30 and the second interlayer film 32. Damage caused by the removal process does not reach the Si substrate 13. In this embodiment, Cu contamination does not occur even when the light shielding film grounding hole 42 is formed. Therefore, in the manufacturing method of the solid-state imaging device 100 of the present embodiment, it is possible to prevent Cu contamination of the chip, wafer, and process apparatus due to the Cu residue described in the comparative example, and to produce a normal chip without loss. Can do. Further, the normal chip can be used as a product chip, and various subsequent processes can be performed on the product chip. As a result, in the manufacturing method of the solid-state imaging device 100 of the present embodiment, the product yield can be improved.
  • Second Embodiment> In the first embodiment, the example in which the wet etching method is used as the technique for removing the Cu residue has been described, but the present disclosure is not limited to this.
  • the Cu residue may be removed by lift-off using a chemical solution that dissolves the interlayer film.
  • the second embodiment an example will be described.
  • the solid-state imaging device can be manufactured in the same manner as in the first embodiment except that the lift-off method is used as the Cu removal method.
  • the configuration of the solid-state imaging device of the present embodiment can also be configured in the same manner as the solid-state imaging device 100 (FIG. 1) of the first embodiment. Therefore, here, only the removal method of Cu residue will be described in detail.
  • 20 to 22 show the procedure of the Cu residue removal process in this embodiment.
  • 20 to 22 are schematic cross-sectional views of the bonding member 1 after various processes.
  • the first interlayer film 30, the first semiconductor unit 10 (Si substrate 13), Only the structure near the interface is shown.
  • the same reference numerals are given to the same configurations as those of the bonding member 1 after various steps shown in FIGS. 15 to 17 of the first embodiment. Is shown.
  • the various processing steps shown in FIGS. 8 to 14 described in the first embodiment are sequentially performed.
  • a film for example, a SiN film, a SiCN film, a SiC film, a SiCO film, etc.
  • a stopper film 31 is formed.
  • the film thickness of the stopper film 31 is appropriately set according to, for example, the selection ratio of the chemical solution to be used, as in the first embodiment.
  • first cavity etching process dry etching is performed on the region corresponding to the pixel portion of the Cu diffusion preventing film 33, and a part of the Cu diffusion preventing film 33 and the second interlayer film 32 in the region is removed (first cavity etching process). ). However, this first cavity etching process is performed until the Cu residues 210 and 211 are exposed on the etched surface (state of FIG. 20).
  • the second interlayer film 32, the stopper film 31, the first interlayer film 30, and the side walls of the Si substrate 13 that define the Cu residues 210 and 211 are formed.
  • the Cu residues 210 and 211 are lifted off and removed (state shown in FIG. 21).
  • the micro holes 50 are formed in the normal chip region of the second interlayer film 32, and damage occurs.
  • the stopper film 31 having a high resistance to the chemical used for removing the Cu residue is provided between the first interlayer film 30 and the second interlayer film 32, the micro holes 50 are formed on the Si substrate. 13 (first interlayer film 30) is not reached. That is, in this embodiment, in the above removal process of the Cu residues 210 and 211, a part of the Cu residues 210 and 211 does not diffuse into the Si substrate 13, and Cu contamination does not occur.
  • second cavity etching process After removing the Cu residues 210 and 211, dry again for the region corresponding to the pixel portion on the first semiconductor portion 10 side of the bonding member 1 (region other than the formation region of the Cu wiring junction 34). Etching is performed (second cavity etching process).
  • the second cavity etching process by the second cavity etching process, the second interlayer film 32, the stopper film 31, and a part of the first interlayer film 30 in the region of the pixel portion are removed (state shown in FIG. 22).
  • the region is engraved so that the first interlayer film 30 having a predetermined thickness remains on the region corresponding to the pixel portion of the Si substrate 13.
  • a light shielding film is formed on a predetermined region of the first interlayer film 30, and a color filter, an on-chip microlens, and the like are further formed on the pixel portion.
  • the solid-state imaging device is manufactured as described above.
  • a stopper film 31 having a high resistance to a chemical solution used for removing Cu residue is provided between the first interlayer film 30 and the second interlayer film 32 as in the first embodiment. Therefore, also in the present embodiment, the damage generated by the Cu residue removal process does not reach the Si substrate 13, and thus the same effect as in the first embodiment can be obtained.
  • the semiconductor device (solid-state imaging device) according to the present disclosure can be applied to various electronic devices.
  • the solid-state imaging device described in the first and second embodiments includes a camera system such as a digital still camera and a digital video camera, a mobile phone having an imaging function, or other devices having an imaging function. It can be applied to electronic equipment.
  • a camera will be described as an example of a configuration of the electronic device.
  • FIG. 23 shows a schematic configuration of a camera according to an application example. Note that FIG. 23 illustrates a configuration example of a digital video camera that can capture still images or moving images.
  • the camera 300 in this example includes a solid-state imaging device 301, an optical system 302 that guides incident light to a light receiving sensor (not shown) of the solid-state imaging device 301, and a shutter device 303 provided between the solid-state imaging device 301 and the optical system 302. And a drive circuit 304 that drives the solid-state imaging device 301. Further, the camera 300 includes a signal processing circuit 305 that processes an output signal of the solid-state imaging device 301.
  • the solid-state imaging device 301 can be configured by, for example, the solid-state imaging device described in the first and second embodiments. Configurations and functions of other parts are as follows.
  • the optical system (optical lens) 302 forms image light (incident light) from a subject on an imaging surface (not shown) of the solid-state imaging device 301. Thereby, signal charges are accumulated in the solid-state imaging device 301 for a certain period.
  • the optical system 302 may be composed of an optical lens group including a plurality of optical lenses.
  • the shutter device 303 controls the light irradiation period and the light shielding period of the incident light to the solid-state imaging device 301.
  • the drive circuit 304 supplies drive signals to the solid-state imaging device 301 and the shutter device 303.
  • the drive circuit 304 controls the signal output operation to the signal processing circuit 305 of the solid-state imaging device 301 and the shutter operation of the shutter device 303 by the supplied drive signal. That is, in this example, a signal transfer operation from the solid-state imaging device 301 to the signal processing circuit 305 is performed by a drive signal (timing signal) supplied from the drive circuit 304.
  • the signal processing circuit 305 performs various types of signal processing on the signal transferred from the solid-state imaging device 301.
  • the signal (video signal) that has been subjected to various signal processing is stored in a storage medium (not shown) such as a memory, or is output to a monitor (not shown).
  • this indication can also take the following structures. (1) Forming an insulating film on one surface of the semiconductor member including the first semiconductor portion and the second semiconductor portion; Forming a stopper film resistant to a predetermined chemical solution on the insulating film; Forming a vertical hole in the surface of the semiconductor member on the stopper film side; Forming a Cu wiring junction for electrically connecting the first semiconductor portion and the second semiconductor portion in the vertical hole; Forming a Cu diffusion prevention film on the surface of the semiconductor member on the Cu wiring joint side; Removing the Cu diffusion prevention film in a region other than the predetermined region including the formation region of the Cu wiring bonding portion to expose an unnecessary Cu portion in the region; Removing the unnecessary Cu portion by using the predetermined chemical solution.
  • a semiconductor member including a first semiconductor portion and a second semiconductor portion; An insulating film on one surface of the semiconductor member; A Cu wiring junction that penetrates the insulating film and electrically connects the first semiconductor portion and the second semiconductor portion; A Cu diffusion prevention film on the Cu wiring junction; A semiconductor device comprising: a stopper film provided between at least the Cu diffusion preventing film and the insulating film and having resistance to a predetermined chemical solution for removing unnecessary Cu portions.

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Abstract

Provided is a method for producing a semiconductor device, the method allowing product yield to be further improved. In this method for producing a semiconductor device, firstly, a stopper layer (31) is formed over an insulating film (30) that has been formed on one surface of a semiconductor member in which a first semiconductor portion and a second semiconductor portion have been bonded together, the film having resistance such that the insulating film is not permeated by a predetermined chemical liquid when treated with the predetermined chemical liquid. Next, on the stopper layer (31) side of the semiconductor member, a Cu wiring joining portion (34) is formed for electrical connection of the first semiconductor portion and the second semiconductor portion. Next, a Cu diffusion prevention layer (33) is formed over the Cu wiring joining portion (34). Next, the area of the Cu diffusion prevention layer (33), except for the area where the Cu wiring joining portion (34) is formed, is removed, exposing unwanted Cu portions (210, 211) present in the area. Using the predetermined chemical liquid, the unwanted Cu portions (210, 211) are then removed.

Description

半導体装置の製造方法、及び、半導体装置Semiconductor device manufacturing method and semiconductor device
　本開示は、半導体装置の製造方法及び半導体装置に関し、より詳細には、２つの半導体部材を貼り合わせ、その後、両者をＣｕ配線で電気的に接合する半導体装置の製造方法及びその製造方法により作製された半導体装置に関する。 The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device, and more specifically, a method for manufacturing a semiconductor device in which two semiconductor members are bonded together and then electrically joined together by Cu wiring, and the manufacturing method thereof. The present invention relates to a semiconductor device.
　半導体装置の微細化技術の分野では、最近、マスク工程の更なる微細化により高集積化を目指す「ｍｏｒｅ　Ｍｏｏｒｅ」と呼ばれる微細化技術の流れが減速し、その代わりに、「ｂｅｙｏｎｄ　Ｍｏｏｒｅ」と呼ばれる微細化技術が注目を集めている。「ｂｅｙｏｎｄ　Ｍｏｏｒｅ」と呼ばれる微細化技術では、半導体装置を構成する複数の素子を、垂直方向に積み上げ、３次元的に配線を施すことにより、素子間の抵抗値及び容量値を低減することができる。 In the field of semiconductor device miniaturization technology, the flow of miniaturization technology called “more Moore”, which aims at higher integration by further miniaturization of the mask process, has recently slowed down, and instead called “beyond Moore” Miniaturization technology is attracting attention. With the miniaturization technology called “beyond Moore”, the resistance value and capacitance value between elements can be reduced by stacking a plurality of elements constituting the semiconductor device in the vertical direction and providing wiring in three dimensions. .
　上述した素子を垂直方向に積層しかつ３次元的に配線を施す技術（以下、３次元化技術という）の開発に、ウエハレベルでのパッケージ技術の開発が加わった場合、半導体装置の製造コストを低減することが可能になる。それゆえ、従来、半導体装置の製造方法において、様々な３次元化技術が提案されている（例えば、特許文献１参照）。 If the development of the technology for stacking the above-mentioned elements in the vertical direction and providing the wiring in three dimensions (hereinafter referred to as three-dimensional technology) with the development of the packaging technology at the wafer level, the manufacturing cost of the semiconductor device is reduced. It becomes possible to reduce. Therefore, conventionally, various three-dimensional techniques have been proposed in semiconductor device manufacturing methods (see, for example, Patent Document 1).
　特許文献１には、次のような半導体装置の作製手法が提案されている。まず、第１ウエハの作製プロセスにおいて、例えばタングステン（Ｗ）やポリシリコンなどからなる埋め込み配線を、Ｓｉ基板の表面に形成する。次いで、第１ウエハの作製プロセスの終了後、Ｓｉ基板の裏面を研削して埋め込み配線を露出させ、バンプを形成する。そして、第１ウエハと同様にして作製された第２ウエハと、第１ウエハとを貼り合わせ、両者を電気的に接続する。 Patent Document 1 proposes a method for manufacturing a semiconductor device as follows. First, in the manufacturing process of the first wafer, a buried wiring made of, for example, tungsten (W) or polysilicon is formed on the surface of the Si substrate. Next, after the manufacturing process of the first wafer is completed, the back surface of the Si substrate is ground to expose the embedded wiring, and bumps are formed. Then, the second wafer manufactured in the same manner as the first wafer and the first wafer are bonded together, and both are electrically connected.
　また、近年、半導体装置の一つである固体撮像装置においても、フットプリントの縮小化や高集積化に対応するため、集積回路の様々な３次元化技術が提案されている（例えば、非特許文献１及び特許文献１参照）。 In recent years, in a solid-state imaging device which is one of semiconductor devices, various three-dimensional technologies for integrated circuits have been proposed in order to cope with a reduction in footprint and high integration (for example, non-patents). Reference 1 and Patent Reference 1).
　非特許文献１に記載された技術では、まず、２つのウエハ間において回路同士を貼り合わせた後、各々のウエハに予め埋め込んで形成した導電性のパッド部に接触するような縦孔、又は、パッド部を貫通するような縦孔を形成する。次いで、形成された縦孔に導電性材料で埋め込むことにより、２つのウエハ間において回路同士を電気的に接続する。 In the technique described in Non-Patent Document 1, first, after bonding circuits between two wafers, a vertical hole that comes into contact with a conductive pad portion formed by embedding in advance in each wafer, or A vertical hole penetrating the pad portion is formed. Next, the circuit is electrically connected between the two wafers by embedding the formed vertical hole with a conductive material.
　また、特許文献２には、裏面照射型の固体撮像装置に３次元化技術を適用した製造手法が提案されている。特許文献２に開示された技術では、まず、画素アレイを備えた第１半導体ウエハと、ロジック回路を備えた第２半導体ウエハとを貼り合わせ、画素アレイ及びロジック回路間をＴＳＶ（through-silicon via）を使って電気的に接続する。その後、完成品状態の固体撮像装置が複数形成されたウエハ部材から各固体撮像装置のチップを分割する。 In addition, Patent Document 2 proposes a manufacturing method in which a three-dimensional technique is applied to a back-illuminated solid-state imaging device. In the technology disclosed in Patent Document 2, first, a first semiconductor wafer provided with a pixel array and a second semiconductor wafer provided with a logic circuit are bonded together, and a TSV (through-silicon via) is provided between the pixel array and the logic circuit. ) To make an electrical connection. Thereafter, the chip of each solid-state imaging device is divided from a wafer member on which a plurality of solid-state imaging devices in a finished product state are formed.
特開平１１－２６１０００号公報JP-A-11-261000 特開２０１０－２４５５０６号公報JP 2010-245506 A
　上述のように、従来、半導体装置の製造方法において、様々な３次元化技術が提案されている。しかしながら、この技術分野では、３次元化技術を用いた半導体装置の製造方法において、より一層、歩留まりの良い半導体装置の製造方法の開発が望まれている。本開示は、上記要望に応えるためになされたものであり、３次元化技術を用いた半導体装置の製造方法において、より一層、製品の歩留まりを向上させることが望ましい。 As described above, conventionally, various three-dimensional techniques have been proposed in semiconductor device manufacturing methods. However, in this technical field, it is desired to develop a semiconductor device manufacturing method with a higher yield in a semiconductor device manufacturing method using a three-dimensional technique. The present disclosure has been made to meet the above-described demand, and it is desirable to further improve the product yield in a method of manufacturing a semiconductor device using a three-dimensional technology.
　本開示の一実施形態の半導体装置の製造方法は、次の手順で行う。まず、第１半導体部及び第２半導体部を貼り合わせた半導体部材の一方の面上に絶縁膜を形成する。次いで、所定の薬液で処理された際に所定の薬液が絶縁膜に浸透しないような耐性を有するストッパー膜を、絶縁膜上に形成する。次いで、半導体部材のストッパー膜側の表面において、第１半導体部及び第２半導体部を電気的に接続するためのＣｕ配線接合部の形成領域に対応する領域に縦孔を形成する。次いで、縦孔にＣｕを埋め込み、Ｃｕ配線接合部を形成する。次いで、半導体部材のＣｕ配線接合部側の表面にＣｕ拡散防止膜を形成する。次いで、半導体部材のＣｕ拡散防止膜側の表面において、Ｃｕ配線接合部の形成領域を含む所定領域以外の領域のＣｕ拡散防止膜を除去して該領域に存在する不要なＣｕ部を露出させる。そして、所定の薬液を用いて、不要なＣｕ部を除去する。 The manufacturing method of a semiconductor device according to an embodiment of the present disclosure is performed according to the following procedure. First, an insulating film is formed on one surface of a semiconductor member to which the first semiconductor portion and the second semiconductor portion are bonded. Next, a stopper film having resistance to prevent the predetermined chemical solution from permeating the insulating film when treated with the predetermined chemical solution is formed on the insulating film. Next, in the surface of the semiconductor member on the stopper film side, a vertical hole is formed in a region corresponding to the formation region of the Cu wiring junction for electrically connecting the first semiconductor portion and the second semiconductor portion. Next, Cu is buried in the vertical hole to form a Cu wiring junction. Next, a Cu diffusion prevention film is formed on the surface of the semiconductor member on the Cu wiring joint side. Next, on the surface of the semiconductor member on the Cu diffusion preventing film side, the Cu diffusion preventing film in a region other than the predetermined region including the formation region of the Cu wiring bonding portion is removed to expose an unnecessary Cu portion existing in the region. Then, an unnecessary Cu portion is removed using a predetermined chemical solution.
　また、本開示の一実施形態の半導体装置は、半導体部材と、絶縁膜と、Ｃｕ配線接合部と、Ｃｕ拡散防止膜と、ストッパー膜とを備える構成とし、各部の構成を次のようにする。半導体部材は、第１半導体部と、第１半導体部に貼り合わせて設けられた第２半導体部とを有する。絶縁膜は、半導体部材の一方の面上に設けられる。Ｃｕ配線接合部は、絶縁膜を貫通するようにして設けられた、第１半導体部及び第２半導体部を電気的に接続する。Ｃｕ拡散防止膜は、Ｃｕ配線接合部上に形成される。ストッパー膜は、絶縁膜の少なくともＣｕ拡散防止膜の形成領域に対応する領域上に形成され、かつ、絶縁膜のＣｕ配線接合部が形成されていない領域上に形成される。さらに、ストッパー膜は、Ｃｕ配線接合部の形成領域以外の領域に存在する不要なＣｕ部を所定の薬液で除去した際に所定の薬液が絶縁膜に浸透しないような耐性を有する。 In addition, a semiconductor device according to an embodiment of the present disclosure includes a semiconductor member, an insulating film, a Cu wiring bonding portion, a Cu diffusion prevention film, and a stopper film, and the configuration of each portion is as follows. . The semiconductor member includes a first semiconductor part and a second semiconductor part provided to be bonded to the first semiconductor part. The insulating film is provided on one surface of the semiconductor member. The Cu wiring junction part electrically connects the first semiconductor part and the second semiconductor part provided so as to penetrate the insulating film. The Cu diffusion preventing film is formed on the Cu wiring junction. The stopper film is formed on a region of the insulating film corresponding to at least a region where the Cu diffusion preventing film is formed, and is formed on a region of the insulating film where no Cu wiring junction is formed. Further, the stopper film has a resistance such that a predetermined chemical solution does not penetrate into the insulating film when an unnecessary Cu portion existing in a region other than the formation region of the Cu wiring junction is removed with a predetermined chemical solution.
　上述のように、本開示の一実施形態の半導体装置の製造方法では、第１半導体部及び第２半導体部を貼り合わせた半導体部材の一方の面上に絶縁膜を形成する。そして、絶縁膜上に、不要なＣｕ部を所定の薬液で除去した際に該所定の薬液が絶縁膜に浸透しないような耐性を有するストッパー膜を形成する。これにより、その後に行う、Ｃｕ配線接合部の形成領域以外の領域に残存する不要なＣｕ部を所定の薬液で除去する工程において、その薬液処理による半導体部材へのダメージを防止することができる。それゆえ、本開示によれば、より一層、製品の歩留まりを向上させることができる。 As described above, in the method for manufacturing a semiconductor device according to an embodiment of the present disclosure, an insulating film is formed on one surface of a semiconductor member to which the first semiconductor portion and the second semiconductor portion are bonded. Then, on the insulating film, a stopper film having a resistance that prevents the predetermined chemical solution from penetrating into the insulating film when an unnecessary Cu portion is removed with the predetermined chemical solution is formed. Thereby, damage to the semiconductor member due to the chemical treatment can be prevented in the subsequent step of removing unnecessary Cu portions remaining in the region other than the formation region of the Cu wiring bonding portion with a predetermined chemical solution. Therefore, according to the present disclosure, the yield of products can be further improved.
本開示の第１の実施形態に係る固体撮像装置の概略構成断面図である。It is a schematic structure sectional view of a solid-state imaging device concerning a 1st embodiment of this indication. 比較例の固体撮像装置の製造手法におけるＣｕ汚染の不具合を説明するための図である。It is a figure for demonstrating the malfunction of Cu contamination in the manufacturing method of the solid-state imaging device of a comparative example. 比較例の固体撮像装置の製造手法におけるＣｕ汚染の不具合を説明するための図である。It is a figure for demonstrating the malfunction of Cu contamination in the manufacturing method of the solid-state imaging device of a comparative example. 比較例の固体撮像装置の製造手法におけるＣｕ汚染の不具合を説明するための図である。It is a figure for demonstrating the malfunction of Cu contamination in the manufacturing method of the solid-state imaging device of a comparative example. 比較例の固体撮像装置の製造手法におけるＣｕ汚染の不具合を説明するための図である。It is a figure for demonstrating the malfunction of Cu contamination in the manufacturing method of the solid-state imaging device of a comparative example. 比較例の固体撮像装置の製造手法において、ウェットエッチングで不要なＣｕを除去した際の不具合を説明するための図である。It is a figure for demonstrating the malfunction at the time of removing unnecessary Cu by wet etching in the manufacturing method of the solid-state imaging device of a comparative example. 比較例の固体撮像装置の製造手法において、ウェットエッチングで不要なＣｕを除去した際の不具合を説明するための図である。It is a figure for demonstrating the malfunction at the time of removing unnecessary Cu by wet etching in the manufacturing method of the solid-state imaging device of a comparative example. 第１の実施形態に係る固体撮像装置の製造手法を説明するための図である。It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１の実施形態に係る固体撮像装置の製造手法を説明するための図である。It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１の実施形態に係る固体撮像装置の製造手法を説明するための図である。It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１の実施形態に係る固体撮像装置の製造手法を説明するための図である。It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１の実施形態に係る固体撮像装置の製造手法を説明するための図である。It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１の実施形態に係る固体撮像装置の製造手法を説明するための図である。It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１の実施形態に係る固体撮像装置の製造手法を説明するための図である。It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１の実施形態に係る固体撮像装置の製造手法を説明するための図である。It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１の実施形態に係る固体撮像装置の製造手法を説明するための図である。It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１の実施形態に係る固体撮像装置の製造手法を説明するための図である。It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１の実施形態に係る固体撮像装置の製造手法を説明するための図である。It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 第１の実施形態に係る固体撮像装置の製造手法を説明するための図である。It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 本開示の第２の実施形態に係る固体撮像装置の製造手法を説明するための図である。It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 2nd Embodiment of this indication. 第２の実施形態に係る固体撮像装置の製造手法を説明するための図である。It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 2nd Embodiment. 第２の実施形態に係る固体撮像装置の製造手法を説明するための図である。It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 2nd Embodiment. 本開示の半導体装置（固体撮像装置）を適用した電子機器の一例を示す図である。It is a figure which shows an example of the electronic device to which the semiconductor device (solid-state imaging device) of this indication is applied.
　以下に、本開示の実施形態に係る半導体装置及びその製造方法の具体例を、図面を参照しながら下記の順で説明する。ただし、本開示は下記の例に限定されない。
１．第１の実施形態
２．第２の実施形態
３．応用例 Hereinafter, specific examples of the semiconductor device and the manufacturing method thereof according to the embodiment of the present disclosure will be described in the following order with reference to the drawings. However, the present disclosure is not limited to the following example.
1. First Embodiment 2. FIG. Second Embodiment 3. Application examples
＜１．第１の実施形態＞
　まず、第１の実施形態に係る半導体装置の概略構成を説明する。本実施形態では、半導体装置の一例として、裏面照射型の固体撮像装置を例に挙げ説明する。なお、以下に説明する本開示の技術の適用例は、固体撮像装置に限定されない。複数の半導体素子（半導体部材）を、垂直方向に積み上げ、さらに３次元的にＣｕ配線を施す半導体装置において、下記に説明するようなＣｕ配線に伴い発生する不具合（Ｃｕ汚染）が生じ得る任意の半導体装置に適用可能である。 <1. First Embodiment>
First, a schematic configuration of the semiconductor device according to the first embodiment will be described. In the present embodiment, a back-illuminated solid-state imaging device will be described as an example of a semiconductor device. Note that an application example of the technology of the present disclosure described below is not limited to a solid-state imaging device. In a semiconductor device in which a plurality of semiconductor elements (semiconductor members) are stacked in a vertical direction and Cu wiring is three-dimensionally provided, any defect that may occur with Cu wiring as described below (Cu contamination) may occur. It can be applied to a semiconductor device.
［固体撮像装置の全体構成］
　図１に、第１の実施形態に係る固体撮像装置の要部の概略断面図を示す。 [Overall configuration of solid-state imaging device]
FIG. 1 is a schematic cross-sectional view of a main part of the solid-state imaging device according to the first embodiment.
（１）全体構成
　固体撮像装置１００は、貼り合わせ部材１（半導体部材）と、第１層間膜３０（絶縁膜）と、ストッパー膜３１と、第２層間膜３２と、Ｃｕ拡散防止膜３３と、Ｃｕ配線接合部３４とを備える。 (1) Overall Configuration The solid-state imaging device 100 includes a bonding member 1 (semiconductor member), a first interlayer film 30 (insulating film), a stopper film 31, a second interlayer film 32, and a Cu diffusion prevention film 33. And a Cu wiring joint 34.
　貼り合わせ部材１は、第１半導体部１０（ＣＭＯＳ（Complementary Metal-Oxide-Semiconductor）イメージセンサ部）と、第２半導体部２０（ロジック回路部）とを有し、両者が接合界面Ｓｊで接合される。また、第１層間膜３０は、第１半導体部１０の第２半導体部２０側とは反対側の面上（後述のＳｉ基板１３上）に形成される。さらに、ストッパー膜３１、第２層間膜３２及びＣｕ拡散防止膜３３は、第１層間膜３０の凸部（Ｃｕ配線接合部３４の形成領域を含む所定領域）上に、この順で積層される。また、本実施形態では、Ｃｕ配線接合部３４は、図１に示すように、第１半導体部１０と第２半導体部２０とを電気的に接続する縦孔配線で構成され、第１層間膜３０の凸部の領域に形成される。 The bonding member 1 includes a first semiconductor part 10 (CMOS (Complementary Metal-Oxide-Semiconductor) image sensor part) and a second semiconductor part 20 (logic circuit part), which are joined at a joining interface Sj. The The first interlayer film 30 is formed on the surface of the first semiconductor unit 10 opposite to the second semiconductor unit 20 (on the Si substrate 13 described later). Further, the stopper film 31, the second interlayer film 32, and the Cu diffusion prevention film 33 are laminated in this order on the convex portion of the first interlayer film 30 (a predetermined region including the formation region of the Cu wiring junction 34). . Further, in the present embodiment, the Cu wiring bonding portion 34 is constituted by a vertical hole wiring that electrically connects the first semiconductor portion 10 and the second semiconductor portion 20 as shown in FIG. It is formed in the region of 30 convex portions.
　なお、本実施形態では、後述するように、固体撮像装置１００の製造過程において、まず、第１層間膜３０、ストッパー膜３１、第２層間膜３２及びＣｕ拡散防止膜３３を、第１半導体部１０の表面全体を覆うように形成する。そして、画素部領域（後述のフォトダイオード１１ａの上部領域）のＣｕ拡散防止膜３３、第２層間膜３２、ストッパー膜３１、及び、第１層間膜３０の一部をドライエッチングにより除去する（彫り込む）。それゆえ、固体撮像装置１００の完成品では、図１に示すように、Ｃｕ配線接合部３４の形成領域を含む所定領域に凸部が形成され、該凸部にのみ、ストッパー膜３１、第２層間膜３２及びＣｕ拡散防止膜３３が残存した状態となる。 In this embodiment, as will be described later, in the manufacturing process of the solid-state imaging device 100, first, the first interlayer film 30, the stopper film 31, the second interlayer film 32, and the Cu diffusion prevention film 33 are first formed in the first semiconductor unit. 10 is formed so as to cover the entire surface. Then, a part of the Cu diffusion prevention film 33, the second interlayer film 32, the stopper film 31, and the first interlayer film 30 in the pixel region (the upper region of the photodiode 11a described later) is removed by dry etching (engraving) Included). Therefore, in the completed product of the solid-state imaging device 100, as shown in FIG. 1, a convex portion is formed in a predetermined region including the formation region of the Cu wiring junction 34, and the stopper film 31 and the second film are formed only on the convex portion. The interlayer film 32 and the Cu diffusion preventing film 33 remain.
　また、図１には示さないが、固体撮像装置１００は、フォトダイオード１１ａを含む画素部領域の第１層間膜３０上に形成されたカラーフィルタ及びオンチップマイクロレンズを備える。さらに、図１には示さないが、固体撮像装置１００は、第１層間膜３０上に形成された遮光膜（ＯＰＢ：OpticalBlack）を備える。なお、遮光膜は、フォトダイオード１１ａへの入射光の経路を妨げないように、第１層間膜３０上に形成される。 Although not shown in FIG. 1, the solid-state imaging device 100 includes a color filter and an on-chip microlens formed on the first interlayer film 30 in the pixel portion region including the photodiode 11a. Further, although not shown in FIG. 1, the solid-state imaging device 100 includes a light shielding film (OPB: OpticalBlack) formed on the first interlayer film 30. The light shielding film is formed on the first interlayer film 30 so as not to disturb the path of incident light to the photodiode 11a.
（２）各部の構成
　第１半導体部１０は、フォトダイオード１１ａを有する光電変換層１１と、光電変換層１１の第１層間膜３０側とは反対側に設けられた第１多層配線層１２とを備える。なお、光電変換層１１は、その内部に設けられた縦孔配線１１ｂにより第１多層配線層１２と電気的に接続される。 (2) Configuration of Each Part The first semiconductor unit 10 includes a photoelectric conversion layer 11 having a photodiode 11a, and a first multilayer wiring layer 12 provided on the opposite side of the photoelectric conversion layer 11 from the first interlayer film 30 side. Is provided. The photoelectric conversion layer 11 is electrically connected to the first multilayer wiring layer 12 by a vertical hole wiring 11b provided therein.
　第１多層配線層１２は、複数のＣｕ配線層１４を積層して構成される。各Ｃｕ配線層１４は、層間絶縁膜１５と、その内部に埋め込まれたＣｕ配線部１６と、自身より第１層間膜３０側に位置する層との電気接続を得るために設けられたビア１７とを有する。また、互いに隣り合う２つのＣｕ配線層１４間には、Ｃｕ拡散防止膜１８が設けられる。 The first multilayer wiring layer 12 is configured by laminating a plurality of Cu wiring layers 14. Each Cu wiring layer 14 includes a via 17 provided to obtain electrical connection between the interlayer insulating film 15, the Cu wiring portion 16 embedded therein, and a layer located on the first interlayer film 30 side from itself. And have. Further, a Cu diffusion prevention film 18 is provided between two adjacent Cu wiring layers 14.
　第２半導体部２０は、演算回路を構成する各種ＭＯＳトランジスタ２１ａが形成されたトランジスタ部２１と、トランジスタ部２１の第１半導体部１０側に設けられた第２多層配線層２２とを備える。なお、トランジスタ部２１は、その内部に設けられた縦孔配線２１ｂにより第２多層配線層２２と電気的に接続される。 The second semiconductor section 20 includes a transistor section 21 in which various MOS transistors 21a constituting an arithmetic circuit are formed, and a second multilayer wiring layer 22 provided on the first semiconductor section 10 side of the transistor section 21. The transistor portion 21 is electrically connected to the second multilayer wiring layer 22 by a vertical hole wiring 21b provided therein.
　第２多層配線層２２は、複数のＣｕ配線層２４を積層して構成される。各Ｃｕ配線層２４は、層間絶縁膜２５と、その内部に埋め込まれたＣｕ配線部２６と、自身よりトランジスタ部２１側に位置する層との電気接続を得るために設けられたビア２７とを有する。また、互いに隣り合う２つのＣｕ配線層２４間には、Ｃｕ拡散防止膜２８が設けられる。 The second multilayer wiring layer 22 is formed by laminating a plurality of Cu wiring layers 24. Each Cu wiring layer 24 includes an interlayer insulating film 25, a Cu wiring part 26 embedded therein, and a via 27 provided to obtain electrical connection with a layer located closer to the transistor part 21 than itself. Have. Further, a Cu diffusion preventing film 28 is provided between two adjacent Cu wiring layers 24.
　第１層間膜３０は、例えばＳｉＯ２膜等の絶縁膜で構成される。なお、第１層間膜３０におけるＣｕ配線接合部３４の形成領域には、上述のように、凸部が形成される。 The first interlayer film 30 is made of an insulating film such as a SiO 2 film. In the first interlayer film 30, the convex portion is formed in the formation region of the Cu wiring joint 34 as described above.
　ストッパー膜３１は、Ｃｕ配線接合部３４の形成領域以外の領域に残存する不要なＣｕ部（以下、Ｃｕ残という）を薬液で除去する際に、その薬液が第１層間膜３０（第１半導体部１０のＳｉ基板１３）に浸透することを抑制するために設けられた膜である。それゆえ、ストッパー膜３１の形成材料は、Ｃｕ残の除去処理に用いる薬液に対して、耐性の高い材料で形成される。 When the stopper film 31 removes an unnecessary Cu portion (hereinafter referred to as Cu residue) remaining in a region other than the formation region of the Cu wiring bonding portion 34 with a chemical solution, the chemical solution is used as the first interlayer film 30 (first semiconductor). It is a film provided to prevent penetration into the Si substrate 13) of the part 10. Therefore, the material for forming the stopper film 31 is formed of a material that is highly resistant to the chemical used for the Cu removal process.
　なお、本実施形態のようにウェットエッチング法でＣｕ残を除去する場合には、用いるウェット薬液に対して、Ｃｕよりエッチング耐性の高い（エッチングレートの低い）材料でストッパー膜３１を形成する。また、後述の第２の実施形態のように、リフトオフ法でＣｕ残を除去する場合には、用いる薬液に対して、第１層間膜３０及び第２層間膜３２より耐性の高い材料でストッパー膜３１を形成する。 When removing Cu residue by a wet etching method as in the present embodiment, the stopper film 31 is formed of a material having a higher etching resistance (lower etching rate) than Cu with respect to the wet chemical used. Further, when removing Cu residue by lift-off method as in the second embodiment to be described later, the stopper film is made of a material more resistant to the chemical solution used than the first interlayer film 30 and the second interlayer film 32. 31 is formed.
　上述のような耐性を有するストッパー膜３１としては、例えば、ＳｉＮ膜や、ＳｉＣＮ膜、ＳｉＣ膜、ＳｉＣＯ膜等のＣ（炭素）を含む膜などで構成することができる。本実施形態では、このようなストッパー膜３１を固体撮像装置１００の製造過程で設けることにより、Ｃｕ残の除去処理により発生するＳｉ基板１３へのダメージを防止することができ、固体撮像装置１００の歩留まりを向上させることができる。 The stopper film 31 having the above-described resistance can be composed of, for example, a film containing C (carbon) such as a SiN film, a SiCN film, a SiC film, a SiCO film, or the like. In the present embodiment, by providing such a stopper film 31 in the manufacturing process of the solid-state imaging device 100, it is possible to prevent damage to the Si substrate 13 that occurs due to the removal process of Cu residue. Yield can be improved.
　第２層間膜３２は、第１層間膜３０と同様に、例えばＳｉＯ２膜等の絶縁膜で構成される。なお、本実施形態では、ストッパー膜３１上に、第２層間膜３２を形成する例を説明するが、本開示はこれに限定されず、第２層間膜３２を設けない構成にしてもよい。また、Ｃｕ拡散防止膜３３は、例えばＳｉＮ膜等の絶縁膜で構成される。 Similar to the first interlayer film 30, the second interlayer film 32 is formed of an insulating film such as a SiO 2 film. In the present embodiment, an example in which the second interlayer film 32 is formed on the stopper film 31 will be described. However, the present disclosure is not limited to this, and the second interlayer film 32 may not be provided. Further, the Cu diffusion preventing film 33 is made of an insulating film such as a SiN film.
　Ｃｕ配線接合部３４は、第１半導体部１０（ＣＭＯＳイメージセンサ部）と第２半導体部２０（ロジック回路部）とを電気的に接続するＣｕ配線であり、第１ビア３４ａと、第２ビア３４ｂと、ビア接合部３４ｃとで構成される。なお、本実施形態では、第１半導体部１０と第２半導体部２０とを電気的に接続するＣｕ配線として、Ｃｕ配線接合部３４を一つ設ける例を説明したが、本開示はこれに限定されず、Ｃｕ配線接合部３４を複数設けてもよい。 The Cu wiring junction 34 is a Cu wiring that electrically connects the first semiconductor unit 10 (CMOS image sensor unit) and the second semiconductor unit 20 (logic circuit unit), and includes a first via 34 a and a second via. 34b and a via junction 34c. In the present embodiment, an example in which one Cu wiring junction 34 is provided as a Cu wiring that electrically connects the first semiconductor unit 10 and the second semiconductor unit 20 has been described, but the present disclosure is limited to this. Alternatively, a plurality of Cu wiring junctions 34 may be provided.
　第１ビア３４ａは、第２層間膜３２、ストッパー膜３１、第１層間膜３０及び光電変換層１１を貫通する縦孔配線であり、Ｃｕで形成される。第１ビア３４ａの一方の端部（第１多層配線層１２側の端部）は、第１多層配線層１２の最も光電変換層１１側に位置するＣｕ配線層１４のＣｕ配線部１６に接続される。また、第１ビア３４ａの他方の端部（第１多層配線層１２側とは反対側の端部）は、ビア接合部３４ｃに接続される。 The first via 34a is a vertical hole wiring that penetrates the second interlayer film 32, the stopper film 31, the first interlayer film 30, and the photoelectric conversion layer 11, and is formed of Cu. One end of the first via 34a (the end on the first multilayer wiring layer 12 side) is connected to the Cu wiring part 16 of the Cu wiring layer 14 located closest to the photoelectric conversion layer 11 of the first multilayer wiring layer 12. Is done. The other end of the first via 34a (the end opposite to the first multilayer wiring layer 12 side) is connected to the via junction 34c.
　第２ビア３４ｂは、第２層間膜３２、ストッパー膜３１、第１層間膜３０、光電変換層１１及び第１多層配線層１２（すなわち、第１半導体部１０）を貫通する縦孔配線であり、Ｃｕで形成される。第２ビア３４ｂの一方の端部（第２多層配線層２２側の端部）は、第２多層配線層２２の最も第１半導体部１０側に位置するＣｕ配線層２４のＣｕ配線部２６に接続される。また、第２ビア３４ｂの他方の端部（第２多層配線層２２側とは反対側の端部）は、ビア接合部３４ｃに接続される。 The second via 34 b is a vertical hole wiring that penetrates the second interlayer film 32, the stopper film 31, the first interlayer film 30, the photoelectric conversion layer 11, and the first multilayer wiring layer 12 (that is, the first semiconductor unit 10). , Cu. One end portion (the end portion on the second multilayer wiring layer 22 side) of the second via 34 b is connected to the Cu wiring portion 26 of the Cu wiring layer 24 located closest to the first semiconductor portion 10 side of the second multilayer wiring layer 22. Connected. The other end of the second via 34b (the end opposite to the second multilayer wiring layer 22 side) is connected to the via junction 34c.
　ビア接合部３４ｃは、第１ビア３４ａ及び第２ビア３４ｂを接合する配線部であり、Ｃｕで形成される。本実施形態の固体撮像装置１００では、このビア接合部３４ｃにより、第１半導体部１０と第２半導体部２０とが電気的に接続される。なお、ビア接合部３４ｃは、第２層間膜３２の表面に埋め込むようにして形成される。 The via junction 34c is a wiring portion that joins the first via 34a and the second via 34b, and is formed of Cu. In the solid-state imaging device 100 of the present embodiment, the first semiconductor unit 10 and the second semiconductor unit 20 are electrically connected by the via junction 34c. The via junction 34 c is formed so as to be embedded in the surface of the second interlayer film 32.
［比較例］
　ここで、本実施形態の固体撮像装置１００の製造方法について説明する前に、ストッパー膜３１を設けずに固体撮像装置を作製した場合（比較例）に発生し得る不具合について説明する。 [Comparative example]
Here, before describing the manufacturing method of the solid-state imaging device 100 of the present embodiment, a problem that may occur when the solid-state imaging device is manufactured without providing the stopper film 31 (comparative example) will be described.
　本実施形態のように、第１半導体部１０と第２半導体部２０とを貼り合わせて固体撮像装置１００を作製する場合、両者を貼り合わせた後に両者を電気的に接続する配線部（Ｃｕ配線接合部３４）を形成する。この際、第１半導体部１０及び第２半導体部２０間の導通を得るための配線部は、上述のように、低抵抗特性を有するＣｕ配線で構成される。なお、Ｃｕ配線は、一般に、ドライエッチングで加工することが難しいので、メッキプロセスとＣＭＰ（Chemical Mechanical Polishing）プロセスとを組み合わせたダマシンプロセスにより形成される。 When the solid-state imaging device 100 is manufactured by bonding the first semiconductor unit 10 and the second semiconductor unit 20 as in the present embodiment, a wiring unit (Cu wiring) that electrically connects the two after bonding the two. A junction 34) is formed. At this time, the wiring part for obtaining conduction between the first semiconductor part 10 and the second semiconductor part 20 is composed of Cu wiring having low resistance characteristics as described above. Since Cu wiring is generally difficult to process by dry etching, it is formed by a damascene process that combines a plating process and a CMP (Chemical-Mechanical-Polishing) process.
　しかしながら、上記製造手法では、第１半導体部と第２半導体部との貼り合わせに起因して第１半導体部の表面に欠陥（凹箇所）やピンホールが発生しているので、Ｃｕ配線接合部の形成時には、そのような欠陥やピンホールにもＣｕ膜が形成される。このような欠陥やピンホールに残存したＣｕ部（Ｃｕ残）は、その後の工程でメタル汚染を引き起こす可能性がある。この場合、製品チップの歩留まりが低下し、最悪の場合には、生産ラインにＣｕ汚染が発生する可能性もある。 However, in the manufacturing method described above, defects (concave portions) and pinholes are generated on the surface of the first semiconductor part due to the bonding between the first semiconductor part and the second semiconductor part. At the time of forming, a Cu film is also formed on such defects and pinholes. Such a defect or a Cu portion remaining in the pinhole (Cu residue) may cause metal contamination in a subsequent process. In this case, the yield of product chips is lowered, and in the worst case, Cu contamination may occur in the production line.
　以下に、この不具合の例を、図２～７を参照しながら説明する。なお、図２～７は、第１半導体部及び第２半導体部の貼り合わせ部材に対して各種処理工程を実施した後の貼り合わせ部材の概略断面図である。なお、図２～７に示す各種貼り合わせ部材において、図１に示す第１の実施形態の固体撮像装置１００の構成と同様の構成には、同じ符号を付して示す。また、図２～７では、説明を簡略化するため、層間膜と第１半導体部との界面付近の構成のみを示す。 Below, an example of this defect will be described with reference to FIGS. 2 to 7 are schematic cross-sectional views of the bonding member after various processing steps are performed on the bonding members of the first semiconductor portion and the second semiconductor portion. In the various bonding members shown in FIGS. 2 to 7, the same components as those of the solid-state imaging device 100 of the first embodiment shown in FIG. 2 to 7 show only the configuration in the vicinity of the interface between the interlayer film and the first semiconductor portion for the sake of simplicity.
（１）不具合例１
　不具合例１では、層間膜上に遮光膜を形成する際に発生し得る不具合を、図２～５を参照しながら説明する。 (1) Failure example 1
In defect example 1, a problem that may occur when a light shielding film is formed on an interlayer film will be described with reference to FIGS.
　比較例では、まず、第１半導体部と第２半導体部とを貼り合わせた後、第１半導体部のＳｉ基板１３の表面全面に渡って層間膜２００を形成する。次いで、層間膜２００、並びに、第１半導体部及び第２半導体部材の貼り合わせ部材の所定領域に、Ｃｕ配線接合部３４をダマシンプロセスにより形成する。その後、層間膜２００及びＣｕ配線接合部３４上に、Ｃｕ拡散防止膜３３を形成する（図２の状態）。 In the comparative example, first, the first semiconductor portion and the second semiconductor portion are bonded together, and then the interlayer film 200 is formed over the entire surface of the Si substrate 13 of the first semiconductor portion. Next, a Cu wiring junction 34 is formed by a damascene process in a predetermined region of the interlayer film 200 and the bonding member of the first semiconductor part and the second semiconductor member. Thereafter, a Cu diffusion preventing film 33 is formed on the interlayer film 200 and the Cu wiring bonding portion 34 (state shown in FIG. 2).
　なお、上記製造過程において、Ｃｕ配線接合部３４の形成時には、貼り合わせ部材の第１半導体部側の表面に発生した欠陥（凹箇所）やピンホールにもＣｕ残２１０が形成される。すなわち、Ｃｕ配線接合部３４の形成領域以外の領域に、Ｃｕ残２１０が散在した状態となる。また、層間膜２００の表面からＳｉ基板１３の所定深さまで達するような欠陥等が存在する場合には、Ｃｕ残２１０は、図２に示すように、層間膜２００を貫通し、かつ、Ｓｉ基板１３の所定深さまで延在して形成される。 In the above manufacturing process, when the Cu wiring bonding portion 34 is formed, the Cu residue 210 is also formed on the defects (concave portions) and pinholes generated on the surface of the bonded member on the first semiconductor portion side. That is, the Cu residue 210 is scattered in a region other than the region where the Cu wiring bonding portion 34 is formed. In addition, when there is a defect or the like that reaches the predetermined depth of the Si substrate 13 from the surface of the interlayer film 200, the Cu residue 210 penetrates the interlayer film 200 as shown in FIG. 13 extending to a predetermined depth.
　次いで、画素部（不図示）の領域に形成されたＣｕ拡散防止膜３３、及び、層間膜２００の一部をドライエッチングで除去する（図３の状態）。この工程を実施する理由は次の通りである。Ｃｕ拡散防止膜３３を例えばＳｉＮ膜やＳｉＣＮ膜などで構成した場合、これらの絶縁膜が画素部の光入射側に存在すると、感度劣化等の画素特性の劣化が発生し易い。また、フォトダイオード及びレンズ間の距離は、できる限り短い方が好ましい。これらのことから、上述のように、画素部の領域（Ｃｕ配線接合部３４の形成領域を含む所定領域（凸部）以外の領域）に対して彫り込みプロセス（キャビティエッチングプロセス）を行う。 Next, the Cu diffusion prevention film 33 and a part of the interlayer film 200 formed in the region of the pixel portion (not shown) are removed by dry etching (state shown in FIG. 3). The reason for carrying out this step is as follows. When the Cu diffusion preventing film 33 is composed of, for example, a SiN film or a SiCN film, if these insulating films are present on the light incident side of the pixel portion, pixel characteristics such as sensitivity deterioration are likely to occur. The distance between the photodiode and the lens is preferably as short as possible. For these reasons, as described above, the engraving process (cavity etching process) is performed on the region of the pixel portion (the region other than the predetermined region (projection) including the formation region of the Cu wiring joint 34).
　なお、このキャビティエッチングプロセスでは、図３に示すように、Ｓｉ基板１３上に、所定の厚さの層間膜２００が残るように画素部の領域を彫り込む。この結果、層間膜２００の画素部以外の領域、例えば、Ｃｕ配線接合部３４の形成領域には凸部が形成され、Ｃｕ配線接合部３４の領域と画素部の領域との境界には段差が画成される。また、このキャビティエッチングプロセスにより、図３に示すように、貼り合わせ部材の層間膜２００側の表面には、Ｃｕ残２１０が露出した状態となる。 In this cavity etching process, as shown in FIG. 3, the region of the pixel portion is engraved so that the interlayer film 200 with a predetermined thickness remains on the Si substrate 13. As a result, a convex portion is formed in a region other than the pixel portion of the interlayer film 200, for example, a formation region of the Cu wiring junction 34, and a step is formed at the boundary between the region of the Cu wiring junction 34 and the region of the pixel portion. Defined. Further, by this cavity etching process, as shown in FIG. 3, the Cu residue 210 is exposed on the surface of the bonded member on the side of the interlayer film 200.
　次いで、表面にＣｕ残２１０が露出した状態の層間膜２００において、遮光膜の形成領域の一部に、遮光膜の接地するための孔（遮光膜用接地孔２２０）をドライエッチングで形成する（図４の状態）。なお、この際、層間膜２００からＳｉ基板１３の所定深さまでドライエッチングで彫り込み、遮光膜用接地孔２２０を形成する。 Next, in the interlayer film 200 with the Cu residue 210 exposed on the surface, a hole for grounding the light shielding film (light shielding film grounding hole 220) is formed by dry etching in a part of the formation region of the light shielding film ( The state of FIG. At this time, the light shielding film grounding hole 220 is formed by carving from the interlayer film 200 to a predetermined depth of the Si substrate 13 by dry etching.
　しかしながら、この遮光膜用接地孔２２０の形成処理（ドライエッチング）により、Ｃｕ残の一部がＳｉ基板１３に飛散し（図３中の破線矢印）、Ｓｉ基板１３にＣｕ汚染（Ｃｕコンタミ）が発生する。この場合、画素特性が劣化する可能性がある。また、このようなＣｕ飛散が発生する場合、プロセス装置自体がＣｕで汚染される可能性もある。 However, due to the formation process (dry etching) of the light-shielding film grounding hole 220, a part of the remaining Cu is scattered on the Si substrate 13 (broken line arrow in FIG. 3), and Cu contamination (Cu contamination) occurs on the Si substrate 13. appear. In this case, the pixel characteristics may be deteriorated. Further, when such Cu scattering occurs, the process apparatus itself may be contaminated with Cu.
　また、遮光膜用接地孔２２０の形成領域に遮光膜２２１を形成した場合（図５の状態）、次のような不具合も生じる。図５に示すように、遮光膜２２１の一部がＣｕ残２１０上に形成された場合、該Ｃｕ残２１０の一部（Ｃｕ）が遮光膜２２１に拡散して、遮光膜２２１の形成材料と反応する。この場合、その後に行う遮光膜２２１のエッチング工程で、遮光膜２２１を所望のパターンに加工することが困難になる。 Further, when the light shielding film 221 is formed in the formation region of the light shielding film grounding hole 220 (the state shown in FIG. 5), the following problems occur. As shown in FIG. 5, when a part of the light shielding film 221 is formed on the Cu residue 210, a part (Cu) of the Cu residue 210 is diffused into the light shielding film 221, react. In this case, it becomes difficult to process the light shielding film 221 into a desired pattern in the subsequent etching process of the light shielding film 221.
（２）不具合例２
　上述したＣｕ残２１０の飛散によるＣｕ汚染、及び、遮光膜２２１の加工不良の不具合を解消するためには、Ｃｕ残２１０の発生を抑制することが求められる。しかしながら、実際には、ランダムにかつ突発的に発生するＣｕ残２１０を制御（抑制）することは困難である。そこで、上記不具合を解消する別の手法として、図３の工程（キャビティエッチングプロセス）後に、Ｃｕ残２１０を所定の薬液で除去するプロセスを設ける手法が考えられる。しかしながら、この手法においても次のような不具合（不具合例２）が発生する。 (2) Failure example 2
In order to eliminate the above-described Cu contamination due to the scattering of the Cu residue 210 and the defect of the processing failure of the light shielding film 221, it is required to suppress the occurrence of the Cu residue 210. However, in practice, it is difficult to control (suppress) the Cu residue 210 that occurs randomly and unexpectedly. Therefore, as another method for solving the above problem, a method of providing a process of removing the Cu residue 210 with a predetermined chemical after the step (cavity etching process) in FIG. 3 is conceivable. However, even with this method, the following problem (defect example 2) occurs.
　図６に、画素部（不図示）に対してキャビティエッチングプロセスを行った後の貼り合わせ部材の概略断面図を示す。なお、図６には、層間膜２００の表面からＳｉ基板１３の所定深さまで延在して形成されたＣｕ残２１０だけでなく、層間膜２００の欠陥（凹部）に残存したＣｕ残２１１も示す。 FIG. 6 shows a schematic cross-sectional view of the bonded member after the cavity etching process is performed on the pixel portion (not shown). 6 shows not only the Cu residue 210 formed to extend from the surface of the interlayer film 200 to a predetermined depth of the Si substrate 13, but also the Cu residue 211 remaining in the defect (concave portion) of the interlayer film 200. .
　図６に示すように、Ｃｕ残２１０，２１１を表面に露出した後、その露出面に対して、例えば、フッ酸／過酸化水素（ＦＰＭ）溶液や硫酸／過酸化水素溶液などの薬液を用いたウェットエッチング処理を行い、Ｃｕ残２１０，２１１を除去する（図７の状態）。 As shown in FIG. 6, after the Cu residues 210 and 211 are exposed on the surface, a chemical such as a hydrofluoric acid / hydrogen peroxide (FPM) solution or a sulfuric acid / hydrogen peroxide solution is used on the exposed surface. The remaining wet etching process is performed to remove Cu residues 210 and 211 (state shown in FIG. 7).
　しかしながら、このウェットエッチング処理の際、層間膜２００中の微小欠陥（ピンホールなど）にも薬液が浸透し、該薬液がＳｉ基板１３に到達した場合には、Ｓｉ基板１３もエッチングされる。この場合、図７に示すように、層間膜２００の一部に、Ｓｉ基板１３の所定深さまで貫通した微小孔２１２が形成される。この場合、薬液を介して、ＣｕがＳｉ基板１３に拡散し、Ｓｉ基板１３がＣｕ汚染される。さらに、この際、薬液の浸透により、層間膜２００が変質する可能性もある。 However, when this wet etching process is performed, the chemical solution penetrates into minute defects (pinholes and the like) in the interlayer film 200, and when the chemical solution reaches the Si substrate 13, the Si substrate 13 is also etched. In this case, as shown in FIG. 7, a minute hole 212 penetrating to a predetermined depth of the Si substrate 13 is formed in a part of the interlayer film 200. In this case, Cu diffuses into the Si substrate 13 via the chemical solution, and the Si substrate 13 is contaminated with Cu. Furthermore, at this time, the interlayer film 200 may be altered by the penetration of the chemical solution.
　すなわち、ウェットエッチング処理により、Ｃｕ残２１０，２１１を除去した場合には、正常チップの領域（Ｃｕ残２１０，２１１が形成されていない画素部の領域）にもダメージが発生し、該正常チップの特性を劣化させる可能性がある。 That is, when the Cu residues 210 and 211 are removed by the wet etching process, the normal chip region (the pixel portion region where the Cu residues 210 and 211 are not formed) is also damaged, and the normal chip is damaged. There is a possibility of deteriorating characteristics.
［固体撮像装置の製造手法］
　上述のように、ストッパー膜３１を設けずに固体撮像装置を作製した場合（比較例の場合）には、Ｃｕ残の影響により様々な不具合が発生する。そこで、本実施形態の固体撮像装置１００の製造方法では、その製造過程の途中で、Ｃｕ残のＳｉ基板１３への拡散を防止するためのストッパー膜３１を設け、これにより、上述したＣｕ残の影響（Ｃｕ汚染）を抑制する。 [Manufacturing method of solid-state imaging device]
As described above, when a solid-state imaging device is manufactured without providing the stopper film 31 (in the case of a comparative example), various problems occur due to the influence of Cu residue. Therefore, in the method of manufacturing the solid-state imaging device 100 according to the present embodiment, the stopper film 31 for preventing the diffusion of Cu residue into the Si substrate 13 is provided in the course of the manufacturing process. The influence (Cu contamination) is suppressed.
　ここで、本実施形態の固体撮像装置１００の製造方法を、図８～１９を参照しながら説明する。なお、図８～１９は、貼り合わせ部材１に対するＳｉ基板１３の研磨工程から遮光膜の形成工程までの各種工程の手順を示す図であり、各図は、各種工程後の貼り合わせ部材１の概略断面図である。また、図８～１９では、説明を簡略化するため、Ｓｉ基板１３（第１半導体部１０）の各種膜が形成される表面付近の構成のみを示す。 Here, a manufacturing method of the solid-state imaging device 100 of the present embodiment will be described with reference to FIGS. 8 to 19 are diagrams showing procedures of various processes from the polishing process of the Si substrate 13 to the bonding member 1 to the light shielding film forming process. Each figure shows the bonding member 1 after the various processes. It is a schematic sectional drawing. 8 to 19 show only the configuration in the vicinity of the surface on which various films of the Si substrate 13 (first semiconductor portion 10) are formed in order to simplify the description.
　さらに、図８～１９のうち、図１３～１７には、本実施形態の固体撮像装置１００の製造方法の特徴及び効果の理解を容易するために、欠陥（凹箇所）やピンホールにＣｕ残２１０が形成されている領域の貼り合わせ部材１の概略断面図を示す。その他の図面では、欠陥（凹箇所）やピンホールが発生していない領域の貼り合わせ部材１の概略断面図を示す。 Further, among FIGS. 8 to 19, FIGS. 13 to 17 show Cu remaining in defects (concave portions) and pinholes in order to facilitate understanding of the characteristics and effects of the manufacturing method of the solid-state imaging device 100 of the present embodiment. The schematic sectional drawing of the bonding member 1 of the area | region in which 210 is formed is shown. In other drawings, a schematic cross-sectional view of the bonding member 1 in a region where no defect (concave portion) or pinhole is generated is shown.
　まず、図示しないが、従来の裏面照射型の固体撮像装置の製造方法と同様にして、第１半導体部１０及び第２半導体部２０をそれぞれ作製し、さらに、両者を貼り合わせて、貼り合せ部材１を作製する。 First, although not shown, the first semiconductor unit 10 and the second semiconductor unit 20 are respectively produced in the same manner as in the conventional method of manufacturing a backside illumination type solid-state imaging device, and further, the two are bonded together to form a bonding member. 1 is produced.
　次いで、貼り合わせ部材１のＳｉ基板１３（第１半導体部１０）側の表面を研削及び研磨して、Ｓｉ基板１３の厚さを所定の厚さまで薄くする（図８の状態）。 Next, the surface of the bonding member 1 on the Si substrate 13 (first semiconductor portion 10) side is ground and polished to reduce the thickness of the Si substrate 13 to a predetermined thickness (state shown in FIG. 8).
　次いで、Ｓｉ基板１３の研磨した面全体に渡って、例えばＣＶＤ（Chemical Vapor Deposition）法等の手法を用いて、第１層間膜３０（例えばＳｉＯ２膜等）を形成する（図９の状態）。 Next, a first interlayer film 30 (for example, a SiO 2 film) is formed over the entire polished surface of the Si substrate 13 by using, for example, a CVD (Chemical Vapor Deposition) method (state of FIG. 9). .
　次いで、第１層間膜３０上に、例えばＲＦ（Radio Frequency）スパッタリング法等の手法を用いて、ストッパー膜３１を形成する（図１０の状態）。 Next, the stopper film 31 is formed on the first interlayer film 30 by using a technique such as RF (Radio Frequency) sputtering method (state of FIG. 10).
　なお、この際、後述のＣｕ残の除去時に用いるウェットエッチングの薬液（酸性薬液）に対して、Ｃｕよりエッチング耐性の高い（エッチングレートの低い）膜、例えば、ＳｉＮ膜、ＳｉＣＮ膜、ＳｉＣ膜、ＳｉＣＯ膜等でストッパー膜３１を構成する。 At this time, a film having higher etching resistance (lower etching rate) than Cu, for example, a SiN film, a SiCN film, a SiC film, with respect to a wet etching chemical (acid chemical) used when removing Cu residue described below, The stopper film 31 is composed of a SiCO film or the like.
また、この際、ストッパー膜３１の膜厚は、例えば３０ｎｍ以上に設定することができる。ただし、ストッパー膜３１の膜厚は、これに限定されず、例えば使用する薬液の選択比（Ｃｕ膜とストッパー膜３１とのエッチングレート比）に応じて適宜設定される。例えば、ウェットエッチングの薬液としてフッ酸／過酸化水素溶液を含む酸性薬液を用い、ストッパー膜３１として、ＳｉＣＮ膜を用いた場合には、Ｃｕ膜とストッパー膜３１とのエッチングレート比は１０倍以上となる。それゆえ、この場合には、このエッチングレート比を考慮して、Ｃｕ残２１０，２１１が完全に除去されても、十分な厚さのストッパー膜３１が残るように、ストッパー膜３１の膜厚を設定する。 At this time, the film thickness of the stopper film 31 can be set to 30 nm or more, for example. However, the thickness of the stopper film 31 is not limited to this, and is appropriately set according to, for example, the selection ratio of the chemical solution to be used (the etching rate ratio between the Cu film and the stopper film 31). For example, when an acidic chemical solution containing a hydrofluoric acid / hydrogen peroxide solution is used as a chemical solution for wet etching and a SiCN film is used as the stopper film 31, the etching rate ratio between the Cu film and the stopper film 31 is 10 times or more. It becomes. Therefore, in this case, considering the etching rate ratio, the film thickness of the stopper film 31 is set so that a sufficient thickness of the stopper film 31 remains even if the Cu residues 210 and 211 are completely removed. Set.
　次いで、ストッパー膜３１上に、例えばＣＶＤ法等の手法を用いて、第２層間膜３２（例えばＳｉＯ２膜等）を形成する（図１１の状態）。 Next, a second interlayer film 32 (for example, a SiO 2 film) is formed on the stopper film 31 using a technique such as a CVD method (state of FIG. 11).
　次いで、例えばドライエッチング等の手法を用いて、貼り合わせ部材１の第２層間膜３２側の表面におけるＣｕ配線接合部３４（後述の図１３参照）の形成領域に縦孔４０を形成する（図１２の状態）。 Next, a vertical hole 40 is formed in the formation region of the Cu wiring bonding portion 34 (see FIG. 13 described later) on the surface of the bonding member 1 on the second interlayer film 32 side using a technique such as dry etching (see FIG. 13). 12 states).
　具体的には、第１ビア３４ａの形成領域には、第２層間膜３２から第１多層配線層１２の最も光電変換層１１側に位置するＣｕ配線層１４のＣｕ配線部１６まで延在する縦孔を形成し、該縦孔の開口部にＣｕ配線部１６を露出させる。また、第２ビア３４ｂの形成領域には、第２層間膜３２から第２多層配線層２２の最も第１半導体部１０側に位置するＣｕ配線層２４のＣｕ配線部２６まで延在する縦孔を形成し、該縦孔の開口部にＣｕ配線部２６を露出させる。さらに、ビア接合部３４ｃの形成領域に対応する第２層間膜３２の領域も、例えばドライエッチング法等の手法を用いて彫り込む。 Specifically, the first via 34 a extends from the second interlayer film 32 to the Cu wiring portion 16 of the Cu wiring layer 14 positioned closest to the photoelectric conversion layer 11 of the first multilayer wiring layer 12. A vertical hole is formed, and the Cu wiring portion 16 is exposed at the opening of the vertical hole. Further, in the formation region of the second via 34 b, a vertical hole extending from the second interlayer film 32 to the Cu wiring part 26 of the Cu wiring layer 24 positioned closest to the first semiconductor part 10 of the second multilayer wiring layer 22. And the Cu wiring part 26 is exposed at the opening of the vertical hole. Furthermore, the region of the second interlayer film 32 corresponding to the formation region of the via junction 34c is also engraved using a technique such as a dry etching method.
　次いで、図示しないが、Ｃｕ配線接合部３４とＳｉ基板１３との間の絶縁性を確保するため、縦孔４０を画成する側壁面に、例えばＳｉＯ２膜からなる絶縁膜を形成する。次いで、第２層間膜３２上に、例えば電解メッキ法等の手法を用いて、Ｃｕ膜を形成する。この処理により、縦孔４０にＣｕ膜が埋め込まれる。その後、Ｃｕ膜の不要な部分を化学機械研磨（ＣＭＰ）法により除去する。具体的には、第２層間膜３２が表面に露出するまで、Ｃｕ膜の表面をＣＭＰ法で研磨する。 Next, although not shown, an insulating film made of, for example, a SiO 2 film is formed on the side wall surface defining the vertical hole 40 in order to ensure insulation between the Cu wiring bonding portion 34 and the Si substrate 13. Next, a Cu film is formed on the second interlayer film 32 by using a technique such as an electrolytic plating method. By this process, the Cu film is embedded in the vertical hole 40. Thereafter, unnecessary portions of the Cu film are removed by a chemical mechanical polishing (CMP) method. Specifically, the surface of the Cu film is polished by CMP until the second interlayer film 32 is exposed on the surface.
　なお、この際、貼り合わせ部材１の第１半導体部１０側の表面に発生したピンホールや欠陥（凹箇所）にも、Ｃｕ残２１０，２１１が形成される（図１３の状態）。 At this time, Cu residues 210 and 211 are also formed in pinholes and defects (concave portions) generated on the surface of the bonding member 1 on the first semiconductor portion 10 side (state of FIG. 13).
　次いで、第２層間膜３２及びＣｕ配線接合部３４上に、例えばＲＦスパッタリング法等の手法を用いて、Ｃｕ拡散防止膜３３（例えばＳｉＮ膜等）を形成する（図１４の状態）。なお、本実施形態では、Ｃｕ拡散防止膜３３上に、さらに、保護膜として例えばＳｉＯ２膜等の絶縁膜を形成してもよい。 Next, a Cu diffusion prevention film 33 (for example, a SiN film) is formed on the second interlayer film 32 and the Cu wiring bonding portion 34 by using a technique such as an RF sputtering method (state of FIG. 14). In the present embodiment, an insulating film such as a SiO 2 film may be further formed on the Cu diffusion preventing film 33 as a protective film.
　次いで、Ｃｕ拡散防止膜３３の画素部に対応する領域に対してドライエッチング処理を行い、その領域のＣｕ拡散防止膜３３、及び、第２層間膜３２の一部を除去する（第１のキャビティエッチングプロセス）。ただし、この第１のキャビティエッチングプロセスは、エッチング面にＣｕ残２１０，２１１が露出するまで行う（図１５の状態）。 Next, dry etching is performed on the region of the Cu diffusion prevention film 33 corresponding to the pixel portion, and the Cu diffusion prevention film 33 and a part of the second interlayer film 32 in the region are removed (first cavity). Etching process). However, this first cavity etching process is performed until the Cu residues 210 and 211 are exposed on the etched surface (state of FIG. 15).
　次いで、Ｃｕ残２１０，２１１が表面に露出した貼り合わせ部材１に対して、例えば、フッ酸／過酸化水素溶液や硫酸／過酸化水素溶液などの酸化剤を含む酸性薬液を用いて、ウェットエッチング処理を行い、Ｃｕ残２１０，２１１を除去する（図１６の状態）。 Next, wet etching is performed on the bonding member 1 on which the Cu residues 210 and 211 are exposed on the surface using, for example, an acidic chemical solution containing an oxidizing agent such as a hydrofluoric acid / hydrogen peroxide solution or a sulfuric acid / hydrogen peroxide solution. Processing is performed to remove Cu residues 210 and 211 (state shown in FIG. 16).
　なお、この際、第２層間膜３２中の微小欠陥（ピンホールなど）にも薬液が浸透するので、図１６に示すように、第２層間膜３２の正常チップの領域（Ｃｕ残２１０，２１１が存在しない画素領域）にも微小孔４１が発生し、ダメージが生じる。しかしながら、本実施形態では、第１層間膜３０及び第２層間膜３２間に、薬液に対してエッチング耐性の高いストッパー膜３１を設けているので、この微小孔４１はＳｉ基板１３（第１層間膜３０）に到達しない。それゆえ、本実施形態では、Ｃｕ残２１０，２１１の上記除去処理において、正常チップの領域のＳｉ基板１３にＣｕ残２１０，２１１の一部が拡散せず、Ｃｕ汚染が発生しない。 At this time, since the chemical solution also penetrates into minute defects (pinholes and the like) in the second interlayer film 32, as shown in FIG. 16, the normal chip region ( Cu residues 210 and 211 in the second interlayer film 32). A microhole 41 is also generated in a pixel area where no symbol exists and damage occurs. However, in this embodiment, since the stopper film 31 having high etching resistance against the chemical solution is provided between the first interlayer film 30 and the second interlayer film 32, the microhole 41 is formed in the Si substrate 13 (first interlayer film). It does not reach the membrane 30). Therefore, in this embodiment, in the above removal processing of the Cu residues 210 and 211, a part of the Cu residues 210 and 211 does not diffuse into the Si substrate 13 in the normal chip region, and Cu contamination does not occur.
　そして、Ｃｕ残２１０，２１１を除去した後、貼り合わせ部材１の第１半導体部１０側の画素部に対応する領域に対して（Ｃｕ配線接合部３４の形成領域以外の領域）、再度、ドライエッチングを行う（第２のキャビティエッチングプロセス）。本実施形態では、この第２のキャビティエッチングプロセスにより、画素部の領域における第２層間膜３２、ストッパー膜３１、及び、第１層間膜３０の一部を除去する（図１７の状態）。 Then, after removing the Cu residues 210 and 211, dry again with respect to the region corresponding to the pixel portion on the first semiconductor portion 10 side of the bonding member 1 (region other than the formation region of the Cu wiring junction 34). Etching is performed (second cavity etching process). In the present embodiment, a part of the second interlayer film 32, the stopper film 31, and the first interlayer film 30 in the region of the pixel portion is removed by this second cavity etching process (state of FIG. 17).
　この第２のキャビティエッチングプロセスにより、画素部の領域において、画素特性劣化の原因となり得るストッパー膜３１を除去する。なお、第２のキャビティエッチングプロセスでは、図１７に示すように、Ｓｉ基板１３の画素部に対応する領域上には、所定の厚さの第１層間膜３０が残るように該領域を彫り込む。 By the second cavity etching process, the stopper film 31 that may cause deterioration of the pixel characteristics is removed in the pixel portion region. In the second cavity etching process, as shown in FIG. 17, the region is engraved so that the first interlayer film 30 having a predetermined thickness remains on the region corresponding to the pixel portion of the Si substrate 13. .
　本実施形態では、上述のように、貼り合わせ部材１の第１半導体部１０側の画素部に対応する領域をドライエッチングにより２段階で彫り込むので、Ｃｕ配線接合部３４の形成領域を含む凸部と画素部の領域との境界には２つの段差が画成される。 In the present embodiment, as described above, since the region corresponding to the pixel portion on the first semiconductor portion 10 side of the bonding member 1 is engraved in two stages by dry etching, the protrusion including the formation region of the Cu wiring junction 34 is formed. Two steps are defined at the boundary between the pixel portion and the pixel portion region.
　その後、従来の製法と同様にして、第１層間膜３０上に遮光膜を形成する。具体的には、まず、図１８に示すように、第１層間膜３０の遮光膜の形成領域の一部に、遮光膜用接地孔４２をドライエッチングで形成する。なお、この際、第１層間膜３０の表面からＳｉ基板１３の所定深さまでドライエッチングで彫り込み、遮光膜用接地孔４２を形成する。また、本実施形態では、この遮光膜用接地孔４２の形成処理の前にＣｕ残２１０，２１１を除去しているので、上記比較例の作製手法と異なり、このエッチング処理において、Ｃｕ汚染は発生しない。 Thereafter, a light shielding film is formed on the first interlayer film 30 in the same manner as in the conventional manufacturing method. Specifically, first, as shown in FIG. 18, a light shielding film ground hole 42 is formed by dry etching in a part of the light shielding film formation region of the first interlayer film 30. At this time, dry etching is performed from the surface of the first interlayer film 30 to a predetermined depth of the Si substrate 13 to form a light shielding film grounding hole 42. Further, in this embodiment, the Cu residues 210 and 211 are removed before the formation process of the light shielding film grounding hole 42. Therefore, unlike the manufacturing method of the comparative example, Cu contamination occurs in the etching process. do not do.
　次いで、図１９に示すように、第１層間膜３０の遮光膜用接地孔４２が形成された領域上に、例えばＲＦスパッタリング法等の手法を用いて、Ｔａ系の金属膜を積層して、遮光膜４３を形成する。その後、図示しないが、従来の裏面照射型の固体撮像装置の製造方法と同様にして、画素部に、カラーフィルタ、オンチップマイクロレンズ等を形成する。本実施形態では、上述のようにして固体撮像装置１００を作製する。 Next, as shown in FIG. 19, a Ta-based metal film is laminated on the region of the first interlayer film 30 where the light shielding film ground hole 42 is formed, using a technique such as RF sputtering. A light shielding film 43 is formed. Thereafter, although not shown, a color filter, an on-chip microlens, and the like are formed in the pixel portion in the same manner as in the conventional method of manufacturing a backside illumination type solid-state imaging device. In the present embodiment, the solid-state imaging device 100 is manufactured as described above.
　上述のように、本実施形態の固体撮像装置１００の製造手法では、第１層間膜３０及び第２層間膜３２間に、薬液に対してエッチング耐性の高いストッパー膜３１を設けるので、Ｃｕ残の除去処理により発生するダメージがＳｉ基板１３まで到達しない。また、本実施形態では、遮光膜用接地孔４２の形成時にも、Ｃｕ汚染が発生しない。それゆえ、本実施形態の固体撮像装置１００の製造手法では、上記比較例で説明したＣｕ残による、チップ、ウエハ、プロセス装置のＣｕ汚染を防止することができ、正常チップをロス無く作製することができる。また、その正常チップを製品チップとし、該製品チップに対して、その後に続く各種プロセスを実施することができる。その結果、本実施形態の固体撮像装置１００の製造手法では、製品の歩留まりを向上させることができる。 As described above, in the manufacturing method of the solid-state imaging device 100 according to the present embodiment, the stopper film 31 having high etching resistance against the chemical solution is provided between the first interlayer film 30 and the second interlayer film 32. Damage caused by the removal process does not reach the Si substrate 13. In this embodiment, Cu contamination does not occur even when the light shielding film grounding hole 42 is formed. Therefore, in the manufacturing method of the solid-state imaging device 100 of the present embodiment, it is possible to prevent Cu contamination of the chip, wafer, and process apparatus due to the Cu residue described in the comparative example, and to produce a normal chip without loss. Can do. Further, the normal chip can be used as a product chip, and various subsequent processes can be performed on the product chip. As a result, in the manufacturing method of the solid-state imaging device 100 of the present embodiment, the product yield can be improved.
＜２．第２の実施形態＞
　上記第１の実施形態では、Ｃｕ残の除去処理の手法として、ウェットエッチング法を用いる例を説明したが、本開示はこれに限定されない。例えば、層間膜を溶解するような薬液を用いて、Ｃｕ残をリフトオフして除去してもよい。第２の実施形態では、その一例を説明する。 <2. Second Embodiment>
In the first embodiment, the example in which the wet etching method is used as the technique for removing the Cu residue has been described, but the present disclosure is not limited to this. For example, the Cu residue may be removed by lift-off using a chemical solution that dissolves the interlayer film. In the second embodiment, an example will be described.
　なお、本実施形態の固体撮像装置の製造方法において、Ｃｕ残の除去手法にリフトオフ法を用いたこと以外は、第１の実施形態と同様にして、固体撮像装置を作製することができる。また、本実施形態の固体撮像装置の構成も、上記第１の実施形態の固体撮像装置１００（図１）と同様に構成することができる。それゆえ、ここでは、Ｃｕ残の除去手法についてのみ詳細に説明する。 In addition, in the manufacturing method of the solid-state imaging device of the present embodiment, the solid-state imaging device can be manufactured in the same manner as in the first embodiment except that the lift-off method is used as the Cu removal method. The configuration of the solid-state imaging device of the present embodiment can also be configured in the same manner as the solid-state imaging device 100 (FIG. 1) of the first embodiment. Therefore, here, only the removal method of Cu residue will be described in detail.
　図２０～２２に、本実施形態におけるＣｕ残の除去工程の手順を示す。なお、図２０～２２は、各種工程後の貼り合わせ部材１の概略断面図であり、ここでは、説明を簡略化するため、第１層間膜３０と第１半導体部１０（Ｓｉ基板１３）との界面付近の構成のみを示す。また、図２０～２２に示す各種工程後の貼り合わせ部材１において、上記第１の実施形態の図１５～１７に示す各種工程後の貼り合わせ部材１の構成と同様の構成には、同じ符号を付して示す。 20 to 22 show the procedure of the Cu residue removal process in this embodiment. 20 to 22 are schematic cross-sectional views of the bonding member 1 after various processes. Here, in order to simplify the description, the first interlayer film 30, the first semiconductor unit 10 (Si substrate 13), Only the structure near the interface is shown. Further, in the bonding member 1 after various steps shown in FIGS. 20 to 22, the same reference numerals are given to the same configurations as those of the bonding member 1 after various steps shown in FIGS. 15 to 17 of the first embodiment. Is shown.
　本実施形態では、まず、上記第１の実施形態で説明した図８～１４の各種処理工程を順次実施する。なお、この処理過程では、Ｃｕ残をリフトオフ法で除去する際に用いる薬液に対して、第２層間膜３２より耐性の高い膜（例えば、ＳｉＮ膜、ＳｉＣＮ膜、ＳｉＣ膜、ＳｉＣＯ膜等）により、ストッパー膜３１を形成する。また、この際、ストッパー膜３１の膜厚は、上記第１の実施形態と同様に、例えば使用する薬液の選択比に応じて適宜設定される。 In this embodiment, first, the various processing steps shown in FIGS. 8 to 14 described in the first embodiment are sequentially performed. In this process, a film (for example, a SiN film, a SiCN film, a SiC film, a SiCO film, etc.) having higher resistance than the second interlayer film 32 with respect to a chemical solution used when removing Cu residue by the lift-off method is used. A stopper film 31 is formed. At this time, the film thickness of the stopper film 31 is appropriately set according to, for example, the selection ratio of the chemical solution to be used, as in the first embodiment.
　次いで、Ｃｕ拡散防止膜３３の画素部に対応する領域に対してドライエッチング処理を行い、その領域のＣｕ拡散防止膜３３及び第２層間膜３２の一部を除去する（第１のキャビティエッチングプロセス）。ただし、この第１のキャビティエッチングプロセスは、エッチング面にＣｕ残２１０，２１１が露出するまで行う（図２０の状態）。 Next, dry etching is performed on the region corresponding to the pixel portion of the Cu diffusion preventing film 33, and a part of the Cu diffusion preventing film 33 and the second interlayer film 32 in the region is removed (first cavity etching process). ). However, this first cavity etching process is performed until the Cu residues 210 and 211 are exposed on the etched surface (state of FIG. 20).
　次いで、例えば、フッ酸、バッファードフッ酸等の薬液を用いて、Ｃｕ残２１０，２１１を画成する第２層間膜３２、ストッパー膜３１、第１層間膜３０及びＳｉ基板１３の側壁部を溶かし、Ｃｕ残２１０，２１１をリフトオフして除去する（図２１の状態）。 Next, for example, using a chemical solution such as hydrofluoric acid or buffered hydrofluoric acid, the second interlayer film 32, the stopper film 31, the first interlayer film 30, and the side walls of the Si substrate 13 that define the Cu residues 210 and 211 are formed. The Cu residues 210 and 211 are lifted off and removed (state shown in FIG. 21).
　なお、この際、第２層間膜３２の表面も一部溶解するとともに（説明を簡略化するため不図示）、第２層間膜３２中の微小欠陥（ピンホールなど）にも薬液が浸透する。それゆえ、このリフトオフ処理工程では、図２１に示すように、第２層間膜３２の正常チップの領域に微小孔５０が形成され、ダメージが生じる。しかしながら、本実施形態においても、第１層間膜３０及び第２層間膜３２間に、Ｃｕ残除去に用いる薬液に対して耐性の高いストッパー膜３１を設けているので、この微小孔５０はＳｉ基板１３（第１層間膜３０）に到達しない。すなわち、本実施形態では、Ｃｕ残２１０，２１１の上記除去処理において、Ｓｉ基板１３にＣｕ残２１０，２１１の一部が拡散せず、Ｃｕ汚染が発生しない。 At this time, a part of the surface of the second interlayer film 32 is also dissolved (not shown for simplification of description), and the chemical solution penetrates into minute defects (such as pinholes) in the second interlayer film 32. Therefore, in this lift-off process, as shown in FIG. 21, the micro holes 50 are formed in the normal chip region of the second interlayer film 32, and damage occurs. However, also in this embodiment, since the stopper film 31 having a high resistance to the chemical used for removing the Cu residue is provided between the first interlayer film 30 and the second interlayer film 32, the micro holes 50 are formed on the Si substrate. 13 (first interlayer film 30) is not reached. That is, in this embodiment, in the above removal process of the Cu residues 210 and 211, a part of the Cu residues 210 and 211 does not diffuse into the Si substrate 13, and Cu contamination does not occur.
　次いで、Ｃｕ残２１０，２１１を除去した後、貼り合わせ部材１の第１半導体部１０側の画素部に対応する領域に対して（Ｃｕ配線接合部３４の形成領域以外の領域）、再度、ドライエッチングを行う（第２のキャビティエッチングプロセス）。本実施形態では、この第２のキャビティエッチングプロセスにより、画素部の領域における第２層間膜３２、ストッパー膜３１、及び、第１層間膜３０の一部を除去する（図２２の状態）。なお、この第２のキャビティエッチングプロセスでは、図２２に示すように、Ｓｉ基板１３の画素部に対応する領域上に所定厚さの第１層間膜３０が残るように該領域を彫り込む。 Next, after removing the Cu residues 210 and 211, dry again for the region corresponding to the pixel portion on the first semiconductor portion 10 side of the bonding member 1 (region other than the formation region of the Cu wiring junction 34). Etching is performed (second cavity etching process). In the present embodiment, by the second cavity etching process, the second interlayer film 32, the stopper film 31, and a part of the first interlayer film 30 in the region of the pixel portion are removed (state shown in FIG. 22). In the second cavity etching process, as shown in FIG. 22, the region is engraved so that the first interlayer film 30 having a predetermined thickness remains on the region corresponding to the pixel portion of the Si substrate 13.
　その後、上記第１の実施形態と同様にして、第１層間膜３０の所定領域上に遮光膜を形成し、さらに、画素部に、カラーフィルタ、オンチップマイクロレンズ等を形成する。本実施形態では、上述のようにして固体撮像装置を作製する。 Thereafter, similarly to the first embodiment, a light shielding film is formed on a predetermined region of the first interlayer film 30, and a color filter, an on-chip microlens, and the like are further formed on the pixel portion. In the present embodiment, the solid-state imaging device is manufactured as described above.
　本実施形態においても、上記第１の実施形態と同様に、第１層間膜３０及び第２層間膜３２間に、Ｃｕ残の除去処理に用いる薬液に対して耐性の高いストッパー膜３１を設ける。それゆえ、本実施形態においても、Ｃｕ残の除去処理により発生するダメージがＳｉ基板１３まで到達しないので、上記第１の実施形態と同様の効果が得られる。 Also in the present embodiment, a stopper film 31 having a high resistance to a chemical solution used for removing Cu residue is provided between the first interlayer film 30 and the second interlayer film 32 as in the first embodiment. Therefore, also in the present embodiment, the damage generated by the Cu residue removal process does not reach the Si substrate 13, and thus the same effect as in the first embodiment can be obtained.
＜３．応用例＞
　本開示に係る半導体装置（固体撮像装置）は、各種電子機器に適用可能である。例えば、上記第１及び第２の実施形態で説明した固体撮像装置は、デジタルスチルカメラやデジタルビデオカメラ等のカメラシステム、撮像機能を有する携帯電話、又は、撮像機能を備えた他の機器などの電子機器に適用することができる。ここでは、電子機器の一構成例として、カメラを例に挙げ説明する。 <3. Application example>
The semiconductor device (solid-state imaging device) according to the present disclosure can be applied to various electronic devices. For example, the solid-state imaging device described in the first and second embodiments includes a camera system such as a digital still camera and a digital video camera, a mobile phone having an imaging function, or other devices having an imaging function. It can be applied to electronic equipment. Here, a camera will be described as an example of a configuration of the electronic device.
　図２３に、応用例に係るカメラの概略構成を示す。なお、図２３には、静止画像又は動画を撮影することのできるデジタルビデオカメラの構成例を示す。 FIG. 23 shows a schematic configuration of a camera according to an application example. Note that FIG. 23 illustrates a configuration example of a digital video camera that can capture still images or moving images.
　この例のカメラ３００は、固体撮像装置３０１と、固体撮像装置３０１の受光センサ（不図示）に入射光を導く光学系３０２と、固体撮像装置３０１及び光学系３０２間に設けられたシャッタ装置３０３と、固体撮像装置３０１を駆動する駆動回路３０４とを備える。さらに、カメラ３００は、固体撮像装置３０１の出力信号を処理する信号処理回路３０５を備える。 The camera 300 in this example includes a solid-state imaging device 301, an optical system 302 that guides incident light to a light receiving sensor (not shown) of the solid-state imaging device 301, and a shutter device 303 provided between the solid-state imaging device 301 and the optical system 302. And a drive circuit 304 that drives the solid-state imaging device 301. Further, the camera 300 includes a signal processing circuit 305 that processes an output signal of the solid-state imaging device 301.
　固体撮像装置３０１は、例えば、上記第１及び第２の実施形態で説明した固体撮像装置で構成することができる。その他の各部の構成及び機能は次の通りである。 The solid-state imaging device 301 can be configured by, for example, the solid-state imaging device described in the first and second embodiments. Configurations and functions of other parts are as follows.
　光学系（光学レンズ）３０２は、被写体からの像光（入射光）を固体撮像装置３０１の撮像面（不図示）上に結像させる。これにより、固体撮像装置３０１内に、一定期間、信号電荷が蓄積される。なお、光学系３０２は、複数の光学レンズを含む光学レンズ群で構成してもよい。また、シャッタ装置３０３は、入射光の固体撮像装置３０１への光照射期間及び遮光期間を制御する。 The optical system (optical lens) 302 forms image light (incident light) from a subject on an imaging surface (not shown) of the solid-state imaging device 301. Thereby, signal charges are accumulated in the solid-state imaging device 301 for a certain period. The optical system 302 may be composed of an optical lens group including a plurality of optical lenses. The shutter device 303 controls the light irradiation period and the light shielding period of the incident light to the solid-state imaging device 301.
　駆動回路３０４は、固体撮像装置３０１及びシャッタ装置３０３に駆動信号を供給する。そして、駆動回路３０４は、供給した駆動信号により、固体撮像装置３０１の信号処理回路３０５への信号出力動作、及び、シャッタ装置３０３のシャッタ動作を制御する。すなわち、この例では、駆動回路３０４から供給される駆動信号（タイミング信号）により、固体撮像装置３０１から信号処理回路３０５への信号転送動作を行う。 The drive circuit 304 supplies drive signals to the solid-state imaging device 301 and the shutter device 303. The drive circuit 304 controls the signal output operation to the signal processing circuit 305 of the solid-state imaging device 301 and the shutter operation of the shutter device 303 by the supplied drive signal. That is, in this example, a signal transfer operation from the solid-state imaging device 301 to the signal processing circuit 305 is performed by a drive signal (timing signal) supplied from the drive circuit 304.
　信号処理回路３０５は、固体撮像装置３０１から転送された信号に対して、各種の信号処理を施す。そして、各種信号処理が施された信号（映像信号）は、メモリなどの記憶媒体（不図示）に記憶される、又は、モニタ（不図示）に出力される。 The signal processing circuit 305 performs various types of signal processing on the signal transferred from the solid-state imaging device 301. The signal (video signal) that has been subjected to various signal processing is stored in a storage medium (not shown) such as a memory, or is output to a monitor (not shown).
　なお、本開示は、以下のような構成を取ることもできる。
（１）
　　第１半導体部及び第２半導体部を含む半導体部材の一方の面上に絶縁膜を形成するステップと、
　前記絶縁膜上に、所定の薬液に耐性を有するストッパー膜を形成するステップと、
　前記半導体部材の前記ストッパー膜側の表面に縦孔を形成するステップと、
　前記縦孔に記第１半導体部及び前記第２半導体部を電気的に接続するＣｕ配線接合部を形成するステップと、
　前記半導体部材の前記Ｃｕ配線接合部側の表面にＣｕ拡散防止膜を形成するステップと、
　前記Ｃｕ配線接合部の形成領域を含む所定領域以外の領域の前記Ｃｕ拡散防止膜を除去して該領域の不要なＣｕ部を露出させるステップと、
　前記不要なＣｕ部を前記所定の薬液を用いて除去するステップと
　を含む半導体装置の製造方法。
（２）
　前記不要なＣｕ部を、ウェットエッチング法により除去する
　（１）に記載の半導体装置の製造方法。
（３）
　前記不要なＣｕ部を、リフトオフ法により除去する
　（１）に記載の半導体装置の製造方法。
（４）
　前記ストッパー膜が、ＳｉＮ膜、ＳｉＣＮ膜、ＳｉＣ膜及びＳｉＣＯ膜のいずれかである
　（１）～（３）のいずれか一項に記載の半導体装置の製造方法。
（５）
　さらに、前記不要なＣｕ部を除去するステップの後、前記所定領域以外の領域の前記ストッパー膜を除去するステップを含む
　（１）～（４）のいずれか一項に記載の半導体装置の製造方法。
（６）
　前記Ｃｕ配線接合部を、ダマシンプロセスにより形成する
　（１）～（５）のいずれか一項に記載の半導体装置の製造方法。
（７）
　第１半導体部および第２半導体部を含む半導体部材と、
　前記半導体部材の一方の面上の絶縁膜と、
　前記絶縁膜を貫通すると共に前記第１半導体部及び前記第２半導体部を電気的に接続するＣｕ配線接合部と、
　前記Ｃｕ配線接合部上のＣｕ拡散防止膜と、
　少なくとも前記Ｃｕ拡散防止膜と前記絶縁膜との間に設けられると共に、不要なＣｕ部を除去する所定の薬液に耐性を有するストッパー膜と
　を備える半導体装置。 In addition, this indication can also take the following structures.
(1)
Forming an insulating film on one surface of the semiconductor member including the first semiconductor portion and the second semiconductor portion;
Forming a stopper film resistant to a predetermined chemical solution on the insulating film;
Forming a vertical hole in the surface of the semiconductor member on the stopper film side;
Forming a Cu wiring junction for electrically connecting the first semiconductor portion and the second semiconductor portion in the vertical hole;
Forming a Cu diffusion prevention film on the surface of the semiconductor member on the Cu wiring joint side;
Removing the Cu diffusion prevention film in a region other than the predetermined region including the formation region of the Cu wiring bonding portion to expose an unnecessary Cu portion in the region;
Removing the unnecessary Cu portion by using the predetermined chemical solution.
(2)
The method for manufacturing a semiconductor device according to (1), wherein the unnecessary Cu portion is removed by a wet etching method.
(3)
The method for manufacturing a semiconductor device according to (1), wherein the unnecessary Cu portion is removed by a lift-off method.
(4)
The method for manufacturing a semiconductor device according to any one of (1) to (3), wherein the stopper film is any one of a SiN film, a SiCN film, a SiC film, and a SiCO film.
(5)
The method for manufacturing a semiconductor device according to any one of (1) to (4), further including a step of removing the stopper film in a region other than the predetermined region after the step of removing the unnecessary Cu portion. .
(6)
The method for manufacturing a semiconductor device according to any one of (1) to (5), wherein the Cu wiring junction is formed by a damascene process.
(7)
A semiconductor member including a first semiconductor portion and a second semiconductor portion;
An insulating film on one surface of the semiconductor member;
A Cu wiring junction that penetrates the insulating film and electrically connects the first semiconductor portion and the second semiconductor portion;
A Cu diffusion prevention film on the Cu wiring junction;
A semiconductor device comprising: a stopper film provided between at least the Cu diffusion preventing film and the insulating film and having resistance to a predetermined chemical solution for removing unnecessary Cu portions.
 本出願は、日本国特許庁において２０１１年１０月１２日に出願された日本特許出願番号２０１１－２２４８８５号を基礎として優先権を主張するものであり、この出願のすべての内容を参照によって本出願に援用する。
  This application claims priority on the basis of Japanese Patent Application No. 2011-224895 filed on October 12, 2011 at the Japan Patent Office. The entire contents of this application are hereby incorporated by reference. Incorporated into.

Claims (7)

  1. 　第１半導体部及び第２半導体部を含む半導体部材の一方の面上に絶縁膜を形成するステップと、
    　前記絶縁膜上に、所定の薬液に耐性を有するストッパー膜を形成するステップと、
    　前記半導体部材の前記ストッパー膜側の表面に縦孔を形成するステップと、
    　前記縦孔に記第１半導体部及び前記第２半導体部を電気的に接続するＣｕ配線接合部を形成するステップと、
    　前記半導体部材の前記Ｃｕ配線接合部側の表面にＣｕ拡散防止膜を形成するステップと、
    　前記Ｃｕ配線接合部の形成領域を含む所定領域以外の領域の前記Ｃｕ拡散防止膜を除去して該領域の不要なＣｕ部を露出させるステップと、
    　前記不要なＣｕ部を前記所定の薬液を用いて除去するステップと
    　を含む半導体装置の製造方法。     Forming an insulating film on one surface of the semiconductor member including the first semiconductor portion and the second semiconductor portion;
    Forming a stopper film resistant to a predetermined chemical solution on the insulating film;
    Forming a vertical hole in the surface of the semiconductor member on the stopper film side;
    Forming a Cu wiring junction for electrically connecting the first semiconductor portion and the second semiconductor portion in the vertical hole;
    Forming a Cu diffusion prevention film on the surface of the semiconductor member on the Cu wiring joint side;
    Removing the Cu diffusion prevention film in a region other than the predetermined region including the formation region of the Cu wiring bonding portion to expose an unnecessary Cu portion in the region;
    Removing the unnecessary Cu portion by using the predetermined chemical solution.
  2. 　前記不要なＣｕ部を、ウェットエッチング法により除去する
    　請求項１に記載の半導体装置の製造方法。     The method for manufacturing a semiconductor device according to claim 1, wherein the unnecessary Cu portion is removed by a wet etching method.
  3. 　前記不要なＣｕ部を、リフトオフ法により除去する
    　請求項１に記載の半導体装置の製造方法。     The method for manufacturing a semiconductor device according to claim 1, wherein the unnecessary Cu portion is removed by a lift-off method.
  4. 　前記ストッパー膜が、ＳｉＮ膜、ＳｉＣＮ膜、ＳｉＣ膜及びＳｉＣＯ膜のいずれかである
    　請求項１に記載の半導体装置の製造方法。     The method for manufacturing a semiconductor device according to claim 1, wherein the stopper film is any one of a SiN film, a SiCN film, a SiC film, and a SiCO film.
  5. 　さらに、前記不要なＣｕ部を除去するステップの後、前記所定領域以外の領域の前記ストッパー膜を除去するステップを含む
    　請求項１に記載の半導体装置の製造方法。     The method for manufacturing a semiconductor device according to claim 1, further comprising a step of removing the stopper film in a region other than the predetermined region after the step of removing the unnecessary Cu portion.
  6. 　前記Ｃｕ配線接合部を、ダマシンプロセスにより形成する
    　請求項１に記載の半導体装置の製造方法。     The method for manufacturing a semiconductor device according to claim 1, wherein the Cu wiring junction is formed by a damascene process.
  7. 　第１半導体部および第２半導体部を含む半導体部材と、
    　前記半導体部材の一方の面上の絶縁膜と、
    　前記絶縁膜を貫通すると共に前記第１半導体部及び前記第２半導体部を電気的に接続するＣｕ配線接合部と、
    　前記Ｃｕ配線接合部上のＣｕ拡散防止膜と、
    　少なくとも前記Ｃｕ拡散防止膜と前記絶縁膜との間に設けられると共に、不要なＣｕ部を除去する所定の薬液に耐性を有するストッパー膜と
    　を備える半導体装置。     A semiconductor member including a first semiconductor portion and a second semiconductor portion;
    An insulating film on one surface of the semiconductor member;
    A Cu wiring junction that penetrates the insulating film and electrically connects the first semiconductor portion and the second semiconductor portion;
    A Cu diffusion prevention film on the Cu wiring junction;
    A semiconductor device comprising: a stopper film provided between at least the Cu diffusion preventing film and the insulating film and having resistance to a predetermined chemical solution for removing unnecessary Cu portions.
PCT/JP2012/075845 2011-10-12 2012-10-04 Method for producing semiconductor device, and semiconductor device WO2013054739A1 (en)

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JP2003007705A (en) * 2001-06-26 2003-01-10 Mitsubishi Electric Corp Formation method of copper wiring
JP2005079434A (en) * 2003-09-02 2005-03-24 Matsushita Electric Ind Co Ltd Semiconductor device and method for manufacturing the same
JP2005116630A (en) * 2003-10-03 2005-04-28 Ebara Corp Wiring forming method and apparatus thereof
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JP2003007705A (en) * 2001-06-26 2003-01-10 Mitsubishi Electric Corp Formation method of copper wiring
JP2005079434A (en) * 2003-09-02 2005-03-24 Matsushita Electric Ind Co Ltd Semiconductor device and method for manufacturing the same
JP2005116630A (en) * 2003-10-03 2005-04-28 Ebara Corp Wiring forming method and apparatus thereof
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