JP6385515B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a plurality of element portions.

  In a photoelectric conversion device such as a CMOS image sensor which is a kind of semiconductor device, a photoelectric conversion unit having a plurality of photoelectric conversion elements and a signal processing unit for processing an electric signal from the photoelectric conversion unit are monolithically formed on one semiconductor substrate. I made it. It has been studied that the photoelectric conversion unit and the signal processing unit are separately formed into separate parts (chips), these parts are stacked, and the parts are electrically connected by a conductive member. By doing in this way, the occupation area (footprint) of the photoelectric conversion apparatus in the electronic device in which the photoelectric conversion apparatus is mounted can be efficiently utilized. Such a structure can be applied to various semiconductor devices that realize a so-called system-in-package.

  In Patent Document 1, a through connection conductor (64), a connection conductor (65), and a connection wiring (72) are provided as conductive members for obtaining electrical connection between semiconductor substrates (3445) corresponding to components. (Refer to FIG. 3 of Patent Document 1). Alternatively, it is described that one through connection conductor (84) is provided as a conductive member (see FIG. 15 of Patent Document 1).

JP 2010-245506 A

  In the technique of Patent Document 1, examination on electrical connection is not sufficient. When the through connection conductor (64) and the connection conductor (65) are provided and connected by the connection wiring (72), the wiring capacity and the wiring resistance increase by penetrating the semiconductor layer twice, and the wiring delay causes There is a problem that the performance of the semiconductor device may be degraded. Further, when the through connection conductor (84) is used, poor connection between the through connection hole (85), the wiring (40), and the wiring (53) occurs due to misalignment during manufacture and / or cracks during use. There is a problem that it is easy.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device with high electrical connection performance and reliability using a conductive member.

  Means for solving the problem is a method for manufacturing a semiconductor device, wherein the first element portion includes a first semiconductor layer, and the first wiring includes a first wiring electrically connected to the first element portion. A second part having a first part having a second semiconductor layer, a second element part including a second semiconductor layer, and a second wiring part including a second wiring electrically connected to the second element part. A bonding step for bonding the first wiring portion and the second wiring portion between the first element portion and the second element portion, and a first wiring constituting the first wiring A connection step of electrically connecting the first wiring and the second wiring by forming a conductive member in contact with both the pattern and the second wiring pattern constituting the second wiring, and the connection step The through hole that penetrates the first component and exposes the second wiring pattern is the through hole. A first stage in which the first wiring pattern is exposed and the through hole is positioned between a plurality of portions of the first wiring pattern; and the first wiring pattern exposed in the through hole and And a second step of forming the conductive member in contact with both of the second wiring patterns in the through hole.

  According to another aspect of the present invention, there is provided a semiconductor device manufacturing method including a first element portion including a first semiconductor layer and a first wiring electrically connected to the first element portion. A first component having a first wiring part; a second element part including a second semiconductor layer; and a second wiring part including a second wiring electrically connected to the second element part. A joining step of joining two parts so that the first wiring portion and the second wiring portion are located between the first element portion and the second element portion; and a first portion constituting the first wiring A connecting step of forming a conductive member in contact with both the first wiring pattern and the second wiring pattern constituting the second wiring to electrically connect the first wiring and the second wiring; The bonding process is performed so that the first wiring pattern and the second wiring pattern overlap. The connecting step penetrates the first component and exposes a portion of the second wiring pattern that overlaps the first wiring pattern in the joining step, and the through hole exposes the first wiring pattern. And the 1st step formed so that the part which overlaps with the 2nd wiring pattern of the 1st wiring pattern in the joining process may be removed, and the 1st wiring pattern and the 2nd wiring pattern exposed to the through-hole And a second step of forming the conductive member in contact with both in the through hole.

  The means for solving the problem is a semiconductor device, and includes a first element portion including a first semiconductor layer and a first wiring portion including a first wiring electrically connected to the first element portion. And a second element part including a second semiconductor layer, and a second wiring part including a second wiring electrically connected to the second element part, wherein the first element part The first wiring part and the second wiring part are located between the first element part and the second element part, and the first wiring part is located between the first element part and the second wiring part, A conductive member that penetrates through the first element portion and the first wiring portion and contacts the first wiring pattern of the first wiring and the second wiring pattern of the second wiring is provided. A portion that penetrates one wiring portion is located between a plurality of portions of the first wiring pattern.

  According to the present invention, it is possible to provide a semiconductor device having high performance and reliability of electrical connection by a conductive member.

1 is a schematic diagram of an example of a semiconductor device. 1 is a schematic diagram of an example of a semiconductor device. The schematic diagram of an example of the manufacturing method of a semiconductor device. The schematic diagram of an example of the manufacturing method of a semiconductor device. The schematic diagram of another example of the manufacturing method of a semiconductor device. FIG. 6 is a schematic diagram illustrating a method for manufacturing a semiconductor device.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In the following description, a plurality of drawings may be referred to each other. The same or similar components are denoted by common reference numerals, and the description of the components denoted by the common reference numerals is omitted as appropriate.

  A photoelectric conversion device as an example of the semiconductor device of this embodiment will be described with reference to FIG. FIG. 1A is a perspective view of a semiconductor device 1 which is a main part of the semiconductor device. FIGS. 1B and 1C are exploded perspective views of an example of the semiconductor device 1. FIG. 1D is a schematic diagram of the semiconductor device 3 including the semiconductor device 1 and the electronic apparatus 5.

  In the semiconductor device 1 shown in FIG. 1A, as shown in FIG. 1B or FIG. 1C, the first portion 10 and the second portion 20 overlap. The present embodiment mainly relates to a conductive member for obtaining an electrical connection between the first portion 10 and the second portion 20. The first portion 10 includes a first element unit 30 and a first wiring unit 31. The second portion 20 includes a second element unit 50 and a second wiring unit 51. The second wiring part 51 is located between the first part 10 and the second element part 50. In the present embodiment, the first wiring portion 31 of the first portion 10 is located between the first element portion 30 and the second element portion, but the first element portion 30 of the first portion 10 is the first wiring portion 31. And the second element unit 50 may be located.

  In this embodiment, the 1st part 10 has the photoelectric conversion unit 11 which a signal charge generate | occur | produces according to incident light. The photoelectric conversion unit 11 includes a photoelectric conversion element. The photoelectric conversion unit 11 may include a signal generation circuit that generates an electric signal based on signal charges generated by the photoelectric conversion element. The signal generation circuit includes, for example, an amplification transistor, a transfer transistor, a reset transistor, and a selection transistor. The photoelectric conversion unit 11 of another example may include a CCD (Charge Coupled Device) for transferring signal charges with the photoelectric conversion element.

  In the present embodiment, the second portion 20 includes a signal processing unit 22. The signal processing unit 22 processes an electrical signal based on the signal charge generated by the photoelectric conversion unit 11. The signal processing unit 22 can include a noise removal circuit, an amplification circuit, a conversion circuit, and an image processing circuit. The noise removal circuit is, for example, a CDS (Correlated Double Sampling) circuit. The amplifier circuit is, for example, a column amplifier circuit. The conversion circuit is, for example, an ADC (Analog Digital Converter) circuit including a comparator and a counter. The image signal processing circuit includes, for example, a memory and a processor, and generates image data from a digital signal subjected to analog-digital conversion, and performs image processing on the image data.

  In FIG. 1A, the position of the photoelectric conversion unit 11 is surrounded by a one-dot chain line, and the position of the signal processing unit 22 is surrounded by a two-dot chain line. Here, a part of the signal processing unit 22 is located in a part of the orthogonal projection area to the second part 20 of the photoelectric conversion unit 11. However, all or part of the signal processing unit 22 may be located in the entire orthogonal projection region onto the second portion 20 of the photoelectric conversion unit 11. Alternatively, all or part of the signal processing unit 22 may be located in a part of the orthogonal projection region of the photoelectric conversion unit 11 in the second portion 20. A part of the signal processing unit 22 may be provided in the first portion 10. For example, a signal processing unit for analog signals such as a noise removal circuit and an amplifier circuit may be provided in the first portion 10, and a signal processing unit for digital signals such as a conversion circuit and an image processing circuit may be provided in the second portion 20.

  As shown in FIGS. 1B and 1C, the semiconductor device 1 can further include a control unit 12 that controls the photoelectric conversion unit 11 and / or a control unit 21 that controls the signal processing unit 22. . These control units can be provided in at least one of the first portion 10 and the second portion 20. In the example shown in FIG. 1B, the control unit 12 is provided in the first portion 10, and in the example shown in FIG. 1C, the control unit 21 is provided in the second portion 20. The control unit for the photoelectric conversion unit 11 can be provided in the first part 10 and the control unit for the signal processing unit 22 can be provided in the second part 20 separately. The control unit 12 may include a vertical driving circuit that supplies a driving signal to the pixel circuit via a vertical scanning line, and a power supply circuit. The control unit 21 may include a timing generation circuit for driving the signal processing unit 22, a reference signal supply circuit for supplying a reference signal to the conversion circuit, an amplifying circuit, or a horizontal scanning circuit for sequentially reading signals from the conversion circuit.

  As shown in FIG. 1D, the semiconductor device 3 can include a package 2 as a mounting member for primary mounting of the semiconductor device 1. The semiconductor device 1 can be die-bonded and accommodated in this package. The package 2 may include external terminals such as PGA (Pin Grid Array), LGA (Land Grid Array), BGA (Ball Grid Array), and lead frame. As shown in FIG. 1D, the semiconductor device 3 can include a circuit board 4 as a mounting member for secondary mounting. The package 2 can be mounted on the circuit board 4. The circuit board 4 may be a printed board such as a rigid board, a flexible board, or a rigid flexible board. The semiconductor device 3 as a photoelectric conversion device can include an optical system for guiding light to the semiconductor device 1.

  The semiconductor device 3 can be mounted on various electronic devices. In addition to the semiconductor device 3, the electronic device 5 includes a peripheral device 6 such as an arithmetic device, a storage device, a recording device, a communication device, or a display device. These peripheral devices are connected to the semiconductor device 3 and exchange signals directly or indirectly. Examples of the electronic device 5 include information terminals such as mobile phones and personal computers, and video devices such as cameras and displays. Of course, an information terminal with a camera is also included.

  Details of an example of the semiconductor device 1 will be described with reference to FIG. FIG. 2 is a cross-sectional view of the semiconductor device 1 in a plane including the points P and Q shown in FIG. 2 is an example having a control unit 12 as shown in FIG.

  In the following description, it is assumed that the conductor layer is made of a material having higher conductivity than the semiconductor layer, and the insulator layer is made of a material having lower conductivity than the semiconductor layer.

  In the following description of semiconductor compounds and metal compounds, carbonitrides and oxynitrides are included in nitrides. Nitride carbide and oxycarbide are included in the carbide.

  First, regarding the first portion 10, the configurations of the first element unit 30 and the first wiring unit 31 will be described.

  The first element unit 30 includes a first semiconductor layer 303. The first semiconductor layer 303 is, for example, a silicon layer. The first element unit 30 includes a photodiode PD provided in the first semiconductor layer 303 as a semiconductor element (photoelectric conversion element) constituting the photoelectric conversion unit 11 in FIG. The photodiode PD includes a p-type semiconductor region 32, an n-type semiconductor region 34, and a p-type semiconductor region 35 of the first semiconductor layer 303. The photoelectric conversion element may be a photogate. The photoelectric conversion unit 11 may include a signal generation circuit that generates an electric signal based on signal charges generated by the photoelectric conversion element. The signal generation circuit can be composed of a semiconductor element such as a MOS transistor. FIG. 2 shows the transfer transistor Tr1 and the reset transistor Tr2 of the photoelectric conversion unit 11 of the first portion 10. Further, transistors Tr3 and Tr4 are shown as semiconductor elements of the control unit 12 of the first portion 10 in FIG.

  In this example, a part of the surface 103 of the first semiconductor layer 303 constituting the first element unit 30 forms an interface with the gate insulating films of the MOS transistors Tr1, Tr2, Tr3, Tr4. The first element unit 30 is provided with an element isolation 38 such as STI (Shallow Trench Isolation) or LOCOS (LOCal Oxidation of Silicon). A first protective film (not shown) made of an insulating layer such as silicon nitride or silicon oxide is provided on the first semiconductor layer 303 to protect the surface 103 of the first semiconductor layer 303. As described above, the first element unit 30 may include the element isolation 38, the gate insulating film, the gate electrode, and the first protective film in addition to the first semiconductor layer 303.

  The first wiring part 31 includes a conductor layer and an insulator layer. The first wiring unit 31 can have a plurality of wiring levels. One wiring level can have a wiring pattern and a plug. A typical conductor layer constitutes a wiring pattern. Furthermore, a typical conductor layer constitutes a main conductive layer having a high current density in the wiring pattern, but the conductor layer constitutes a sub conductive layer having a current density smaller than that of the main conductive layer in the wiring pattern. There is also. The conductor layer may constitute a via plug for obtaining conduction with the lower wiring level or a contact plug for obtaining conduction with the first element unit 30.

  Via plugs and contact plugs can also be composed of a main conductive layer and a sub conductive layer. These sub-conductive layers can typically be barrier metals. The barrier function of the barrier metal includes a barrier against diffusion between the main conductive layer and the insulator layer, or a barrier against reaction between the main conductive layer and the insulator layer. However, “barrier metal” is a convenient name given to the sub-conductive layer and does not necessarily have any barrier function. Even when these barrier functions are not required, the barrier metal can be used simply as a base for forming the main conductive layer or for the purpose of mitigating electromigration or stress migration.

  The insulator layer can function as an inter-wiring insulating layer that insulates wiring patterns at the same wiring level and / or an interlayer insulating layer that insulates wiring patterns at different wiring levels. The first wiring part 31 has a large number of electrical paths (wirings) composed of one or more conductor layers. One wiring can be composed of a contact plug, a via plug, and a wiring pattern.

  A detailed configuration of the first wiring unit 31 will be described. The first wiring part 31 is provided with contact plugs 44, wiring patterns 40a, 40b, 40c and via plugs. These contact plugs, wiring patterns, and via plugs formed of a conductor layer constitute a large number of electrical paths. The contact plug 44 is mainly made of a tungsten layer, and has a barrier metal including a titanium layer and / or a titanium nitride layer in addition to the tungsten layer. The wiring patterns 40a, 40b, 40c and the via plug are mainly made of a copper layer, and have a barrier metal including a tantalum nitride layer and / or a tantalum layer in addition to the copper layer. The wiring pattern 40a is composed of one copper layer, and the wiring pattern 40b and the via plug, and the wiring pattern 40c and via plug are each integrally composed of one copper layer. The first wiring 311 of this example includes a wiring pattern 40c, and is connected to a semiconductor element through a contact plug 44, wiring patterns 40a and 40b, and a via plug at a portion not shown.

  The first wiring portion 31 is provided with an insulator film 39 including an insulator layer mainly made of silicon oxide as an interlayer insulating layer or an inter-wiring insulating layer. A typical insulator film 39 is a multilayer film having a plurality of insulator layers. The insulator film 39 of the first wiring part 31 can further have an insulator layer (not shown) made of silicon nitride, silicon carbide or the like as a copper diffusion prevention layer contained in the wiring patterns 40a, 40b, and 40c. . These can be arranged between the interlayer insulating layer and the wiring pattern.

  Next, regarding the second portion 20, the configurations of the second element unit 50 and the second wiring unit 51 will be described.

  The second element unit 50 includes a second semiconductor layer 505 and includes MOS transistors Tr5, Tr6, Tr7, Tr8 as semiconductor elements constituting the signal processing unit 22. In this example, a part of the surface 203 of the second semiconductor layer 505 forms an interface with the gate insulating films of the MOS transistors Tr5, Tr6, Tr7, Tr8. The second element unit 50 is provided with an element isolation 58 such as STI or LOCOS. A second protective film (not shown) made of an insulator such as silicon nitride or silicon oxide that protects the surface 203 of the second semiconductor layer 505 is provided on the second semiconductor layer 505. In addition to the second semiconductor layer 505, the second element unit 50 may include an element isolation 58, a gate insulating film, a gate electrode, and a second protective film.

  The second wiring part 51 includes a conductor layer and an insulator layer. The conductor layer and the insulator layer of the second wiring part 51 also have the same functions as the conductor layer and the insulator layer of the first wiring part 31.

  A detailed configuration of the second wiring unit 51 will be described. The second wiring portion 51 is provided with a contact plug 54a, a plurality of wiring patterns 53a, 53b, 53c and via plugs 54b, 54c. These contact plugs, wiring patterns, and via plugs formed of a conductor layer constitute a large number of electrical paths. The contact plug 54a and the via plug 54c are mainly made of a tungsten layer, and have a barrier metal including a titanium layer and / or a titanium nitride layer in addition to the tungsten layer. The wiring patterns 53a and 53b and the via plug 54b are mainly made of a copper layer, and have a barrier metal including a tantalum nitride layer and / or a tantalum layer in addition to the copper layer. The wiring pattern 53a includes one copper layer. The wiring pattern 53b and the via plug 54b are integrally formed of one copper layer. The wiring pattern 53c is mainly made of an aluminum layer, and has a barrier metal including a titanium layer and / or a titanium nitride layer in addition to the aluminum layer. The second wiring 512 of this example includes a wiring pattern 53c, and is connected to a semiconductor element via a contact plug 54a (not shown), wiring patterns 53a and 53b, and via plugs 54b and 54c.

  The second wiring portion 51 is provided with an insulator film 49 including an insulator layer mainly made of silicon oxide as an interlayer insulating layer or an inter-wiring insulating layer. A typical insulator film 49 is a multilayer film having a plurality of insulator layers. The insulating film 49 of the second wiring portion 51 can further include an insulating layer (not shown) made of silicon nitride or silicon carbide as a copper diffusion preventing layer contained in the wiring patterns 53a and 53b. These can be arranged between the interlayer insulating layer and the wiring pattern.

  In the wiring patterns 40a, 40b, 40c, 53a, 53b and the plugs of the first wiring part 31 and the second wiring part 51, the copper layer, the tungsten layer, and the aluminum layer function as a main conductive layer having high conductivity in the wiring. The main conductive layer is made of a material having higher conductivity than the sub-conductive layer such as a tantalum layer, a tantalum nitride layer, a titanium layer, or a titanium nitride layer used for the barrier metal, and has a small cross-sectional area in the direction in which the current flows. Low resistance.

  Although the wiring pattern 40a, 40b, 40c, 53a, 53b has shown the example which mainly consists of a copper layer, the wiring pattern which mainly consists of an aluminum layer like the wiring pattern 53c can also be employ | adopted for these. The copper layer and the aluminum layer may be not only single copper but also an alloy to which other metals are added. For example, the copper layer may contain less aluminum, silicon, or the like than copper, and the aluminum layer may contain less copper, silicon, or the like than aluminum. Although the example in which the main insulator layer of the insulator film 39 is made of silicon oxide has been given, silicate glass such as BSG, PSG, or BPSG can also be used. Alternatively, a material having a lower dielectric constant than silicon oxide (low-k material) can be used.

  The example in which the wiring pattern of the first wiring part 31 is three levels of wiring patterns 40a, 40b, and 40c and the wiring pattern of the second wiring part 51 is three levels of 53a, 53b, and 53c is shown. However, the number of levels of the wiring pattern can be set as appropriate, and may be different between the first wiring part 31 and the second wiring part 51. For example, the number of levels of the wiring pattern of the second wiring unit 51 may be larger than the number of levels of the wiring pattern of the first wiring unit 31.

  Subsequently, another structure of the electronic device 1 will be described.

  The first portion 10 and the second portion 20 are joined by the first wiring portion 31 and the second wiring portion 51. The insulator film 39 of the first wiring part 31 and the insulator film 49 of the second wiring part 51 are joined via the joint surface 60.

  The semiconductor device 1 of this example is a back-illuminated photoelectric conversion device in which a surface (back surface 104) opposite to the surface (front surface 103) on which the transistors Tr1 to Tr4 of the first semiconductor layer 303 are provided is a light receiving surface. Configure. In the back-illuminated photoelectric conversion device, the thickness of the first semiconductor layer 303 of the first portion 10 is less than 10 μm, for example, 2 to 5 μm. The thickness of the second semiconductor layer 505 is thicker than that of the first semiconductor layer 303, and the second semiconductor layer 505 functions as a support for the first semiconductor layer 303. The thickness of the second semiconductor layer 505 is 10 μm or more, for example, 20 to 500 μm.

  An optical member 41 is provided on the back surface 104 side of the first semiconductor layer 303.

  The optical member 41 can include an antireflection layer 61, an insulator layer 62, a light shielding layer 63, an insulator layer 69, a planarization layer 71, a color filter array 73, and a microlens array 74. The optical member 41 is in contact with the p-type semiconductor region 32 constituting the light receiving surface (back surface 104) of the first element unit 30. The optical member 41 has a light incident surface 401 on the side opposite to the first element unit 30 side. In this example, the light incident surface 401 is constituted by a microlens array 74.

  The electrode pads 78 are arranged on the same level as the wiring pattern 53c. On the electrode pad 78, an opening 77 that penetrates the plurality of insulator layers, the first semiconductor layer 303, and the optical member 41 is provided. A bonding wire 79 connected to the electrode pad 78 is provided in the opening 77. Wire bonding is connected to the internal terminals of the package. Note that the connection between the semiconductor device 1 and the package is not limited to wire bonding, and flip-chip connection can also be used.

  The semiconductor device 1 is provided with a conductive member 68 that connects the first wiring 311 and the second wiring 512 to each other. The conductive material constituting the conductive member 68 is gold, silver, copper, aluminum, tungsten, tantalum, titanium, manganese, or a compound such as nitride or carbide thereof.

  The conductive member 68 passes through the first semiconductor layer 303 of the first element unit 30 and is connected to the first wiring 311 of the first wiring unit 31, and further penetrates the first wiring unit 31 to form the second wiring unit 51. The second wiring 512 is connected. In this example, the conductive member 68 contacts the wiring pattern 40 c of the first wiring 311 and contacts the wiring pattern 53 c of the second wiring 512. In the present embodiment, the conductive member 68 can be positioned between a plurality of portions of the wiring pattern 40 c of the first wiring 311. In other words, the plurality of portions of the wiring pattern 40 c sandwich the conductive member 68. A plurality of portions sandwiching the conductive member 68 of the wiring pattern 40 c are portions (opposed portions) facing the conductive member 68. A portion located between the plurality of portions of the wiring pattern 40 c of the conductive member 68 is a portion that penetrates the first wiring portion 31. A plurality of portions (opposing portions) of the wiring pattern 40c sandwiching the conductive member 68 preferably overlap with the wiring pattern 53c of the second wiring 512, but may not overlap. The overlapping part of the two wiring patterns 40c and 53c is a part of one wiring pattern that overlaps the other wiring pattern. Here, the overlapping of the wiring patterns means that a plurality of wiring patterns are located in the direction from the first semiconductor layer 303 toward the second semiconductor layer 505 (the normal direction of the first semiconductor layer 303 and the second semiconductor layer 505). Means that.

  FIG. 2B-1 is a plan view when the conductive member 68 is surrounded by the first wiring 311, and FIG. 2C-1 is a perspective view thereof. The wiring pattern 40 c has portions 3111, 3112, 3113, 3114. The conductive member 68 is located between the portion 3111 and the portion 3113, and is located between the portion 3112 and the portion 3114. The conductive member 68 is located between the portions 3111 and 3112 and is located between the portions 3113 and 3114. These portions 3111, 3112, 3113, and 3114 desirably overlap with the wiring pattern 53 c constituting the second wiring 512, but do not need to overlap. Further, these portions 3111, 3112, 3113, 3114 are in contact with the conductive member 68. In this example, the conductive member 68 is in contact with the side surface of the first wiring 311. This side surface is constituted by portions 3111, 3112, 3113, 3114. Here, the conductive member 68 is in contact with the side surface of the first wiring 311, but the conductive member 68 may be in contact with the upper surface of the first wiring 311 instead of the side surface of the first wiring 311. The conductive member 68 may be in contact with the side surface and the upper surface of the first wiring 311.

  FIG. 2B-2 is a plan view when the conductive member 68 is sandwiched between the first wirings 311, and FIG. 2C-2 is a perspective view thereof. The wiring pattern 40 c has portions 3115, 3116, and 3117. The conductive member 68 is located between the portion 3115 and the portion 3117. In addition, the conductive member 68 is located between the portion 3115 and the portion 3116 of the first wiring 311, and is located between the portion 3116 and the portion 3117. In the example of FIG. 2B-2, the conductive member 68 faces the side surfaces of the three continuous portions 3115, 3116, and 3117 of the first wiring 311. Then, the angle formed by the side surfaces of two sets of two portions (portion 3115 and portion 3115, portion 3116 and portion 3117) of the three portions is 90 °. In addition, the angle formed by the side surfaces of a pair of two parts (part 3115 and part 3117) of the three parts is 0 ° (parallel). As in the example of FIG. 2B-1, the portions 3115, 3116, and 3117 overlap with the wiring pattern 53 c constituting the second wiring 512.

  FIG. 2B-3 is a plan view when the conductive member 68 is sandwiched between the first wirings 311. FIG. 2C-3 is a perspective view thereof. The wiring pattern 40 c has portions 3118 and 3119. The two portions 3118 and 3119 are discontinuous portions of the wiring pattern 40 c of the first wiring 311. In the example of FIG. 2B-3, the portions 3118 and 3119 overlap the wiring pattern 53c of the second wiring 512. The conductive member 68 is sandwiched between the side surfaces of the portions 3118 and 3119. In the example of FIG. 2B-3, the conductive member 68 has an angle formed by two portions 3118 and 3119 of 0 ° (parallel). 2B and 2C-3, both of the two portions 3114 and 3115 of the first wiring 311 sandwiching the conductive member 68 are the same even if the conductive member 68 is replaced with an insulating member. It may be a part of the wiring 311. Here, an example is shown in which the two portions 3118 and 3119 are electrically continuous in the wiring pattern 40c. However, two portions such as the wiring patterns 40b and 40a may be electrically connected to each other to form the first wiring 311 as one electric path.

  When the conductive member 68 is positioned between the plurality of portions of the wiring pattern of the first wiring 311, the angle on the conductive member 68 side formed by the surfaces (opposing surfaces) facing the conductive member 68 of the plurality of portions is 180. Means less than °. That is, it is only necessary that the opposing surface is composed of only one plane. Here, an example in which the opposing surface is configured by combining a plurality of planes is shown, but the conductive member 68 may face a side surface without a clear boundary such as a smooth curved surface. The angle on the conductive member 68 side formed by a surface (opposing surface) of the plurality of portions facing the conductive member 68 is preferably 90 ° or less. For example, if the conductive member 68 has a cylindrical shape and the side surface of the wiring pattern 40c has an arc shape in plan view, the center angle of the arc is preferably 90 ° or more. This is because the angle formed by the tangent at one end of the arc and the tangent at the other end is 90 ° or more.

  The conductive member 68 may be in contact with any one or a plurality of wiring patterns 40a, 40b, and 40c, and the conductive member 68 may be in contact with any one or a plurality of wiring patterns 53a, 53b, and 53c. In addition, the conductive member 68 may be in contact with the main conductive layer of the wiring pattern, or may be in contact with a sub conductive layer such as a barrier metal of the wiring pattern. In some cases, the secondary conductive layer of the barrier metal of the wiring pattern penetrates the main conductive layer. In this example, the side surface of the aluminum layer that is the main conductive layer 42 of the wiring pattern 40c and the side surface of the titanium nitride layer (and titanium layer) that are the sub conductive layers 41a and 41b are in contact. The conductive member 68 is surrounded or sandwiched between the side surfaces of the main conductive layer 42. Further, the upper surface of the aluminum layer which is the main conductive layer 56 of the wiring pattern 53c and the side surface of the titanium nitride layer (and titanium layer) which are the sub conductive layers 55a and 55b are in contact.

  In the present embodiment, the electrical paths of the first wiring 311 and the second wiring 512 do not pass through the outside of the first wiring part 31 and the second wiring part 51, and the inside of the first wiring part 31 and the second wiring part 51 Is formed. Thereby, an increase in wiring capacitance and / or wiring resistance between the first wiring 311 and the second wiring 512 can be suppressed, and the semiconductor device can be operated at high speed.

  In addition, electrical connection between the first wiring 311 and the conductive member 68 can be ensured at a plurality of portions located on both sides of the conductive member 68. As a result, a structure in which poor connection between the first wiring 311 and the conductive member 68 does not occur is obtained. One cause of the connection failure may be a chemical change such as a crack caused by a thermal cycle during use or corrosion or diffusion of the conductive member 68 or the wiring pattern 40c. In addition, a cause of connection failure may be misalignment during manufacturing, which will be described later.

  The conductive member 68 is surrounded by an insulating region 45 provided in the first semiconductor layer 303. The insulating region 45 in this example is a solid region, but may be a gas or vacuum region. The photoelectric conversion unit 11 and the signal processing unit 22, the photoelectric conversion unit 11 and the control unit 21, or the control unit 12 and the signal processing unit 22 are electrically connected by the conductive member 68. Alternatively, a part of the signal processing unit provided in the first part 10 and a part of the signal processing unit provided in the second part 20 are electrically connected.

  A block 90 shown in FIG. 2 shows a region including the conductive member 68, the first wiring 311, the second wiring 512, and the insulating region 42 related to the connection between the parts. A plurality of the blocks 90 are preferably arranged in parallel. By arranging a plurality of blocks 90 in parallel, a signal for each column or row of the photoelectric conversion unit 11 is transferred to the signal processing unit 22, and the signal processing unit 22 is based on signal charges generated by the photoelectric conversion unit 11. The signal can be processed. Further, the blocks 90 may be arranged in columns, or the columns and parallel may be used in combination.

  The above is an example of the configuration of the semiconductor device 1. These configurations can be changed as appropriate.

  Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 3 and 4 are cross-sectional views showing the same part (plane including points P and Q in FIG. 1) as in FIG.

  This will be described with reference to FIG. A first semiconductor substrate 303a is prepared. The first semiconductor substrate 303a is, for example, a silicon substrate. An element isolation 38 such as STI is formed on the first surface (front surface) 103 of the first semiconductor substrate 303a. Next, the photodiode PD and transistors Tr1, Tr2, Tr3, Tr4 are formed on the first semiconductor substrate 303a. In this way, the first element unit 30 is formed.

  Next, an interlayer insulating layer is formed on the first element unit 30, and a contact plug 44 is formed in the interlayer insulating layer. A wiring pattern 40 a is formed using a single damascene method so as to be connected to the contact plug 44. Further, after forming an interlayer insulating layer, a wiring pattern 40b and a via plug, a wiring pattern 40c and a via plug are formed by using a dual damascene method. Thereafter, an insulating layer which is a surface layer of the insulating film 39 is formed on the wiring pattern 40c, and is planarized. In this way, the first wiring part 31 is formed. A first wiring 311 is formed in the first wiring portion 31.

  As described above, the first component 10a to be the first portion 10 is created.

  This will be described with reference to FIG. A second semiconductor substrate 505a is prepared. The second semiconductor substrate 505a is, for example, a silicon substrate. An element isolation 38 such as STI is formed on the first surface (front surface) 203 of the second semiconductor substrate 505a. Next, Tr5, Tr6, Tr7, Tr8 are formed on the second semiconductor substrate 505a. In this way, the second element unit 50 is formed.

  Next, an interlayer insulating layer is formed on the second element unit 50, and a contact plug 54a is formed in the interlayer insulating layer. A wiring pattern 53a is formed using a single damascene method so as to be connected to the contact plug 54a. Further, after forming the interlayer insulating layer, the wiring pattern 53b and the via plug 54b, the wiring pattern 53c and the via plug 54c are formed by using a dual damascene method. Thereafter, an insulating layer that is a surface layer of the insulating film 49 is formed and planarized. In this way, the second wiring part 51 is formed. A second wiring 512 is formed in the second wiring portion 51.

  As described above, the second component 20a to be the second portion 20 is created.

  This will be described with reference to FIG. The first component 10a and the second component 20a are prepared as described above, the first component 10a and the second component 20a, the first component 10a and the second component 20a, the first element unit 30 and the second component. It joins so that the 1st wiring part 31 and the 2nd wiring part 51 may be located between the element parts 50. FIG. In addition to the plasma bonding between the planarized surface of the insulator film 39 and the surface layer of the insulator film 49, the bonding is performed between the metal layers exposed on the surfaces of the first wiring portion 31 and the second wiring portion 51. It can be realized by metal bonding or bonding via an adhesive layer. At this time, it is preferable to join the wiring pattern 40c of the first wiring 311 and the wiring pattern 53c of the second wiring 512 so as to overlap each other. At the time of manufacturing the first component 10a and the second component 20a, the positional relationship between the first wiring 311 and the second wiring 512 is set. Either one of the wiring pattern 40c of the first wiring 311 and the wiring pattern 53c of the second wiring 512 may overlap the other, or a part of one may overlap the other. Between the wiring pattern 40c of the first wiring 311 and the wiring pattern 53c of the second wiring 512, an insulating layer that forms a surface layer of the planarized insulating film 39 and a surface layer of the planarized insulating film 49 are provided. The insulator layer to be formed is located. Note that the insulating layer forming at least one surface layer of the insulating film of the first wiring portion 31 and the second wiring portion 51 may be omitted, and the wiring pattern may be exposed on the surface of the wiring portion.

  Next, the first semiconductor layer 303 is obtained by thinning the first semiconductor substrate 303a from the opposite side (back side) of the first element part 30 to the first wiring part 31 side to the position 104. This thinning is performed by a known method such as polishing such as CMP, grinding such as grinding, or etching. In this thinning, the initial first semiconductor substrate 303a has a thickness of 700 μm or more, whereas the thickness of the first semiconductor layer 303 after the thinning of the first semiconductor substrate 303a is 500 μm or less, further 10 μm or less. Can be done. At this point, the thickness of the first semiconductor layer 303 can be made smaller than the thickness of the second semiconductor layer 505. When the flip chip connection is used, the second semiconductor substrate 505a is preferably thinned, but can be used as the second semiconductor layer 505 as it is.

  Thus, a joining process is performed and a laminated body is obtained. Next, a connection step for connecting the first wiring 311 and the second wiring 512 is performed by forming a conductive member in the laminate. The connection process is performed through a plurality of stages.

  This will be described with reference to FIG. As a first step, a connection hole is formed inside the insulating region 45 from the first semiconductor layer 303 side. This connection hole penetrates the first semiconductor layer 303 and opens to a depth just before reaching the wiring pattern 40c. The connection hole is formed by etching an insulator layer located between the wiring pattern 40 c and the first semiconductor layer 303 in the insulator layer of the insulator film 39. By reducing the thickness of the first semiconductor substrate 303a as described above, the aspect ratio of the connection hole can be reduced and miniaturization can be achieved. Next, an insulating film such as silicon oxide is formed in a region including the side wall and the bottom of the connection hole. By etching back the insulating film, the insulating region 59 is left only on the side wall of the connection hole.

  Further, the remaining insulator layer located between the connection hole and the wiring pattern 40c is etched to deepen the connection hole. The connection hole reaches the wiring pattern 40c, and a part of the wiring pattern 40c is removed by etching or the like. Specifically, the sub conductive layer 41a, the main conductive layer 42, and the sub conductive layer 41b are etched in this order. The etching conditions for the wiring pattern 40c may be different from the etching conditions for the insulator layer. Here, the part of the wiring pattern 40c to be removed may be a part or all of the part of the wiring pattern 40c that constitutes the first wiring 311 that overlaps the wiring pattern 53c of the second wiring 512. In this example, a part of the portion of the wiring pattern 40c that overlaps the wiring pattern 53c is removed, and after the removal, the remaining portion of the portion that overlaps the wiring pattern 53c remains.

  Further, by etching the insulator film 39, the connection hole passes through the joint surface 60 of the first wiring part 31 and the second wiring part 51 and penetrates the first component 10a. Further, the insulator film 49 is etched until the wiring pattern 53c formed in the second wiring portion 51 is reached. The connection hole is formed by etching the insulating layer located between the wiring pattern 40c and the wiring pattern 53c, among the insulating layer of the insulating film 39 and the insulating layer of the insulating film 49. These insulator layers may include an insulator layer on the surface of the insulator film 39 or the insulator film 49. In this way, the through hole 67 reaching the wiring pattern 53c of the second wiring 512 is formed. Thereby, the side surface of the wiring pattern 40c is exposed in the through hole 67, and the upper surface of the wiring pattern 53c is exposed. And the through-hole 67 is located between several parts of the wiring pattern 40c. In other words, the plurality of portions of the wiring pattern 40 c face each other through the through hole 67. The exposed part of the wiring pattern 53c is a part or all of the part of the wiring pattern 53c constituting the second wiring 512 that overlaps the wiring pattern 40c of the first wiring 311 at the time after the bonding process. It is possible. The formation position of the through hole 67 can be set inside the outline of the wiring pattern 40c. As a result, there is a risk that the through-hole 67 does not reach one of the wiring pattern 40c and the wiring pattern 53c even if an alignment shift occurs during the joining process of the first component 10a and the second component 20a or when the through-hole 67 is formed. It is reduced. Next, deposits on the exposed wiring pattern 40c are removed by wet etching with a chemical solution. Although wet etching is used, dry etching is also possible as long as it can remove deposits.

  This will be described with reference to FIG. As a second step, the conductive member 68 is formed by embedding a conductive material such as copper in the through hole 67. In this example, the conductive member 68 contacts the side surface of the wiring pattern 40c and the upper surface of the wiring pattern 53c. Note that the first wiring 311 and the second wiring 512 can be electrically connected even if a conductive material is thinly deposited along the side surface and the bottom surface of the through hole 67 and the conductive member 68 is used as a conductive film. An insulating region 59 is formed between the conductive member 68 and the first semiconductor layer 303. For this reason, the conductive member 68 and the first semiconductor layer 303 are not electrically connected. In addition, since it is formed inside the insulating region 45 formed in the first semiconductor layer 303, this also prevents the conductive member 68 and the semiconductor element of the first element unit 30 from being electrically connected. . Note that one of the insulating region 59 and the insulating region 45 may be omitted. When the insulating region 45 is not formed, it is possible to increase the arrangement density of the conductive members 68 and reduce the occupied area of the block 90. In this example, copper is used as the conductive material embedded in the through-hole 67, but aluminum or tungsten may be used.

  An optical member 41 is formed on the opposite side of the first element part 30 from the first wiring part 31. First, the antireflection layer 61 and the insulator layer 62 are formed on the back surface 104 of the first semiconductor layer 303. Thereafter, the light shielding layer 63 is formed. The antireflection layer 61 is preferably formed of a material having a refractive index between silicon and silicon oxide, such as silicon nitride or hafnium oxide. The antireflection layer 61 may be configured by laminating a plurality of films. The insulator layer 62 is, for example, a silicon oxide layer. The light shielding layer 63 can be formed by depositing and patterning aluminum or tungsten. The light shielding layer 63 is preferably disposed between the pixels, on the optical black pixel, and on the element affected by the incidence of light. It is also possible to connect the light shielding layer 63 and the first semiconductor layer 303 by depositing the light shielding layer 63 after patterning the antireflection layer 61 and the insulator layer 62 before depositing the light shielding layer 63.

  Further, a planarization layer 71 is formed on the light shielding layer 63. The planarization layer 71 is an inorganic insulator film or an organic insulator film, and can be composed of a plurality of layers. Further, the planarization layer 71 can be planarized as appropriate by CMP or the like. A color filter array 73 and a microlens array 74 made of resin are appropriately formed on the planarizing layer 71 in this order. At this time, the resin material is formed by using a coating method such as spin coating. However, since the through hole 67 is filled with the conductive material first, film unevenness such as striation occurs when the resin film is formed. This can be suppressed.

  Thereafter, an opening 77 is formed in the electrode pad 78. Thereby, the configuration shown in FIG. 2 is obtained. In the present embodiment, the example in which the formation process of the opening 77 is performed after the formation of the color filter 73 and the on-chip lens 74 is shown, but it can be performed before the formation of the color filter 73 and the on-chip lens 74. After the color filter 73 and the on-chip lens 74 are formed, heat treatment at a high temperature (about 400 ° C.) cannot be performed to protect the color filter 73 and the on-chip lens 74 that are resins. When the semiconductor device 1 is damaged by the processing of the opening 77, a heat treatment for recovering the damage may be required, and the order of the steps can be changed as appropriate.

  Thereafter, the semiconductor device 1 is bonded to the package using a die bond. Then, a bonding wire 79 connected to the electrode pad 78 is formed in the opening 77. The package is sealed with a transparent plate. An LGA (Land Grid Array) which is an external terminal of the package is fixed to the circuit board by reflow soldering. The semiconductor device 3 can be manufactured as described above.

  Another example of the method for manufacturing a semiconductor device will be described with reference to FIGS.

  FIG. 5A shows a state after the first component 10a and the second component 20a are joined. The wiring pattern 40c of the first component 10a has an opening 67c at a position where the through hole 67 is provided. The opening 67c is provided in advance in the first component 10a before the joining step. The opening 67c can be formed when the wiring pattern 40c is patterned.

  This will be described with reference to FIG. Patterning is performed from the back surface 104 side of the first semiconductor layer 303 to form a large-diameter connection hole 67a. The connection hole 67a is formed to reach the wiring pattern 40c. The connection hole 67a exposes the sub conductive layer 41a that is the upper surface of the wiring pattern 40c. In forming the connection hole 67a, the wiring pattern 40c can be prevented from being damaged by employing an etching condition in which the sub conductive layer 41a serves as an etching stopper for the insulator film 39.

  This will be described with reference to FIG. Subsequently, a connection hole 67b having a small diameter (width) smaller than that of the connection hole 67a is formed. The connection hole 67b is formed so as to reach the wiring pattern 53c. The connection hole 67b exposes the sub conductive layer 55b which is the upper surface of the wiring pattern 53c. In this example, the side surface of the wiring pattern 40c (main conductive layer 42) is exposed in the connection hole 67b. However, if the upper surface of the wiring pattern 40c is exposed in the connection hole 67a, the side surface of the wiring pattern 40c (main conductive layer 42) does not need to be exposed in the connection hole 67b.

  In forming the connection hole 67b, damage to the wiring pattern 53c can be suppressed by adopting etching conditions in which the sub conductive layer 55b serves as an etching stopper for the insulator film 49.

  Since a part of the connection hole 67b is formed in the opening 67c previously formed in the wiring pattern 40c, it is possible to minimize or eliminate the damage to the wiring pattern 40c with the formation of the connection hole 67b. In this example, the main conductive layer 42 of the wiring pattern 40c is an aluminum layer. However, when the main conductive layer 42 is a copper layer, it is particularly effective to provide the opening 67c in advance. Since copper is difficult to dry etch, by providing the opening 67c in advance, the connection hole 67b can be opened without etching the copper layer. In the embodiment in which the large-diameter connection hole 67a and the small-diameter connection hole 67b are formed as in this example, the main conductive layer 42 such as an aluminum layer is etched without providing the opening 67c in advance. The connection hole 67b may be formed by the above.

  Further, in the formation of the small-diameter connection hole 67b, an etching method having a large selection ratio between the wiring pattern 40c and the insulator film 39 is adopted, so that the connection hole 67a is self-aligned using the wiring pattern 40c as an etching mask. A connection hole 67b having a smaller diameter can be formed. That is, the same mask pattern can be used. Note that the width of the connection hole 67b may be larger than the width of the opening 67c or may be smaller than the width of the opening 67c. When the width of the connection hole 67b is larger than the width of the opening 67, the formation of the connection hole 67b is accompanied by the removal of the wiring pattern 40c, and the side surface of the wiring pattern 40c can be exposed. When the width of the connection hole 67b is smaller than the width of the opening 67c, it is considered that the formation of the connection hole 67b does not cause the removal of the wiring pattern 40c and the side surface of the wiring pattern 40c is not exposed.

  This will be described with reference to FIG. Next, the sub conductive layer 41a of the wiring pattern 40c and the sub conductive layer 55b of the wiring pattern 53c corresponding to the bottoms of the connection holes 67a and 67b are removed by etching. As a result, the main conductive layer 42 of the first wiring 311 and the main conductive layer 56 of the second wiring 512 are exposed in the through hole 67. It is not essential to remove the exposed portion of the sub conductive layer 41a and / or the sub conductive layer 55b of the wiring pattern 53c, and the sub conductive layer 55b may be left exposed.

  Thereafter, a conductive material is embedded in the through hole 67. When copper is used as the conductive material, copper may diffuse from the exposed surfaces of the main conductive layers 42 and 56, which are aluminum layers. This copper diffusion is a reliable connection between the first wiring 311 and the second wiring 512. May be reduced. In particular, when the side surfaces and the upper surfaces of the main conductive layers 42 and 56 of the aluminum layer become exposed surfaces, copper may diffuse from the side surfaces of the aluminum layer. Therefore, it is preferable to form the diffusion prevention film 69 along the inner surface of the through hole 67 prior to embedding the conductive material (copper). The portion of the diffusion prevention film 69 that protrudes from the through hole 67 can be removed together with the conductive material when planarized by CMP after the conductive material is buried. As the material of the diffusion preventing film 69, metals such as titanium, titanium nitride, titanium carbide, tantalum, tantalum nitride, and tantalum carbide, and metal compounds can be used. The diffusion prevention film 69 may be a titanium layer, a titanium compound layer, a single layer of a tantalum layer and a tantalum compound layer, or a multilayer film including two or more layers selected from these. Thus, the conductive member 68 has a structure having a buried layer made of a conductive material (copper) and a diffusion prevention layer against diffusion of the buried material into the wiring pattern.

  The positional relationship among the through hole 67, the first wiring 311 and the second wiring 512 will be described with reference to FIG. FIG. 6 is a plan view schematically showing a state when the through hole 67 of FIG. 2 is formed.

  This will be described with reference to FIGS. 6 (a-1), (a-2), and (a-3). It is the schematic diagram which showed the place where a part of through-hole 67 is in contact with 2nd wiring from the upper surface. Here, the width of the through hole 67 is a.

  FIG. 6A-2 shows a case where the through hole 67 is formed as designed in the photomask. FIG. 6A-1 shows a state where the through hole 67 is shifted leftward by a distance b with respect to the state of FIG. 6A-2. FIG. 6A-3 shows a state in which the through hole 67 is shifted rightward by a distance b with respect to the state of FIG. 6A-2. The rightward direction is positive, and the leftward shift amount is negative. In the state of FIG. 6A-1 and FIG. 6A-3, the conductive member 68 contacts only one of the second wiring 512 and the first wiring 311 even if a conductive material is embedded in the through hole 67. Connection between wiring is not possible.

  FIG. 6B-2 shows a case where the through hole 67 is formed as designed in a photomask different from the photomask described in FIG. 6A-2. FIG. 6B-1 shows a state in which the through hole 67 is shifted leftward by a distance b with respect to the state of FIG. 6B-2. FIG. 6B-3 shows a state in which the through hole 67 is shifted to the right by the distance b with respect to the state of FIG. 6B-2. The rightward direction is positive, and the leftward shift amount is negative. In any of the states shown in FIGS. 6B-1, 6B-2, and 6B-3, the conductive member 68 can be connected to the second wiring 512 by connecting the conductive material into the through hole 67. Since both the 1 wiring 311 contacts, wiring connection can be performed.

  For this purpose, even if an alignment deviation of distance b occurs, the through hole 67 does not protrude from a region where the first wiring 311 and the second wiring 512 overlap (hereinafter referred to as a connection region) in the bonding process. In addition, a photomask for forming the through hole 67 may be designed. That is, in the mask pattern on the photomask, which means an ideal formation position of the through hole 67, the formation position of the through hole 67 is separated from the end of the connection region by the distance c. That is, the width of the connection region may be made larger than the width a of the through hole. The distance c is preferably set to be equal to or longer than the assumed alignment displacement distance b. The distance b depends on the performance of the exposure apparatus used for patterning the photoresist for forming the through hole 67, but may be less than 1 μm, for example. Therefore, the distance c is preferably 1 μm or more. In relation to the diameter of the through hole 67, the distance b is less than a / 10. Therefore, the distance c is preferably a / 10 or more. Naturally, since the outline of the connection region is determined by at least the outline of the first wiring 311, it is preferable to design the photomask so that the through hole 67 is formed at a distance c or more from the end of the first wiring 311. . In addition, as long as a through-hole is formed using the mask pattern on a photomask which means an ideal formation position, a through-hole does not need to be formed in the position according to a mask pattern. For example, the design that the through hole is surrounded by the first wiring 311 on the mask pattern is substantially equivalent to the formation of the through hole surrounded by the first wiring 311 as long as this mask is used. The same.

  A method for manufacturing a semiconductor device including the bonding process and the connection process described in this embodiment will be summarized.

  In the connecting step, the first component 10a and the second component 20a are joined. The first component 10 a includes a first element unit 30 including a first semiconductor layer 303 and a first wiring unit 31 including a first wiring 311 electrically connected to the first element unit 30. The second component 20 a includes a second element unit 50 including a second semiconductor layer 505 and a second wiring unit 51 including a second wiring 512 electrically connected to the second element unit 50.

  The joining process is performed so that the first wiring part 31 and the second wiring part 51 are located between the first element part 30 and the second element part 50. In the bonding step, the wiring pattern 40c and the wiring pattern 53c can be overlapped.

  In the connecting step, a conductive member 68 that contacts both the wiring pattern 40c constituting the first wiring 311 and the wiring pattern 53c constituting the second wiring 512 is formed to electrically connect the first wiring 311 and the second wiring 512 to each other. Connect to.

  The connecting step includes a first step of forming a through hole 67 that penetrates the first component 10a and exposes the wiring pattern 53c. Further, the through hole 67 can expose a portion of the wiring pattern 53c that overlaps the wiring pattern 40c at the time of the bonding process. The through hole 67 can be formed such that the through hole 67 exposes the wiring pattern 40c. The through hole 67 can be formed so as to be positioned between a plurality of portions of the wiring pattern 40c. Further, the through hole 67 can be formed by removing a portion of the wiring pattern 40c that overlaps the wiring pattern 53 at the time of the bonding process. Further, the connecting step includes a second stage in which the conductive member 68 that contacts both the wiring pattern 40 c and the wiring pattern 53 c exposed in the through hole 67 is formed in the through hole 67.

  By doing so, a semiconductor device with high performance and reliability of electrical connection between the first wiring 311 and the second wiring 512 by the conductive member 68 can be provided.

303 1st semiconductor layer 30 1st element part 40c wiring pattern 31 1st wiring part 311 1st wiring 505 2nd semiconductor layer 50 2nd element part 53c wiring pattern 51 2nd wiring part 512 2nd wiring 67 through-hole 68 conductive member

Claims (19)

A first element portion including a first semiconductor layer provided with a photoelectric conversion element;
A first wiring portion including a first wiring pattern;
A second element portion including a second semiconductor layer;
A second wiring portion including a second wiring pattern, and a semiconductor device comprising:
The first wiring portion and the second wiring portion are located between the first semiconductor layer and the second semiconductor layer, and the first wiring portion is located between the first semiconductor layer and the second wiring portion. Is located,
The first through the semiconductor layer, the conductive member is provided in contact with said first wiring pattern and the second wiring pattern,
Between the first semiconductor layer and the conductive member, an insulating region in contact with the conductive member is provided,
The conductive member has a portion located between a first portion and a second portion of the first wiring pattern ;
The first wiring pattern includes at least one of a first conductive layer and a titanium layer, a titanium compound layer, a tantalum layer, and a tantalum compound layer disposed on a surface of the first conductive layer on the first element portion side. Including a layer, and
The conductive member includes a side surface of the first portion facing the conductive member, a side surface of the second portion facing the conductive member, and a diffusion prevention film that contacts the insulating region. device.   The semiconductor device according to claim 1, wherein the conductive member is surrounded by the first wiring pattern. The conductive member penetrates through a first insulator layer located between the first wiring pattern and the first semiconductor layer, and is located between the first wiring pattern and the second wiring pattern. Penetrates the insulator layer,
3. The semiconductor device according to claim 1, wherein a width of a portion of the conductive member that penetrates the first insulator layer is larger than a width of a portion of the conductive member that penetrates the second insulator layer. The semiconductor device according to claim 3 , wherein a conductive material other than titanium, a titanium compound, tantalum, and a tantalum compound is embedded in the through hole in the first semiconductor layer . An insulator is located between the first semiconductor layer and the first wiring pattern,
The semiconductor device according to claim 4 , wherein the insulating region is provided between the conductive member and the insulator . The semiconductor device according to claim 5 , wherein the insulator is an interlayer insulating layer included in the first wiring portion . The first conductive layer is a copper layer, a tungsten layer or an aluminum layer,
The layer includes at least one of a tantalum layer, a tantalum nitride layer, a titanium layer, or a titanium nitride layer,
The semiconductor device according to claim 6 , wherein the conductive member is in contact with the first conductive layer and the layer . The second wiring pattern includes a second conductive layer and a layer including at least one of a titanium layer, a titanium compound layer, a tantalum layer, and a tantalum compound layer,
The semiconductor device according to claim 7 , wherein the conductive member penetrates through the layer included in the second wiring pattern and contacts the second conductive layer . The first portion and the second portion, the semiconductor device according to any one of claims 1 to 8 overlapping the second wiring pattern. The semiconductor device according to claim 1, wherein the conductive member is in contact with a surface of the first wiring pattern on the first semiconductor layer side .   The semiconductor device according to claim 1, wherein the second semiconductor layer is thicker than the first semiconductor layer. The semiconductor device according to claim 1, wherein a wiring pattern different from the first wiring pattern is provided between the first wiring pattern and the first semiconductor layer . The semiconductor device according to claim 1 , wherein the diffusion prevention film includes at least one of a titanium layer, a titanium compound layer, a tantalum layer, and a tantalum compound layer . The semiconductor device according to any one of claims 1 to 13, wherein the diffusion prevention film includes at least one of titanium nitride, titanium carbide, tantalum nitride, and tantalum carbide . 15. The semiconductor device according to claim 1 , further comprising an optical member including a microlens array disposed on a side opposite to the first wiring portion side with respect to the first element portion . The semiconductor device according to claim 15, wherein a layer included in the optical member covers the conductive member . A semiconductor device according to any one of claims 1 to 16,
A package containing the semiconductor device and having a terminal;
A semiconductor device in which an opening for connection with the terminal is provided in the first semiconductor layer. A semiconductor device according to any one of claims 1 to 17,
A package containing the semiconductor device;
A circuit board on which the package is mounted ,
A semiconductor device including an optical system for guiding light to the semiconductor device. A semiconductor device comprising the semiconductor device according to any one of claims 1 to 18 ,
An electronic device comprising a peripheral device connected to the semiconductor device,
The electronic apparatus according to claim 1, wherein the peripheral device is an arithmetic device, a storage device, a recording device, a communication device, or a display device.

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