JP6632670B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

  The present invention relates to a semiconductor device having a plurality of element portions.

  2. Description of the Related Art In a photoelectric conversion device such as a CMOS image sensor which is a kind of a semiconductor device, a photoelectric conversion unit having a plurality of photoelectric conversion elements and a signal processing unit for processing an electric signal from the photoelectric conversion unit are monolithically formed on one semiconductor substrate. I was making it. It has been studied to form the photoelectric conversion unit and the signal processing unit separately on separate components (chips), overlap these components, and electrically connect the components with a conductive member. By doing so, the occupied area (footprint) of the photoelectric conversion device in the electronic device on which the photoelectric conversion device is mounted can be efficiently used. Such a structure can be applied to various semiconductor devices that realize a so-called system-in-package.

  In Patent Document 1, a through-connection conductor (64), a connection conductor (65), and a connection wiring (72) are provided as conductive members for obtaining electrical connection between semiconductor substrates (3445) corresponding to components. (See FIG. 3 of Patent Document 1). Alternatively, it is described that one through connection conductor (84) is provided as a conductive member (see FIG. 15 of Patent Document 1).

JP 2010-245506 A

  The technique of Patent Document 1 does not sufficiently study the electrical connection. When the penetrating connection conductor (64) and the connection conductor (65) are provided and connected by the connection wiring (72), the wiring capacity and the wiring resistance are increased by penetrating the semiconductor layer twice, and the wiring delay is caused by the wiring delay. There is a problem that the performance of the semiconductor device may be reduced. Further, when the through connection conductor (84) is used, poor connection between the through connection hole (85), the wiring (40), and the wiring (53) occurs due to misalignment at the time of manufacturing and / or cracking during use. There is a problem that it is easy.

  Therefore, an object of the present invention is to provide a semiconductor device with high performance and reliability of electrical connection by a conductive member.

  Means for solving the problem is a method of manufacturing a semiconductor device, comprising: a first element portion including a first semiconductor layer; and a first line including a first line electrically connected to the first element portion. , A first element having a first element, a second element section including a second semiconductor layer, and a second wiring section including a second wiring electrically connected to the second element section. Bonding the first wiring portion and the second wiring portion so that the first wiring portion and the second wiring portion are located between the first device portion and the second device portion; and a first wiring forming the first wiring portion A connection step of forming a conductive member in contact with both the pattern and the second wiring pattern forming the second wiring to electrically connect the first wiring and the second wiring. A through hole that penetrates the first component and exposes the second wiring pattern; A first step of exposing the first wiring pattern and forming the through hole so as to be located between a plurality of portions of the first wiring pattern; and a first step of exposing the first wiring pattern to the through hole and Forming the conductive member in contact with both of the second wiring patterns in the through hole.

  Further, a means for solving the problem is a method of manufacturing a semiconductor device, comprising: a first element portion including a first semiconductor layer; and a first element portion including a first wiring electrically connected to the first element portion. A first component having a first wiring portion, a second element portion including a second semiconductor layer, and a second wiring portion including a second wiring electrically connected to the second element portion. A joining step of joining the two components so that the first wiring section and the second wiring section are located between the first element section and the second element section; and a second step of forming the first wiring section. Forming a conductive member in contact with both the first wiring pattern and the second wiring pattern forming the second wiring, and electrically connecting the first wiring and the second wiring. The bonding step is performed such that the first wiring pattern and the second wiring pattern overlap. The connecting step includes penetrating the first component, exposing a through-hole exposing a portion of the second wiring pattern overlapping the first wiring pattern in the joining step, and exposing the through-hole exposing the first wiring pattern. And a first step of forming a portion of the first wiring pattern overlapping the second wiring pattern in the joining step, and the first wiring pattern and the second wiring pattern exposed in the through-hole. A second step of forming the conductive member in contact with both in the through hole.

  Means for solving the problem is a semiconductor device, comprising: a first element portion including a first semiconductor layer; and a first wiring portion including a first wiring electrically connected to the first element portion. A second element portion including a second semiconductor layer, and a second wiring portion including a second wiring electrically connected to the second element portion, wherein the first element portion The first wiring part and the second wiring part are located between the first wiring part and the second wiring part, and the first wiring part is located between the first wiring part and the second wiring part; A conductive member penetrating the first element portion and the first wiring portion and in contact with a first wiring pattern of the first wiring and a second wiring pattern of the second wiring is provided. A part penetrating one wiring part is located between a plurality of parts of the first wiring pattern.

  According to the present invention, it is possible to provide a semiconductor device having high performance and reliability of electrical connection by a conductive member.

FIG. 13 is a schematic view of an example of a semiconductor device. FIG. 13 is a schematic view of an example of a semiconductor device. FIG. 4 is a schematic view of an example of a method for manufacturing a semiconductor device. FIG. 4 is a schematic view of an example of a method for manufacturing a semiconductor device. FIG. 9 is a schematic view of another example of the method for manufacturing a semiconductor device. 6A to 6C are schematic views illustrating a method for manufacturing a semiconductor device.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In the following description, a plurality of drawings may be referred to each other. The same or similar components are denoted by the same reference numerals, and the description of the components denoted by the same reference numerals will be appropriately omitted.

  A photoelectric conversion device as an example of the semiconductor device of the present embodiment will be described with reference to FIG. FIG. 1A is a perspective view of a semiconductor device 1 which is a main part of a semiconductor device. 1B and 1C are exploded perspective views of an example of the semiconductor device 1. FIG. FIG. 1D is a schematic diagram of a semiconductor device 3 including the semiconductor device 1 and an electronic device 5.

  In the semiconductor device 1 shown in FIG. 1A, the first part 10 and the second part 20 overlap as shown in FIG. 1B or FIG. The present embodiment mainly relates to a conductive member for obtaining an electrical connection between the first portion 10 and the second portion 20. The first portion 10 includes a first element unit 30 and a first wiring unit 31. The second part 20 includes a second element part 50 and a second wiring part 51. The second wiring part 51 is located between the first part 10 and the second element part 50. In the present embodiment, the first wiring part 31 of the first part 10 is located between the first element part 30 and the second element part, but the first element part 30 of the first part 10 is And the second element unit 50.

  In the present embodiment, the first portion 10 includes the photoelectric conversion unit 11 that generates a signal charge according to incident light. The photoelectric conversion unit 11 includes a photoelectric conversion element. The photoelectric conversion unit 11 may include a signal generation circuit that generates an electric signal based on a signal charge generated in the photoelectric conversion element. The signal generation circuit includes, for example, an amplification transistor, a transfer transistor, a reset transistor, and a selection transistor. The photoelectric conversion unit 11 of another example may include a photoelectric conversion element and a charge coupled device (CCD) for transferring signal charges.

  In the present embodiment, the second part 20 has a signal processing unit 22. The signal processing unit 22 processes an electric signal based on the signal charge generated by the photoelectric conversion unit 11. The signal processing unit 22 can include a noise removal circuit, an amplification circuit, a conversion circuit, and an image processing circuit. The noise elimination circuit is, for example, a CDS (Correlated Double Sampling: correlated double sampling) circuit. The amplifier circuit is, for example, a column amplifier circuit. The conversion circuit is, for example, an ADC (Analog Digital Converter) circuit including a comparator and a counter. The image signal processing circuit includes, for example, a memory and a processor, and generates image data from a digital signal that has been converted from analog to digital, and performs image processing on the image data.

  In FIG. 1A, the position of the photoelectric conversion unit 11 is indicated by a dashed line, and the position of the signal processing unit 22 is indicated by a dashed line. Here, a part of the signal processing unit 22 is located in a part of an orthographic region of the photoelectric conversion unit 11 onto the second part 20. However, all or a part of the signal processing unit 22 may be located in the entire orthographic region of the photoelectric conversion unit 11 onto the second portion 20. Alternatively, all or a part of the signal processing unit 22 may be located in a part of the orthogonal projection area of the photoelectric conversion unit 11 in the second part 20. Note that a part of the signal processing unit 22 may be provided in the first part 10. For example, a signal processing unit for an analog signal such as a noise removal circuit or an amplifier circuit may be provided in the first part 10, and a signal processing unit for a digital signal such as a conversion circuit or an image processing circuit may be provided in the second part 20.

  As shown in FIGS. 1B and 1C, the semiconductor device 1 can further include a control unit 12 for controlling the photoelectric conversion unit 11 and / or a control unit 21 for controlling the signal processing unit 22. . These control units can be provided on at least one of the first part 10 and the second part 20. In the example shown in FIG. 1B, the control unit 12 is provided in the first part 10, and in the example shown in FIG. 1C, the control unit 21 is provided in the second part 20. A control unit for the photoelectric conversion unit 11 may be provided in the first part 10, and a control unit for the signal processing unit 22 may be provided in the second part 20. The control unit 12 may include a vertical drive circuit that supplies a drive signal to a pixel circuit via a vertical scan line, and a power supply circuit. The control unit 21 may include a timing generation circuit for driving the signal processing unit 22, a reference signal supply circuit for supplying a reference signal to the conversion circuit, a horizontal scanning circuit for sequentially reading signals from the amplification circuit or the conversion circuit.

  As shown in FIG. 1D, the semiconductor device 3 can include a package 2 as a mounting member for the primary mounting of the semiconductor device 1. The semiconductor device 1 can be die-bonded and accommodated in this package. The package 2 may include external terminals such as PGA (Pin Grid Array), LGA (Land Grid Array), BGA (Ball Grid Array), and a lead frame. As shown in FIG. 1D, the semiconductor device 3 can include a circuit board 4 as a mounting member for secondary mounting. The package 2 can be mounted on the circuit board 4. The circuit board 4 may be a printed board such as a rigid board, a flexible board, or a rigid flexible board. The semiconductor device 3 as a photoelectric conversion device may include an optical system for guiding light to the semiconductor device 1.

  The semiconductor device 3 can be mounted on various electronic devices. The electronic device 5 includes a peripheral device 6 such as an arithmetic device, a storage device, a recording device, a communication device, or a display device, in addition to the semiconductor device 3. These peripheral devices are connected to the semiconductor device 3 and exchange signals directly or indirectly. Examples of the electronic device 5 include information terminals such as mobile phones and personal computers, and video devices such as cameras and displays. Of course, an information terminal with a camera is also included.

  Details of an example of the semiconductor device 1 will be described with reference to FIG. FIG. 2 is a cross-sectional view of the semiconductor device 1 on a plane including the points P and Q shown in FIG. FIG. 2 shows an example having a control unit 12 as shown in FIG.

  In the following description, the conductor layer is made of a material having higher conductivity than the semiconductor layer, and the insulator layer is made of a material having lower conductivity than the semiconductor layer.

  In the following description of semiconductor compounds and metal compounds, carbonitrides and oxynitrides are included in nitrides. Nitride carbide and oxycarbide are included in carbide.

  First, with respect to the first portion 10, the respective configurations of the first element portion 30 and the first wiring portion 31 will be described.

  The first element unit 30 includes a first semiconductor layer 303. The first semiconductor layer 303 is, for example, a silicon layer. The first element unit 30 includes a photodiode PD provided in the first semiconductor layer 303 as a semiconductor element (photoelectric conversion element) that configures the photoelectric conversion unit 11 in FIG. The photodiode PD includes the p-type semiconductor region 32, the n-type semiconductor region 34, and the p-type semiconductor region 35 of the first semiconductor layer 303. The photoelectric conversion element may be a photogate. The photoelectric conversion unit 11 may include a signal generation circuit that generates an electric signal based on a signal charge generated in the photoelectric conversion element. The signal generation circuit can be configured by a semiconductor element such as a MOS transistor. FIG. 2 shows the transfer transistor Tr1 and the reset transistor Tr2 of the photoelectric conversion unit 11 of the first part 10. Also, transistors Tr3 and Tr4 are shown as semiconductor elements of the control unit 12 of the first portion 10 in FIG.

  In this example, a part of the surface 103 of the first semiconductor layer 303 constituting the first element section 30 forms an interface with the gate insulating films of the MOS transistors Tr1, Tr2, Tr3, Tr4. The first element unit 30 is provided with an element isolation 38 such as STI (Shallow Trench Isolation) or LOCOS (LOCal Oxidation of Silicon). On the first semiconductor layer 303, a first protective film (not shown) made of an insulator layer such as silicon nitride or silicon oxide is provided to protect the surface 103 of the first semiconductor layer 303. As described above, the first element section 30 may include the element isolation 38, the gate insulating film, the gate electrode, and the first protective film in addition to the first semiconductor layer 303.

  The first wiring section 31 includes a conductor layer and an insulator layer. The first wiring unit 31 may have a plurality of wiring levels. One wiring level may have a wiring pattern and a plug. A typical conductor layer forms a wiring pattern. Further, a typical conductive layer forms a main conductive layer having a large current density in a wiring pattern, but a conductive layer forms a sub-conductive layer having a smaller current density than the main conductive layer in a wiring pattern. There is also. The conductor layer may constitute a via plug for obtaining conduction with a lower wiring level or a contact plug for obtaining conduction with the first element portion 30 in some cases.

  Via plugs and contact plugs can also be composed of a main conductive layer and a sub-conductive layer. These sub-conductive layers can typically be barrier metals. Examples of the barrier function of the barrier metal include a barrier against diffusion between the main conductive layer and the insulator layer or a barrier against a reaction between the main conductive layer and the insulator layer. However, the “barrier metal” is a convenient name given to the sub-conductive layer, and does not necessarily have any barrier function. Even when these barrier functions are not required, the barrier metal can be used simply as a base for forming the main conductive layer or for the purpose of alleviating electromigration and stress migration.

  The insulator layer can function as an inter-wiring insulating layer that insulates wiring patterns of the same wiring level and / or an interlayer insulating layer that insulates wiring patterns of different wiring levels. The first wiring portion 31 has a large number of electric paths (wirings) formed of one or more conductive layers. One wiring can be composed of a contact plug, a via plug, and a wiring pattern.

  The detailed configuration of the first wiring unit 31 will be described. The first wiring portion 31 is provided with a contact plug 44, wiring patterns 40a, 40b, 40c and a via plug. These contact plugs, wiring patterns, and via plugs formed of the conductor layer form a number of electric paths. The contact plug 44 is mainly made of a tungsten layer, and has a barrier metal including a titanium layer and / or a titanium nitride layer in addition to the tungsten layer. The wiring patterns 40a, 40b, 40c and the via plug are mainly made of a copper layer, and have a barrier metal including a tantalum nitride layer and / or a tantalum layer in addition to the copper layer. The wiring pattern 40a is formed by one copper layer, and the wiring pattern 40b and the via plug, and the wiring pattern 40c and the via plug are each integrally formed by one copper layer. The first wiring 311 of this example includes a wiring pattern 40c, and is connected to the semiconductor element at a portion (not shown) through the contact plug 44 via the wiring patterns 40a and 40b and the via plug.

  The first wiring portion 31 is provided with an insulator film 39 including an insulator layer mainly made of silicon oxide, as an interlayer insulating layer or an inter-wiring insulating layer. A typical insulator film 39 is a multilayer film having a plurality of insulator layers. The insulator film 39 of the first wiring portion 31 can further include an insulator layer (not shown) made of silicon nitride, silicon carbide, or the like as a copper diffusion prevention layer contained in the wiring patterns 40a, 40b, and 40c. . These can be arranged between the interlayer insulating layer and the wiring pattern.

  Next, with respect to the second portion 20, the respective configurations of the second element portion 50 and the second wiring portion 51 will be described.

  The second element section 50 includes a second semiconductor layer 505 and has MOS transistors Tr5, Tr6, Tr7, and Tr8 as semiconductor elements constituting the signal processing unit 22. In this example, part of the surface 203 of the second semiconductor layer 505 forms an interface with the gate insulating films of the MOS transistors Tr5, Tr6, Tr7, and Tr8. The second element section 50 is provided with an element isolation 58 such as STI or LOCOS. On the second semiconductor layer 505, a second protective film (not shown) made of an insulator such as silicon nitride or silicon oxide for protecting the surface 203 of the second semiconductor layer 505 is provided. The second element unit 50 may include an element isolation 58, a gate insulating film, a gate electrode, and a second protective film in addition to the second semiconductor layer 505.

  The second wiring section 51 includes a conductor layer and an insulator layer. The conductor layer and the insulator layer of the second wiring part 51 also have the same functions as the conductor layer and the insulator layer of the first wiring part 31.

  The detailed configuration of the second wiring unit 51 will be described. The second wiring portion 51 is provided with a contact plug 54a, a plurality of wiring patterns 53a, 53b, 53c and via plugs 54b, 54c. These contact plugs, wiring patterns, and via plugs formed of the conductor layer form a number of electric paths. The contact plug 54a and the via plug 54c are mainly made of a tungsten layer, and have a barrier metal including a titanium layer and / or a titanium nitride layer in addition to the tungsten layer. The wiring patterns 53a and 53b and the via plug 54b are mainly made of a copper layer, and have a barrier metal including a tantalum nitride layer and / or a tantalum layer in addition to the copper layer. The wiring pattern 53a includes one copper layer. The wiring pattern 53b and the via plug 54b are integrally formed by one copper layer. The wiring pattern 53c is mainly made of an aluminum layer, and has a barrier metal including a titanium layer and / or a titanium nitride layer in addition to the aluminum layer. The second wiring 512 of this example includes a wiring pattern 53c, and is connected to the semiconductor element via a contact plug 54a (not shown) via the wiring patterns 53a and 53b and via plugs 54b and 54c.

  In the second wiring portion 51, an insulating film 49 including an insulating layer mainly made of silicon oxide is provided as an interlayer insulating layer or an interwiring insulating layer. A typical insulator film 49 is a multilayer film having a plurality of insulator layers. The insulator film 49 of the second wiring portion 51 can further include an insulator layer (not shown) made of silicon nitride or silicon carbide as a copper diffusion preventing layer contained in the wiring patterns 53a and 53b. These can be arranged between the interlayer insulating layer and the wiring pattern.

  In the wiring patterns 40a, 40b, 40c, 53a, 53b and plugs of the first wiring portion 31 and the second wiring portion 51, the copper layer, the tungsten layer, and the aluminum layer function as main conductive layers having high conductivity in the wiring. The main conductive layer is made of a material having higher conductivity than the sub-conductive layers such as a tantalum layer, a tantalum nitride layer, a titanium layer, and a titanium nitride layer used as a barrier metal, and has a small cross-sectional area in a direction in which current flows, Low resistance.

  Although the example in which the wiring patterns 40a, 40b, 40c, 53a, and 53b mainly include a copper layer has been described, a wiring pattern mainly including an aluminum layer, such as the wiring pattern 53c, may be employed. Note that the copper layer and the aluminum layer are not limited to simple copper, but may be alloys to which other metals are added. For example, the copper layer may include as an additive less aluminum, silicon, and the like than copper, and the aluminum layer may include less than aluminum as an additive, such as copper and silicon. Although the example in which the main insulator layer of the insulator film 39 is made of silicon oxide has been described, silicate glass such as BSG, PSG, or BPSG may be used. Alternatively, a material (low-k material) having a lower dielectric constant than silicon oxide can be used.

  The example in which the wiring pattern of the first wiring portion 31 has three levels of the wiring patterns 40a, 40b, and 40c and the wiring pattern of the second wiring portion 51 has three levels of 53a, 53b, and 53c has been described. However, the number of levels of the wiring pattern can be set as appropriate, and may be different between the first wiring portion 31 and the second wiring portion 51. For example, the number of levels of the wiring pattern of the second wiring section 51 may be larger than the number of levels of the wiring pattern of the first wiring section 31.

  Subsequently, another structure of the electronic device 1 will be described.

  The first part 10 and the second part 20 are joined at the first wiring part 31 and the second wiring part 51. The insulator film 39 of the first wiring portion 31 and the insulator film 49 of the second wiring portion 51 are joined via a joining surface 60.

  The semiconductor device 1 of this example is a back-illuminated photoelectric conversion device in which the surface (back surface 104) of the first semiconductor layer 303 opposite to the surface on which the transistors Tr1 to Tr4 are provided (back surface 104) is a light receiving surface. Constitute. In the back-illuminated photoelectric conversion device, the thickness of the first semiconductor layer 303 of the first portion 10 is less than 10 μm, for example, 2 to 5 μm. The thickness of the second semiconductor layer 505 is larger than that of the first semiconductor layer 303, and the second semiconductor layer 505 functions as a support for the first semiconductor layer 303. The thickness of the second semiconductor layer 505 is 10 μm or more, for example, 20 to 500 μm.

  The optical member 41 is provided on the back surface 104 side of the first semiconductor layer 303.

  The optical member 41 may include an anti-reflection layer 61, an insulator layer 62, a light shielding layer 63, an insulator layer 69, a flattening layer 71, a color filter array 73, and a microlens array 74. The optical member 41 is in contact with the p-type semiconductor region 32 constituting the light receiving surface (the back surface 104) of the first element unit 30. The optical member 41 has a light incident surface 401 on the side opposite to the first element section 30 side. In this example, the light incident surface 401 is constituted by the micro lens array 74.

  The electrode pads 78 are arranged on the same level as the wiring pattern 53c. On the electrode pad 78, an opening 77 penetrating the plurality of insulator layers, the first semiconductor layer 303, and the optical member 41 is provided. The opening 77 is provided with a bonding wire 79 connected to the electrode pad 78. Wire bonding is connected to the internal terminals of the package. Note that the connection between the semiconductor device 1 and the package is not limited to wire bonding connection, and flip-chip connection can also be used.

  The semiconductor device 1 is provided with a conductive member 68 that connects the first wiring 311 and the second wiring 512 to each other. The conductive material forming the conductive member 68 is gold, silver, copper, aluminum, tungsten, tantalum, titanium, manganese, or a compound such as a nitride or carbide thereof.

  The conductive member 68 penetrates through the first semiconductor layer 303 of the first element section 30 and connects to the first wiring 311 of the first wiring section 31, and further penetrates through the first wiring section 31 and forms the second wiring section 51. To the second wiring 512. In this example, the conductive member 68 contacts the wiring pattern 40c of the first wiring 311 and contacts the wiring pattern 53c of the second wiring 512. In the present embodiment, the conductive member 68 can be located between a plurality of portions of the wiring pattern 40c of the first wiring 311. In other words, a plurality of portions of the wiring pattern 40c sandwich the conductive member 68. The plurality of portions of the wiring pattern 40c that sandwich the conductive member 68 are portions facing the conductive member 68 (opposed portions). A portion of the conductive member 68 located between the plurality of portions of the wiring pattern 40c is a portion penetrating the first wiring portion 31. A plurality of portions (opposing portions) of the wiring pattern 40c sandwiching the conductive member 68 preferably overlap the wiring pattern 53c of the second wiring 512, but do not have to overlap. The overlapping portion of the two wiring patterns 40c and 53c is a portion of one wiring pattern that overlaps the other wiring pattern. Here, the overlapping of the wiring patterns means that a plurality of wiring patterns are located in the direction from the first semiconductor layer 303 to the second semiconductor layer 505 (the normal direction of the first semiconductor layer 303 and the second semiconductor layer 505). Means that.

  FIG. 2 (b-1) is a plan view when the conductive member 68 is surrounded by the first wiring 311. FIG. 2 (c-1) is a perspective view thereof. The wiring pattern 40c has portions 3111, 3112, 3113, and 3114. The conductive member 68 is located between the portion 3111 and the portion 3113, and is located between the portion 3112 and the portion 3114. The conductive member 68 is located between the portion 3111 and the portion 3112, and is located between the portion 3113 and the portion 3114. It is desirable that these portions 3111, 3112, 3113, and 3114 overlap the wiring pattern 53c forming the second wiring 512, but they do not have to overlap. These portions 3111, 3112, 3113, and 3114 are in contact with the conductive member 68. In this example, the conductive member 68 is in contact with the side surface of the first wiring 311. This side is composed of parts 3111, 3112, 3113, 3114. Here, the example in which the conductive member 68 is in contact with the side surface of the first wiring 311 has been described, but the conductive member 68 may be in contact with the upper surface of the first wiring 311 instead of the side surface of the first wiring 311. The conductive member 68 may be in contact with the side surface and the upper surface of the first wiring 311.

  FIG. 2B-2 is a plan view when the conductive member 68 is sandwiched between the first wirings 311. FIG. 2C-2 is a perspective view thereof. The wiring pattern 40c has portions 3115, 3116, and 3117. The conductive member 68 is located between the portion 3115 and the portion 3117. The conductive member 68 is located between the portion 3115 and the portion 3116 of the first wiring 311, and is located between the portion 3116 and the portion 3117. In the example of FIG. 2B-2, the conductive member 68 faces the side surfaces of three continuous portions 3115, 3116, and 3117 of the first wiring 311. The angle formed by the side surfaces of two sets of two of the three parts (the part 3115 and the part 3115 and the part 3116 and the part 3117) is 90 °. The angle formed by the side surfaces of one set of two portions (the portion 3115 and the portion 3117) of the three portions is 0 ° (parallel). As in the example of FIG. 2B-1, the portions 3115, 3116, and 3117 overlap the wiring pattern 53c forming the second wiring 512.

  FIG. 2B-3 is a plan view when the conductive member 68 is sandwiched between the first wirings 311. FIG. 2C-3 is a perspective view thereof. The wiring pattern 40c has portions 3118 and 3119. The two portions 3118 and 3119 are discontinuous portions of the wiring pattern 40c of the first wiring 311. In the example of FIG. 2B-3, the portions 3118 and 3119 overlap the wiring pattern 53c of the second wiring 512. The conductive member 68 is sandwiched between the side surfaces of the portions 3118 and 3119. In the example of FIG. 2B-3, the angle between the two portions 3118 and 3119 of the conductive member 68 is 0 ° (parallel). 2 (b-3) and 2 (c-3), both of the two portions 3114 and 3115 of the first wiring 311 sandwiching the conductive member 68 have the first shape even if the conductive member 68 is replaced with an insulating member. It may be a part of the wiring 311. Here, an example is shown in which the two portions 3118 and 3119 are electrically continuous in the wiring pattern 40c. However, the two portions may be electrically continuous via another wiring level such as the wiring patterns 40b and 40a to form the first wiring 311 as one electric path.

  The fact that the conductive member 68 is located between the plurality of portions of the wiring pattern of the first wiring 311 means that the surfaces of the plurality of portions facing the conductive member 68 (opposing surfaces) have an angle of 180 degrees on the conductive member 68 side. Means less than °. In other words, it is only necessary that the facing surface is not composed of only one plane. Here, the example in which the opposing surface is configured by combining a plurality of planes is described, but the conductive member 68 may face a side surface having no clear boundary such as a smooth curved surface. It is preferable that an angle on the conductive member 68 side formed by a surface (opposing surface) facing the conductive member 68 of the plurality of portions is 90 ° or less. For example, if the conductive member 68 has a columnar shape and the side surface of the wiring pattern 40c has an arc shape in plan view, it is preferable that the central angle of the arc be 90 ° or more. This is because the angle between the tangent at one end of the arc and the tangent at the other end is 90 ° or more.

  The conductive member 68 may contact one or more of the wiring patterns 40a, 40b, and 40c, and the conductive member 68 may contact one or more of the wiring patterns 53a, 53b, and 53c. The conductive member 68 may come into contact with the main conductive layer of the wiring pattern, or may come into contact with a sub-conductive layer such as a barrier metal of the wiring pattern. In some cases, the wiring pattern penetrates through the sub-conductive layer of the barrier metal and contacts the main conductive layer. In this example, the side surface of the aluminum layer that is the main conductive layer 42 of the wiring pattern 40c and the side surface of the titanium nitride layer (and the titanium layer) that is the sub-conductive layers 41a and 41b are in contact with each other. The conductive member 68 is surrounded or sandwiched between the side surfaces of the main conductive layer 42. In addition, the wiring pattern 53c is in contact with the upper surface of the aluminum layer that is the main conductive layer 56 and the side surfaces of the titanium nitride layer (and the titanium layer) that is the sub-conductive layers 55a and 55b.

  In the present embodiment, the electric path of the first wiring 311 and the second wiring 512 does not pass through the outside of the first wiring section 31 and the second wiring section 51 and is in the first wiring section 31 and the second wiring section 51. Is formed. Accordingly, an increase in wiring capacitance and / or wiring resistance between the first wiring 311 and the second wiring 512 can be suppressed, and the semiconductor device can operate at high speed.

  Further, electrical connection between the first wiring 311 and the conductive member 68 can be ensured at a plurality of portions located on both sides of the conductive member 68. Therefore, a structure is obtained in which poor connection between the first wiring 311 and the conductive member 68 does not easily occur. One cause of the connection failure may be a crack resulting from a thermal cycle during use, or a chemical change such as corrosion or diffusion of the conductive member 68 or the wiring pattern 40c. In addition, one cause of the connection failure may be misalignment at the time of manufacturing described later.

  The conductive member 68 is surrounded by the insulating region 45 provided in the first semiconductor layer 303. Although the insulating region 45 in this example is a solid region, it may be a gas or vacuum region. The conductive member 68 electrically connects the photoelectric conversion unit 11 and the signal processing unit 22, or the photoelectric conversion unit 11 and the control unit 21, or the control unit 12 and the signal processing unit 22. Alternatively, a part of the signal processing unit provided in the first part 10 and a part of the signal processing unit provided in the second part 20 are electrically connected.

  A block 90 shown in FIG. 2 indicates a region including the conductive member 68, the first wiring 311, the second wiring 512, and the insulating region 42 related to the connection between the portions. Preferably, a plurality of the blocks 90 are arranged in parallel. By arranging a plurality of blocks 90 in parallel, signals for each column or each row of the photoelectric conversion unit 11 are transferred to the signal processing unit 22, and the signal processing unit 22 generates an electric signal based on the signal charges generated in the photoelectric conversion unit 11. The signal can be processed. In addition, the blocks 90 may be arranged in columns, or both columns and parallel may be used.

  The above is an example of the configuration of the semiconductor device 1. These configurations can be changed as appropriate.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 3 and 4 are cross-sectional views showing the same part as that of FIG. 2 (the plane including the points P and Q in FIG. 1).

  This will be described with reference to FIG. A first semiconductor substrate 303a is prepared. The first semiconductor substrate 303a is, for example, a silicon substrate. An element isolation 38 such as STI is formed on the first surface (front surface) 103 of the first semiconductor substrate 303a. Next, the photodiode PD and the transistors Tr1, Tr2, Tr3, Tr4 are formed on the first semiconductor substrate 303a. Thus, the first element section 30 is formed.

  Next, an interlayer insulating layer is formed on the first element section 30, and a contact plug 44 is formed in the interlayer insulating layer. A wiring pattern 40a is formed using a single damascene method so as to connect to the contact plug 44. After an interlayer insulating layer is further formed, a wiring pattern 40b and a via plug, and a wiring pattern 40c and a via plug are formed by using a dual damascene method. Thereafter, an insulator layer serving as a surface layer of the insulator film 39 is formed on the wiring pattern 40c, and is flattened. Thus, the first wiring section 31 is formed. A first wiring 311 is formed in the first wiring section 31.

  As described above, the first part 10a to be the first part 10 is created.

  This will be described with reference to FIG. A second semiconductor substrate 505a is prepared. The second semiconductor substrate 505a is, for example, a silicon substrate. The element isolation 38 such as STI is formed on the first surface (front surface) 203 of the second semiconductor substrate 505a. Next, Tr5, Tr6, Tr7, Tr8 are formed on the second semiconductor substrate 505a. Thus, the second element section 50 is formed.

  Next, an interlayer insulating layer is formed on the second element unit 50, and a contact plug 54a is formed in the interlayer insulating layer. A wiring pattern 53a is formed using a single damascene method so as to connect to the contact plug 54a. After an interlayer insulating layer is further formed, a wiring pattern 53b and a via plug 54b, a wiring pattern 53c and a via plug 54c are formed by using a dual damascene method. After that, an insulator layer serving as a surface layer of the insulator film 49 is formed, and is flattened. Thus, the second wiring section 51 is formed. The second wiring portion 51 has a second wiring 512 formed therein.

  As described above, the second part 20a to be the second part 20 is created.

  This will be described with reference to FIG. The first component 10a and the second component 20a are prepared as described above, and the first component 10a and the second component 20a are connected to each other, the first component 10a and the second component 20a are connected to the first element unit 30, and the second component 20a. The first wiring part 31 and the second wiring part 51 are joined so as to be located between the element part 50 and the element part 50. This bonding is performed by plasma bonding between the flattened surface layer of the insulator film 39 and the surface layer of the insulator film 49, and between the metal layers exposed on the surfaces of the first wiring portion 31 and the second wiring portion 51. It can be realized by metal bonding or bonding via an adhesive layer. At this time, it is preferable to join the wiring patterns 40c of the first wiring 311 and the wiring pattern 53c of the second wiring 512 so as to overlap. At the time of manufacturing the first component 10a and the second component 20a, the positional relationship between the first wiring 311 and the second wiring 512 is set. All of one of the wiring pattern 40c of the first wiring 311 and the wiring pattern 53c of the second wiring 512 may overlap with the other, or one of them may overlap with the other. Between the wiring pattern 40c of the first wiring 311 and the wiring pattern 53c of the second wiring 512, an insulator layer forming the surface layer of the planarized insulator film 39 and a surface layer of the planarized insulator film 49 are provided. The insulator layer to be formed is located. Note that the insulator layer forming at least one surface layer of the insulator films of the first wiring portion 31 and the second wiring portion 51 may be omitted, and the wiring pattern may be exposed on the surface of the wiring portion.

  Next, the first semiconductor substrate 303a is thinned from the side opposite to the first wiring section 31 side (the back side) of the first element section 30 to the position 104 to obtain the first semiconductor layer 303. This thinning is performed by a known method such as polishing such as CMP, grinding such as grinding, and etching. This thinning means that the thickness of the first semiconductor layer 303 after the thinning of the first semiconductor substrate 303a is 500 μm or less, and further 10 μm or less, while the initial first semiconductor substrate 303a has a thickness of 700 μm or more. It can be done. At this point, the thickness of the first semiconductor layer 303 can be smaller than the thickness of the second semiconductor layer 505. When flip-chip connection is used, the second semiconductor substrate 505a is preferably thinned, but can be used as the second semiconductor layer 505 as it is.

  The joining step is performed in this way, and a laminate is obtained. Next, a connection step of connecting the first wiring 311 and the second wiring 512 by forming a conductive member on the stacked body is performed. The connection process is performed through a plurality of steps.

  This will be described with reference to FIG. As a first step, a connection hole is formed inside the insulating region 45 from the first semiconductor layer 303 side. The connection hole penetrates the first semiconductor layer 303 and opens to a depth immediately before reaching the wiring pattern 40c. The formation of the connection holes is performed by etching the insulator layer located between the wiring pattern 40c and the first semiconductor layer 303 in the insulator layer of the insulator film 39. By reducing the thickness of the first semiconductor substrate 303a as described above, the aspect ratio of the connection hole can be reduced, and miniaturization is possible. Next, an insulating film such as silicon oxide is formed in a region including the side wall and the bottom of the connection hole. By etching back the insulating film, the insulating region 59 is left only on the side wall of the connection hole.

  Further, the remaining insulator layer located between the connection hole and the wiring pattern 40c is etched to deepen the connection hole. The connection hole reaches the wiring pattern 40c, and a part of the wiring pattern 40c is removed by etching or the like. Specifically, the etching is performed in the order of the sub-conductive layer 41a, the main conductive layer 42, and the sub-conductive layer 41b. Etching conditions for the wiring pattern 40c may be different from those for the insulating layer. Here, the part of the wiring pattern 40c to be removed may be a part or all of a part of the wiring pattern 40c constituting the first wiring 311 that overlaps the wiring pattern 53c of the second wiring 512. In this example, a part of the wiring pattern 40c overlapping the wiring pattern 53c is removed, and after the removal, the remaining part of the part overlapping the wiring pattern 53c remains.

  Further, by etching the insulator film 39, the connection hole passes through the joint surface 60 between the first wiring portion 31 and the second wiring portion 51, and penetrates the first component 10a. Further, the insulating film 49 is etched until the wiring pattern 53c formed on the second wiring portion 51 is reached. The formation of the connection holes is performed by etching the insulator layer located between the wiring pattern 40c and the wiring pattern 53c in the insulator layer of the insulator film 39 and the insulator layer of the insulator film 49. These insulator layers may include the insulator film 39 and the insulator layer on the surface of the insulator film 49. Thus, the through hole 67 reaching the wiring pattern 53c of the second wiring 512 is formed. Thereby, the side surface of the wiring pattern 40c is exposed in the through hole 67, and the upper surface of the wiring pattern 53c is exposed. Then, the through holes 67 are located between the plurality of portions of the wiring pattern 40c. In other words, a plurality of portions of the wiring pattern 40c face each other via the through hole 67. The exposed portion of the wiring pattern 53c refers to a part or the whole of the portion of the wiring pattern 53c constituting the second wiring 512 that overlaps the wiring pattern 40c of the first wiring 311 at the time after the bonding step. It is possible. The formation position of the through hole 67 can be set inside the outline of the wiring pattern 40c. As a result, even if an alignment error occurs during the bonding process between the first component 10a and the second component 20a or when the through hole 67 is formed, there is a risk that the through hole 67 does not reach one of the wiring pattern 40c and the wiring pattern 53c. It is reduced. Next, the deposit on the exposed wiring pattern 40c is removed by wet etching with a chemical solution. Although wet etching is used, dry etching is also possible as long as it can remove the deposit.

  This will be described with reference to FIG. In the second stage, a conductive material 68 is formed by embedding a conductive material such as copper in the through hole 67, for example. In this example, the conductive member 68 contacts the side surface of the wiring pattern 40c and the upper surface of the wiring pattern 53c. Note that it is also possible to conduct the first wiring 311 and the second wiring 512 by depositing a thin conductive material along the side and bottom surfaces of the through hole 67 and using the conductive member 68 as a conductive film. An insulating region 59 is formed between the conductive member 68 and the first semiconductor layer 303. Therefore, the conductive member 68 and the first semiconductor layer 303 are not electrically connected. Further, since the conductive member 68 is formed inside the insulating region 45 formed in the first semiconductor layer 303, the conductive member 68 and the semiconductor element of the first element unit 30 are also prevented from being electrically connected. . Note that one of the insulating region 59 and the insulating region 45 may be omitted. If the insulating region 45 is not formed, the arrangement density of the conductive members 68 can be increased, and the area occupied by the block 90 can be reduced. In this example, copper is used as the conductive material embedded in the through hole 67, but aluminum or tungsten may be used.

  An optical member 41 is formed on a side of the first element section 30 opposite to the first wiring section 31. First, the antireflection layer 61 and the insulator layer 62 are formed on the back surface 104 of the first semiconductor layer 303. After that, the light shielding layer 63 is formed. The antireflection layer 61 is preferably formed of a material having a refractive index between silicon and silicon oxide, such as silicon nitride or hafnium oxide. The antireflection layer 61 may have a configuration in which a plurality of films are stacked. The insulator layer 62 is, for example, a silicon oxide layer. The light-shielding layer 63 can be formed by depositing aluminum and tungsten and patterning it. The light-shielding layer 63 is preferably disposed between each pixel, on an optical black pixel, and on an element affected by light incidence. It is also possible to connect the light shielding layer 63 and the first semiconductor layer 303 by patterning the antireflection layer 61 and the insulator layer 62 before depositing the light shielding layer 63 and then depositing the light shielding layer 63.

  Further, a flattening layer 71 is formed on the light shielding layer 63. The planarization layer 71 is an inorganic insulator film or an organic insulator film, and can be composed of a plurality of layers. The flattening layer 71 can be appropriately flattened by CMP or the like. On the flattening layer 71, a color filter array 73 and a micro lens array 74 made of resin are appropriately formed in this order. At this time, the resin material is formed by using a coating method such as spin coating. However, since the through holes 67 are buried with the conductive material first, film unevenness such as striation occurs at the time of forming the resin film. Can be suppressed.

  After that, an opening 77 is formed in the electrode pad 78. Thereby, the configuration shown in FIG. 2 is obtained. In the present embodiment, the example in which the step of forming the opening 77 is performed after the formation of the color filter 73 and the on-chip lens 74 has been described. After the formation of the color filter 73 and the on-chip lens 74, high-temperature (about 400 ° C.) heat treatment cannot be performed to protect the color filter 73 and the on-chip lens 74 that are resins. If the semiconductor device 1 is damaged by the processing of the opening 77, a heat treatment for recovering the damage may be required, and the order of the steps can be appropriately changed.

  After that, the semiconductor device 1 is bonded to the package using die bonding. Then, a bonding wire 79 connected to the electrode pad 78 is formed in the opening 77. Seal the package with a transparent plate. An LGA (Land Grid Array), which is an external terminal of the package, is fixed to the circuit board by reflow soldering. As described above, the semiconductor device 3 can be manufactured.

  Another example of a method for manufacturing a semiconductor device will be described with reference to FIGS.

  FIG. 5A shows a state after the first component 10a and the second component 20a have been joined. The wiring pattern 40c of the first component 10a has an opening 67c at a position where the through hole 67 is provided. The opening 67c is provided in the first component 10a before the joining step. The opening 67c can be formed at the time of patterning the wiring pattern 40c.

  This will be described with reference to FIG. Patterning is performed from the back surface 104 side of the first semiconductor layer 303 to form a large-diameter connection hole 67a. The connection hole 67a is formed so as to reach the wiring pattern 40c. The connection hole 67a exposes the sub-conductive layer 41a, which is the upper surface of the wiring pattern 40c. In forming the connection hole 67a, by employing an etching condition in which the sub-conductive layer 41a serves as an etching stopper of the insulator film 39, the damage of the wiring pattern 40c can be suppressed.

  This will be described with reference to FIG. Subsequently, a small-diameter connection hole 67b having a smaller diameter (width) than the connection hole 67a is formed. The connection hole 67b is formed so as to reach the wiring pattern 53c. The connection hole 67b exposes the sub-conductive layer 55b which is the upper surface of the wiring pattern 53c. Further, in this example, the side surface of the wiring pattern 40c (the main conductive layer 42) is exposed in the connection hole 67b. However, if the upper surface of the wiring pattern 40c is exposed in the connection hole 67a, it is not necessary to expose the side surface of the wiring pattern 40c (main conductive layer 42) in the connection hole 67b.

  In forming the connection hole 67b, by employing an etching condition in which the sub-conductive layer 55b serves as an etching stopper for the insulator film 49, damage to the wiring pattern 53c can be suppressed.

  Since a part of the connection hole 67b is formed in the opening 67c formed in the wiring pattern 40c in advance, it is possible to minimize or eliminate damage to the wiring pattern 40c due to the formation of the connection hole 67b. In this example, the main conductive layer 42 of the wiring pattern 40c is an aluminum layer. However, when the main conductive layer 42 is a copper layer, it is particularly effective to provide the opening 67c in advance. Since copper is difficult to dry-etch, by providing the opening 67c in advance, it becomes possible to open the connection hole 67b without etching the copper layer. In the case where the large-diameter connection hole 67a and the small-diameter connection hole 67b are formed as in this example, the main conductive layer 42 such as an aluminum layer is etched without providing the opening 67c in advance. May be used to form the connection hole 67b.

  In the formation of the connection hole 67b having a small diameter, an etching method having a large selectivity between the wiring pattern 40c and the insulator film 39 is employed, and the connection hole 67a is formed in a self-aligned manner using the wiring pattern 40c as an etching mask. The connection hole 67b having a smaller diameter can be formed. That is, the same mask pattern can be used. Note that the width of the connection hole 67b may be larger than the width of the opening 67c, or may be smaller than the width of the opening 67c. When the width of the connection hole 67b is larger than the width of the opening 67, the formation of the connection hole 67b involves the removal of the wiring pattern 40c, and the side surface of the wiring pattern 40c may be exposed. When the width of the connection hole 67b is smaller than the width of the opening 67c, it is considered that the formation of the connection hole 67b does not remove the wiring pattern 40c and the side surface of the wiring pattern 40c is not exposed.

  This will be described with reference to FIG. Next, the sub-conductive layer 41a of the wiring pattern 40c and the sub-conductive layer 55b of the wiring pattern 53c corresponding to the bottoms of the connection holes 67a and 67b are removed by etching. Thereby, the main conductive layer 42 of the first wiring 311 and the main conductive layer 56 of the second wiring 512 are exposed in the through hole 67. The removal of the exposed portion of the sub-conductive layer 55b of the sub-conductive layer 41a and / or the wiring pattern 53c is not essential, and the sub-conductive layer 55b may be left exposed.

  After that, a conductive material is embedded in the through holes 67. When copper is used as the conductive material, copper may diffuse from the exposed surfaces of the main conductive layers 42 and 56, which are aluminum layers, and the diffusion of copper may increase the reliability of the connection between the first wiring 311 and the second wiring 512. It may reduce the performance. In particular, when the side surfaces and upper surfaces of the main conductive layers 42 and 56 of the aluminum layer are exposed surfaces, copper may diffuse from the side surfaces of the aluminum layer. Therefore, it is preferable to form the diffusion prevention film 69 along the inner surface of the through hole 67 prior to embedding the conductive material (copper). The portion of the diffusion prevention film 69 that protrudes from the through hole 67 can be removed together with the conductive material during planarization by CMP after embedding the conductive material. As the material of the diffusion prevention film 69, metals and metal compounds such as titanium, titanium nitride, titanium carbide, tantalum, tantalum nitride, and tantalum carbide can be used. The diffusion preventing film 69 may be a single layer of a titanium layer, a titanium compound layer, a tantalum layer, and a tantalum compound layer, or a multilayer film including two or more layers selected from these. Thus, the conductive member 68 has a structure including a buried layer made of a conductive material (copper) and a diffusion prevention layer against diffusion of the buried material into the wiring pattern.

  The positional relationship among the through hole 67, the first wiring 311 and the second wiring 512 will be described with reference to FIG. FIG. 6 is a plan view schematically showing a state when the through hole 67 of FIG. 2 is formed.

  This will be described with reference to FIGS. 6 (a-1), (a-2) and (a-3). FIG. 4 is a schematic diagram illustrating a portion where a part of a through hole is in contact with a second wiring as viewed from above. Here, the width of the through hole 67 is assumed to be a.

  FIG. 6A-2 shows a case where the through holes 67 are formed as designed in the photomask. FIG. 6A-1 shows a state in which the through hole 67 is shifted leftward by a distance b from the state of FIG. 6A-2. FIG. 6A-3 shows a state in which the through hole 67 is shifted rightward by a distance b from the state of FIG. 6A-2. The shift amount in the left direction is shown as negative while the right direction is shown as positive. 6A-1 and FIG. 6A-3, the conductive member 68 contacts only one of the second wiring 512 and the first wiring 311 even if the conductive material is embedded in the through-hole 67. Wiring cannot be connected.

  FIG. 6B-2 shows a case where the through-hole 67 is formed as designed by a photomask different from the photomask described with reference to FIG. 6A-2. FIG. 6B-1 shows a state in which the through hole 67 is shifted leftward by a distance b from the state of FIG. 6B-2. FIG. 6B-3 shows a state in which the through hole 67 is shifted rightward by a distance b from the state of FIG. 6B-2. The shift amount in the left direction is shown as negative while the right direction is shown as positive. In any of the states shown in FIGS. 6 (b-1), 6 (b-2) and 6 (b-3), by burying a conductive material in the through-hole 67, the conductive member 68 is connected to the second wiring 512 and the second wiring 512. Since both of the wires 311 are in contact with each other, connection between the wires can be performed.

  For this reason, even if an alignment deviation of the distance b occurs, the through hole 67 does not protrude from a region where the first wiring 311 and the second wiring 512 overlap (hereinafter, referred to as a connection region) in the bonding process. Next, a photomask for forming the through hole 67 may be designed. That is, in the mask pattern on the photomask that indicates the ideal formation position of the through hole 67, the formation position of the through hole 67 is kept away from the end of the connection region by the distance c. That is, the width of the connection region may be larger than the width a of the through hole. It is preferable that the distance c is equal to or longer than the assumed distance b of the alignment deviation. The distance b depends on the performance of the exposure apparatus used for patterning the photoresist for forming the through hole 67, but may be, for example, less than 1 μm. Therefore, the distance c is preferably set to 1 μm or more. In relation to the diameter of the through hole 67, the distance b is less than a / 10. Therefore, the distance c is preferably set to a / 10 or more. Naturally, since the outline of the connection region is determined by at least the outline of the first wiring 311, it is preferable to design the photomask so as to form the through hole 67 at a distance c or more from the end of the first wiring 311. . In addition, as long as the through-hole is formed using the mask pattern on the photomask that indicates the ideal formation position, the through-hole does not have to be formed at the position according to the mask pattern. For example, the fact that the through-hole is designed to be surrounded by the first wiring 311 on the mask pattern means that as long as this mask is used, the through-hole is formed so as to be surrounded by the first wiring 311. Is the same.

  A method for manufacturing a semiconductor device including the joining step and the connecting step described in the present embodiment will be summarized.

  In the connecting step, the first component 10a and the second component 20a are joined. The first component 10a has a first element unit 30 including the first semiconductor layer 303 and a first wiring unit 31 including a first wiring 311 electrically connected to the first element unit 30. The second component 20a has a second element unit 50 including the second semiconductor layer 505, and a second wiring unit 51 including a second wiring 512 electrically connected to the second element unit 50.

  The bonding step is performed such that the first wiring section 31 and the second wiring section 51 are located between the first element section 30 and the second element section 50. The bonding step can be performed such that the wiring patterns 40c and the wiring patterns 53c overlap.

  In the connection step, a conductive member 68 that contacts both the wiring pattern 40c forming the first wiring 311 and the wiring pattern 53c forming the second wiring 512 is formed, and the first wiring 311 and the second wiring 512 are electrically connected. Connect to

  The connecting step includes a first step of forming a through hole 67 that penetrates the first component 10a and exposes the wiring pattern 53c. The through hole 67 can expose a portion of the wiring pattern 53c that overlaps the wiring pattern 40c at the time of the bonding step. The through hole 67 can be formed so that the through hole 67 exposes the wiring pattern 40c. This through hole 67 can be formed so as to be located between a plurality of portions of the wiring pattern 40c. The through-hole 67 can be formed by removing a portion of the wiring pattern 40c that overlaps the wiring pattern 53 at the time of the bonding step. The connection step includes a second step of forming a conductive member 68 in the through-hole 67 in contact with both the wiring pattern 40c and the wiring pattern 53c exposed in the through-hole 67.

  This makes it possible to provide a semiconductor device having high performance and reliability in electrical connection between the first wiring 311 and the second wiring 512 by the conductive member 68.

303 first semiconductor layer 30 first element section 40c wiring pattern 31 first wiring section 311 first wiring 505 second semiconductor layer 50 second element section 53c wiring pattern 51 second wiring section 512 second wiring 67 through hole 68 conductive member

Claims (21)

A first component having a first element portion including a first semiconductor layer and a first wiring portion including a first wiring pattern, and a second element portion including a second semiconductor layer and a second wiring portion including a second wiring pattern. A joining step of joining the second component and the second component so that the first wiring portion and the second wiring portion are located between the first element portion and the second element portion;
Forming a conductive member in contact with the first wiring pattern and the second wiring pattern after the bonding step so that the first wiring pattern and the second wiring pattern are electrically connected; ,
In the joining step, the first wiring pattern is made of a material different from the first conductive layer and the first conductive layer, and is disposed between the first conductive layer and the first semiconductor layer; A second conductive layer in contact with the first conductive layer,
The forming step includes:
A first step of partially removing the first wiring pattern and forming a through hole exposing the second wiring pattern;
Forming a first layer containing at least one of titanium, a titanium compound, tantalum, and a tantalum compound so as to be in contact with a side surface of the first wiring pattern exposed to the through hole and the second wiring pattern; A second step of providing copper, aluminum, or tungsten in contact with the first layer inside the semiconductor device.   The method according to claim 1, wherein a photoelectric conversion element is provided in the first semiconductor layer. The through hole is a first insulator layer located between the first wiring pattern and the first semiconductor layer, and a second insulator located between the first wiring pattern and the second wiring pattern. Formed through the layer and
The width of a portion of the through hole penetrating the first insulator layer is larger than a width of a portion of the through hole penetrating the second insulator layer. A method for manufacturing a semiconductor device. In the joining step, the first wiring pattern has a plate shape;
4. The method according to claim 1, wherein a through hole is formed in the first wiring pattern in the forming step. 5. The second wiring pattern is made of a third conductive layer containing at least one of titanium, titanium nitride, tantalum and tantalum nitride, and a material different from the third conductive layer in contact with the third conductive layer. A third conductive layer disposed between the third conductive layer and the second semiconductor layer,
The method according to claim 1, wherein in the second step, the first layer is formed so as to be in contact with the fourth conductive layer.   6. The method according to claim 1, wherein, in the second step, copper, aluminum, or tungsten is embedded in the through hole. 7.   In a cross section passing through the first conductive layer and the second conductive layer, a width from one side surface to the other side surface of the first wiring pattern exposed to the through hole is a first width portion. And a second width portion narrower than the first width and closer to the second wiring pattern than the first width portion. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed.   In the first step, the through hole is formed such that a width of the through hole is larger in a portion exposing the second conductive layer than in a portion exposing the first conductive layer. The method for manufacturing a semiconductor device according to claim 1. The side surface of the first wiring pattern exposed to the through hole includes a curved surface,
9. The method according to claim 7, wherein the first layer is in contact with the curved surface. The first conductive layer contains at least copper or aluminum,
The method according to any one of claims 1 to 9, wherein the second conductive layer includes at least one of tantalum, tantalum nitride, titanium, and titanium nitride.   The method according to claim 5, wherein the fourth conductive layer contains at least copper or aluminum.   12. The optical device according to claim 1, further comprising, after the forming step, an optical member including a microlens array disposed on a side of the first element unit opposite to the first wiring unit. 13. The method for manufacturing a semiconductor device according to item 5. The second wiring portion includes a third wiring pattern,
An insulating material is provided between the second wiring pattern and the third wiring pattern,
13. The method of manufacturing a semiconductor device according to claim 1, wherein a bonding wire connected to the third wiring pattern is provided after the bonding step. A first semiconductor layer;
A second semiconductor layer;
A first wiring portion disposed between the first semiconductor layer and the second semiconductor layer and including a first wiring pattern;
A second wiring portion disposed between the first wiring portion and the second semiconductor layer and including a second wiring pattern;
A semiconductor device comprising: a conductive member that electrically connects the first wiring pattern and the second wiring pattern;
The first wiring pattern is made of a material different from a first conductive layer and a material of the first conductive layer, is disposed between the first conductive layer and the first semiconductor layer, and is provided in the first conductive layer. And a second conductive layer in contact with
The conductive member,
A first region located between the second side surface opposite to the first side surface and said first side surface of the second conductive layer of the first wiring pattern, the third of the first conductive layer of the first wiring pattern A second region located between a side surface and a fourth side surface facing the third side surface ,
Titanium, a titanium compound, a first layer containing at least one of tantalum and a tantalum compound, and in contact with the first layer, containing any of copper, aluminum and tungsten,
The first layer is in contact with the first side surface , the second side surface , the third side surface, and the fourth side surface of the first wiring pattern and the second wiring pattern,
The second region is a semiconductor device which comprises said not narrower than the width of the first region. Said first side, said second side, said third side, and at least one of the fourth aspect, the cross-section through said second conductive layer and the first conductive layer includes a curved surface,
The semiconductor device according to claim 14, wherein the curved surface is in contact with the first layer. Said first side, said second side, said third side, and at least one of the fourth aspect, the semiconductor device according to claim 1 4, characterized in that it is constituted by combining a plurality of planes . The second wiring pattern is made of a third conductive layer containing at least one of titanium, titanium nitride, tantalum and tantalum nitride, and a material different from the third conductive layer in contact with the third conductive layer. A third conductive layer disposed between the third conductive layer and the second semiconductor layer,
The first layer, semiconductor devices according to any one of claims 14 to 16 in contact with the fourth conductive layer. The conductive member is a semiconductor device according to any one of claims 14 to 1 7, characterized in that provided through the first wiring pattern.   In the first step, removing the first conductive layer and the second conductive layer of the first wiring pattern so that a side surface of the first wiring pattern is a surface configured by combining a plurality of planes. The method for manufacturing a semiconductor device according to claim 1, wherein: A semiconductor device according to any one of claims 14 to 18 ,
A package accommodating the semiconductor device;
And a circuit board on which the package is mounted,
A semiconductor device including an optical system for guiding light to the semiconductor device. A semiconductor device comprising a semiconductor device according to any one of claims 14 to 1 8, an electronic device and a peripheral device connected to said semiconductor device,
The electronic device, wherein the peripheral device is a computing device, a storage device, a recording device, a communication device, or a display device.

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