JP2006339406A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the resistance to a stress applied to a pad of a semiconductor device. <P>SOLUTION: A plurality of line-shaped wires 90 are provided below the pad 2. Respective wires 90 are arranged in a cycle ≤2 μm. Below the wires 90, a plurality of power supply lines 80 and 82 and a ground line 81 are further provided, and floating lines 83 and 84 are provided along the their boundaries. The line direction of the wires 90 and the line direction of the power supply lines 80 and 82, the ground line 81, and the floating lines 83 and 84 are the same direction or orthogonal to each other. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a structure of a semiconductor device having a bonding pad, and more particularly to a technique for improving strength against stress applied to a bonding pad during probing or wire bonding.

  During probing in an electrical test of a semiconductor chip and wire bonding in assembling a semiconductor device, mechanical stress is applied to a bonding pad (hereinafter simply referred to as “pad”) formed on the upper surface of the semiconductor chip. The stress applied to the pad becomes a factor causing cracks in the interlayer insulating film under the pad. When a crack generated in the interlayer insulating film reaches the wiring, it causes deterioration of the metal migration resistance of the wiring and causes a short circuit between the wirings. Further, when the stress reaches the semiconductor element as the active element, the electrical characteristics of the active element change. For this reason, conventionally, there has been a tendency to dispose a pad above a wiring or an active element.

  However, in recent years, in order to achieve high integration of semiconductor devices, it is desired to effectively use the region below the pad, and attempts have been made to dispose wiring and active elements below the pad. (For example, Patent Documents 1 to 5). In particular, Patent Documents 1 to 4 propose a semiconductor device structure in which an active circuit such as a protection circuit and an input / output circuit and a ring-shaped power supply wiring that surrounds an internal circuit are arranged below the pad.

  Patent Documents 3 and 4 disclose a structure in which a dummy wiring (buffer part) separated from a signal line is further provided between the pad and the signal line and active circuit below the pad. According to such a structure, stress applied to the pad is absorbed by the dummy wiring, and damage to the interlayer insulating film, the signal line, and the active circuit below the pad is suppressed. As a specific example of the dummy wiring, for example, Patent Document 3 (FIG. 1) shows an example of a dummy wiring having a mesh structure.

  Further, in Patent Document 5, by providing a via for connecting a pad and a signal line in a region excluding the lower region of the pad, the stress from the pad is prevented from being transmitted to an interlayer insulating film below the via. Technology is disclosed.

JP 2003-289104 A JP 2002-16069 A JP 2000-49190 A Japanese Patent Laid-Open No. 11-307724 Japanese Patent Laid-Open No. 5-67645

  As described above, it is desired to effectively use the region below the pad for the purpose of high integration of the semiconductor device. However, the stress applied to the pad is caused by cracks in the interlayer insulating film below the pad and fluctuations in characteristics of the active element. It becomes a factor to bring about. As in Patent Documents 3 and 4, by providing a wiring serving as a buffer between the pad and the lower active element, the stress transmitted from the pad to the active element is reduced. However, depending on the layout of the buffer and other wirings disposed under the pad, stress concentrates on a specific portion of the interlayer insulating film, and cracks are likely to occur in that portion.

  Further, the power supply wiring provided in the semiconductor device is formed relatively wide in order to reduce its resistance, and can absorb stress compared to other fine wiring. Therefore, as in Patent Documents 1 and 2, there is also an advantage that layout is easy under the pad. However, when the power supply wiring is laid out under the pad, the uppermost wiring layer above the power supply wiring is used as a pad and cannot be used as the power supply wiring. That is, since the wiring layer that can be used for the power supply wiring is limited, the resistance of the power supply wiring is increased. In particular, the uppermost wiring layer tends to be formed thick because it is used for a pad, and its influence is great. For example, the protection circuit provided in the input / output circuit operates so that surge current caused by electrostatic discharge (ESD) applied to the pad is released to the power supply wiring. The function is lowered and the reliability of the semiconductor device is lowered.

  The present invention has been made to solve the above-described problems. In a semiconductor device in which a pad is disposed above an active element and a wiring, resistance to stress applied to the pad is improved, and the pad is connected to a power source. An object is to suppress the increase in resistance of the power supply wiring when the wiring is disposed above the wiring.

  A semiconductor device according to a first aspect of the present invention is formed using an active element formed on a semiconductor substrate, a pad disposed above the active element, and a wiring layer below the pad, A plurality of line-shaped first wirings disposed below the pads, and each of the first wirings is arranged side by side with a period of 2 μm or less.

  A semiconductor device according to a second aspect of the present invention is formed using an active element formed on a semiconductor substrate, a pad disposed above the active element, and a wiring layer below the pad, A plurality of line-shaped first wirings disposed below the pad and a plurality of line-shaped first wirings disposed below the pad are formed using a wiring layer below the first wiring. And the direction of the line of the first wiring and the direction of the line of the second wiring are the same or perpendicular to each other.

  A semiconductor device according to a third aspect of the present invention is formed using an active element formed on a semiconductor substrate, a pad disposed above the active element, and a wiring layer below the pad, A plurality of line-shaped first wirings disposed below the pads, wherein the first wirings include a power supply potential line and a ground potential line for supplying a predetermined power supply voltage to the active element, and A floating wiring disposed between the power supply potential line and the ground potential line is included.

  A semiconductor device according to a fourth aspect of the present invention is formed using an active element formed on a semiconductor substrate, a pad disposed above the active element, and a wiring layer below the pad, A plurality of line-shaped first wirings disposed below the pad; and a second wiring formed using a wiring layer below the first wiring and disposed below the pad. The first wiring includes at least one of a power supply potential line and a ground potential line for supplying a predetermined power supply voltage to the active element, and the second wiring has a width equal to or larger than the width of each of the first wirings. And is electrically connected to the power supply potential line or the ground potential line included in the first wiring.

  A semiconductor device according to a fifth aspect of the present invention is formed using an active element formed on a semiconductor substrate, a pad disposed above the active element, and a wiring layer below the pad, A plurality of line-shaped first wirings disposed below the pad; and a second wiring formed using the same wiring layer as the pad, wherein the first wiring supplies a predetermined power source to the active element. Including at least one of a power supply potential line and a ground potential line for supplying a voltage, and the second wiring is electrically connected to the power supply potential line or the ground potential line included in the first wiring It is.

  According to the semiconductor device according to the first aspect, since each of the plurality of line-shaped first wirings arranged below the pad is arranged in a cycle of 2 μm or less, the stress from the pad is While being appropriately absorbed by the first wiring, it is released to the lower layer through the gap of the first wiring. As a result, the stress concentration in the interlayer insulating film under the pad is relaxed, and the generation of cracks is prevented.

  According to the semiconductor device of the second aspect, the direction of the first wiring line below the pad and the direction of the second wiring line are the same or perpendicular to each other. While moderately absorbed by the wiring, the stress concentration in the interlayer insulating film between the first wiring and the second wiring is alleviated, and the occurrence of cracks is prevented.

  According to the semiconductor device according to the third aspect, since the plurality of line-shaped first wirings disposed below the pad is provided, stress concentration in the interlayer insulating film under the pad can be alleviated, and cracks are generated. Is prevented. Further, since the second wiring includes the power supply potential line and the ground potential line and the floating wiring is provided between them, it is possible to contribute to high integration of the semiconductor device and to prevent a short circuit between the power supply and the ground.

  According to the semiconductor device of the fourth aspect, since the plurality of line-shaped first wirings disposed below the pad are provided, stress concentration in the interlayer insulating film under the pad can be alleviated, and cracks are generated. Is prevented. In addition, since the first wiring includes a power supply potential line and / or a ground potential line, and a second wiring having a width equal to or larger than the width of the first wiring is connected to the first wiring, The increase in resistance of the power supply wiring due to the provision of the pad on the top can be suppressed.

  According to the semiconductor device of the fifth aspect, since the plurality of line-shaped first wirings disposed below the pad are provided, stress concentration in the interlayer insulating film under the pad can be alleviated, and cracks are generated. Is prevented. Further, since the first wiring includes the power supply potential line and / or the ground potential line, and the second wiring in the same wiring layer as the pad is connected to the first wiring, the high resistance of the power supply wiring due to the provision of the pad on the power supply wiring Can be suppressed.

  FIG. 1 is a circuit diagram of an input / output unit in a semiconductor device according to an embodiment of the present invention. The semiconductor device includes an input / output circuit 10 including an output buffer 11, a protection circuit 12, and an input buffer 13 between the internal circuit 1 and the pad 2. The internal circuit 1 includes a logic circuit that outputs a signal to the output buffer 11 and a signal from the input buffer 13, and a level shifter that converts a power supply voltage to a level for the logic circuit.

  The output buffer 11 outputs a signal from the internal circuit 1 to the pad 2, and includes a plurality of inverter circuits composed of a PMOS transistor 111 and an NMOS transistor 112 connected in parallel. The input buffer 13 inputs a signal input to the pad 2 to the internal circuit 1 and is an inverter circuit configured by a PMOS transistor 131 and an NMOS transistor 132.

  The protection circuit 12 is for protecting the semiconductor device from electrostatic discharge (ESD) applied to the pad 2. The protection circuit 12 includes an inrush resistor 123 interposed between the pad 2 and the output buffer 11 and the input buffer 13, a plurality of clamp diodes 121 connected between the pad 2 and the power source, and between the pad 2 and the ground. And a plurality of clamp diodes 122 connected to each other.

  When noise with a voltage higher than the power supply or a voltage lower than the ground is applied to the pad 2 by ESD, the inrush resistor 123 dulls the noise waveform, and the clamp diodes 121 and 122 supply the surge current generated by the noise to the power supply or Escape to the ground. This prevents the output buffer 11 and the input buffer 13 from being destroyed by a surge.

  In FIG. 1, only one pad 2 is shown for simplicity of explanation, but a semiconductor device normally includes a plurality of pads 2, and each of the output buffer 11, the protection circuit 12, and the input buffer 13 has one pad 2. One is provided for each pad 2.

  2 and 3 are diagrams showing the layout of the pad 2 in the semiconductor device according to the present embodiment. As shown in FIG. 2, on the outer periphery of the chip 100 of the semiconductor device, a frame-shaped power supply wiring 3 surrounding the internal circuit 1 (in this specification, the power supply potential line and the ground potential line are collectively referred to as “power supply wiring”). The pad 2 is laid out side by side above the power supply wiring 3. That is, the power supply wiring 3 is continuously arranged so as to straddle the lower region of the plurality of pads 2.

  3 is an enlarged view of a portion where the pad 2 is disposed, and shows the positional relationship between the input / output circuit 10 and the pad 2 shown in FIG. 1 (the illustration of the power supply wiring 3 is omitted in FIG. 3). is doing). As shown in this figure, in the present embodiment, the pad 2 is disposed above the input / output circuit 10.

  As described above, by providing the power supply wiring 3 and the input / output circuit 10 below the pad 2, the semiconductor device is highly integrated. However, in that case, depending on the layout of the wiring under the pad 2, stress concentrates on a specific portion of the interlayer insulating film, and cracks tend to occur in that portion. The inventors of the present invention have repeatedly studied the wiring layout below the pad 2 and found a wiring layout excellent in resistance to stress applied to the pad 2. Hereinafter, the wiring layout according to the present invention will be described in detail using specific examples.

  4 to 22 are diagrams showing the configuration of the input / output unit of the semiconductor device according to the present embodiment. 4 to 16 are layout diagrams of wirings and vias of the input / output unit, and FIGS. 17 to 22 are cross-sectional views of the input / output unit.

  First, correspondence between the layout diagrams of FIGS. 4 to 16 and the cross-sectional views of FIGS. 17 to 22 will be described. 17 corresponds to a cross section taken along the line AA shown in the layout diagrams of FIGS. 4 to 16. Similarly, FIG. 18 is a BB line, FIG. 19 is a CC line, and FIG. 20 is a DD line. 21 corresponds to a cross section taken along line E-E, and FIG. 22 corresponds to line F-F.

  4 shows a layout of the active region formed in the semiconductor substrate 200 shown in FIGS. 17 to 22 and the polysilicon electrode layer formed on the semiconductor substrate 200. 5 shows the layout of the first via layer formed in the lowermost interlayer insulating film 201, and FIG. 6 shows the first metal wiring layer formed in the interlayer insulating film 202 on the interlayer insulating film 201. The layout is shown. 7 and 8 show the layouts of the second via layer and the second metal wiring layer formed in the interlayer insulating film 203 on the interlayer insulating film 202, respectively. 9 and 10 show the layouts of the third via layer and the third metal wiring layer formed in the interlayer insulating film 204 on the interlayer insulating film 203, respectively. 11 and 12 show the layout of the fourth via layer and the fourth metal wiring layer formed in the interlayer insulating film 205 on the interlayer insulating film 204. FIG. 13 and 14 lay out the fifth via layer and the fifth metal wiring layer formed in the interlayer insulating film 206 on the interlayer insulating film 205. 15 shows the layout of the fourth via layer formed in the interlayer insulating film 207 on the interlayer insulating film 206, and FIG. 16 shows the opening of the sixth metal wiring layer on the interlayer insulating film 207 and the passivation film 208 covering it. 99 layouts are shown respectively. Note that the leftmost portion in each layout diagram is a region where the internal circuit 1 is formed, but a specific layout of that portion is omitted for simplicity.

  In the present embodiment, the first via layer in interlayer insulating film 201 and the sixth via layer in interlayer insulating film 207 are formed of tungsten, and the sixth metal wiring layer, which is the uppermost wiring layer, is formed of aluminum. . The first to fifth metal wiring layers and the second to fifth via layers in the interlayer insulating films 202 to 206 are formed of copper. Of the copper wiring layer and via layer, the first metal wiring layer is formed in the interlayer insulating film 202 by a single damascene method, and the other second to fifth metal wiring layers and second to fifth via layers are formed. Are formed in the interlayer insulating films 203 to 206 by a dual damascene method. As the interlayer insulating films 201 to 206, for example, a silicon oxide film is generally used. However, the materials and forming methods of each wiring layer, each via layer, and each interlayer insulating film in the present invention may be general, and the application of the present invention is not limited to the combinations exemplified here.

  Hereinafter, the structure of the semiconductor device according to the present embodiment will be described with reference to FIGS. For convenience of explanation, each wiring and via shown in each drawing is hatched according to its function. More specifically, a power supply node and a ground (reference potential) node, an output node of the logic circuit of the internal circuit 1, an output node of the output buffer 11, an output node of the input buffer 13, and a floating node are distinguished. 4 to 22, the same reference numerals are assigned to the same elements.

  Active elements such as the PMOS transistor 111 and the NMOS transistor 112 of the output buffer 11 shown in FIG. 1, the clamp diodes 121 and 122 of the protection circuit 12, and the PMOS transistor 131 and the NMOS transistor 132 of the input buffer 13 are formed on the semiconductor substrate 200, respectively. The They are formed in each of the active regions defined as shown in FIG. 4 by the isolation insulating film 20 formed on the semiconductor substrate 200.

  As shown in FIGS. 4 and 17, the PMOS transistor 111 of the output buffer 11 is formed in the active region in the N well 17. Each of the PMOS transistors 111 includes a gate electrode 36 formed using a polysilicon wiring layer, a P-type source region 25 and a drain region 26. As shown in FIG. 18, the NMOS transistor 112 is formed in the active region in the P well 18, and each NMOS transistor 112 includes a gate electrode 37, an N-type source region 27, and a drain region 28. .

  The gate electrode 36 of the PMOS transistor 111 is connected to the wiring 40 of the first metal wiring layer (FIG. 6) through the via 36c of the first via layer (FIG. 5). The gate electrode 37 of the NMOS transistor 112 is connected to the wiring 44 of the first metal wiring layer through the via 37c of the first via layer. That is, the wirings 40 and 44 are signal input lines of the output buffer 11 including the PMOS transistor 111 and the NMOS transistor 112, and are connected to the logic circuit in the internal circuit 1.

  The source region 25 of the PMOS transistor 111 includes a via 25c in the first via layer, a wiring 45 in the first metal wiring layer, a via 45c in the second via layer (FIG. 7), and a wiring 57 in the second metal wiring layer (FIG. 8). And it connects to the wiring 72 of the third metal wiring layer (FIG. 10) via the via 57c of the third via layer (FIG. 9). The wiring 72 and the wiring 80 of the fourth metal wiring layer (FIG. 12) are connected to each other via the via 72c of the fourth via layer (FIG. 11), and both are connected to the frame-shaped power source shown in FIG. Power supply potential lines included in the wiring 3 (for convenience of explanation, the wirings 72 and 80 are hereinafter referred to as “power supply lines”, respectively). Although details will be described later, the wiring 80 of the fourth metal wiring layer is divided into a plurality of lines as shown in FIG.

  The source region 27 of the NMOS transistor 112 includes a via 27c in the first via layer, a wiring 47 in the first metal wiring layer, a via 47c in the second via layer, a wiring 59 in the second metal wiring layer, and a via 59c in the third via layer. To the wiring 73 of the third metal wiring layer. The wiring 73 and the wiring 81 of the fourth metal wiring layer are connected to each other via a via 73c of the fourth via layer, and both are ground potential lines included in the frame-shaped power supply wiring 3 shown in FIG. (Hereinafter, the wirings 73 and 81 are referred to as “ground lines”). The wiring 80 of the fourth metal wiring layer is also divided into a plurality of lines as shown in FIG.

  Referring to FIG. 4 again, the PMOS transistor 131 of the input buffer 13 is formed in the active region in the N well 17, and the NMOS transistor 132 is formed in the active region in the P well 16. The PMOS transistor 131 and the NMOS transistor 132 share the gate electrode 35. The PMOS transistor 131 includes a P-type source region 21 and a drain region 22, and the NMOS transistor 132 includes an N-type source region 23 and a drain region 24, respectively.

  The source region 21 of the PMOS transistor 131 includes a via 21c in the first via layer, a wiring 41 in the first metal wiring layer, a via 41c in the second via layer, a wiring 55 in the second metal wiring layer, and a via 55c in the third via layer. To the wiring 70 of the third metal wiring layer. The wiring 70 is formed in a frame shape in the same manner as the power supply line 72 and the ground line 73 described above. The wiring 70 is connected to the power supply line 72 through the via 65c in the third via layer and the wiring 65 in the second metal wiring layer. That is, the wiring 70 functions as a frame-shaped power supply potential line like the power supply line 72, and forms part of the frame-shaped power supply wiring 3 shown in FIG. However, as can be seen from FIGS. 21 and 22, the wiring 70 is disposed at a position shifted from the region below the pad 2. Above the wiring 70, a frame-like fourth metal wiring layer wiring 78, a fifth metal wiring layer wiring 88, and a sixth metal wiring layer wiring 94 are disposed, and these wirings 70, 78, 88 and 94 are all connected by vias 70c, 78c and 88c of the fourth to sixth via layers (hereinafter, the wirings 70, 78, 88 and 94 are also referred to as “power supply lines”).

  The source region 23 of the NMOS transistor 132 includes a first via layer via 23c, a first metal wiring layer wiring 42, a second via layer via 42c, a second metal wiring layer wiring 56, and a third via layer via 56c. To the wiring 71 of the third metal wiring layer. The wiring 71 is arranged in a frame shape on the inner side of the power supply line 72 and the ground line 73 in the same manner as those. The wiring 71 is connected to the ground line 73 via the via 66c of the third via layer and the wiring 66 of the second metal wiring layer. That is, the wiring 71 functions as a frame-like ground potential line like the ground line 73, and forms part of the frame-like power supply wiring 3 shown in FIG. However, as can be seen from FIGS. 21 and 22, the wiring 71 is also arranged at a position shifted from the region below the pad 2. Above the wiring 71, a ground line 79 of the fourth metal wiring layer, a wiring 89 of the fifth metal wiring layer, and a wiring 95 of the sixth metal wiring layer are also provided. , 89, 95 are all connected by vias 71c, 79c, 89c of the fourth to sixth via layers (hereinafter, the wirings 71, 79, 89, 95 are also referred to as “ground lines”).

  10 to 16, wirings 76, 86, 92, 95 of the third to sixth metal wiring layers (they are connected via vias 76c, 86c, 92c of the fourth to sixth via layers). Are power supply potential lines for the internal circuit 1. Further, the wirings 77, 87, 93, 96 of the third to sixth metal wiring layers (they are connected via the vias 77c, 87c, 93c of the fourth to sixth via layers) are for the internal circuit 1. The ground potential line. These power supply wirings for the internal circuit 1 are arranged in a frame shape on the outer peripheral portion of the internal circuit 1, and form a part of the frame-shaped power supply wiring 3 shown in FIG.

  Here, the drain region 26 of the PMOS transistor 111, the drain region 28 of the NMOS transistor 112, and the gate electrode 35 of the input buffer 13 are all first metal wiring via the via 26c, the via 28c, and the via 35c of the first via layer, respectively. Connect to layer wiring 46. As a result, the output of the output buffer 11 is connected to the input of the input buffer 13 as shown in the circuit diagram of FIG. The wiring 46 is connected to the wiring 58 of the second metal wiring layer through the via 46c of the second via layer.

  Further, as shown in the circuit diagram of FIG. 1, the output buffer 11 and the input buffer 13 are connected to the pad 2 via the protection circuit 12. In the present embodiment, the inrush resistance 123 of the protection circuit 12 is a polysilicon resistor 38 (hereinafter referred to as “inrush resistance 38”) formed using a polysilicon wiring layer (FIG. 4) on the semiconductor substrate 200. . The clamp diode 122 is formed in the P well 18 and includes an anode region 29 and a cathode region 30 formed on the P well 18 as shown in FIG. The clamp diode 121 is formed in the N well 19 and includes an anode region 32 and a cathode region 31 formed in the upper portion of the N well 19 as shown in FIG.

  The wiring 46 of the first metal wiring layer which is the output line of the output buffer 11 and the input line of the input buffer 13 is connected to the first metal wiring via the via 38c and the inrush resistor 38 of the first via layer as shown in FIG. Connect to layer wiring 49.

  As shown in FIG. 19, the wiring 49 is connected to the cathode region 30 of the clamp diode 122 through the via 30c of the first via layer. The anode region 29 of the clamp diode 122 includes a via 29c in the first via layer, a wiring 48 in the first metal wiring layer, a via 48c in the second via layer, a wiring 60 in the second metal wiring layer, and a via in the third via layer. It is connected to the ground line 73 of the third metal wiring layer through 60c.

  As shown in FIG. 20, the wiring 49 is also connected to the anode region 32 of the clamp diode 121 through the via 32c of the first via layer. The cathode region 31 of the clamp diode 121 includes a via 31c in the first via layer, a wiring 50 in the first metal wiring layer, a via 50c in the second via layer, a wiring 62 in the second metal wiring layer, and a via in the third via layer. It is connected to the wiring 74 of the third metal wiring layer via 62c. The wiring 74 is a frame-shaped wiring formed outside the ground line 73, and is connected to the power supply line 72 via the via 65 c of the third via layer and the wiring 65. The wiring 74 is connected to a wiring 82 of a fourth metal wiring layer, which is also formed in a frame shape above the wiring 74, via a via 74c of the fourth via layer (hereinafter, the wirings 74 and 82 are “power supply lines”). Called). The power supply line 72 and the power supply line 82 form part of the frame-shaped power supply wiring 3 shown in FIG. As shown in FIG. 12, the power line 82 is also divided into a plurality of lines in the same manner as the power line 80 and the ground line 81 described above.

  The wiring 49 further includes a via 49c in the second via layer, a wiring 61 in the second metal wiring layer, a via 61c in the third via layer, a wiring 75 in the third metal wiring layer, a via 75c in the fourth via layer, and a fourth metal. The wiring 85 of the wiring layer, the via 85c of the fifth via layer, the wiring 91 of the fifth metal wiring layer, and the via 91c of the sixth via layer are connected to the wiring 96 of the sixth metal wiring layer which is the pad 2. A passivation film 208 is formed on the sixth metal wiring layer, but an opening 99 is provided above the wiring 96, and the portion exposed to the opening 99 functions as the pad 2. .

  With the above configuration, an input / output unit corresponding to the circuit of FIG. 1 is obtained. 12, 14, and 17 to 22 show the wirings 83 and 84 of the fourth metal wiring layer and the wiring 90 of the fifth metal wiring layer, which are separated from the power source, the ground, and the signal line. The floating wiring thus formed does not function as a part of the internal circuit 1 and the input / output circuit 10 and thus has not been described above. However, the wirings 83, 84, and 90 form part of the characteristics of the structure of the semiconductor device of the present embodiment, and will be referred to in the following description.

  From here, the structural features of the semiconductor device of the present embodiment will be described. First, in the semiconductor device of the present embodiment, a plurality of line-shaped wirings 90 are disposed in a region below the pad 2 in the fifth metal wiring layer. However, in this embodiment, a plurality of wirings 90 are connected at both ends as shown in FIG.

  In general, a wiring formed of copper, aluminum, or the like has a lower elastic modulus than that of an interlayer insulating film formed of a silicon oxide film or the like and can absorb stress. However, when the wiring is deformed due to the stress from the pad and the interface with the interlayer insulating film is distorted, the stress is concentrated on the portion and cracks are likely to occur.

  If the wiring 90 disposed below the pad 2 is a “line and space structure” in which a plurality of line-shaped wirings are arranged as in the present embodiment, the stress from the pad 2 is moderately applied to the wiring 90. While being absorbed, it is released to the lower layer through the gap of the wiring 90. As a result, in the interlayer insulating film 207 under the pad 2, distortion generated at the interface with the wiring 90 is suppressed, and generation of cracks in the interlayer insulating film 207 is prevented. Note that although the case where the potential of the wiring 90 is floating is described in this embodiment mode, the present invention is not limited to this, and the wiring 90 is electrically connected to other circuits, for example, electrically connected to the pad 2. It may be connected.

  As a result of experiments, the present inventor has a particularly high effect of preventing the occurrence of cracks when the period in which the wirings 90 arranged below the pads are arranged (the sum of the line width and space width of each wiring 90) is 2 μm or less. I found out. Among them, it was also found that the effect is further improved when the width of each line-like wiring is made smaller than the interval (that is, the line width of each wiring 90 is ½ or less of the above cycle). .

  In the present embodiment, the plurality of wirings 90 are integrally formed by being connected to each other at both ends thereof as shown in FIG. 14, but may be formed separately from each other. Further, as far as the wiring 90 is concerned, the direction (longitudinal direction) of the line may not be the one shown in FIG. 14, and for example, the direction may be different by 90 ° (see FIG. 23). However, when a line-shaped wiring (for example, the wirings 80 to 84 of the fourth metal wiring layer in the present embodiment) is further provided below the line-shaped wiring 90, the direction of both lines is the same. (It will be described later in detail).

  In the present embodiment, the wiring 90 is floating, but the same potential as that of the pad 2 may be applied, for example, by forming the wiring 90 integrally with the wiring 91 in the fifth metal wiring layer. Good. It is also conceivable to provide a via for connecting the pad 2 and the wiring 90 in the interlayer insulating film 207 (sixth via layer) under the pad 2, but the sixth via layer is formed by a CMP (Chemical Mechanical Polishing) method. It is not desirable when forming using a metal. The reason will be described below.

  24 to 27 are process diagrams showing a via forming method using the CMP method. In this example, a tungsten via is formed in the interlayer insulating film 301 and the interlayer insulating film 303 on the copper wiring 302, and an aluminum wiring is formed thereon. That is, this example corresponds to the formation process of the sixth via layer and the sixth metal wiring layer in the formation of the semiconductor device of the present embodiment.

  In this via formation method, first, a via hole 304 is formed in the interlayer insulating film 303 (FIG. 24), and then a tungsten film 305 is deposited on the interlayer insulating film 303 to fill the via hole 304. At this time, as shown in FIG. 25, in the region where the via hole 304 is formed, a part of the tungsten film 305 is filled in the via hole 304.

  Thereafter, excess tungsten film 305 on the upper surface of interlayer insulating film 303 is removed by CMP to form via 306 (FIG. 26), and then aluminum is deposited on interlayer insulating film 303 and patterned. Then, an aluminum wiring 307 is formed (FIG. 27). When the excess tungsten film 305 on the upper surface of the interlayer insulating film 303 is removed by CMP, due to the difference between the polishing speed of the tungsten film 305 and the polishing speed of the interlayer insulating film 303, FIGS. As shown in FIG. 2, erosion occurs in which the finished film thickness of the interlayer insulating film 303 after CMP is not uniform. That is, the thickness of the interlayer insulating film 303 in the region where the via 306 is formed is thinner than that in the region where the via 306 is not formed. Erosion caused by CMP means that polishing of a dense region of wiring (corresponding to the via 304 in the example of FIG. 27) proceeds excessively as compared with a non-wiring region or a region having a low wiring density. This is a phenomenon in which the surface of the dense region is recessed from other regions. As shown in FIG. 25, when the wiring dense region where many buried portions of tungsten 305 are present and the region where few buried portions of tungsten 305 are separated, the polishing of the tungsten film 305 proceeds faster than the interlayer insulating film 303. Then, the pressure of the polishing pad applied to the interlayer insulating film 303 becomes relatively high in the wiring dense region. As a result, in the CMP process after the exposure of the interlayer insulating film 303, the polishing rate by CMP differs between the wiring dense region and the low wiring density region, and the interlayer insulating film 303 in the wiring dense region as shown in FIG. It is excessively polished and erosion occurs.

  In the semiconductor device of the present embodiment, when a wiring dense region is disposed under the pad 2, the thickness of the interlayer insulating film 207 under the pad 2 is reduced in the region where the via is formed. As the interlayer insulating film 207 becomes thinner, distortion due to stress tends to occur. Therefore, it is desirable that the interlayer insulating film 207 be as thick as possible, particularly under the pad 2 where the stress is generated. For this reason, it is desirable that no wiring be disposed under the pad 2 in the interlayer insulating film 207 (sixth via layer) or the wiring density be reduced. That is, it is most desirable not to provide the via of the sixth via layer in the region below the pad 2.

  In the present embodiment, a plurality of line-shaped wirings 80 to 84 are further disposed in the fourth metal wiring layer below the plurality of line-shaped wirings 90. Also in the line & space structure by these wirings 80 to 84, the stress from the pad 2 is moderately absorbed and released to the lower layer through the gap. Accordingly, an effect of preventing the occurrence of cracks in the interlayer insulating film 206 between the wiring 90 and the wirings 80 to 84 can be obtained.

  Here, the floating wirings 83 and 84 (hereinafter referred to as “floating lines”) are provided for the following two purposes. The first purpose is to make the period of the line and space structure in the fourth metal wiring layer uniform. This is because if the period of the line and space structure is non-uniform, the stress is not uniformly distributed but concentrated on a specific portion, and cracks are likely to occur. The second purpose is to prevent a short circuit among the power supply line 80, the ground line 81, and the power supply line 82. As shown in FIG. 12, the floating line 83 is provided between the power supply line 80 and the ground line 81, and the floating line 84 is provided between the ground line 81 and the power supply line 82. Therefore, for example, between the power supply line 80 and the ground line 81, the short circuit between the power supply and the ground does not occur unless the floating line 83 and the power supply line 80 are short-circuited and the floating line 83 and the ground line 81 are short-circuited. This is particularly effective when the period of the line and space structure including both the power supply potential line and the ground potential line is short.

  In other words, the floating lines 83 and 84 are not part of an integrated circuit including the internal circuit 1 and the input / output circuit 10 but maintain the uniformity of the line and space structure of the wiring disposed below the pad 2. In particular, it is separated from each of the power supply, ground, signal line, and pad so that no through current that would lead to destruction of the semiconductor device flows even if it is short-circuited to the power supply or ground. It is a thing.

  Ideally, it is desirable that the floating lines 83 and 84 are completely insulated from all of the power supply line, ground line, signal line and pad included in the semiconductor device. The floating lines 83 and 84 are fixed as current sources so that when a short circuit occurs with either the line 80 or the ground line 81, the semiconductor device can be prevented from being damaged due to a large current flowing, and further burnout can be prevented. The potential wiring is preferably connected through a large resistor. For example, it is considered that the semiconductor device can be prevented from being destroyed if a resistance value of 1 kΩ or more is secured between the floating lines 83 and 84 and another fixed potential wiring. That is, the concept of “floating” in the floating lines 83 and 84 of the present invention is that they are separated by a resistance value of 1 kΩ or more from a fixed potential wiring serving as a current source such as a power supply line, a ground line, a signal line and a pad. Is included. As a matter of course, when the semiconductor device has other floating dummy wirings and dummy pads, the floating lines 83 and 84 may be electrically connected to them.

  Further, as a result of the experiments by the present inventors, the line 90 in the fourth metal wiring layer below the pad 2 (power supply lines 80 and 82, ground line 81, floating lines 83 and 84) is also the case of the wiring 90. Similarly, it has been found that when each width is made smaller than the distance between each other (for example, wiring width = 0.2 μm, wiring distance = 0.5 μm), the effect of preventing cracks is enhanced. However, if the widths of the power supply lines 80 and 82 and the ground line 81 are made narrower than necessary, the resistance of the power supply wiring is increased, which is not desirable. In this experiment, when the width of each of the line-shaped wirings is set to be approximately the same as their spacing (for example, wiring width = 0.2 μm, wiring spacing = 0.2 μm), the resistance of the power wiring is prevented from being increased. However, good results were obtained in which cracking was sufficiently prevented.

  In this experiment, when line-shaped wiring (power supply lines 80, 82, ground lines 81, floating lines 83, 84) is further arranged below the line-shaped wiring 90 as in the present embodiment. When the directions of both lines were made the same, particularly good crack prevention effect was obtained. The reason why the effect decreases when the directions of the two lines are different is considered to be that when the two lines intersect each other in plan view, stress is concentrated at the intersection. Therefore, when the line-shaped power supply lines 80 and 82, the ground line 81, and the floating lines 83 and 84 are further provided below the line-shaped wiring 90 as in the present embodiment, the line direction of the wiring 90 is determined. Is preferably the same as the direction of the power lines 80 and 82, the ground line 81, and the floating lines 83 and 84 as in the example of FIG.

  Further, in the present embodiment, the power lines 80 and 82 of the fourth metal wiring layer and the ground line 81 are thinned in a line, so that the power lines 72 and 74 and the ground line 73 of the third metal wiring layer are reduced. It is desirable to make the width wider than this to prevent the resistance of the power supply wiring from increasing. If the power lines 72 and 74 and the ground line 73 of the third metal wiring layer are formed in thin lines like the power lines 80 and 82 and the ground line 81, the resistance to stress is further improved. However, since the stress from the pad 2 is sufficiently relaxed by the fifth metal wiring layer and the fourth metal wiring layer and the stress reaching the third metal wiring layer is relatively small, the wiring width of the third metal wiring layer is reduced. Even if it is increased, the decrease in the reliability of the semiconductor device is relatively small. Regarding the third metal wiring layer, the power supply potential of the input / output buffer is stabilized by increasing the wiring width and reducing the resistance of the power supply wiring compared to the fourth metal wiring layer or the fifth metal wiring layer. In addition, the protection performance against ESD surge can be enhanced.

  Further, as described above, in the present embodiment, frame-shaped power supply lines 70, 78, 88, 94 and ground lines 71, 79, 89, 95 are also provided in regions other than the lower side of the pad 2. Are electrically connected to the power lines 72 and 74 and the ground line 73 below the pad 2, respectively. In particular, the power line 94 and the ground line 95 of the sixth metal wiring layer that are the same as the pad 2 are thicker than the other metal wiring layers (for example, the first to fifth metal wiring layers are about 0.2 μm). In the case, the sixth metal wiring layer is about 2 μm). Therefore, the sixth metal wiring layer can be used for the power supply wiring as in this embodiment, which can greatly contribute to the prevention of the high resistance of the power supply wiring. As a result, the protection circuit 12 of the input / output circuit 10 can effectively release the surge current to the power supply wiring, and the reliability of the semiconductor device is improved.

It is a circuit diagram of the input-output part of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows the layout of the pad in the semiconductor device which concerns on embodiment. It is a figure which shows the layout of the pad in the semiconductor device which concerns on embodiment. FIG. 3 is a layout diagram of an input / output unit of the semiconductor device according to the embodiment. FIG. 3 is a layout diagram of an input / output unit of the semiconductor device according to the embodiment. FIG. 3 is a layout diagram of an input / output unit of the semiconductor device according to the embodiment. FIG. 3 is a layout diagram of an input / output unit of the semiconductor device according to the embodiment. FIG. 3 is a layout diagram of an input / output unit of the semiconductor device according to the embodiment. FIG. 3 is a layout diagram of an input / output unit of the semiconductor device according to the embodiment. FIG. 3 is a layout diagram of an input / output unit of the semiconductor device according to the embodiment. FIG. 3 is a layout diagram of an input / output unit of the semiconductor device according to the embodiment. FIG. 3 is a layout diagram of an input / output unit of the semiconductor device according to the embodiment. FIG. 3 is a layout diagram of an input / output unit of the semiconductor device according to the embodiment. FIG. 3 is a layout diagram of an input / output unit of the semiconductor device according to the embodiment. FIG. 3 is a layout diagram of an input / output unit of the semiconductor device according to the embodiment. FIG. 3 is a layout diagram of an input / output unit of the semiconductor device according to the embodiment. It is sectional drawing of the input-output part of the semiconductor device which concerns on embodiment. It is sectional drawing of the input-output part of the semiconductor device which concerns on embodiment. It is sectional drawing of the input-output part of the semiconductor device which concerns on embodiment. It is sectional drawing of the input-output part of the semiconductor device which concerns on embodiment. It is sectional drawing of the input-output part of the semiconductor device which concerns on embodiment. It is sectional drawing of the input-output part of the semiconductor device which concerns on embodiment. It is a figure which shows the modification of embodiment. It is a figure for demonstrating the effect of this invention. It is a figure for demonstrating the effect of this invention. It is a figure for demonstrating the effect of this invention. It is a figure for demonstrating the effect of this invention.

Explanation of symbols

2 pads, 3 power supply wiring, 10 input / output circuit, 11 output buffer, 12 protection circuit, 13 input buffer, 72, 74 power supply line, 73 ground line, 80, 81, 82, 90 line wiring, 83, 84 floating line.

Claims (23)

An active element formed on a semiconductor substrate;
A pad disposed above the active element;
A plurality of line-shaped first wirings formed using a wiring layer below the pad and disposed below the pad;
Each of said 1st wiring is arranged side by side with a period of 2 micrometers or less, The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1,
The width of each said 1st wiring is a semiconductor device characterized by being 1/2 or less of the said period. A semiconductor device according to claim 1 or 2, wherein
A plurality of line-shaped second wirings formed using a wiring layer below the first wirings and disposed below the pads;
The semiconductor device according to claim 1, wherein a direction of the line of the first wiring and a direction of the line of the second wiring are the same or orthogonal. The semiconductor device according to claim 3,
The semiconductor device, wherein the second wiring includes at least one of a power supply potential line and a ground potential line for supplying a predetermined power supply voltage to the active element. The semiconductor device according to claim 4,
The second wiring is
Both the power supply potential line and the ground potential line;
And a floating wiring disposed between the power supply potential line and the ground potential line. A semiconductor device according to claim 4 or claim 5, wherein
A third wiring formed using a wiring layer below the second wiring and disposed below the pad;
The third wiring is
A semiconductor device having a width equal to or greater than each width of the second wiring and electrically connected to the power supply potential line or the ground potential line included in the second wiring. A semiconductor device according to any one of claims 4 to 6,
A fourth wiring formed using the same wiring layer as the pad;
The fourth wiring is
A semiconductor device, wherein the semiconductor device is electrically connected to the power supply potential line or the ground potential line included in the second wiring. A semiconductor device according to claim 6 or claim 7, wherein
The semiconductor device, wherein the active element includes a protection element connected between the pad and the power supply potential line and between the pad and the ground potential line. An active element formed on a semiconductor substrate;
A pad disposed above the active element;
A plurality of line-shaped first wirings formed using a wiring layer below the pad and disposed below the pad;
A plurality of line-shaped second wirings formed using a wiring layer below the first wirings and disposed below the pads;
The semiconductor device according to claim 1, wherein a direction of the line of the first wiring and a direction of the line of the second wiring are the same or orthogonal. The semiconductor device according to claim 9,
The semiconductor device, wherein the second wiring includes at least one of a power supply potential line and a ground potential line for supplying a predetermined power supply voltage to the active element. The semiconductor device according to claim 10,
The second wiring is
Both the power supply potential line and the ground potential line;
And a floating wiring disposed between the power supply potential line and the ground potential line. A semiconductor device according to claim 10 or claim 11,
A third wiring formed using a wiring layer below the second wiring and disposed below the pad;
The third wiring is
A semiconductor device having a width equal to or greater than each width of the second wiring and electrically connected to the power supply potential line or the ground potential line included in the second wiring. A semiconductor device according to any one of claims 10 to 12,
A fourth wiring formed using the same wiring layer as the pad;
The fourth wiring is
A semiconductor device, wherein the semiconductor device is electrically connected to the power supply potential line or the ground potential line included in the second wiring. A semiconductor device according to claim 12 or claim 13, wherein
The semiconductor device, wherein the active element includes a protection element connected between the pad and the power supply potential line and between the pad and the ground potential line. An active element formed on a semiconductor substrate;
A pad disposed above the active element;
A plurality of line-shaped first wirings formed using a wiring layer below the pad and disposed below the pad;
The first wiring is
A semiconductor device comprising: a power supply potential line and a ground potential line for supplying a predetermined power supply voltage to the active element; and a floating wiring disposed between the power supply potential line and the ground potential line . The semiconductor device according to claim 15, wherein
A second wiring formed using a wiring layer below the first wiring and disposed below the pad;
The second wiring is
A semiconductor device having a width equal to or greater than a width of each of the first wirings and electrically connected to the power supply potential line or the ground potential line included in the first wiring. A semiconductor device according to claim 15 or claim 16, wherein
A third wiring formed using the same wiring layer as the pad;
The third wiring is
A semiconductor device, wherein the semiconductor device is electrically connected to the power supply potential line or the ground potential line included in the first wiring. A semiconductor device according to any one of claims 15 to 17,
The semiconductor device, wherein the active element includes a protection element connected between the pad and the power supply potential line and between the pad and the ground potential line. An active element formed on a semiconductor substrate;
A pad disposed above the active element;
A plurality of line-shaped first wirings formed using a wiring layer below the pad and disposed below the pad;
A second wiring formed using a wiring layer below the first wiring and disposed below the pad;
The first wiring is
Including at least one of a power supply potential line and a ground potential line for supplying a predetermined power supply voltage to the active element,
The second wiring is
A semiconductor device having a width equal to or greater than a width of each of the first wirings and electrically connected to the power supply potential line or the ground potential line included in the first wiring. The semiconductor device according to claim 19, wherein
A third wiring formed using the same wiring layer as the pad;
The third wiring is
A semiconductor device, wherein the semiconductor device is electrically connected to the power supply potential line or the ground potential line included in the first wiring. A semiconductor device according to claim 19 or claim 20, wherein
The semiconductor device, wherein the active element includes a protection element connected between the pad and the power supply potential line and between the pad and the ground potential line. An active element formed on a semiconductor substrate;
A pad disposed above the active element;
A plurality of line-shaped first wirings formed using a wiring layer below the pad and disposed below the pad;
A second wiring formed using the same wiring layer as the pad;
The first wiring includes at least one of a power supply potential line and a ground potential line for supplying a predetermined power supply voltage to the active element,
The semiconductor device, wherein the second wiring is electrically connected to the power supply potential line or the ground potential line included in the first wiring. 23. The semiconductor device according to claim 22, wherein
The semiconductor device, wherein the active element includes a protection element connected between the pad and the power supply potential line and between the pad and the ground potential line.

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