JPH03200331A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH03200331A
JPH03200331A JP34120989A JP34120989A JPH03200331A JP H03200331 A JPH03200331 A JP H03200331A JP 34120989 A JP34120989 A JP 34120989A JP 34120989 A JP34120989 A JP 34120989A JP H03200331 A JPH03200331 A JP H03200331A
Authority
JP
Japan
Prior art keywords
wiring
slits
current
bending portion
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP34120989A
Other languages
Japanese (ja)
Other versions
JP2931346B2 (en
Inventor
Hisaaki Takamizo
高溝 久明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP34120989A priority Critical patent/JP2931346B2/en
Publication of JPH03200331A publication Critical patent/JPH03200331A/en
Application granted granted Critical
Publication of JP2931346B2 publication Critical patent/JP2931346B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To divide a current path in a bending portion into a plurality of the current paths and prevent an electromigration from being generated at a bending point by providing the bending portion of a wide wiring with a number of slits. CONSTITUTION:A plurality of slits 12 are provided in a direction wherein a wiring 11 extends and the slits 12 are also bent according to a bend in the bending portion 13 of the wiring 11. Since the wiring 11 may be separated into a plurality of thin wirings 14, the slits 12 are formed with prescribed widths according to the minimum design rule of a process concerned and may be formed by etching at the same time as the one conducted in the patterning process of the wiring 11. Thus, since the provision of the slits 12 separates the wiring 11 in the bending portion 13 into a plurality of the thin wirings 14, a current 15 flowing in the bending portion 13 is disposed to every thin wiring 14 before the wiring 11 bend. Thus, when a current density is made not larger than a prescribed value, an electromigration phenomenon is not generated.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は配線の曲折部に局部的な電流集中が生じること
によるエレクトロマイグレーション破壊を防止できる半
導体集積回路に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit that can prevent electromigration damage caused by localized current concentration at bent portions of wiring.

(ロ)従来の技術 従来より、集積回路の高集積化・高密度化が高められ、
デバイスの小型化が進むにつれて、相互接続のための配
線の幅が微細になっている。その一方で、電源ライン(
■ゎo+Vis)は所要の電流容量を確保しく電流密度
を一定値以下に抑える)且つ抵抗分による電圧降下を抑
えるために信号ライン等よりは太い配線が要求されてい
ることも事実である。従って、製造プロセスがサブミク
ロンルールに移行しようとも、数箇所には必ず前記太い
配線が延在することになる。
(b) Conventional technology Higher integration and higher density of integrated circuits have been achieved than in the past.
As devices become smaller, the width of wiring for interconnections becomes finer. On the other hand, the power line (
It is also true that wiring thicker than signal lines, etc. is required in order to secure the required current capacity and suppress the current density below a certain value) and to suppress the voltage drop due to resistance. Therefore, even if the manufacturing process shifts to the submicron rule, the thick wiring will always extend at several locations.

(ハ〉発明が解決しようとする課題 しかしながら、電流は抵抗が最も少い部分を流れようと
する性質があるため、例えば第3図に示すように配線(
1)が直角に曲折した部分では、電流(2)が配線(1
)の内側(図示A点)に集中するようになる。配線(1
)の線幅が太いほど集中の度合が強くなり、その結果電
流密度が一定値(約106A / cm ” )を超え
てエレクトロマイグレーション現象が発生してしまう(
例えば、特開昭64−45142号公報)。この現象が
生じると、配線の断線やヒロック発生による短絡が発生
し、配線の信頼性を低下させる原因となっていた。
(C) Problems to be Solved by the Invention However, since current tends to flow through the part with the least resistance, for example, as shown in Figure 3, the wiring (
At the part where 1) is bent at a right angle, the current (2) is connected to the wire (1).
) (point A in the figure). Wiring (1
) The thicker the line width, the stronger the degree of concentration, and as a result, the current density exceeds a certain value (approximately 106 A/cm") and an electromigration phenomenon occurs (
For example, Japanese Patent Application Laid-Open No. 64-45142). When this phenomenon occurs, short circuits occur due to wire breaks and hillocks, which causes a reduction in the reliability of the wires.

(ニ)課題を解決するための手段 本発明は上記従来の欠点に鑑み成されたもので、配線(
11)の曲折部(13)に配線(11)の延在方向と平
行にスリット(12〉を設けることにより、エレクトロ
マイグレーションによる破壊を防止した半導体集積回路
を提供するものである。
(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional drawbacks, and the wiring (
By providing a slit (12) in the bent portion (13) of the wiring (11) in parallel to the extending direction of the wiring (11), a semiconductor integrated circuit is provided that is prevented from being destroyed by electromigration.

(*)作用 本発明によれば、スリット(12)を設けたことにより
曲折部(13)の配線が複数本の細状配線(14)に分
断されるので、電流(15)は各細状配線(14〉ごと
に流れ、その為曲折点(A>での電流集中が緩和される
(*) Effect According to the present invention, by providing the slit (12), the wiring at the bending part (13) is divided into a plurality of thin wires (14), so that the current (15) is applied to each thin wire. The current flows through each wire (14), which alleviates the current concentration at the bending point (A).

(へ)実施例 以下に本発明を図面を参照しながら詳細に説明する。(f) Example The present invention will be explained in detail below with reference to the drawings.

第1図は本発明の一実施例を示す平面図である。図中、
(11)は配線、(12)はスリットである。
FIG. 1 is a plan view showing one embodiment of the present invention. In the figure,
(11) is a wiring, and (12) is a slit.

配線(11)は、シリコン半導体基板上に拡散領域やゲ
ート電極(ポリシリコン、ポリサイド等)を形成するこ
とにより構成された個々の半導体デバイスを相互接続す
るものであり、アルミニウム(AP)又はアルミニウム
・シリコン(Ajl!−5t)ノ蒸着又はスパッタ法に
よる堆積とホトレジストプロセスによるバターニングに
よって形成きれる。
The wiring (11) interconnects individual semiconductor devices constructed by forming diffusion regions and gate electrodes (polysilicon, polycide, etc.) on a silicon semiconductor substrate, and is made of aluminum (AP) or aluminum. It can be formed by depositing silicon (Ajl!-5t) by evaporation or sputtering and patterning by a photoresist process.

多層配線の何層口に位置するかは任意であるが、下層は
集積度を向上する為に利用したいので、電源ライン(V
Dn;Vss)等のように線幅が100μ〜200μに
も達する配線(11〉は上層へと追いやられるのが普通
である。尚、このような電源ラインを要求するデバイス
としては、出力バッファトランジスタ等があげられる。
It is up to you which layer of the multilayer wiring it is located, but since you want to use the lower layer to improve the degree of integration, the power supply line (V
Wires (11) with a line width of 100μ to 200μ, such as Dn; etc. can be mentioned.

スリット(12)は、同図から明らかなように配線(1
1)の延在方向に対して平行に複数本設けられ、配線(
11)の曲折部(13)においては曲折に従ってスリッ
ト(12)も曲げられる。スリット(12〉の幅は太く
する必要が無く、配線(11)が複数本の細状配線(1
4)に分離されれば良いから、そのプロセスの最小設計
ルールで一定幅(3〜5μ)に形成する。
As is clear from the figure, the slit (12) is connected to the wiring (1
1) A plurality of wires are provided parallel to the extending direction of the wiring (
At the bending part (13) of 11), the slit (12) is also bent according to the bending. The width of the slit (12) does not need to be wide, and the wiring (11) has multiple thin wiring (1
4), so it is formed to have a constant width (3 to 5 μm) according to the minimum design rule of the process.

スリット(12)の形成は配線(11)のバターニング
工程と同時的にエツチング加工すれば良い。また、1つ
の細状配線(14)からその内側の他の細状配線(14
)へと電流(15)が流れないように、曲折部〈13)
においてはスリット(12)は連続しなければならない
。配線(12)はSin、 、 SiN等の(層間)絶
縁膜上を延在させるので、スリット(12)内は前記絶
縁膜が露出することになる。
The slits (12) may be formed by etching simultaneously with the patterning process of the wiring (11). Also, from one thin wire (14) to another thin wire (14) inside it,
) to prevent the current (15) from flowing to the bent part <13).
In this case, the slits (12) must be continuous. Since the wiring (12) extends over an (interlayer) insulating film such as Sin, SiN, etc., the insulating film is exposed inside the slit (12).

斯る構成によれば、スリット(12)を設けたことによ
って曲折部(13)の配線(11)が複数本の細状配線
(14)に分離されるので、曲折部(13)を流れる電
ffff(15)は配線(11)が曲折する以前に各細
状配線(14)ごとに分散されることになる。エレクト
ロマイグレーション現象とは、配線(11)に一定値(
約10’A/an”)以上の大電流が流れた時に、素材
であるAe原子が電子の移動方向に移動する現象を指し
、A4原子が移動した跡にボイドが発生し、ボイド発生
により配線断面積が減少し、電流密度がさらに高くなり
、ジュール熱による温度上昇が生じ、ボイドの成長が加
速され、そして断線に至るというメカニズムで配線(1
1)の故障が発生する。また、AP原子が移動し蓄積し
た場所にはヒロックが発生し、これが近接配線間の短絡
故障を生じる。すなわち、電流密度を一定値以下として
おけば、エレクトロマイグレーション現象は生じないの
である。
According to this configuration, the wiring (11) of the bent portion (13) is separated into a plurality of thin wires (14) by providing the slit (12), so that the electric current flowing through the bent portion (13) is reduced. ffff(15) is distributed to each thin wire (14) before the wire (11) is bent. The electromigration phenomenon refers to the electromigration phenomenon when the wiring (11) has a certain value (
Refers to the phenomenon in which Ae atoms, which are the material, move in the direction of electron movement when a large current of approximately 10'A/an'' or more flows, and voids are generated in the traces where A4 atoms have moved. The wiring (1
1) failure occurs. In addition, hillocks occur at locations where AP atoms move and accumulate, which causes short-circuit failures between adjacent wirings. In other words, if the current density is kept below a certain value, electromigration will not occur.

従って、本発明は電流(15〉が各細状配線(14)に
分散され、細状配線(14)はスリット(12)によっ
て個々に分離されているので、曲折部(13)において
電流(15〉が−点に集中することが無く、電流密度が
前記一定値を超えることが無いので、エレクトロマイグ
レーション現象を防止できる。
Therefore, in the present invention, the current (15) is distributed to each thin wire (14), and the thin wires (14) are individually separated by the slits (12). ) is not concentrated at the - point and the current density does not exceed the above-mentioned constant value, so electromigration phenomenon can be prevented.

第2図は本発明の第2の実施例を示す。前の実施例と異
るのは、図面から明らかなように内側のスリット(12
)はど遠方まで伸びていることである。この様な形状と
しておけば、電流(15)の特性に従って曲折点(13
)に向かった電流(例えば、図示13a)は、その位置
から最も近い細状配線(例えば、図示14a)に必ず捕
えられるので、先の実施例より電流(15)の分散を確
実にできる。
FIG. 2 shows a second embodiment of the invention. The difference from the previous embodiment is that the inner slit (12
) extends far into the distance. With this shape, the bending point (13) will be determined according to the characteristics of the current (15)
) (for example, 13a in the figure) is always captured by the thin wire closest to the position (for example, 14a in the figure), so that the current (15) can be dispersed more reliably than in the previous embodiment.

さらに、線幅が太い配線(11)下に層間絶縁膜を介し
て下層の配線(16)が延在するような場合、ストレス
マイグレーションによる下層配線(16)の断線をも防
止できる。ストレスマイグレーションとは、AQと絶縁
膜との熱膨張によるストレスによって引き起こされるも
のであり、線幅が太くなるほど他に与えるストレス量も
大となるので下層の配線(16)の断線を引き起こすの
であるが、本発明のようにスリット(12)を設ければ
ストレスも分散されるから、下層の配線(16)の断線
も防止できるのである。この効果は第1.第2の実施例
共に同様である。
Furthermore, in the case where the lower layer wiring (16) extends below the wire (11) with a large line width via an interlayer insulating film, disconnection of the lower layer wiring (16) due to stress migration can also be prevented. Stress migration is caused by stress due to thermal expansion of the AQ and insulating film, and the thicker the line width, the greater the amount of stress applied to other lines, causing disconnection of the underlying wiring (16). By providing the slits (12) as in the present invention, stress is also dispersed, thereby preventing disconnection of the underlying wiring (16). This effect is the first. The same applies to the second embodiment.

(ト)発明の詳細 な説明した如く本発明によれば、幅広の配線(11)の
曲折部(13)に多数本のスリット(12)を設けたの
で、曲折部(13)における電流通路を複数に分散して
、曲折点(図示A)のエレクトロマイグレーション発生
を防止できる利点を有する。
(g) As described in detail, according to the present invention, a large number of slits (12) are provided in the bent portion (13) of the wide wiring (11), so that the current path in the bent portion (13) is It has the advantage that electromigration can be prevented from occurring at the bending point (A in the figure) by dispersing it into a plurality of parts.

また、曲折部(13)の下に下層配線(16)を有する
構成では、幅広の配線(11)が下層配線(16)に与
えるストレスをもスリット(12)によって分散できる
ので、下層配m(x6)のストレスマイグレーションに
よる故障をも防止できる利点を有する。
In addition, in the configuration in which the lower layer wiring (16) is provided under the bent portion (13), the stress exerted on the lower layer wiring (16) by the wide wiring (11) can be dispersed by the slit (12). This has the advantage that failures due to stress migration (x6) can also be prevented.

従って本発明によれば、信頼性の高い多層配線構造とす
ることができる。
Therefore, according to the present invention, a highly reliable multilayer wiring structure can be achieved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図と第2図は本発明を説明するための平面図、第3
図は従来例を説明するための断面図である。
Figures 1 and 2 are plan views for explaining the present invention, and Figure 3 is a plan view for explaining the present invention.
The figure is a sectional view for explaining a conventional example.

Claims (3)

【特許請求の範囲】[Claims] (1)直角又は直角に近い角度で曲折し延在する電極配
線を具備する半導体集積回路において、前記曲折部に前
記電極配線の延在方向と平行に延在する複数本のスリッ
トを設けたことを特徴とする半導体集積回路。
(1) In a semiconductor integrated circuit having an electrode wiring extending at a right angle or at an angle close to a right angle, a plurality of slits extending parallel to the extending direction of the electrode wiring are provided in the bent part. A semiconductor integrated circuit characterized by:
(2)前記スリットは前記曲折部の内側において遠方ま
で伸びていることを特徴とする請求項第1項に記載の半
導体集積回路。
(2) The semiconductor integrated circuit according to claim 1, wherein the slit extends far inside the bent portion.
(3)前記曲折部に層間絶縁膜を介して下層の配線層が
重畳して延在することを特徴とする請求項第1項に記載
の半導体集積回路。
(3) The semiconductor integrated circuit according to claim 1, wherein a lower wiring layer overlaps and extends over the bent portion with an interlayer insulating film interposed therebetween.
JP34120989A 1989-12-27 1989-12-27 Semiconductor integrated circuit Expired - Lifetime JP2931346B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34120989A JP2931346B2 (en) 1989-12-27 1989-12-27 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34120989A JP2931346B2 (en) 1989-12-27 1989-12-27 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPH03200331A true JPH03200331A (en) 1991-09-02
JP2931346B2 JP2931346B2 (en) 1999-08-09

Family

ID=18344225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34120989A Expired - Lifetime JP2931346B2 (en) 1989-12-27 1989-12-27 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JP2931346B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077203A (en) * 1999-08-05 2001-03-23 Infineon Technologies Ag Integrated semiconductor chip
US7392497B2 (en) * 2004-07-20 2008-06-24 International Business Machines Corporation Regular routing for deep sub-micron chip design

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077203A (en) * 1999-08-05 2001-03-23 Infineon Technologies Ag Integrated semiconductor chip
JP4629837B2 (en) * 1999-08-05 2011-02-09 インフィネオン テクノロジーズ アクチエンゲゼルシャフト Integrated semiconductor chip
US7392497B2 (en) * 2004-07-20 2008-06-24 International Business Machines Corporation Regular routing for deep sub-micron chip design

Also Published As

Publication number Publication date
JP2931346B2 (en) 1999-08-09

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