JPH0437157A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to eliminate the need for increasing the wiring width of an upper wiring layer, prevent a drop in a current capacity induced by reducing a film thickness of said upper wiring layer at an offset section of a lower layer wiring in a multi-layer wiring and hence contribute toward the miniaturization of the wiring layer by allowing the lower wiring layer to intersect the upper wiring layer on the slant. CONSTITUTION:In a semiconductor device which comprises a substrate 2, a lower wiring layer 4 installed on the substrate 2, and an upper wiring layer 8, which is installed by way of an interlaminar insulation layer 6 on a rough section where the lower wiring layer 4 is formed, and provides a film thickness d1 on a first section, which is larger than a film thickness d2 on an offset of the aforesaid rough section. The lower wiring layer 4 intersects the upper wiring layer 8 on the slant. The average film thickness of the upper wiring layer over the intersected region in its cross section is adapted to be larger than the film thickness d2 on the offset of the aforesaid rough section. More specifically. The sections B-B, and C-C of the upper layer in its cross section are as illustrated so that the film thickness of the upper wiring layer 8 may be reduced, thereby producing some section whose film thickness is d2 and other section which is possessed of the film thickness d1 on the lower wiring layer 4 or on the upper part of the flat section of the substrate 2.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a semiconductor device, and particularly to a semiconductor device with multilayer wiring, in which the upper layer wiring at the stepped portion of the lower layer wiring in the multilayer wiring is provided without widening the wiring width of the upper layer wiring layer. The purpose of the present invention is to provide a semiconductor device and a method for manufacturing the same that can prevent a decrease in current capacity due to a decrease in layer thickness and contribute to miniaturization of wiring layers. A lower wiring layer and an upper wiring layer provided on the uneven portion formed by the lower wiring layer via an insulating layer between the eyebrows, and whose film thickness on the step of the uneven portion is smaller than the film thickness on the flat portion. The wiring direction of the lower wiring layer and the wiring direction of the upper wiring layer diagonally intersect with each other, and the average film thickness of the widthwise cross section of the upper wiring layer in the intersecting region is equal to the unevenness. The thickness of the film is larger than that on the step.

[Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having multilayer wiring.

[Prior Art] In recent years, as semiconductor devices have become more highly integrated and faster, interconnect layers have become increasingly finer, and interconnect layers are required to have a higher current capacity in order to prevent defects due to electromigration. There is. For this reason, the issue is whether improvements are being made in wiring and electrode materials, and how to solve the problem of thinning of the upper wiring layer at the stepped portion of the lower wiring in multilayer wiring, or the so-called decrease in S thickness. It had become.

For example, as shown in FIG. 7, a plurality of rows of lower wiring layers 4 with a line width are provided in parallel on the base substrate 2 at intervals of yiis. An upper wiring layer 8 is provided with an interlayer insulating layer 6 interposed therebetween, and the wiring direction of the upper wiring layer 8 is orthogonal to the wiring direction of the lower wiring layer 4.

In such a multilayer wiring, the film thickness of the upper wiring layer 8 is reduced at the step portion of the uneven portion formed by the lower wiring 4. For example, above the lower wiring layer 4 and the flat portion of the base substrate 2, the upper wiring layer 8 has a desired film thickness d1, but the upper wiring layer 8 at the stepped portion of the lower wiring 4 has a thickness d1 greater than that of the upper wiring layer 8. The film thickness d2 becomes much thinner. In the thinned portion, resistance increases and current capacity decreases.

Conventionally, to solve this problem, the wiring width of the upper wiring layer 8 is increased to compensate for the increase in wiring resistance and the decrease in current capacity due to the decrease in the film thickness of the upper wiring layer 8 at this stepped portion. Ta.

[The problem that the invention tries to solve! M] However, as semiconductor devices have become more highly integrated in recent years, the number of layers has increased further, the level difference has become larger, and the reduction in the thickness of the upper wiring layer has become even more serious. Furthermore, with the miniaturization of wiring, it has become difficult in terms of layout to compensate for the effect of a decrease in the thickness of the upper wiring layer by widening the wiring width.

Therefore, the present invention prevents a decrease in current capacity due to a decrease in the film thickness of the upper wiring layer at the stepped portion of the lower wiring in multilayer wiring, without increasing the wiring width of the upper wiring layer, and makes the wiring layer m thinner. Semiconductor devices and their′# that can contribute to
The purpose is to provide a way to send money.

[Means to solve problems] The present invention will be explained in detail with reference to FIG.

FIG. 1(a) is a plan view showing a semiconductor device according to the present invention;
Figures 1(b), (c), and (d) are respectively Figure 1(a).
FIG. 2 is a cross-sectional view showing a cross section along line AA, a cross section along BB, and a cross section along line C-C of the semiconductor device of FIG.

On the base substrate 2, a plurality of lower wiring layers 4 having a line width are provided in parallel at intervals of a space width S. Further, on these lower wiring layers 4, an upper wiring layer 8 is provided with a glabella insulating layer 6 interposed therebetween. As shown in the plan view of FIG. 1(a), the wiring direction of the lower wiring layer 4 and the wiring direction of the upper wiring layer 8 are not orthogonal but intersect obliquely.

At this time, when looking at the A-A cross section in the wiring direction of the upper wiring layer 8, as shown in FIG. 8 has the desired film thickness d1, but the film thickness of the upper wiring layer 8 decreases at the stepped portion of the lower wiring layer 4, and the film thickness becomes much thinner than the film thickness d1, that is, the film thickness d2. . This upper wiring layer 8
The occurrence of decrease in film thickness is the same as in the conventional case.

On the other hand, the BB cross section in the width direction of the upper wiring layer 8, the C
Looking at the -C cross section, as shown in FIGS. 1(c) and 1(d), there is a portion where the film thickness of the upper layer wiring layer 8 decreases to a thickness of d2, and there is also a portion where the film thickness of the upper layer wiring layer 8 decreases to d2. It has a portion having a film thickness d1 above the flat portion of the layer 4 or the underlying substrate 2. Therefore, the average film thickness d of the upper wiring layer 8 in the cross section in the width direction is always larger than the film thickness d2 on the step of the lower wiring layer 4. This holds true at any position in the area where it intersects with the lower wiring layer 4.

[Function] That is, in the present invention, in the region where the lower wiring layer 4 and the upper wiring layer 8 three-dimensionally intersect, the film thickness of the upper wiring layer 8 is reduced at the stepped portion of the lower wiring 4, as in the conventional case. However,
Since the wiring direction of the lower wiring layer 4 and the wiring direction of the upper wiring layer 8 obliquely intersect, the average film thickness d of the width direction cross section of the upper wiring layer 8 is always larger than its film thickness d2. Therefore, the cross-sectional area of the upper wiring layer 8 is always larger than the cross-sectional area of the conventional upper wiring layer 8 at the position where the film thickness decrease occurs.

Thereby, the current capacity of the upper wiring layer 8 can be prevented from decreasing and a high current capacity can be maintained without increasing the wiring width of the upper wiring layer 8.

[Example] The present invention will be specifically described below based on an illustrative example.

FIG. 2 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

For example, on a base substrate 2 such as a semiconductor substrate having an insulating film on its surface, two lower wiring layers 4 each having a line width of 1 are provided in parallel with a space width S between them. Further, an upper wiring layer 8 is provided on these lower wiring layers 4 via a glabella insulating layer 6, and intersects with the lower wiring layer 4 three-dimensionally.

In this intersection region, the wiring direction of the lower wiring layer 4 is linearly inclined with respect to the wiring direction of the upper wiring layer 8. The lower wiring layer 4 before and after the intersection with the upper wiring layer 8
The displacement Ll, that is, the displacement of the lower wiring layer 4 in the width direction of the upper wiring layer 8, is larger than the sum of the line @1 and the space width S of the lower wiring layer 4. That is, L + > M + s.

With this condition, the space portion of the lower wiring NJ4 does not occupy the entire cross section of the upper wiring layer 8 in the width direction at any position in the intersection area between the lower wiring layer 4 and the upper wiring layer 8. The proportion occupied by the space portion of the lower wiring layer 4 in the cross section of the upper wiring layer 8 in the width direction is S/(''±S)
is always smaller than . Therefore, if the thickness of the upper wiring layer 8 above the flat part of the lower wiring layer 4 and the base substrate 2 is d, and the thickness of the upper wiring layer 8 at the stepped part of the lower wiring 4 is d2, then the thickness of the upper wiring layer 8 is The average film thickness d in the cross section in the width direction is d >< J d + + s d 2 )/(l
+s 1.

Therefore, the cross-sectional area of the upper wiring layer 8 is smaller than that of the conventional upper wiring layer 8.
is always larger than the cross-sectional area at the film thickness d2 where the film thickness decrease occurs.

Normally, line width 1 and space width S are almost equal, so Oh S Then, d, > d.

By being d＞　(d,+d2＞　/2＞a2 becomes.

As described above, according to the first embodiment, in the intersection area between the upper wiring layer 8 and the lower wiring layer 4, the wiring direction is linearly inclined in the width direction of the upper wiring layer 8 of the lower wiring layer 4. Since the displacement L1 is larger than the sum of the line width 1 and the space width S of the lower wiring layer 4, the average film thickness d in the cross section in the width direction of the upper wiring layer 8 can be adjusted to It can always be made larger than the film thickness d2 of the wiring layer 8. Thereby, the cross-sectional area of the upper wiring layer 8 can always be made larger than the cross-sectional area of the conventional upper wiring layer 8 at the film thickness d2 where reduction occurs.

In the first embodiment, the amount of displacement L+ of the lower wiring layer 4 with respect to the width direction of the upper wiring layer 8 is defined as the amount of displacement L+ of the lower wiring layer 4.
Although the displacement amount is larger than the sum of the line width 1 and the space width S, if this displacement amount is larger than the space width S, a certain effect can be achieved. That is, in the cross section of the upper wiring layer 8 in the width direction, there is always at least one location above the flat portion where the film thickness is d1. As a result, the cross-sectional area can always be made larger than the cross-sectional area at the film thickness d2 where the reduction of the conventional upper wiring layer 8 occurs.

Next, a modification of the semiconductor device according to the first embodiment will be described using FIG. 3.

In the first embodiment, the lower wiring layer 4 is provided in parallel.
In contrast, in this modification, as shown in FIG. 3, three lower wiring layers 4 each having a line width are provided in parallel with an interval of a space width S. ing.

In this case, the lower wiring layer 4 in the width direction of the upper wiring layer 8
By setting the amount of displacement L1 of The film thickness d2 of the wiring layer 8 can always be made larger than that of the wiring layer 8. The cross-sectional area of the i-layer 8 can always be made larger than the cross-sectional area of the conventional upper wiring layer 8 at the film thickness d2 where reduction occurs.

Further, as shown in FIG. 3, in correlation with the width of the upper wiring layer 8, the intersection area between the upper wiring layer 8 and the lower wiring layer 4 is inclined linearly in the wiring direction of the lower wiring layer 4. It is also possible to extend the area equally on both sides. This is because the cross-sectional area of the upper wiring layer 8 in the width direction can be ensured at a certain value or more in the linearly inclined intersection area of the lower wiring layer 4.

Further, as shown in FIG. 3, even if a through hole 10 opened upward or downward is provided in the intersection area between the upper wiring layer 8 and the lower wiring layer 4, the effect is not affected.

Furthermore, when there are four or more lower wiring layers 4, for example N, the displacement L1 of the upper wiring layer 4 in the width direction of the upper wiring layer 8 is calculated as > (J +-5) (N-1). By doing so, it is possible to achieve the same effects as the first embodiment or the modified example.

Next, a semiconductor device according to a second embodiment of the present invention will be explained using FIG.

Three lower wiring layers 4 of line width p are provided in parallel at intervals of a space width S, and an upper wiring layer 8 is provided on the lower wiring layer 4 with an interlayer insulating layer 6 interposed therebetween. intersect three-dimensionally. In this intersection area, the lower wiring layer 4 is bent in the shape of a "<". The wiring direction of this lower wiring layer 4 is a continuous straight line except for the area where it intersects with the upper wiring layer 8. Therefore, the amount of displacement L2 of the lower wiring layer 4 at the angle of refraction of this dogleg shape is equal before and after the intersection with the upper wiring N8, and the value thereof is L 2 > s.

With this condition, the space portion of the lower wiring layer 4 will not occupy the entire cross section of the lower wiring layer 8 in the width direction at any position in the intersection area between the lower wiring layer 4 and the upper wiring layer 8. In the cross section of the upper wiring layer 8 in the width direction, at least one part can have a film thickness d1 above the flat part.

Therefore, the average film thickness d of the upper wiring layer 8 in the cross section in the width direction is always larger than the film thickness d2 of the upper wiring layer 8 at the stepped portion of the lower wiring 4.

As described above, according to the second embodiment, since the displacement L2 at the bending point of the "<" shape of the lower wiring layer 4 with respect to the width direction of the upper wiring layer 8 is larger than the space width S, the upper wiring layer 8 The average film thickness d in the cross section in the width direction of the layer 8 can always be made larger than the film thickness d2 of the upper layer wiring F18 at the stepped portion of the lower layer wiring 4.
The cross-sectional area of the upper wiring layer 8 can always be made larger than the cross-sectional area at the film thickness d2.

Furthermore, except for the area where it intersects with the upper wiring layer 8, the wiring direction of the lower wiring layer 4 is a continuous straight line before and after this intersection, so it is not necessary to change the layout of the cables in the conventional semiconductor device. Therefore, the second embodiment can be easily applied to existing types of semiconductor devices by simply changing the mask of the lower wiring layer 4.

Next, a modification of the semiconductor device according to the second embodiment will be described with reference to FIG.

In the second embodiment, the displacement L2 of the lower wiring layer 4 at the bending point of the character "<" is equal before and after the intersection with the upper wiring layer 8, whereas in the present modification As shown in FIG. 5, the amount of displacement of the lower wiring layer 4 at the bending point of the character "<" increases with respect to before and after the intersection with the upper wiring layer 8.

In this case, the amount of displacement of the lower wiring layer 4 from both ends of the intersection area in the width direction of the upper wiring layer 8 is expressed as: , L,
Then, if L −, L s > s, the same effect as the second embodiment can be achieved. In such a case, the amount of displacement of the lower wiring layer 4 in the wiring direction before and after the intersection area is L4-L.

Therefore, according to this modification, the amount of displacement of the lower wiring layer 4 from both ends of the intersection area with respect to the width direction of the upper wiring layer 8,
, L, respectively, it is possible to control the displacement of the lower wiring layer 4 before and after the crossing area, jlL, -2. Furthermore, the amount of displacement of the lower wiring layer N4 before and after the crossing area, Although −L can be made smaller than in the first embodiment, the same effect as in the first embodiment can be achieved.

Next, referring to FIG. 6, a semiconductor device 1 according to a third embodiment of the present invention will be described.

Whereas in the second embodiment, the lower wiring layer 4 is bent only once in the shape of a "<" in the intersection area between the lower wiring layer 4 and the upper wiring layer 8, the third embodiment , the lower wiring layer 4 is bent twice in the shape of a "<". That is, it has two refraction points.

The wiring direction of this lower wiring layer 4 is a continuous straight line except for the area where it intersects with the upper wiring layer 8. Therefore, the displacement amounts LS, L of the lower wiring layer 4 at the two bending points
4 are equal before and after the intersection with the upper wiring layer 8, respectively. If these values are L, , L,>s, the same effect as the second embodiment can be achieved.

Therefore, according to the third embodiment, the lower wiring layer 4 is
By bending the lower wiring layer 4 twice in the shape of a square to have two bending points, even if the displacement L of the lower wiring layer 4 at the bending point is smaller or equal to that of the second embodiment, the above-mentioned It is possible to achieve the same effect as the second embodiment.

Note that in the third embodiment, the lower wiring layer 4 is
Although a case has been described in which the beam is refracted twice in the shape of <'' and has two refraction points, it may be refracted three or more times to have three or more refraction points.

Furthermore, in the second embodiment, its modification, and the third embodiment, the case where there are three lower wiring layers 4 has been described, but the present invention is of course applicable to the case where there are four or more. Ru.

The first to third embodiments described above can be selected and combined depending on the relationship with the width of the upper wiring layer 8 and the layout requirements of the lower layer 4.

Further, in the first to third embodiments described above, the case where a plurality of lower wiring layers 4 are provided is described, but the effects of the present invention can be achieved even if there is not a plurality of lower wiring layers 4.

[Effects of the Invention] As described above, according to the present invention, the lower wiring layer provided on the substrate and the uneven portion formed by the lower wiring layer are provided via the glabella insulating layer, and the steps of the uneven portion are In a semiconductor device having an upper wiring layer whose film thickness is smaller than that on a flat part, the wiring direction of the lower wiring layer and the wiring direction of the upper wiring layer intersect diagonally. Therefore, the average film thickness of the cross section in the width direction of the upper wiring layer is always larger than the film thickness on the step, and therefore the cross-sectional area of the upper wiring layer is larger than the cross-sectional area of the conventional upper wiring layer at the position where reduction occurs. Always get bigger.

This prevents the current capacity of the upper wiring layer from decreasing without increasing the wiring width of the upper wiring layer, maintains a high current capacity, and contributes to miniaturization of the wiring layer.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the present invention in detail, FIG. 2 is a plan view showing a semiconductor device according to the first embodiment of the present invention, and FIG. 3 is a modification of the semiconductor device according to the first embodiment. 4 is a plan view showing a semiconductor device according to a second embodiment of the present invention. FIG. 5 is a plan view showing a modification of the semiconductor device according to the second embodiment. FIG. 7 is a plan view showing a semiconductor device according to a third embodiment of the invention, and a cross-sectional view showing a conventional semiconductor device. In the figure, 2... base board, 4... lower wiring layer, 6... interlayer insulating layer, 8..., E layer heavy line layer, 10. ...Through hole. J5 Throat Moan - Yashu ml > No + 5

Claims (1)

[Claims] 1. A substrate, a lower wiring layer provided on the substrate, and an interlayer insulating layer provided on the uneven part formed by the lower wiring layer, and on the step of the uneven part. In a semiconductor device having an upper wiring layer whose film thickness is smaller than the film thickness on a flat part, the wiring direction of the lower wiring layer and the wiring direction of the upper wiring layer diagonally intersect, and this intersection A semiconductor device characterized in that an average film thickness in a cross-sectional width direction of the upper wiring layer in the area where the upper wiring layer is formed is larger than a film thickness on the step of the uneven portion. 2. The semiconductor device according to claim 1, wherein the lower wiring layer includes N lower wiring layers having a line width l running in parallel at intervals of a space width s, and the wiring of the lower wiring layer in the intersecting region. The direction is linearly inclined with respect to the wiring direction of the upper wiring layer, and the amount of displacement L of the lower wiring layer with respect to the width direction of the upper wiring layer is L>(l+s)(N-1). semiconductor devices. 3. The semiconductor device according to claim 1, wherein the wiring direction of the lower wiring layer in the intersecting region is bent in a dogleg shape, and the wiring direction of the lower wiring layer with respect to the width direction of the upper wiring layer is bent. 2. The semiconductor device according to claim 1, wherein the amount of displacement at the bending point of the square shape is larger than the space width of the lower wiring layer. 4. The semiconductor device according to claim 3, wherein the wiring direction of the lower wiring layer in the intersecting region is bent into a dogleg shape two or more times, and the bent point of the dogleg shape of the lower wiring layer is bent at least twice. A semiconductor device, wherein there are two or more refraction points, and an amount of displacement at at least one of the two or more refraction points is larger than a space width of the lower wiring layer.