JP3168473B2 - Integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device having a multilayer wiring structure.

[0002]

2. Description of the Related Art In recent years, the scale of integrated circuit devices has tended to increase significantly, and the amount of data handled by a computer at one time has been reduced from 4 bits, 8 bits, 16 bits to 32 bits, and even 64 bits. Has increased. Accordingly, the number of bus lines for transmitting data in the integrated circuit device used in such a computer has naturally increased from 16 lines to 32 lines and 64 lines.

FIG. 5 is an explanatory diagram showing an example of a configuration of a conventional integrated circuit device. In this figure, BL is an element block,
a ₀ , a ₁ , a ₂ , ..., an _-1 are bus lines in the X direction, b ₀ , b ₁ , b ₂ , ..., b _n-1 are bus lines in the Y direction, c ₀ , C ₁ , c ₂ ,..., Cn _-1 are branch wirings from the bus line, d ₁ and d ₂ are other wirings crossing the bus line, and A is a wiring interlayer connection.

In this integrated circuit device, an n-bit element block BL is provided on a semiconductor chip, and X-direction bus lines a ₀ , a ₁ , a ₂ ,.
_n-1 and bus lines b ₀ , b ₁ , b ₂ ,.
, B _n-1 and branch lines c ₀ , c ₁ ,
c _2, ···, and c _n-1, another wiring across the bus lines d _1, d ₂ are formed.

In this case, the X-direction bus lines a ₀ ,
a ₁ , a ₂ ,..., a _n−1 are formed by lower wiring layers, and bus lines b ₀ , b ₁ , b ₂ ,.
.., B _n-1 are formed by an upper wiring layer via an interlayer insulating film, and branch wirings c ₀ , c ₁ ,.
_{c 2, ···, c n-} 1 is formed by a wiring layer via the wiring interlayer connection portion, another wiring d _1, d ₂ across the bus lines formed by the upper layer or the lower wiring layer Have been.

Further, bus lines a ₀ , a ₁ , a in the X direction
_2, ···, a _n-1 and Y-direction of the bus line b _0, b _1,
b ₂ ,..., b _n−1 are connected at the intersection by a wiring interlayer connection part A.

In this conventional integrated circuit device, the bus lines in the X direction or the Y direction are formed side by side on the same plane, so that the number of bus lines is large and the width of the bus lines is large. In such a case, it was necessary to increase the wiring area in order to form a bus line. As a result, the ratio of the wiring area to the entire surface of the semiconductor chip has increased, which has hindered the improvement in the degree of integration of the integrated circuit device.
It was required to solve this.

[0008] In order to meet the above demands, the above-mentioned 2
A three-layer wiring structure has been adopted in place of the layer wiring structure. In this three-layer wiring structure, the first wiring layer is dedicated to the vertical wiring, the second wiring layer is the horizontal wiring layer, and the third wiring layer is extremely complicated in wiring. 2
It has been used exceptionally when one wiring layer is insufficient, or especially when it is desired to connect wires at the shortest distance for the purpose of reducing delay time. The bus line was also designed according to this circuit layout policy.

[0009]

In any case, in the above-mentioned integrated circuit device, a large number of bus lines are formed in parallel on a wiring layer on the same plane. It was necessary to widen the wiring area. Therefore, the ratio of the wiring area to the entire surface of the chip cannot be suppressed, and the degree of integration of the integrated circuit device cannot be improved in response to demand. The present invention has been made in view of the above problems, and has as its object to reduce the wiring area of a bus line and improve the degree of integration.

[0010]

SUMMARY OF THE INVENTION An integrated circuit device according to the present invention is provided.
In an integrated circuit device having a multilayer wiring structure,
Upper layer with multiple bus lines sandwiching an intermediate wiring layer
A first wiring layer distributed to a wiring layer and a lower wiring layer;
Bus line group and multiple bus lines between intermediate wiring layers
Distributed over the upper wiring layer and the lower wiring layer
A second bus line group, and the first bus line
Buses included in the bus group and formed in the upper wiring layer
Line and the second bus line group and the lower layer
A bus line formed in a wiring layer and the intermediate wiring layer
And included in the first bus line group, and
A bus line formed in the lower wiring layer;
And formed in the upper wiring layer.
Bus line connected via the intermediate wiring layer
It is characterized by becoming.

[0011]

[0012]

The above problem is that in a multilayer wiring structure of three or more layers, one set of bus lines is distributed, for example, half to the lower wiring layer and the other half to the upper wiring layer, and they are stacked vertically. This problem can be solved by forming in a state in which the wiring is branched, and forming a branch line from the bus line and a signal line crossing the bus line in the intermediate wiring layer.

However, when the bus line is long, if it is formed by laminating as described above, a new problem which has not been seen before may occur. In other words, the wiring passing through the lower wiring layer and the wiring passing through the upper wiring layer have a difference in distance from the substrate, so that their wiring capacities are unbalanced. In particular, the longer the bus line, the greater the degree of imbalance.

This problem is solved by replacing the lower wiring layer and the upper wiring layer at a middle point of the bus line.

[0015]

Embodiments of the present invention will be described below. FIG. 1 shows the structure of an integrated circuit device according to a first embodiment.
FIG. In this figure, BL is an element block.
K, a₀, A₁, A_Two, A_Three, ..., a _n-2, A_n-1
Is the bus line in the X direction, b₀, B₁, B_Two, B_Three, ...
・, B_n-2, B_n-1Is the bus line in the Y direction, c₀,
c₁, C_Two, C_Three, ..., c_n-2, C _n-1Is Bas Rai
Wiring from the terminal, d₁, D_TwoCrosses the bus line
The other wirings, A and B, are wiring interlayer connection parts.

In the integrated circuit device of this embodiment, an n-bit element block BL is provided on a semiconductor chip, and X-direction bus lines a ₀ , a ₁ , a ₂ , a ₃ ,.
..., an _-2 , an _-1 and bus lines b0, _b0 ,
_{b 1, b 2, b 3} , ···, b n-2, b and _n-1, the branch wiring c ₀ from the bus _{line, c 1, c 2, c} 3, ···,
and _{c n-2, c n-} 1, another wiring across the bus lines d _1, d ₂ are formed.

In this case, the bus line in the X direction
a₀, A₁, A_Two, A_Three, ..., a_n-2, A_n-1When,
Bus line b in Y direction₀, B₁, B_Two, B_Three, ...,
b_{n- Two}, B_n-1Is the even bus line a₀, A_Two,
.., a_n-2And b₀, B _Two, ..., b_n-2And odd
Th bus line a₁, A_Three, ..., a_n-1And b
₁, B_Three, ..., b_n-1Distributed to the even-numbered buses
Lines as lower wiring layers, odd-numbered bus lines as upper layers
Wiring layer, between which branch wiring from bus line
c₀, C₁, C_Two, C_Three, ..., c_n-2, C_n-1And ba
Other wiring d across the line₁, D_TwoWith the intermediate wiring layer
It is formed.

Further, even-numbered layers formed in the intermediate wiring layer
Branch wiring c from the eye bus line₀, C_Two, ..., c
_n-2Is formed in the lower wiring layer by the wiring interlayer connection portion A.
Even-numbered bus line a in the X direction₀, A_Two, ...
・, A_n-2From the odd-numbered bus line
Branch wiring c₁, C_Three, ..., c_n-1Is the wiring layer connection portion B
Odd number in the X direction formed in the upper wiring layer
Bus line a₁, A _Three, ..., a_n-1Connected with
I have.

In FIG. 1, in order to clearly represent the lower wiring layer and the upper wiring layer, the lower wiring layer is represented by a wide white line, and the upper wiring layer is represented by a thin black line. In the device, it is constituted by wiring having the same width.

FIGS. 2A and 2B are diagrams for explaining the configuration of the wiring interlayer connection portion of the first embodiment. In this figure, 1 is a semiconductor chip, 2 is an insulating film, 3 is a lower wiring layer, 4 is an intermediate wiring layer, 5 is an upper wiring layer, and A and B are wiring interlayer connection parts.

FIG. 2A shows an even-numbered bus line, which is a lower wiring layer 3 formed by being buried in the insulating film 2 above the semiconductor chip 1, and being buried in the insulating film 2 thereabove. It shows a configuration of a wiring interlayer connection portion A for connecting a branch wiring from a bus line, which is an intermediate wiring layer 4, and the wiring interlayer connection portion A is formed by a usual method for forming a contact hole.

FIG. 2B shows an odd-numbered bus line, which is an upper wiring layer 5 formed by being buried in the insulating film 2 above the semiconductor chip 1, and being buried in the insulating film 2 therebelow. 3 shows a configuration of a wiring interlayer connecting portion B for connecting branch wiring from a bus line which is an intermediate wiring layer 4.

In this embodiment, since the even-numbered bus lines and the odd-numbered bus lines are distributed to the lower wiring layer and the upper wiring layer, the wiring layer area can be reduced. The formation of the branch wiring from the substrate and other wiring crossing the bus line facilitates the design and manufacture of the integrated circuit device.

In this embodiment, it has been described that the even-numbered bus lines and the odd-numbered bus lines are distributed to two wiring layers. However, the bus lines are distributed to three or more wiring layers. Needless to say, the wiring layer area can be further reduced.

(Second Embodiment) FIG. 3 shows the integration of the second embodiment.
FIG. 3 is an explanatory diagram of a configuration of a circuit device. In this figure, a₀,
a₁, A_Two, A_Three, A_Four, A_{Five ,}..., a_n-2, A
_n-1Is the first bus line, e₀, E₁, E_Two, E_Three, E
_Four, E_{Five ,}..., e_{n- Two}, E_n-1Is the second bus line,
f₀, F₁, F_Two, F_Three, F_Four, F_{Five ,}...
f_n-2, F_n-1Is an intermediate wiring layer, and A and B are connection parts between wiring layers.
It is.

In the integrated circuit device of this embodiment,
Number bus line a₀, A_Two, A _Four, ..., a_n-2
Are formed as lower wiring layers, and odd-numbered bus lines a
₁, A_Three, A_{Five ,}..., a_n-1Is used as the upper wiring layer
First bus line pair formed and even bus lines
e₀, E_Two, E_Four, ..., e_n-2Is the lower wiring layer
Formed odd-numbered bus lines e₁, E_Three, E_{Five ,}・
.., e_n-1Bus formed as an upper wiring layer
A line pair is partially arranged in parallel, and this bus line pair
The part of the upper layer bus line that is parallel to is removed,
An insulating film is interposed between the lower wiring layer and the upper wiring layer.
Intermediate wiring layer f₀, F₁, F_Two, F _Three, F_Four, F
_{Five ,}..., f_n-2, F_n-1And wiring interlayer connection A,
B, the lower wiring layer of the first bus line pair and the second
Between the upper wiring layer of the bus line pair and the first bus line;
Upper wiring layer of in pair and lower wiring layer of second bus line pair
Are connected.

Therefore, the second bus line pair
Since the lower wiring layer and the upper wiring layer of the bus line pair are interchanged before reaching the bus line pair, the distance between the upper and lower wiring layers and the substrate is averaged, and the wiring capacitance can be equalized.

(Third Embodiment) FIG. 4 shows an integration of the third embodiment.
FIG. 3 is an explanatory diagram of a configuration of a circuit device. In this figure, g₀,
g₁, G_Two, G_Three, ..., g_n-2, G_n-1Is the first bus
Sline, i₀, I₁, I_Two, I_Three, ..., i_n-2,
i_n-1Is the second bus line, h₀, H₁, H_Two, H_Three,
..., h_n-2, H_n-1Is the second element from the first bus line
Branch wiring to child block BL2, j₀, J₁, J_Two, J
_Three, ..., j _n-2, J_n-1Is the third element block
Branch wiring from one bus line, k₁, K_TwoIs a signal line,
l₁Is the wiring other than the other bus lines, and BL1 is the first element.
Child block, BL2 is the second element block, BL3 is the third element block.
The element blocks A and B are connection portions between wiring layers.

This embodiment is a combination of the integrated circuit device of the first embodiment and the integrated circuit device of the second embodiment.

That is, the first bus line g₀, G₁,
g_Two, G_Three, ..., g_n-2, G_{n- 1}And the first bass line
Wiring h from the gate to the second element block BL2₀,
h₁, H _Two, H_Three, ..., h_n-2, H_n-1Configuration,
And the first bus line g₀, G ₁, G_Two, G_Three, ...
・, G_n-2, G_n-1And a third element block from the first bus line.
Branch wiring j to lock BL3₀, J₁, J_Two, J_Three,
.., j_n-2, J_n-1Is the same as in the first embodiment.
It is like.

The configuration of the first bus line and the second bus line is the same as the configuration of the second embodiment in which the lower wiring layer and the upper wiring layer are interchanged.

According to this embodiment, the first element block B
L1, second element block BL2, third element block BL
In the wiring area between the three wiring lines, a large number (for example, 64) of bus lines are formed as one set, and are formed in a state in which the bus lines are distributed half by half into a lower wiring layer and an upper wiring layer, and are stacked vertically. From the bus line, branch wiring is formed in the second element block and the third element block using the second wiring layer,
A complicated wiring can be realized by effectively using the wiring area.

Further, at the branch portion to the third element block, a structure is employed in which the wiring of the upper wiring layer and the wiring of the lower wiring layer of the bus line are exchanged. Note that the signal lines k ₁ , k
₂ is formed by the intermediate wiring layers, the wiring l ₁ other non-bus lines are formed as in the conventional art.
For the wiring l ₁ other than the other bus lines,
Inheriting the conventional usage of the wiring layer, the wiring in the horizontal direction with respect to the substrate uses the lower wiring layer, and the wiring in the vertical direction uses the upper wiring layer. However, when the horizontal wiring crosses the bus line, only the crossing portion uses the intermediate wiring layer.

[0034]

As described above, according to the present invention,
Since the width of the wiring area is reduced to half or less, the area of the wiring area can be greatly reduced, the degree of integration of the entire chip can be improved, and the lower layer of the bus lines distributed to the upper and lower wiring layers By exchanging the wiring layer and the upper wiring layer, the wiring capacitance of the upper and lower wiring layers can be equalized, which greatly contributes to the technical field of the integrated circuit device.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a configuration of an integrated circuit device according to a first embodiment.

FIGS. 2A and 2B are explanatory diagrams of a configuration of a wiring interlayer connection portion of the first embodiment.

FIG. 3 is an explanatory diagram of a configuration of an integrated circuit device according to a second embodiment.

FIG. 4 is a diagram illustrating the configuration of an integrated circuit device according to a third embodiment.

FIG. 5 is a diagram illustrating an example of a configuration of a conventional integrated circuit device.

[Explanation of symbols]

BL element blocks _{a 0, a 1, a 2} , a 3, ···, a n-2, a n-1 X
Bus lines b ₀ , b ₁ , b ₂ , b ₃ ,..., B _n-2 , b _n-1 Y
Branch lines from the bus lines c ₀ , c ₁ , c ₂ , c ₃ ,..., C _n-2 , c _n-1 bus lines d ₁ , d ₂ B Wiring interlayer connection

Claims (1)

(57) [Claims] 1. An integrated circuit device having a multilayer wiring structure.
The upper wiring layer with multiple bus lines with an intermediate wiring layer
And a first bus line distributed to a lower wiring layer
Inner layer and upper wiring layer with multiple bus lines sandwiching intermediate wiring layer
And a second bus line distributed to the lower wiring layer
In the first bus line group and in the upper wiring layer.
The formed bus line and the second bus line group
Bus line included and formed in the lower wiring layer
Are connected via the intermediate wiring layer, and are included in the first bus line group and connected to the lower wiring layer.
The formed bus line and the second bus line group
Bus line included and formed in the upper wiring layer
Are connected via the intermediate wiring layer .