JPS58139449A - Multilayer integrated circuit with vertical signal wirings - Google Patents

Abstract

PURPOSE:To facilitate wiring design by laminating in a multilayer semiconductors formed with an IC through an interlayer insulators, and forming signal wirings which pass vertically linearly, thereby facilitating the wiring design and reducing the occupying area of a through hole pad. CONSTITUTION:Respective flat surfaces IC have various circuit blocks 1 and inlayer wirings 2 in 3-layer LSI of L1-L3, and connected substantially vertically linear interlayer wirings 3. The wirings 3 are formed, for example, by forming a through hole which reaches, for example, lower layer wirings, covering a wiring material layer of upper layer and patterning it. In this structure, the through hole pad becomes at the intermediate layer has approx. half of the necessary number capable of commonly connected elevationally to the intermediate layer, the reducing effect can be increased to increase the intermediate layer, the occupying area can be eliminated, the position of the interlayer wirings can be fixed, thereby alleviating the complicated design by a computer in a multilayer LSI.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to the arrangement of glabellar wiring in a multilayer integrated circuit.

(b) Technical background The recent increase in the amount of integration in S11 circuit technology has been remarkable.
It is becoming a reality that integrated circuits formed in one plane cannot be accommodated no matter how high the integration density is.

Multilayer integrated circuits are being considered as a solution to this situation. This is done by stacking multiple semiconductor layers that form an integrated circuit, and connecting the circuits of each layer with glabellar wiring.
The aim is to realize even larger-scale integrated circuits, but even in circuits that can be configured as single-plane large-scale integrated circuits (hereinafter abbreviated as LSI), signal lines can be made shorter by adopting a multilayer configuration. There may be benefits such as gains.

One of the technologies necessary to realize multilayer LSI is SOI.
For example, there is a technique in which a semiconductor layer is formed on an insulator by depositing a non-monocrystalline silicon layer on silicon dioxide and converting it into a single crystal. Advances in this technology have made it possible to cover a semiconductor layer on which an integrated circuit has already been formed with an insulating layer, and then deposit a new single crystal semiconductor layer on top of that to form an integrated circuit there. There is.

In designing a multilayer LSI, as in the design of a single-plane LSI, circuits are arranged in blocks according to function and size in each layer, and wiring is performed within and between layers.
This arrangement and wiring will be performed by an electronic computer system. Design performed using an electronic computer system will hereinafter be referred to as CAD according to convention.

(C) Prior Art and Problems Multilayer LSI technology is currently under development, and there is no standard design method yet.

Due to its large scale, it has no choice but to rely on CAD, but the conventional approach is to design each layer of integrated circuits according to the method used for planar LSIs, and to design interlayer wiring as necessary. This is a method in which a via hole is provided in the area.

In order to provide a via hole, it is necessary to prepare a pad in the intralayer wiring pattern, but in such a method, the position of the via hole is uncertain, which complicates the design of the wiring pattern. Furthermore, for each interlayer wiring, one pad must be provided for each of the upper and lower intralayer wirings, which increases the wiring area.

FIG. 1 schematically shows this situation.

Figure 1 shows an example of a multilayer LSI with a three-layer structure.
, L2. L3 represents a planar integrated circuit in each layer, which is composed of a plurality of circuit blocks 1 and intralayer wiring 2 that connects them. The planar integrated circuits are connected to each other by interlayer wiring 3, but as described above, the positions thereof are irregular.

A via hole pad is provided at a connection point 4 between the intralayer wiring 2 and the interlayer wiring 3.

(d) Object of the Invention An object of the present invention is to facilitate wiring design and reduce the area occupied by the via hole pad in the intralayer wiring by fixing the position of the interlayer wiring.

<e> Structure of the Invention In order to achieve the above object, the multilayer LSI of the present invention includes a plurality of semiconductor layers in which an integrated circuit is formed in each layer, a plurality of semiconductor layers, and a plurality of semiconductor layers that are interconnected. The signal line extends through an insulating layer that is insulated from the semiconductor layer and connects the integrated circuits in each layer in a direction perpendicular to the semiconductor layer, and the signal line connects all of the semiconductor layers in a substantially vertical direction. It has a structure that penetrates in a straight line.

<1> Examples of the invention FIG. 2 schematically shows an embodiment of the present invention.

The multilayer LSI in FIG. 2 also has L1. L2, L3
It consists of three layers of planar integrated circuits, and each planar integrated circuit has various circuit programs 1, intralayer wiring 2, and is interconnected by interlayer wiring 3'.

As is clear from the figure, in the interlayer arrangement &m3', the Ll/L2 connection and the L2/L3 connection are provided at the same position in the horizontal plane, and Ll, , L2, and L3 are connected almost in a straight line. There is.

The main types of wiring that require layered connections include various power lines, ground lines, and various noise lines such as data buses.
If there is a point where the same type of wiring in all layers intersects in a plane, it is sufficient to provide a via hole pad at that position and form interlayer wiring, but if such a point does not exist, A point is selected that is convenient for the wiring in the layer, or a point that does not cause any extreme disadvantage to the wiring in any layer.

The following methods can be used to form interlayer wiring. One method is to form a pipe hole that reaches the lower layer wiring, and then apply an upper layer of wiring material and pattern it, similar to normal multilayer wiring.The other method is to cover the lower layer integrated circuit. In this method, a via hole is provided in the layer to be formed, a polycrystalline silicon layer is deposited to fill the via hole, and the polycrystalline silicon layer is formed into a single crystal.

In the latter case, the silicon in the via hole is doped with impurities at a high concentration, but this doping may be performed either before or after the single crystallization step.

In the present invention, the via hole pads can be shared for upper and lower connections in the intermediate layer, so the number of via hole pads required is approximately halved. Therefore, as the number of intermediate layers increases, the decrease in the number of pads becomes more significant.

(g) As described in the detailed explanation of the invention, if the position of the interlayer wiring is fixed,
In designing a multilayer LSI, the complexity of CAD software is reduced, and the wiring area is also reduced due to the reduction in the number of Neuer Hall paths.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a multilayer LSI according to the prior art, and FIG. 2 is a diagram showing a multilayer LSI according to the present invention.
1 is a circuit block, 2 is an intralayer wiring, 3°3' is an interlayer wiring, and 4 is a connection point between the intralayer wiring and the interlayer wiring. -'''''

Claims (1)

[Claims] a plurality of semiconductor layers in which an integrated circuit is formed in each layer;
A multilayer integrated circuit comprising a plurality of semiconductor layers and a signal line that connects the integrated circuits of each layer in a direction perpendicular to the semiconductor layers by passing through an insulating layer that insulates and separates the plurality of semiconductor layers from each other. A multilayer integrated circuit having a vertical signal line, characterized in that the signal line passes through all of the semiconductor layers in a substantially straight line in the vertical direction.