JPH04218943A - Manufacture of large-scale integrated circuit device - Google Patents

Abstract

PURPOSE:To enable making the circuits of many IC chips into one chip without redesigning them by forming regions corresponding to a plurality of evaluated chips in one and the same semiconductor substrate and by selectively connecting pads corresponding to the bonding pads of the regions corresponding to respective chips through an electrode wiring layer on a layer insulation film. CONSTITUTION:Regions A and B corresponding to an evaluated and confirmed chip are arranged and formed in the chip 1. Then, metal wirings 17, 27 are formed with an insulating film 26 between and used as mutual wiring 6 and external wiring 7 between the regions A and B corresponding to the chip. Further, a VIA contact 28 is formed on a bonding pad 2 or 3 and aluminum is vapor-deposited on the contact to combine the metal wirings of respective layers.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a large-scale integrated circuit device that simplifies the system configuration of a data processing device or the like.

0002

[Background Art] In order to configure a system such as a personal computer, a plurality of LSIs (Large-Scale Integrated Circuits) are usually used.
Use in combination. These are CPU (Central Processing Unit)
, ROM (read-only memory), RAM (random access memory), key input control section, serial input/output section, parallel input/output section, counter timing control section, display drive section, etc., and each Mutual wiring between chips is provided by a printed circuit board. However, with this method, the interconnections on the printed circuit board are complicated and the manufacturing process is time-consuming, leading to an increase in costs. Also, because the capacitance of printed wiring is large, even if each chip becomes faster, it does not speed up the overall system. In addition, due to the high failure rate, there is a strong demand from users that "it is possible to integrate multiple LSIs used in the system into a single chip."

[0003] As a method to meet the above-mentioned demand for one chip, (a) redesign the entire system and create a new one-chip L
Possible solutions include creating an SI, and (b) encapsulating multiple chips in one package to create a so-called hybrid IC (integrated circuit). In the case of the method of redesigning the system in item (a) above, the current design method is [
1] Completely manual design method, [2] Automatic design method using a building block method using a computer, [3]
Automatic design using gate arrays, etc. These [1
] to [3] All have advantages and disadvantages, but the biggest disadvantage of redesigning is that each chip has already been developed and the functions and
Even though the characteristics have been sufficiently evaluated and it is acceptable, in order to design something similar again, we have to go through the design and evaluation steps again. Therefore, there are various problems such as the risk of design errors and the time required for development, and it cannot help but be said that this method is inefficient.

[0004] The hybrid IC method described in item (b) above appears as a single component when viewed from the outside, but is simply a miniaturization of the method of mounting and wiring a plurality of chips on the printed circuit board. It's nothing more than that. Of course, there are some advantages to just making it smaller, but as an actual packaging technology, there are still doubts as to how many chips can be hybridized, and even if it were possible, the cost would increase considerably.

[0005]

[Problems to be Solved by the Invention] The present invention has been made in view of the above circumstances, and provides a method for manufacturing a large-scale integrated circuit device that enables a new system to be integrated into one chip, which is different from either redesign or hybridization. This is what we are trying to provide.

[0006]

[Means and effects for solving the problems] The present invention provides a plurality of chips that have pads equivalent to a plurality of bonding pads and are required to perform the function of an integrated circuit whose function has already been confirmed. a step of simultaneously forming equivalent regions on the same semiconductor substrate, a step of forming an interlayer insulating film of a wiring layer on the chip equivalent region, a step between pads for bonding pad equivalents of the plurality of chip equivalent regions, and a step of forming the bonding pads. A method for manufacturing a large-scale integrated circuit device, comprising the step of selectively connecting corresponding pads and bonding pads of the semiconductor substrate with electrode wiring layers provided on the interlayer insulating film. .

In the present invention, in order to realize a desired device, patterns of each chip that have already been designed and evaluated are used as they are to form a single chip. Moreover, by doing the above, each chip and the wiring between them, which were conventionally formed separately, can be formed all at once on one semiconductor substrate.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings. In Figure 1, 1 is a semiconductor chip, A and B are chips 1
These are chip-equivalent regions formed together in the same process within the chip, and these regions have been previously evaluated as chip A and chip B, respectively. 2 and 3 are chip equivalent area A,
Bonding pad when B was previously chips A and B (this is temporarily called an inner bonding pad, but in this invention, it is called a pad equivalent to a bonding pad), 4
is a bonding pad of chip 1 (this is temporarily referred to as an outer bonding pad). In this way, place the chip equivalent areas A and B whose evaluation has already been confirmed into an appropriate space 5.
are placed and formed in the chip 1. This space 5 is a wiring area for mutual wiring 6 between the chip-equivalent areas A and B, and near the periphery is a wiring area for connecting bonding pads (this is used as lead terminals from the LSI to connect to the outside after forming one chip). (temporarily referred to as external wiring) 7 is also provided. That is, chip equivalent areas A and B
The wiring area 5 is used to connect the interconnection wiring 6 between areas A and B between the corresponding bonding pads that each area A and B have.
, B using wiring layers (polysilicon, aluminum, etc.). Furthermore, the necessary number of bonding pads 4 corresponding to external wiring 7 are laid out around the chip, and the external wiring 7 is made of polysilicon or aluminum between the bonding pads 2 and 3 of the corresponding areas A and B and the outer bonding pad 4. etc. FIG. 2 shows a partial cross section of FIG. 1, in which 11 is a transistor region of chip equivalent area A or B, 12 is an N type substrate, 13 and 14 are P+ type source and drain regions,

15 is an insulating film, 16 is a polysilicon gate electrode, 17 is an aluminum wiring, 18 is a wiring crossing area in the wiring area 5, and 17
1 and 172 are aluminum wiring layers corresponding to the wiring 6 in FIG. 1, and 19 is a polysilicon wiring layer.

[0010] The above example is a method of realizing mutual wiring and external wiring in the area corresponding to each chip by providing the wiring area 5 without changing the wafer process of each chip. In other words, printed circuit board wiring is printed on the same wafer as the chip with a wiring area provided, and the chip size after making it into one chip is 5 times larger than the combined area of each chip equivalent area A and B by the wiring area. The following example is shown in Figure 1.
This embodiment of the present invention is an improvement on the example shown in FIG. 2 and is a one-chip method that can reduce the wiring area 5 to almost zero.

[0011] FIGS. 3 and 4 show examples of this.
Here, in order to simplify the explanation, we will explain the chip equivalent areas A and B.
Each of them is an LSI constructed using a silicon gate process as in the case of FIGS. 1 and 2. Therefore, the chip-equivalent regions A and B each have an impurity diffusion layer (P+, N+ diffusion, etc.) that forms the source and drain, a polysilicon layer that forms the gate electrode, and a metal wiring layer that is often used as a normal wiring layer. There are three types, and they are electrically insulated on chips A and B depending on the circuit configuration,
be combined. The input and output signals of the chip-equivalent regions A and B are normally connected to the package leads through bonding pads 4 placed around the chip.
connected to the outside. Bonding pads are typically formed from a metal layer.

FIG. 4 shows a partial cross section of FIG. 3, but since this is an example corresponding to FIG. Let me explain the points. In FIG. 4, 21 is a P well layer, 22, 23
3 are the source and drain layers of the N-channel transistor 25, 24 is a gate electrode made of polysilicon, 26 is an interlayer insulating film, and 27 is a second aluminum wiring layer provided on this insulating film. This corresponds to wiring 6 or 7. 28 is a contact for connecting the aluminum wirings 17 and 27.

As described above, the techniques shown in FIGS. 3 and 4
Metal wirings 17 and 27 are formed on both sides of the metal wiring layer 6, and this second metal wiring layer is used as the mutual wiring 6 and external wiring 7 between the chip corresponding regions A and B. The signals transmitted by the second layer metal wiring 27 may be only input/output signals (including power supply) for each of the chip equivalent regions A and B. Also, electrical connection is required between the second layer metal wiring 27 and the inner bonding pad formed by the first layer metal, but this requires removing the interlayer insulating film 26 only at the necessary locations using photolithographic technology. However, this is possible by creating contact holes between layers. Such a contact 28 is usually called a via contact. That is, a via contact is formed on the bonding pad 2 or 3, and a second layer of metal (aluminum) is deposited on the via contact, thereby bonding the metal wirings of each layer. However, it is clear that the via contact need not necessarily be formed on the bonding pad 2 or 3. A new LSI in which chip-equivalent areas A and B are combined will eventually become an LS
A bonding pad (outer bonding pad) 4 for transmitting signals to the outside is required, but this is formed from the second layer of metal.

In the LSI configured as shown in FIGS. 3 and 4, the second layer of wiring 27 can be formed on the chip corresponding areas A and B, and as in the case of FIG. Since there is no need to provide it in particular, the chip size can be reduced. Furthermore, since aluminum can be used at the intersection of the first and second layer wiring, the resistance can be kept low and high-speed design is possible. In addition, the first layer wiring 17 and the second layer wiring 2
7 do not intersect on the same plane, increasing the degree of freedom in wiring design.

FIG. 5 shows an example of pattern arrangement using the methods shown in FIGS. 3 and 4. A to E are LSIs (chip equivalent areas) whose functions have already been developed and whose functions have been confirmed, and it is possible for the same chip equivalent areas to overlap (for example, D=E). In addition, the wiring between each chip-equivalent area is the second layer of aluminum wiring 27 (
(corresponding to wiring 6 or 7 in Figure 5). Pads 2 and 3 and second layer wiring 6 that each chip equivalent area originally has
, 7 are connected by via contacts. Pads 4 on the outer periphery become bonding pads for the new LSI, and are made from the second layer of aluminum.

Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, in the embodiment, the structure of the chip equivalent regions A, B, etc. is of silicon gate type, but it can be applied to various cases such as aluminum gate type, tungsten gate type, molybdenum gate type, etc. Further, the metal material for the wiring is not limited to aluminum, but various materials such as tungsten and molybdenum can be used. Furthermore, in the embodiment, the outer bonding pads 4 are formed in the outer regions of the chip-equivalent regions A and B, but if the pattern shape allows, the pads 4 can be formed on the same line as the bonding pads 2 and 3 in the chip-equivalent regions A and B. may be formed. Further, although the case of two-layer wiring using aluminum as the metal wiring layer has been described, multi-layer wiring such as three-layer, four-layer, etc. may also be used.

[0017]

As explained above, according to the present invention, since the chip-equivalent area requires almost no modification to the conventional chip structure, a device whose functions and characteristics have been evaluated can be made into a single chip using the same process. Furthermore, since it can be made into a single chip, reliability is improved compared to those using conventional printed circuit boards. Furthermore, the conventional wafer process can be used as is to obtain this device, and the manufacturing process can be simplified. Further, since the second and subsequent layers of wiring can be formed on the chip-equivalent region, the chip size can be reduced. Also, the first and second
Since aluminum can be used for the cross-wiring portions such as layers, resistance can be reduced and high-speed design possible. Also the second
Since the wiring in the subsequent layers does not intersect with that in the first layer on the same plane, the degree of freedom in wiring design is increased. Furthermore, according to the present invention, it is possible to conduct IC wiring for the wiring 6 using a normal IC process without using mechanical connection (using bonding wires), and it is possible to significantly miniaturize the IC. Since bonding and bonding wire crossings within the IC chip do not occur, mass productivity is excellent and the process is simplified. Furthermore, since the present invention does not require bonding within the chip, the number of bonding operations is reduced and the chances of applying mechanical stress to the chip are significantly reduced. Therefore, in this respect as well, reliability is improved compared to conventional devices.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view of an LSI before improvement.

FIG. 2 is a partial cross-sectional view of FIG. 1.

FIG. 3 is a schematic plan view of an embodiment of the present invention.

FIG. 4 is a partial cross-sectional view of FIG. 3;

FIG. 5 is a schematic plan view showing an application example of the above embodiment.

[Explanation of symbols]

1... Semiconductor chip, 2-4... Bonding pad, 6,
7... Wiring, 12... N type board, 17, 27... Wiring, 21...
P well layer, 26... interlayer insulating film, 28... via contact, A, B... chip equivalent area.

Claims (5)

[Claims] [Claim 1] Simultaneously forming on the same semiconductor substrate a plurality of chip-equivalent regions that have pads equivalent to a plurality of bonding pads and are required to perform the function of an integrated circuit whose function has already been confirmed. a step of forming an interlayer insulating film of a wiring layer on the chip-equivalent region, and a step between the bonding-pad-equivalent pads of the plurality of chip-equivalent regions, and between the bonding-pad-equivalent pads and bonding pads of the semiconductor substrate. A method for manufacturing a large-scale integrated circuit device, comprising the step of selectively connecting the electrode wiring layers provided on the interlayer insulating film. 2. The method of manufacturing a large-scale integrated circuit device according to claim 1, wherein each of the chip-equivalent regions is a CPU (central processing unit), a memory, or a peripheral device that is completed individually. 3. The method of manufacturing a large-scale integrated circuit device according to claim 1, wherein the chip-equivalent region is formed of a silicon gate structure. 4. The method of manufacturing a large-scale integrated circuit device according to claim 1, wherein the chip-equivalent region is formed with an aluminum gate structure. 5. The method of manufacturing a large-scale integrated circuit device according to claim 1, wherein the electrode wiring layer has a wiring structure of two or more layers.